drivers/net/arm/ixp4xx_eth.c

   1 /*
   2  * Intel IXP4xx Ethernet driver for Linux
   3  *
   4  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * Ethernet port config (0x00 is not present on IXP42X):
  11  *
  12  * logical port         0x00            0x10            0x20
  13  * NPE                  0 (NPE-A)       1 (NPE-B)       2 (NPE-C)
  14  * physical PortId      2               0               1
  15  * TX queue             23              24              25
  16  * RX-free queue        26              27              28
  17  * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
  18  *
  19  *
  20  * Queue entries:
  21  * bits 0 -> 1  - NPE ID (RX and TX-done)
  22  * bits 0 -> 2  - priority (TX, per 802.1D)
  23  * bits 3 -> 4  - port ID (user-set?)
  24  * bits 5 -> 31 - physical descriptor address
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/phy.h>
  34 #include <linux/platform_device.h>
  35 #include <mach/npe.h>
  36 #include <mach/qmgr.h>
  37
  38 #define DEBUG_DESC              0
  39 #define DEBUG_RX                0
  40 #define DEBUG_TX                0
  41 #define DEBUG_PKT_BYTES         0
  42 #define DEBUG_MDIO              0
  43 #define DEBUG_CLOSE             0
  44
  45 #define DRV_NAME                "ixp4xx_eth"
  46
  47 #define MAX_NPES                3
  48
  49 #define RX_DESCS                64 /* also length of all RX queues */
  50 #define TX_DESCS                16 /* also length of all TX queues */
  51 #define TXDONE_QUEUE_LEN        64 /* dwords */
  52
  53 #define POOL_ALLOC_SIZE         (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
  54 #define REGS_SIZE               0x1000
  55 #define MAX_MRU                 1536 /* 0x600 */
  56 #define RX_BUFF_SIZE            ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
  57
  58 #define NAPI_WEIGHT             16
  59 #define MDIO_INTERVAL           (3 * HZ)
  60 #define MAX_MDIO_RETRIES        100 /* microseconds, typically 30 cycles */
  61 #define MAX_CLOSE_WAIT          1000 /* microseconds, typically 2-3 cycles */
  62
  63 #define NPE_ID(port_id)         ((port_id) >> 4)
  64 #define PHYSICAL_ID(port_id)    ((NPE_ID(port_id) + 2) % 3)
  65 #define TX_QUEUE(port_id)       (NPE_ID(port_id) + 23)
  66 #define RXFREE_QUEUE(port_id)   (NPE_ID(port_id) + 26)
  67 #define TXDONE_QUEUE            31
  68
  69 /* TX Control Registers */
  70 #define TX_CNTRL0_TX_EN         0x01
  71 #define TX_CNTRL0_HALFDUPLEX    0x02
  72 #define TX_CNTRL0_RETRY         0x04
  73 #define TX_CNTRL0_PAD_EN        0x08
  74 #define TX_CNTRL0_APPEND_FCS    0x10
  75 #define TX_CNTRL0_2DEFER        0x20
  76 #define TX_CNTRL0_RMII          0x40 /* reduced MII */
  77 #define TX_CNTRL1_RETRIES       0x0F /* 4 bits */
  78
  79 /* RX Control Registers */
  80 #define RX_CNTRL0_RX_EN         0x01
  81 #define RX_CNTRL0_PADSTRIP_EN   0x02
  82 #define RX_CNTRL0_SEND_FCS      0x04
  83 #define RX_CNTRL0_PAUSE_EN      0x08
  84 #define RX_CNTRL0_LOOP_EN       0x10
  85 #define RX_CNTRL0_ADDR_FLTR_EN  0x20
  86 #define RX_CNTRL0_RX_RUNT_EN    0x40
  87 #define RX_CNTRL0_BCAST_DIS     0x80
  88 #define RX_CNTRL1_DEFER_EN      0x01
  89
  90 /* Core Control Register */
  91 #define CORE_RESET              0x01
  92 #define CORE_RX_FIFO_FLUSH      0x02
  93 #define CORE_TX_FIFO_FLUSH      0x04
  94 #define CORE_SEND_JAM           0x08
  95 #define CORE_MDC_EN             0x10 /* MDIO using NPE-B ETH-0 only */
  96
  97 #define DEFAULT_TX_CNTRL0       (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY |    \
  98                                  TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
  99                                  TX_CNTRL0_2DEFER)
 100 #define DEFAULT_RX_CNTRL0       RX_CNTRL0_RX_EN
 101 #define DEFAULT_CORE_CNTRL      CORE_MDC_EN
 102
 103
 104 /* NPE message codes */
 105 #define NPE_GETSTATUS                   0x00
 106 #define NPE_EDB_SETPORTADDRESS          0x01
 107 #define NPE_EDB_GETMACADDRESSDATABASE   0x02
 108 #define NPE_EDB_SETMACADDRESSSDATABASE  0x03
 109 #define NPE_GETSTATS                    0x04
 110 #define NPE_RESETSTATS                  0x05
 111 #define NPE_SETMAXFRAMELENGTHS          0x06
 112 #define NPE_VLAN_SETRXTAGMODE           0x07
 113 #define NPE_VLAN_SETDEFAULTRXVID        0x08
 114 #define NPE_VLAN_SETPORTVLANTABLEENTRY  0x09
 115 #define NPE_VLAN_SETPORTVLANTABLERANGE  0x0A
 116 #define NPE_VLAN_SETRXQOSENTRY          0x0B
 117 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
 118 #define NPE_STP_SETBLOCKINGSTATE        0x0D
 119 #define NPE_FW_SETFIREWALLMODE          0x0E
 120 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
 121 #define NPE_PC_SETAPMACTABLE            0x11
 122 #define NPE_SETLOOPBACK_MODE            0x12
 123 #define NPE_PC_SETBSSIDTABLE            0x13
 124 #define NPE_ADDRESS_FILTER_CONFIG       0x14
 125 #define NPE_APPENDFCSCONFIG             0x15
 126 #define NPE_NOTIFY_MAC_RECOVERY_DONE    0x16
 127 #define NPE_MAC_RECOVERY_START          0x17
 128
 129
 130 #ifdef __ARMEB__
 131 typedef struct sk_buff buffer_t;
 132 #define free_buffer dev_kfree_skb
 133 #define free_buffer_irq dev_kfree_skb_irq
 134 #else
 135 typedef void buffer_t;
 136 #define free_buffer kfree
 137 #define free_buffer_irq kfree
 138 #endif
 139
 140 struct eth_regs {
 141         u32 tx_control[2], __res1[2];           /* 000 */
 142         u32 rx_control[2], __res2[2];           /* 010 */
 143         u32 random_seed, __res3[3];             /* 020 */
 144         u32 partial_empty_threshold, __res4;    /* 030 */
 145         u32 partial_full_threshold, __res5;     /* 038 */
 146         u32 tx_start_bytes, __res6[3];          /* 040 */
 147         u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
 148         u32 tx_2part_deferral[2], __res8[2];    /* 060 */
 149         u32 slot_time, __res9[3];               /* 070 */
 150         u32 mdio_command[4];                    /* 080 */
 151         u32 mdio_status[4];                     /* 090 */
 152         u32 mcast_mask[6], __res10[2];          /* 0A0 */
 153         u32 mcast_addr[6], __res11[2];          /* 0C0 */
 154         u32 int_clock_threshold, __res12[3];    /* 0E0 */
 155         u32 hw_addr[6], __res13[61];            /* 0F0 */
 156         u32 core_control;                       /* 1FC */
 157 };
 158
 159 struct port {
 160         struct resource *mem_res;
 161         struct eth_regs __iomem *regs;
 162         struct npe *npe;
 163         struct net_device *netdev;
 164         struct napi_struct napi;
 165         struct phy_device *phydev;
 166         struct eth_plat_info *plat;
 167         buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
 168         struct desc *desc_tab;  /* coherent */
 169         u32 desc_tab_phys;
 170         int id;                 /* logical port ID */
 171         int speed, duplex;
 172         u8 firmware[4];
 173 };
 174
 175 /* NPE message structure */
 176 struct msg {
 177 #ifdef __ARMEB__
 178         u8 cmd, eth_id, byte2, byte3;
 179         u8 byte4, byte5, byte6, byte7;
 180 #else
 181         u8 byte3, byte2, eth_id, cmd;
 182         u8 byte7, byte6, byte5, byte4;
 183 #endif
 184 };
 185
 186 /* Ethernet packet descriptor */
 187 struct desc {
 188         u32 next;               /* pointer to next buffer, unused */
 189
 190 #ifdef __ARMEB__
 191         u16 buf_len;            /* buffer length */
 192         u16 pkt_len;            /* packet length */
 193         u32 data;               /* pointer to data buffer in RAM */
 194         u8 dest_id;
 195         u8 src_id;
 196         u16 flags;
 197         u8 qos;
 198         u8 padlen;
 199         u16 vlan_tci;
 200 #else
 201         u16 pkt_len;            /* packet length */
 202         u16 buf_len;            /* buffer length */
 203         u32 data;               /* pointer to data buffer in RAM */
 204         u16 flags;
 205         u8 src_id;
 206         u8 dest_id;
 207         u16 vlan_tci;
 208         u8 padlen;
 209         u8 qos;
 210 #endif
 211
 212 #ifdef __ARMEB__
 213         u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
 214         u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
 215         u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
 216 #else
 217         u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
 218         u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
 219         u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
 220 #endif
 221 };
 222
 223
 224 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 225                                  (n) * sizeof(struct desc))
 226 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
 227
 228 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 229                                  ((n) + RX_DESCS) * sizeof(struct desc))
 230 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
 231
 232 #ifndef __ARMEB__
 233 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
 234 {
 235         int i;
 236         for (i = 0; i < cnt; i++)
 237                 dest[i] = swab32(src[i]);
 238 }
 239 #endif
 240
 241 static spinlock_t mdio_lock;
 242 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
 243 struct mii_bus *mdio_bus;
 244 static int ports_open;
 245 static struct port *npe_port_tab[MAX_NPES];
 246 static struct dma_pool *dma_pool;
 247
 248
 249 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
 250                            int write, u16 cmd)
 251 {
 252         int cycles = 0;
 253
 254         if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
 255                 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
 256                 return -1;
 257         }
 258
 259         if (write) {
 260                 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
 261                 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
 262         }
 263         __raw_writel(((phy_id << 5) | location) & 0xFF,
 264                      &mdio_regs->mdio_command[2]);
 265         __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
 266                      &mdio_regs->mdio_command[3]);
 267
 268         while ((cycles < MAX_MDIO_RETRIES) &&
 269                (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
 270                 udelay(1);
 271                 cycles++;
 272         }
 273
 274         if (cycles == MAX_MDIO_RETRIES) {
 275                 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
 276                        phy_id);
 277                 return -1;
 278         }
 279
 280 #if DEBUG_MDIO
 281         printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
 282                phy_id, write ? "write" : "read", cycles);
 283 #endif
 284
 285         if (write)
 286                 return 0;
 287
 288         if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
 289 #if DEBUG_MDIO
 290                 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
 291                        phy_id);
 292 #endif
 293                 return 0xFFFF; /* don't return error */
 294         }
 295
 296         return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
 297                 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
 298 }
 299
 300 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
 301 {
 302         unsigned long flags;
 303         int ret;
 304
 305         spin_lock_irqsave(&mdio_lock, flags);
 306         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
 307         spin_unlock_irqrestore(&mdio_lock, flags);
 308 #if DEBUG_MDIO
 309         printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
 310                phy_id, location, ret);
 311 #endif
 312         return ret;
 313 }
 314
 315 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
 316                              u16 val)
 317 {
 318         unsigned long flags;
 319         int ret;
 320
 321         spin_lock_irqsave(&mdio_lock, flags);
 322         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
 323         spin_unlock_irqrestore(&mdio_lock, flags);
 324 #if DEBUG_MDIO
 325         printk(KERN_DEBUG "%s #%i: MII read [%i] <- 0x%X, err = %i\n",
 326                bus->name, phy_id, location, val, ret);
 327 #endif
 328         return ret;
 329 }
 330
 331 static int ixp4xx_mdio_register(void)
 332 {
 333         int err;
 334
 335         if (!(mdio_bus = mdiobus_alloc()))
 336                 return -ENOMEM;
 337
 338         if (cpu_is_ixp43x()) {
 339                 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
 340                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
 341                         return -ENODEV;
 342                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
 343         } else {
 344                 /* All MII PHY accesses use NPE-B Ethernet registers */
 345                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
 346                         return -ENODEV;
 347                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
 348         }
 349
 350         __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
 351         spin_lock_init(&mdio_lock);
 352         mdio_bus->name = "IXP4xx MII Bus";
 353         mdio_bus->read = &ixp4xx_mdio_read;
 354         mdio_bus->write = &ixp4xx_mdio_write;
 355         strcpy(mdio_bus->id, "0");
 356
 357         if ((err = mdiobus_register(mdio_bus)))
 358                 mdiobus_free(mdio_bus);
 359         return err;
 360 }
 361
 362 static void ixp4xx_mdio_remove(void)
 363 {
 364         mdiobus_unregister(mdio_bus);
 365         mdiobus_free(mdio_bus);
 366 }
 367
 368
 369 static void ixp4xx_adjust_link(struct net_device *dev)
 370 {
 371         struct port *port = netdev_priv(dev);
 372         struct phy_device *phydev = port->phydev;
 373
 374         if (!phydev->link) {
 375                 if (port->speed) {
 376                         port->speed = 0;
 377                         printk(KERN_INFO "%s: link down\n", dev->name);
 378                 }
 379                 return;
 380         }
 381
 382         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
 383                 return;
 384
 385         port->speed = phydev->speed;
 386         port->duplex = phydev->duplex;
 387
 388         if (port->duplex)
 389                 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
 390                              &port->regs->tx_control[0]);
 391         else
 392                 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
 393                              &port->regs->tx_control[0]);
 394
 395         printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
 396                dev->name, port->speed, port->duplex ? "full" : "half");
 397 }
 398
 399
 400 static inline void debug_pkt(struct net_device *dev, const char *func,
 401                              u8 *data, int len)
 402 {
 403 #if DEBUG_PKT_BYTES
 404         int i;
 405
 406         printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
 407         for (i = 0; i < len; i++) {
 408                 if (i >= DEBUG_PKT_BYTES)
 409                         break;
 410                 printk("%s%02X",
 411                        ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
 412                        data[i]);
 413         }
 414         printk("\n");
 415 #endif
 416 }
 417
 418
 419 static inline void debug_desc(u32 phys, struct desc *desc)
 420 {
 421 #if DEBUG_DESC
 422         printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
 423                " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
 424                phys, desc->next, desc->buf_len, desc->pkt_len,
 425                desc->data, desc->dest_id, desc->src_id, desc->flags,
 426                desc->qos, desc->padlen, desc->vlan_tci,
 427                desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
 428                desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
 429                desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
 430                desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
 431 #endif
 432 }
 433
 434 static inline int queue_get_desc(unsigned int queue, struct port *port,
 435                                  int is_tx)
 436 {
 437         u32 phys, tab_phys, n_desc;
 438         struct desc *tab;
 439
 440         if (!(phys = qmgr_get_entry(queue)))
 441                 return -1;
 442
 443         phys &= ~0x1F; /* mask out non-address bits */
 444         tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
 445         tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
 446         n_desc = (phys - tab_phys) / sizeof(struct desc);
 447         BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
 448         debug_desc(phys, &tab[n_desc]);
 449         BUG_ON(tab[n_desc].next);
 450         return n_desc;
 451 }
 452
 453 static inline void queue_put_desc(unsigned int queue, u32 phys,
 454                                   struct desc *desc)
 455 {
 456         debug_desc(phys, desc);
 457         BUG_ON(phys & 0x1F);
 458         qmgr_put_entry(queue, phys);
 459         BUG_ON(qmgr_stat_overflow(queue));
 460 }
 461
 462
 463 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
 464 {
 465 #ifdef __ARMEB__
 466         dma_unmap_single(&port->netdev->dev, desc->data,
 467                          desc->buf_len, DMA_TO_DEVICE);
 468 #else
 469         dma_unmap_single(&port->netdev->dev, desc->data & ~3,
 470                          ALIGN((desc->data & 3) + desc->buf_len, 4),
 471                          DMA_TO_DEVICE);
 472 #endif
 473 }
 474
 475
 476 static void eth_rx_irq(void *pdev)
 477 {
 478         struct net_device *dev = pdev;
 479         struct port *port = netdev_priv(dev);
 480
 481 #if DEBUG_RX
 482         printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
 483 #endif
 484         qmgr_disable_irq(port->plat->rxq);
 485         napi_schedule(&port->napi);
 486 }
 487
 488 static int eth_poll(struct napi_struct *napi, int budget)
 489 {
 490         struct port *port = container_of(napi, struct port, napi);
 491         struct net_device *dev = port->netdev;
 492         unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
 493         int received = 0;
 494
 495 #if DEBUG_RX
 496         printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
 497 #endif
 498
 499         while (received < budget) {
 500                 struct sk_buff *skb;
 501                 struct desc *desc;
 502                 int n;
 503 #ifdef __ARMEB__
 504                 struct sk_buff *temp;
 505                 u32 phys;
 506 #endif
 507
 508                 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
 509 #if DEBUG_RX
 510                         printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
 511                                dev->name);
 512 #endif
 513                         napi_complete(napi);
 514                         qmgr_enable_irq(rxq);
 515                         if (!qmgr_stat_empty(rxq) &&
 516                             napi_reschedule(napi)) {
 517 #if DEBUG_RX
 518                                 printk(KERN_DEBUG "%s: eth_poll"
 519                                        " napi_reschedule successed\n",
 520                                        dev->name);
 521 #endif
 522                                 qmgr_disable_irq(rxq);
 523                                 continue;
 524                         }
 525 #if DEBUG_RX
 526                         printk(KERN_DEBUG "%s: eth_poll all done\n",
 527                                dev->name);
 528 #endif
 529                         return received; /* all work done */
 530                 }
 531
 532                 desc = rx_desc_ptr(port, n);
 533
 534 #ifdef __ARMEB__
 535                 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
 536                         phys = dma_map_single(&dev->dev, skb->data,
 537                                               RX_BUFF_SIZE, DMA_FROM_DEVICE);
 538                         if (dma_mapping_error(&dev->dev, phys)) {
 539                                 dev_kfree_skb(skb);
 540                                 skb = NULL;
 541                         }
 542                 }
 543 #else
 544                 skb = netdev_alloc_skb(dev,
 545                                        ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
 546 #endif
 547
 548                 if (!skb) {
 549                         dev->stats.rx_dropped++;
 550                         /* put the desc back on RX-ready queue */
 551                         desc->buf_len = MAX_MRU;
 552                         desc->pkt_len = 0;
 553                         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 554                         continue;
 555                 }
 556
 557                 /* process received frame */
 558 #ifdef __ARMEB__
 559                 temp = skb;
 560                 skb = port->rx_buff_tab[n];
 561                 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
 562                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
 563 #else
 564                 dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN,
 565                                 RX_BUFF_SIZE, DMA_FROM_DEVICE);
 566                 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
 567                               ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
 568 #endif
 569                 skb_reserve(skb, NET_IP_ALIGN);
 570                 skb_put(skb, desc->pkt_len);
 571
 572                 debug_pkt(dev, "eth_poll", skb->data, skb->len);
 573
 574                 skb->protocol = eth_type_trans(skb, dev);
 575                 dev->stats.rx_packets++;
 576                 dev->stats.rx_bytes += skb->len;
 577                 netif_receive_skb(skb);
 578
 579                 /* put the new buffer on RX-free queue */
 580 #ifdef __ARMEB__
 581                 port->rx_buff_tab[n] = temp;
 582                 desc->data = phys + NET_IP_ALIGN;
 583 #endif
 584                 desc->buf_len = MAX_MRU;
 585                 desc->pkt_len = 0;
 586                 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 587                 received++;
 588         }
 589
 590 #if DEBUG_RX
 591         printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
 592 #endif
 593         return received;                /* not all work done */
 594 }
 595
 596
 597 static void eth_txdone_irq(void *unused)
 598 {
 599         u32 phys;
 600
 601 #if DEBUG_TX
 602         printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
 603 #endif
 604         while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
 605                 u32 npe_id, n_desc;
 606                 struct port *port;
 607                 struct desc *desc;
 608                 int start;
 609
 610                 npe_id = phys & 3;
 611                 BUG_ON(npe_id >= MAX_NPES);
 612                 port = npe_port_tab[npe_id];
 613                 BUG_ON(!port);
 614                 phys &= ~0x1F; /* mask out non-address bits */
 615                 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
 616                 BUG_ON(n_desc >= TX_DESCS);
 617                 desc = tx_desc_ptr(port, n_desc);
 618                 debug_desc(phys, desc);
 619
 620                 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
 621                         port->netdev->stats.tx_packets++;
 622                         port->netdev->stats.tx_bytes += desc->pkt_len;
 623
 624                         dma_unmap_tx(port, desc);
 625 #if DEBUG_TX
 626                         printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
 627                                port->netdev->name, port->tx_buff_tab[n_desc]);
 628 #endif
 629                         free_buffer_irq(port->tx_buff_tab[n_desc]);
 630                         port->tx_buff_tab[n_desc] = NULL;
 631                 }
 632
 633                 start = qmgr_stat_empty(port->plat->txreadyq);
 634                 queue_put_desc(port->plat->txreadyq, phys, desc);
 635                 if (start) {
 636 #if DEBUG_TX
 637                         printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
 638                                port->netdev->name);
 639 #endif
 640                         netif_wake_queue(port->netdev);
 641                 }
 642         }
 643 }
 644
 645 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 646 {
 647         struct port *port = netdev_priv(dev);
 648         unsigned int txreadyq = port->plat->txreadyq;
 649         int len, offset, bytes, n;
 650         void *mem;
 651         u32 phys;
 652         struct desc *desc;
 653
 654 #if DEBUG_TX
 655         printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
 656 #endif
 657
 658         if (unlikely(skb->len > MAX_MRU)) {
 659                 dev_kfree_skb(skb);
 660                 dev->stats.tx_errors++;
 661                 return NETDEV_TX_OK;
 662         }
 663
 664         debug_pkt(dev, "eth_xmit", skb->data, skb->len);
 665
 666         len = skb->len;
 667 #ifdef __ARMEB__
 668         offset = 0; /* no need to keep alignment */
 669         bytes = len;
 670         mem = skb->data;
 671 #else
 672         offset = (int)skb->data & 3; /* keep 32-bit alignment */
 673         bytes = ALIGN(offset + len, 4);
 674         if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
 675                 dev_kfree_skb(skb);
 676                 dev->stats.tx_dropped++;
 677                 return NETDEV_TX_OK;
 678         }
 679         memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
 680         dev_kfree_skb(skb);
 681 #endif
 682
 683         phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
 684         if (dma_mapping_error(&dev->dev, phys)) {
 685 #ifdef __ARMEB__
 686                 dev_kfree_skb(skb);
 687 #else
 688                 kfree(mem);
 689 #endif
 690                 dev->stats.tx_dropped++;
 691                 return NETDEV_TX_OK;
 692         }
 693
 694         n = queue_get_desc(txreadyq, port, 1);
 695         BUG_ON(n < 0);
 696         desc = tx_desc_ptr(port, n);
 697
 698 #ifdef __ARMEB__
 699         port->tx_buff_tab[n] = skb;
 700 #else
 701         port->tx_buff_tab[n] = mem;
 702 #endif
 703         desc->data = phys + offset;
 704         desc->buf_len = desc->pkt_len = len;
 705
 706         /* NPE firmware pads short frames with zeros internally */
 707         wmb();
 708         queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
 709         dev->trans_start = jiffies;
 710
 711         if (qmgr_stat_empty(txreadyq)) {
 712 #if DEBUG_TX
 713                 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
 714 #endif
 715                 netif_stop_queue(dev);
 716                 /* we could miss TX ready interrupt */
 717                 if (!qmgr_stat_empty(txreadyq)) {
 718 #if DEBUG_TX
 719                         printk(KERN_DEBUG "%s: eth_xmit ready again\n",
 720                                dev->name);
 721 #endif
 722                         netif_wake_queue(dev);
 723                 }
 724         }
 725
 726 #if DEBUG_TX
 727         printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
 728 #endif
 729         return NETDEV_TX_OK;
 730 }
 731
 732
 733 static void eth_set_mcast_list(struct net_device *dev)
 734 {
 735         struct port *port = netdev_priv(dev);
 736         struct dev_mc_list *mclist = dev->mc_list;
 737         u8 diffs[ETH_ALEN], *addr;
 738         int cnt = dev->mc_count, i;
 739
 740         if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
 741                 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
 742                              &port->regs->rx_control[0]);
 743                 return;
 744         }
 745
 746         memset(diffs, 0, ETH_ALEN);
 747         addr = mclist->dmi_addr; /* first MAC address */
 748
 749         while (--cnt && (mclist = mclist->next))
 750                 for (i = 0; i < ETH_ALEN; i++)
 751                         diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
 752
 753         for (i = 0; i < ETH_ALEN; i++) {
 754                 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
 755                 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
 756         }
 757
 758         __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 759                      &port->regs->rx_control[0]);
 760 }
 761
 762
 763 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 764 {
 765         struct port *port = netdev_priv(dev);
 766
 767         if (!netif_running(dev))
 768                 return -EINVAL;
 769         return phy_mii_ioctl(port->phydev, if_mii(req), cmd);
 770 }
 771
 772 /* ethtool support */
 773
 774 static void ixp4xx_get_drvinfo(struct net_device *dev,
 775                                struct ethtool_drvinfo *info)
 776 {
 777         struct port *port = netdev_priv(dev);
 778         strcpy(info->driver, DRV_NAME);
 779         snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
 780                  port->firmware[0], port->firmware[1],
 781                  port->firmware[2], port->firmware[3]);
 782         strcpy(info->bus_info, "internal");
 783 }
 784
 785 static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 786 {
 787         struct port *port = netdev_priv(dev);
 788         return phy_ethtool_gset(port->phydev, cmd);
 789 }
 790
 791 static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 792 {
 793         struct port *port = netdev_priv(dev);
 794         return phy_ethtool_sset(port->phydev, cmd);
 795 }
 796
 797 static int ixp4xx_nway_reset(struct net_device *dev)
 798 {
 799         struct port *port = netdev_priv(dev);
 800         return phy_start_aneg(port->phydev);
 801 }
 802
 803 static struct ethtool_ops ixp4xx_ethtool_ops = {
 804         .get_drvinfo = ixp4xx_get_drvinfo,
 805         .get_settings = ixp4xx_get_settings,
 806         .set_settings = ixp4xx_set_settings,
 807         .nway_reset = ixp4xx_nway_reset,
 808         .get_link = ethtool_op_get_link,
 809 };
 810
 811
 812 static int request_queues(struct port *port)
 813 {
 814         int err;
 815
 816         err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
 817                             "%s:RX-free", port->netdev->name);
 818         if (err)
 819                 return err;
 820
 821         err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
 822                             "%s:RX", port->netdev->name);
 823         if (err)
 824                 goto rel_rxfree;
 825
 826         err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
 827                             "%s:TX", port->netdev->name);
 828         if (err)
 829                 goto rel_rx;
 830
 831         err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
 832                             "%s:TX-ready", port->netdev->name);
 833         if (err)
 834                 goto rel_tx;
 835
 836         /* TX-done queue handles skbs sent out by the NPEs */
 837         if (!ports_open) {
 838                 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
 839                                     "%s:TX-done", DRV_NAME);
 840                 if (err)
 841                         goto rel_txready;
 842         }
 843         return 0;
 844
 845 rel_txready:
 846         qmgr_release_queue(port->plat->txreadyq);
 847 rel_tx:
 848         qmgr_release_queue(TX_QUEUE(port->id));
 849 rel_rx:
 850         qmgr_release_queue(port->plat->rxq);
 851 rel_rxfree:
 852         qmgr_release_queue(RXFREE_QUEUE(port->id));
 853         printk(KERN_DEBUG "%s: unable to request hardware queues\n",
 854                port->netdev->name);
 855         return err;
 856 }
 857
 858 static void release_queues(struct port *port)
 859 {
 860         qmgr_release_queue(RXFREE_QUEUE(port->id));
 861         qmgr_release_queue(port->plat->rxq);
 862         qmgr_release_queue(TX_QUEUE(port->id));
 863         qmgr_release_queue(port->plat->txreadyq);
 864
 865         if (!ports_open)
 866                 qmgr_release_queue(TXDONE_QUEUE);
 867 }
 868
 869 static int init_queues(struct port *port)
 870 {
 871         int i;
 872
 873         if (!ports_open)
 874                 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
 875                                                  POOL_ALLOC_SIZE, 32, 0)))
 876                         return -ENOMEM;
 877
 878         if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
 879                                               &port->desc_tab_phys)))
 880                 return -ENOMEM;
 881         memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
 882         memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
 883         memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
 884
 885         /* Setup RX buffers */
 886         for (i = 0; i < RX_DESCS; i++) {
 887                 struct desc *desc = rx_desc_ptr(port, i);
 888                 buffer_t *buff; /* skb or kmalloc()ated memory */
 889                 void *data;
 890 #ifdef __ARMEB__
 891                 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
 892                         return -ENOMEM;
 893                 data = buff->data;
 894 #else
 895                 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
 896                         return -ENOMEM;
 897                 data = buff;
 898 #endif
 899                 desc->buf_len = MAX_MRU;
 900                 desc->data = dma_map_single(&port->netdev->dev, data,
 901                                             RX_BUFF_SIZE, DMA_FROM_DEVICE);
 902                 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
 903                         free_buffer(buff);
 904                         return -EIO;
 905                 }
 906                 desc->data += NET_IP_ALIGN;
 907                 port->rx_buff_tab[i] = buff;
 908         }
 909
 910         return 0;
 911 }
 912
 913 static void destroy_queues(struct port *port)
 914 {
 915         int i;
 916
 917         if (port->desc_tab) {
 918                 for (i = 0; i < RX_DESCS; i++) {
 919                         struct desc *desc = rx_desc_ptr(port, i);
 920                         buffer_t *buff = port->rx_buff_tab[i];
 921                         if (buff) {
 922                                 dma_unmap_single(&port->netdev->dev,
 923                                                  desc->data - NET_IP_ALIGN,
 924                                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
 925                                 free_buffer(buff);
 926                         }
 927                 }
 928                 for (i = 0; i < TX_DESCS; i++) {
 929                         struct desc *desc = tx_desc_ptr(port, i);
 930                         buffer_t *buff = port->tx_buff_tab[i];
 931                         if (buff) {
 932                                 dma_unmap_tx(port, desc);
 933                                 free_buffer(buff);
 934                         }
 935                 }
 936                 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
 937                 port->desc_tab = NULL;
 938         }
 939
 940         if (!ports_open && dma_pool) {
 941                 dma_pool_destroy(dma_pool);
 942                 dma_pool = NULL;
 943         }
 944 }
 945
 946 static int eth_open(struct net_device *dev)
 947 {
 948         struct port *port = netdev_priv(dev);
 949         struct npe *npe = port->npe;
 950         struct msg msg;
 951         int i, err;
 952
 953         if (!npe_running(npe)) {
 954                 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
 955                 if (err)
 956                         return err;
 957
 958                 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
 959                         printk(KERN_ERR "%s: %s not responding\n", dev->name,
 960                                npe_name(npe));
 961                         return -EIO;
 962                 }
 963                 port->firmware[0] = msg.byte4;
 964                 port->firmware[1] = msg.byte5;
 965                 port->firmware[2] = msg.byte6;
 966                 port->firmware[3] = msg.byte7;
 967         }
 968
 969         memset(&msg, 0, sizeof(msg));
 970         msg.cmd = NPE_VLAN_SETRXQOSENTRY;
 971         msg.eth_id = port->id;
 972         msg.byte5 = port->plat->rxq | 0x80;
 973         msg.byte7 = port->plat->rxq << 4;
 974         for (i = 0; i < 8; i++) {
 975                 msg.byte3 = i;
 976                 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
 977                         return -EIO;
 978         }
 979
 980         msg.cmd = NPE_EDB_SETPORTADDRESS;
 981         msg.eth_id = PHYSICAL_ID(port->id);
 982         msg.byte2 = dev->dev_addr[0];
 983         msg.byte3 = dev->dev_addr[1];
 984         msg.byte4 = dev->dev_addr[2];
 985         msg.byte5 = dev->dev_addr[3];
 986         msg.byte6 = dev->dev_addr[4];
 987         msg.byte7 = dev->dev_addr[5];
 988         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
 989                 return -EIO;
 990
 991         memset(&msg, 0, sizeof(msg));
 992         msg.cmd = NPE_FW_SETFIREWALLMODE;
 993         msg.eth_id = port->id;
 994         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
 995                 return -EIO;
 996
 997         if ((err = request_queues(port)) != 0)
 998                 return err;
 999
1000         if ((err = init_queues(port)) != 0) {
1001                 destroy_queues(port);
1002                 release_queues(port);
1003                 return err;
1004         }
1005
1006         port->speed = 0;        /* force "link up" message */
1007         phy_start(port->phydev);
1008
1009         for (i = 0; i < ETH_ALEN; i++)
1010                 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1011         __raw_writel(0x08, &port->regs->random_seed);
1012         __raw_writel(0x12, &port->regs->partial_empty_threshold);
1013         __raw_writel(0x30, &port->regs->partial_full_threshold);
1014         __raw_writel(0x08, &port->regs->tx_start_bytes);
1015         __raw_writel(0x15, &port->regs->tx_deferral);
1016         __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1017         __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1018         __raw_writel(0x80, &port->regs->slot_time);
1019         __raw_writel(0x01, &port->regs->int_clock_threshold);
1020
1021         /* Populate queues with buffers, no failure after this point */
1022         for (i = 0; i < TX_DESCS; i++)
1023                 queue_put_desc(port->plat->txreadyq,
1024                                tx_desc_phys(port, i), tx_desc_ptr(port, i));
1025
1026         for (i = 0; i < RX_DESCS; i++)
1027                 queue_put_desc(RXFREE_QUEUE(port->id),
1028                                rx_desc_phys(port, i), rx_desc_ptr(port, i));
1029
1030         __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1031         __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1032         __raw_writel(0, &port->regs->rx_control[1]);
1033         __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1034
1035         napi_enable(&port->napi);
1036         eth_set_mcast_list(dev);
1037         netif_start_queue(dev);
1038
1039         qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1040                      eth_rx_irq, dev);
1041         if (!ports_open) {
1042                 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1043                              eth_txdone_irq, NULL);
1044                 qmgr_enable_irq(TXDONE_QUEUE);
1045         }
1046         ports_open++;
1047         /* we may already have RX data, enables IRQ */
1048         napi_schedule(&port->napi);
1049         return 0;
1050 }
1051
1052 static int eth_close(struct net_device *dev)
1053 {
1054         struct port *port = netdev_priv(dev);
1055         struct msg msg;
1056         int buffs = RX_DESCS; /* allocated RX buffers */
1057         int i;
1058
1059         ports_open--;
1060         qmgr_disable_irq(port->plat->rxq);
1061         napi_disable(&port->napi);
1062         netif_stop_queue(dev);
1063
1064         while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1065                 buffs--;
1066
1067         memset(&msg, 0, sizeof(msg));
1068         msg.cmd = NPE_SETLOOPBACK_MODE;
1069         msg.eth_id = port->id;
1070         msg.byte3 = 1;
1071         if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1072                 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1073
1074         i = 0;
1075         do {                    /* drain RX buffers */
1076                 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1077                         buffs--;
1078                 if (!buffs)
1079                         break;
1080                 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1081                         /* we have to inject some packet */
1082                         struct desc *desc;
1083                         u32 phys;
1084                         int n = queue_get_desc(port->plat->txreadyq, port, 1);
1085                         BUG_ON(n < 0);
1086                         desc = tx_desc_ptr(port, n);
1087                         phys = tx_desc_phys(port, n);
1088                         desc->buf_len = desc->pkt_len = 1;
1089                         wmb();
1090                         queue_put_desc(TX_QUEUE(port->id), phys, desc);
1091                 }
1092                 udelay(1);
1093         } while (++i < MAX_CLOSE_WAIT);
1094
1095         if (buffs)
1096                 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1097                        " left in NPE\n", dev->name, buffs);
1098 #if DEBUG_CLOSE
1099         if (!buffs)
1100                 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1101 #endif
1102
1103         buffs = TX_DESCS;
1104         while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1105                 buffs--; /* cancel TX */
1106
1107         i = 0;
1108         do {
1109                 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1110                         buffs--;
1111                 if (!buffs)
1112                         break;
1113         } while (++i < MAX_CLOSE_WAIT);
1114
1115         if (buffs)
1116                 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1117                        "left in NPE\n", dev->name, buffs);
1118 #if DEBUG_CLOSE
1119         if (!buffs)
1120                 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1121 #endif
1122
1123         msg.byte3 = 0;
1124         if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1125                 printk(KERN_CRIT "%s: unable to disable loopback\n",
1126                        dev->name);
1127
1128         phy_stop(port->phydev);
1129
1130         if (!ports_open)
1131                 qmgr_disable_irq(TXDONE_QUEUE);
1132         destroy_queues(port);
1133         release_queues(port);
1134         return 0;
1135 }
1136
1137 static const struct net_device_ops ixp4xx_netdev_ops = {
1138         .ndo_open = eth_open,
1139         .ndo_stop = eth_close,
1140         .ndo_start_xmit = eth_xmit,
1141         .ndo_set_multicast_list = eth_set_mcast_list,
1142         .ndo_do_ioctl = eth_ioctl,
1143
1144 };
1145
1146 static int __devinit eth_init_one(struct platform_device *pdev)
1147 {
1148         struct port *port;
1149         struct net_device *dev;
1150         struct eth_plat_info *plat = pdev->dev.platform_data;
1151         u32 regs_phys;
1152         char phy_id[BUS_ID_SIZE];
1153         int err;
1154
1155         if (!(dev = alloc_etherdev(sizeof(struct port))))
1156                 return -ENOMEM;
1157
1158         SET_NETDEV_DEV(dev, &pdev->dev);
1159         port = netdev_priv(dev);
1160         port->netdev = dev;
1161         port->id = pdev->id;
1162
1163         switch (port->id) {
1164         case IXP4XX_ETH_NPEA:
1165                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1166                 regs_phys  = IXP4XX_EthA_BASE_PHYS;
1167                 break;
1168         case IXP4XX_ETH_NPEB:
1169                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1170                 regs_phys  = IXP4XX_EthB_BASE_PHYS;
1171                 break;
1172         case IXP4XX_ETH_NPEC:
1173                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1174                 regs_phys  = IXP4XX_EthC_BASE_PHYS;
1175                 break;
1176         default:
1177                 err = -ENODEV;
1178                 goto err_free;
1179         }
1180
1181         dev->netdev_ops = &ixp4xx_netdev_ops;
1182         dev->ethtool_ops = &ixp4xx_ethtool_ops;
1183         dev->tx_queue_len = 100;
1184
1185         netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1186
1187         if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1188                 err = -EIO;
1189                 goto err_free;
1190         }
1191
1192         port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1193         if (!port->mem_res) {
1194                 err = -EBUSY;
1195                 goto err_npe_rel;
1196         }
1197
1198         port->plat = plat;
1199         npe_port_tab[NPE_ID(port->id)] = port;
1200         memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1201
1202         platform_set_drvdata(pdev, dev);
1203
1204         __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1205                      &port->regs->core_control);
1206         udelay(50);
1207         __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1208         udelay(50);
1209
1210         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, "0", plat->phy);
1211         port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
1212                                    PHY_INTERFACE_MODE_MII);
1213         if ((err = IS_ERR(port->phydev)))
1214                 goto err_free_mem;
1215
1216         port->phydev->irq = PHY_POLL;
1217
1218         if ((err = register_netdev(dev)))
1219                 goto err_phy_dis;
1220
1221         printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1222                npe_name(port->npe));
1223
1224         return 0;
1225
1226 err_phy_dis:
1227         phy_disconnect(port->phydev);
1228 err_free_mem:
1229         npe_port_tab[NPE_ID(port->id)] = NULL;
1230         platform_set_drvdata(pdev, NULL);
1231         release_resource(port->mem_res);
1232 err_npe_rel:
1233         npe_release(port->npe);
1234 err_free:
1235         free_netdev(dev);
1236         return err;
1237 }
1238
1239 static int __devexit eth_remove_one(struct platform_device *pdev)
1240 {
1241         struct net_device *dev = platform_get_drvdata(pdev);
1242         struct port *port = netdev_priv(dev);
1243
1244         unregister_netdev(dev);
1245         phy_disconnect(port->phydev);
1246         npe_port_tab[NPE_ID(port->id)] = NULL;
1247         platform_set_drvdata(pdev, NULL);
1248         npe_release(port->npe);
1249         release_resource(port->mem_res);
1250         free_netdev(dev);
1251         return 0;
1252 }
1253
1254 static struct platform_driver ixp4xx_eth_driver = {
1255         .driver.name    = DRV_NAME,
1256         .probe          = eth_init_one,
1257         .remove         = eth_remove_one,
1258 };
1259
1260 static int __init eth_init_module(void)
1261 {
1262         int err;
1263         if ((err = ixp4xx_mdio_register()))
1264                 return err;
1265         return platform_driver_register(&ixp4xx_eth_driver);
1266 }
1267
1268 static void __exit eth_cleanup_module(void)
1269 {
1270         platform_driver_unregister(&ixp4xx_eth_driver);
1271         ixp4xx_mdio_remove();
1272 }
1273
1274 MODULE_AUTHOR("Krzysztof Halasa");
1275 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1276 MODULE_LICENSE("GPL v2");
1277 MODULE_ALIAS("platform:ixp4xx_eth");
1278 module_init(eth_init_module);
1279 module_exit(eth_cleanup_module);