2 * Intel PCH/PCU SPI flash driver.
4 * Copyright (C) 2016, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/sizes.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/mtd/spi-nor.h>
21 #include <linux/platform_data/intel-spi.h>
23 #include "intel-spi.h"
25 /* Offsets are from @ispi->base */
28 #define HSFSTS_CTL 0x04
29 #define HSFSTS_CTL_FSMIE BIT(31)
30 #define HSFSTS_CTL_FDBC_SHIFT 24
31 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
33 #define HSFSTS_CTL_FCYCLE_SHIFT 17
34 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
35 /* HW sequencer opcodes */
36 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
37 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
38 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
39 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
40 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
41 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
42 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
44 #define HSFSTS_CTL_FGO BIT(16)
45 #define HSFSTS_CTL_FLOCKDN BIT(15)
46 #define HSFSTS_CTL_FDV BIT(14)
47 #define HSFSTS_CTL_SCIP BIT(5)
48 #define HSFSTS_CTL_AEL BIT(2)
49 #define HSFSTS_CTL_FCERR BIT(1)
50 #define HSFSTS_CTL_FDONE BIT(0)
54 #define FDATA(n) (0x10 + ((n) * 4))
58 #define FREG(n) (0x54 + ((n) * 4))
59 #define FREG_BASE_MASK 0x3fff
60 #define FREG_LIMIT_SHIFT 16
61 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
63 /* Offset is from @ispi->pregs */
64 #define PR(n) ((n) * 4)
65 #define PR_WPE BIT(31)
66 #define PR_LIMIT_SHIFT 16
67 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
68 #define PR_RPE BIT(15)
69 #define PR_BASE_MASK 0x3fff
71 /* Offsets are from @ispi->sregs */
72 #define SSFSTS_CTL 0x00
73 #define SSFSTS_CTL_FSMIE BIT(23)
74 #define SSFSTS_CTL_DS BIT(22)
75 #define SSFSTS_CTL_DBC_SHIFT 16
76 #define SSFSTS_CTL_SPOP BIT(11)
77 #define SSFSTS_CTL_ACS BIT(10)
78 #define SSFSTS_CTL_SCGO BIT(9)
79 #define SSFSTS_CTL_COP_SHIFT 12
80 #define SSFSTS_CTL_FRS BIT(7)
81 #define SSFSTS_CTL_DOFRS BIT(6)
82 #define SSFSTS_CTL_AEL BIT(4)
83 #define SSFSTS_CTL_FCERR BIT(3)
84 #define SSFSTS_CTL_FDONE BIT(2)
85 #define SSFSTS_CTL_SCIP BIT(0)
87 #define PREOP_OPTYPE 0x04
91 #define OPTYPE_READ_NO_ADDR 0
92 #define OPTYPE_WRITE_NO_ADDR 1
93 #define OPTYPE_READ_WITH_ADDR 2
94 #define OPTYPE_WRITE_WITH_ADDR 3
98 #define BYT_SSFSTS_CTL 0x90
100 #define BYT_BCR_WPD BIT(0)
101 #define BYT_FREG_NUM 5
105 #define LPT_SSFSTS_CTL 0x90
106 #define LPT_FREG_NUM 5
110 #define BXT_SSFSTS_CTL 0xa0
111 #define BXT_FREG_NUM 12
116 #define ERASE_OPCODE_SHIFT 8
117 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
118 #define ERASE_64K_OPCODE_SHIFT 16
119 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
121 #define INTEL_SPI_TIMEOUT 5000 /* ms */
122 #define INTEL_SPI_FIFO_SZ 64
125 * struct intel_spi - Driver private data
126 * @dev: Device pointer
127 * @info: Pointer to board specific info
128 * @nor: SPI NOR layer structure
129 * @base: Beginning of MMIO space
130 * @pregs: Start of protection registers
131 * @sregs: Start of software sequencer registers
132 * @nregions: Maximum number of regions
133 * @pr_num: Maximum number of protected range registers
134 * @writeable: Is the chip writeable
135 * @locked: Is SPI setting locked
136 * @swseq_reg: Use SW sequencer in register reads/writes
137 * @swseq_erase: Use SW sequencer in erase operation
138 * @erase_64k: 64k erase supported
139 * @opcodes: Opcodes which are supported. This are programmed by BIOS
140 * before it locks down the controller.
144 const struct intel_spi_boardinfo *info;
159 static bool writeable;
160 module_param(writeable, bool, 0);
161 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
163 static void intel_spi_dump_regs(struct intel_spi *ispi)
168 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
170 value = readl(ispi->base + HSFSTS_CTL);
171 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
172 if (value & HSFSTS_CTL_FLOCKDN)
173 dev_dbg(ispi->dev, "-> Locked\n");
175 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
176 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
178 for (i = 0; i < 16; i++)
179 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
180 i, readl(ispi->base + FDATA(i)));
182 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
184 for (i = 0; i < ispi->nregions; i++)
185 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
186 readl(ispi->base + FREG(i)));
187 for (i = 0; i < ispi->pr_num; i++)
188 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
189 readl(ispi->pregs + PR(i)));
191 value = readl(ispi->sregs + SSFSTS_CTL);
192 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
193 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
194 readl(ispi->sregs + PREOP_OPTYPE));
195 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0));
196 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1));
198 if (ispi->info->type == INTEL_SPI_BYT)
199 dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
201 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
202 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
204 dev_dbg(ispi->dev, "Protected regions:\n");
205 for (i = 0; i < ispi->pr_num; i++) {
208 value = readl(ispi->pregs + PR(i));
209 if (!(value & (PR_WPE | PR_RPE)))
212 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
213 base = value & PR_BASE_MASK;
215 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
216 i, base << 12, (limit << 12) | 0xfff,
217 value & PR_WPE ? 'W' : '.',
218 value & PR_RPE ? 'R' : '.');
221 dev_dbg(ispi->dev, "Flash regions:\n");
222 for (i = 0; i < ispi->nregions; i++) {
223 u32 region, base, limit;
225 region = readl(ispi->base + FREG(i));
226 base = region & FREG_BASE_MASK;
227 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
229 if (base >= limit || (i > 0 && limit == 0))
230 dev_dbg(ispi->dev, " %02d disabled\n", i);
232 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
233 i, base << 12, (limit << 12) | 0xfff);
236 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
237 ispi->swseq_reg ? 'S' : 'H');
238 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
239 ispi->swseq_erase ? 'S' : 'H');
242 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
243 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
248 if (size > INTEL_SPI_FIFO_SZ)
252 bytes = min_t(size_t, size, 4);
253 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
262 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
263 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
269 if (size > INTEL_SPI_FIFO_SZ)
273 bytes = min_t(size_t, size, 4);
274 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
283 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
287 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
288 !(val & HSFSTS_CTL_SCIP), 0,
289 INTEL_SPI_TIMEOUT * 1000);
292 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
296 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
297 !(val & SSFSTS_CTL_SCIP), 0,
298 INTEL_SPI_TIMEOUT * 1000);
301 static int intel_spi_init(struct intel_spi *ispi)
303 u32 opmenu0, opmenu1, lvscc, uvscc, val;
306 switch (ispi->info->type) {
308 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
309 ispi->pregs = ispi->base + BYT_PR;
310 ispi->nregions = BYT_FREG_NUM;
311 ispi->pr_num = BYT_PR_NUM;
312 ispi->swseq_reg = true;
315 /* Disable write protection */
316 val = readl(ispi->base + BYT_BCR);
317 if (!(val & BYT_BCR_WPD)) {
319 writel(val, ispi->base + BYT_BCR);
320 val = readl(ispi->base + BYT_BCR);
323 ispi->writeable = !!(val & BYT_BCR_WPD);
329 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
330 ispi->pregs = ispi->base + LPT_PR;
331 ispi->nregions = LPT_FREG_NUM;
332 ispi->pr_num = LPT_PR_NUM;
333 ispi->swseq_reg = true;
337 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
338 ispi->pregs = ispi->base + BXT_PR;
339 ispi->nregions = BXT_FREG_NUM;
340 ispi->pr_num = BXT_PR_NUM;
341 ispi->erase_64k = true;
348 /* Disable #SMI generation from HW sequencer */
349 val = readl(ispi->base + HSFSTS_CTL);
350 val &= ~HSFSTS_CTL_FSMIE;
351 writel(val, ispi->base + HSFSTS_CTL);
354 * Determine whether erase operation should use HW or SW sequencer.
356 * The HW sequencer has a predefined list of opcodes, with only the
357 * erase opcode being programmable in LVSCC and UVSCC registers.
358 * If these registers don't contain a valid erase opcode, erase
359 * cannot be done using HW sequencer.
361 lvscc = readl(ispi->base + LVSCC);
362 uvscc = readl(ispi->base + UVSCC);
363 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))
364 ispi->swseq_erase = true;
365 /* SPI controller on Intel BXT supports 64K erase opcode */
366 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
367 if (!(lvscc & ERASE_64K_OPCODE_MASK) ||
368 !(uvscc & ERASE_64K_OPCODE_MASK))
369 ispi->erase_64k = false;
372 * Some controllers can only do basic operations using hardware
373 * sequencer. All other operations are supposed to be carried out
374 * using software sequencer.
376 if (ispi->swseq_reg) {
377 /* Disable #SMI generation from SW sequencer */
378 val = readl(ispi->sregs + SSFSTS_CTL);
379 val &= ~SSFSTS_CTL_FSMIE;
380 writel(val, ispi->sregs + SSFSTS_CTL);
383 /* Check controller's lock status */
384 val = readl(ispi->base + HSFSTS_CTL);
385 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
389 * BIOS programs allowed opcodes and then locks down the
390 * register. So read back what opcodes it decided to support.
391 * That's the set we are going to support as well.
393 opmenu0 = readl(ispi->sregs + OPMENU0);
394 opmenu1 = readl(ispi->sregs + OPMENU1);
396 if (opmenu0 && opmenu1) {
397 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
398 ispi->opcodes[i] = opmenu0 >> i * 8;
399 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
404 intel_spi_dump_regs(ispi);
409 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
415 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
416 if (ispi->opcodes[i] == opcode)
422 /* The lock is off, so just use index 0 */
423 writel(opcode, ispi->sregs + OPMENU0);
424 preop = readw(ispi->sregs + PREOP_OPTYPE);
425 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
430 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)
435 val = readl(ispi->base + HSFSTS_CTL);
436 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
440 val |= HSFSTS_CTL_FCYCLE_RDID;
443 val |= HSFSTS_CTL_FCYCLE_WRSR;
446 val |= HSFSTS_CTL_FCYCLE_RDSR;
452 if (len > INTEL_SPI_FIFO_SZ)
455 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
456 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
457 val |= HSFSTS_CTL_FGO;
458 writel(val, ispi->base + HSFSTS_CTL);
460 ret = intel_spi_wait_hw_busy(ispi);
464 status = readl(ispi->base + HSFSTS_CTL);
465 if (status & HSFSTS_CTL_FCERR)
467 else if (status & HSFSTS_CTL_AEL)
473 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
480 ret = intel_spi_opcode_index(ispi, opcode, optype);
484 if (len > INTEL_SPI_FIFO_SZ)
487 /* Only mark 'Data Cycle' bit when there is data to be transferred */
489 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
490 val |= ret << SSFSTS_CTL_COP_SHIFT;
491 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
492 val |= SSFSTS_CTL_SCGO;
493 preop = readw(ispi->sregs + PREOP_OPTYPE);
495 val |= SSFSTS_CTL_ACS;
497 val |= SSFSTS_CTL_SPOP;
499 writel(val, ispi->sregs + SSFSTS_CTL);
501 ret = intel_spi_wait_sw_busy(ispi);
505 status = readl(ispi->sregs + SSFSTS_CTL);
506 if (status & SSFSTS_CTL_FCERR)
508 else if (status & SSFSTS_CTL_AEL)
514 static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
516 struct intel_spi *ispi = nor->priv;
519 /* Address of the first chip */
520 writel(0, ispi->base + FADDR);
523 ret = intel_spi_sw_cycle(ispi, opcode, len,
524 OPTYPE_READ_NO_ADDR);
526 ret = intel_spi_hw_cycle(ispi, opcode, len);
531 return intel_spi_read_block(ispi, buf, len);
534 static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
536 struct intel_spi *ispi = nor->priv;
540 * This is handled with atomic operation and preop code in Intel
541 * controller so skip it here now. If the controller is not locked,
542 * program the opcode to the PREOP register for later use.
544 if (opcode == SPINOR_OP_WREN) {
546 writel(opcode, ispi->sregs + PREOP_OPTYPE);
551 writel(0, ispi->base + FADDR);
553 /* Write the value beforehand */
554 ret = intel_spi_write_block(ispi, buf, len);
559 return intel_spi_sw_cycle(ispi, opcode, len,
560 OPTYPE_WRITE_NO_ADDR);
561 return intel_spi_hw_cycle(ispi, opcode, len);
564 static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
567 struct intel_spi *ispi = nor->priv;
568 size_t block_size, retlen = 0;
572 switch (nor->read_opcode) {
574 case SPINOR_OP_READ_FAST:
581 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
583 writel(from, ispi->base + FADDR);
585 val = readl(ispi->base + HSFSTS_CTL);
586 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
587 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
588 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
589 val |= HSFSTS_CTL_FCYCLE_READ;
590 val |= HSFSTS_CTL_FGO;
591 writel(val, ispi->base + HSFSTS_CTL);
593 ret = intel_spi_wait_hw_busy(ispi);
597 status = readl(ispi->base + HSFSTS_CTL);
598 if (status & HSFSTS_CTL_FCERR)
600 else if (status & HSFSTS_CTL_AEL)
604 dev_err(ispi->dev, "read error: %llx: %#x\n", from,
609 ret = intel_spi_read_block(ispi, read_buf, block_size);
615 retlen += block_size;
616 read_buf += block_size;
622 static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
623 const u_char *write_buf)
625 struct intel_spi *ispi = nor->priv;
626 size_t block_size, retlen = 0;
631 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
633 writel(to, ispi->base + FADDR);
635 val = readl(ispi->base + HSFSTS_CTL);
636 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
637 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
638 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
639 val |= HSFSTS_CTL_FCYCLE_WRITE;
641 ret = intel_spi_write_block(ispi, write_buf, block_size);
643 dev_err(ispi->dev, "failed to write block\n");
647 /* Start the write now */
648 val |= HSFSTS_CTL_FGO;
649 writel(val, ispi->base + HSFSTS_CTL);
651 ret = intel_spi_wait_hw_busy(ispi);
653 dev_err(ispi->dev, "timeout\n");
657 status = readl(ispi->base + HSFSTS_CTL);
658 if (status & HSFSTS_CTL_FCERR)
660 else if (status & HSFSTS_CTL_AEL)
664 dev_err(ispi->dev, "write error: %llx: %#x\n", to,
671 retlen += block_size;
672 write_buf += block_size;
678 static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
680 size_t erase_size, len = nor->mtd.erasesize;
681 struct intel_spi *ispi = nor->priv;
682 u32 val, status, cmd;
685 /* If the hardware can do 64k erase use that when possible */
686 if (len >= SZ_64K && ispi->erase_64k) {
687 cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
690 cmd = HSFSTS_CTL_FCYCLE_ERASE;
694 if (ispi->swseq_erase) {
696 writel(offs, ispi->base + FADDR);
698 ret = intel_spi_sw_cycle(ispi, nor->erase_opcode,
699 0, OPTYPE_WRITE_WITH_ADDR);
711 writel(offs, ispi->base + FADDR);
713 val = readl(ispi->base + HSFSTS_CTL);
714 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
715 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
717 val |= HSFSTS_CTL_FGO;
718 writel(val, ispi->base + HSFSTS_CTL);
720 ret = intel_spi_wait_hw_busy(ispi);
724 status = readl(ispi->base + HSFSTS_CTL);
725 if (status & HSFSTS_CTL_FCERR)
727 else if (status & HSFSTS_CTL_AEL)
737 static bool intel_spi_is_protected(const struct intel_spi *ispi,
738 unsigned int base, unsigned int limit)
742 for (i = 0; i < ispi->pr_num; i++) {
743 u32 pr_base, pr_limit, pr_value;
745 pr_value = readl(ispi->pregs + PR(i));
746 if (!(pr_value & (PR_WPE | PR_RPE)))
749 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
750 pr_base = pr_value & PR_BASE_MASK;
752 if (pr_base >= base && pr_limit <= limit)
760 * There will be a single partition holding all enabled flash regions. We
763 static void intel_spi_fill_partition(struct intel_spi *ispi,
764 struct mtd_partition *part)
769 memset(part, 0, sizeof(*part));
771 /* Start from the mandatory descriptor region */
776 * Now try to find where this partition ends based on the flash
779 for (i = 1; i < ispi->nregions; i++) {
780 u32 region, base, limit;
782 region = readl(ispi->base + FREG(i));
783 base = region & FREG_BASE_MASK;
784 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
786 if (base >= limit || limit == 0)
790 * If any of the regions have protection bits set, make the
791 * whole partition read-only to be on the safe side.
793 if (intel_spi_is_protected(ispi, base, limit))
794 ispi->writeable = false;
796 end = (limit << 12) + 4096;
797 if (end > part->size)
802 struct intel_spi *intel_spi_probe(struct device *dev,
803 struct resource *mem, const struct intel_spi_boardinfo *info)
805 const struct spi_nor_hwcaps hwcaps = {
806 .mask = SNOR_HWCAPS_READ |
807 SNOR_HWCAPS_READ_FAST |
810 struct mtd_partition part;
811 struct intel_spi *ispi;
815 return ERR_PTR(-EINVAL);
817 ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
819 return ERR_PTR(-ENOMEM);
821 ispi->base = devm_ioremap_resource(dev, mem);
822 if (IS_ERR(ispi->base))
823 return ERR_CAST(ispi->base);
827 ispi->writeable = info->writeable;
829 ret = intel_spi_init(ispi);
833 ispi->nor.dev = ispi->dev;
834 ispi->nor.priv = ispi;
835 ispi->nor.read_reg = intel_spi_read_reg;
836 ispi->nor.write_reg = intel_spi_write_reg;
837 ispi->nor.read = intel_spi_read;
838 ispi->nor.write = intel_spi_write;
839 ispi->nor.erase = intel_spi_erase;
841 ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
843 dev_info(dev, "failed to locate the chip\n");
847 intel_spi_fill_partition(ispi, &part);
849 /* Prevent writes if not explicitly enabled */
850 if (!ispi->writeable || !writeable)
851 ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
853 ret = mtd_device_parse_register(&ispi->nor.mtd, NULL, NULL, &part, 1);
859 EXPORT_SYMBOL_GPL(intel_spi_probe);
861 int intel_spi_remove(struct intel_spi *ispi)
863 return mtd_device_unregister(&ispi->nor.mtd);
865 EXPORT_SYMBOL_GPL(intel_spi_remove);
867 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
868 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
869 MODULE_LICENSE("GPL v2");