drivers/mtd/spi-nor/cadence-quadspi.c

   1 /*
   2  * Driver for Cadence QSPI Controller
   3  *
   4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/partitions.h>
  30 #include <linux/mtd/spi-nor.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/sched.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/timer.h>
  37
  38 #define CQSPI_NAME                      "cadence-qspi"
  39 #define CQSPI_MAX_CHIPSELECT            16
  40
  41 struct cqspi_st;
  42
  43 struct cqspi_flash_pdata {
  44         struct spi_nor  nor;
  45         struct cqspi_st *cqspi;
  46         u32             clk_rate;
  47         u32             read_delay;
  48         u32             tshsl_ns;
  49         u32             tsd2d_ns;
  50         u32             tchsh_ns;
  51         u32             tslch_ns;
  52         u8              inst_width;
  53         u8              addr_width;
  54         u8              data_width;
  55         u8              cs;
  56         bool            registered;
  57 };
  58
  59 struct cqspi_st {
  60         struct platform_device  *pdev;
  61
  62         struct clk              *clk;
  63         unsigned int            sclk;
  64
  65         void __iomem            *iobase;
  66         void __iomem            *ahb_base;
  67         struct completion       transfer_complete;
  68         struct mutex            bus_mutex;
  69
  70         int                     current_cs;
  71         int                     current_page_size;
  72         int                     current_erase_size;
  73         int                     current_addr_width;
  74         unsigned long           master_ref_clk_hz;
  75         bool                    is_decoded_cs;
  76         u32                     fifo_depth;
  77         u32                     fifo_width;
  78         u32                     trigger_address;
  79         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  80 };
  81
  82 /* Operation timeout value */
  83 #define CQSPI_TIMEOUT_MS                        500
  84 #define CQSPI_READ_TIMEOUT_MS                   10
  85
  86 /* Instruction type */
  87 #define CQSPI_INST_TYPE_SINGLE                  0
  88 #define CQSPI_INST_TYPE_DUAL                    1
  89 #define CQSPI_INST_TYPE_QUAD                    2
  90
  91 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  92 #define CQSPI_DUMMY_BYTES_MAX                   4
  93 #define CQSPI_DUMMY_CLKS_MAX                    31
  94
  95 #define CQSPI_STIG_DATA_LEN_MAX                 8
  96
  97 /* Register map */
  98 #define CQSPI_REG_CONFIG                        0x00
  99 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 100 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 101 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 102 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 103 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 104 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 105 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 106 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 107
 108 #define CQSPI_REG_RD_INSTR                      0x04
 109 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 110 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 111 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 112 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 113 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 114 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 115 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 116 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 117 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 118 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 119
 120 #define CQSPI_REG_WR_INSTR                      0x08
 121 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 122 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 123 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 124
 125 #define CQSPI_REG_DELAY                         0x0C
 126 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 127 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 128 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 129 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 130 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 131 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 132 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 133 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 134
 135 #define CQSPI_REG_READCAPTURE                   0x10
 136 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 137 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 138 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 139
 140 #define CQSPI_REG_SIZE                          0x14
 141 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 142 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 143 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 144 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 145 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 146 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 147
 148 #define CQSPI_REG_SRAMPARTITION                 0x18
 149 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 150
 151 #define CQSPI_REG_DMA                           0x20
 152 #define CQSPI_REG_DMA_SINGLE_LSB                0
 153 #define CQSPI_REG_DMA_BURST_LSB                 8
 154 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 155 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 156
 157 #define CQSPI_REG_REMAP                         0x24
 158 #define CQSPI_REG_MODE_BIT                      0x28
 159
 160 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 161 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 162 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 163 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 164 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 165
 166 #define CQSPI_REG_IRQSTATUS                     0x40
 167 #define CQSPI_REG_IRQMASK                       0x44
 168
 169 #define CQSPI_REG_INDIRECTRD                    0x60
 170 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 171 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 172 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 173
 174 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 175 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 176 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 177
 178 #define CQSPI_REG_CMDCTRL                       0x90
 179 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 180 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 181 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 182 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 183 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 184 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 185 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 186 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 187 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 188 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 189 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 190 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 191
 192 #define CQSPI_REG_INDIRECTWR                    0x70
 193 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 194 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 195 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 196
 197 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 198 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 199 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 200
 201 #define CQSPI_REG_CMDADDRESS                    0x94
 202 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 203 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 204 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 205 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 206
 207 /* Interrupt status bits */
 208 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 209 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 210 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 211 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 212 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 213 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 214 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 215 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 216
 217 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 218                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 219                                          CQSPI_REG_IRQ_IND_COMP)
 220
 221 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 222                                          CQSPI_REG_IRQ_WATERMARK        | \
 223                                          CQSPI_REG_IRQ_UNDERFLOW)
 224
 225 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 226
 227 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 228 {
 229         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 230         u32 val;
 231
 232         while (1) {
 233                 val = readl(reg);
 234                 if (clear)
 235                         val = ~val;
 236                 val &= mask;
 237
 238                 if (val == mask)
 239                         return 0;
 240
 241                 if (time_after(jiffies, end))
 242                         return -ETIMEDOUT;
 243         }
 244 }
 245
 246 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 247 {
 248         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 249
 250         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 251 }
 252
 253 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 254 {
 255         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 256
 257         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 258         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 259 }
 260
 261 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 262 {
 263         struct cqspi_st *cqspi = dev;
 264         unsigned int irq_status;
 265
 266         /* Read interrupt status */
 267         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 268
 269         /* Clear interrupt */
 270         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 271
 272         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 273
 274         if (irq_status)
 275                 complete(&cqspi->transfer_complete);
 276
 277         return IRQ_HANDLED;
 278 }
 279
 280 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 281 {
 282         struct cqspi_flash_pdata *f_pdata = nor->priv;
 283         u32 rdreg = 0;
 284
 285         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 286         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 287         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 288
 289         return rdreg;
 290 }
 291
 292 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 293 {
 294         const unsigned int poll_idle_retry = 3;
 295         unsigned int count = 0;
 296         unsigned long timeout;
 297
 298         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 299         while (1) {
 300                 /*
 301                  * Read few times in succession to ensure the controller
 302                  * is indeed idle, that is, the bit does not transition
 303                  * low again.
 304                  */
 305                 if (cqspi_is_idle(cqspi))
 306                         count++;
 307                 else
 308                         count = 0;
 309
 310                 if (count >= poll_idle_retry)
 311                         return 0;
 312
 313                 if (time_after(jiffies, timeout)) {
 314                         /* Timeout, in busy mode. */
 315                         dev_err(&cqspi->pdev->dev,
 316                                 "QSPI is still busy after %dms timeout.\n",
 317                                 CQSPI_TIMEOUT_MS);
 318                         return -ETIMEDOUT;
 319                 }
 320
 321                 cpu_relax();
 322         }
 323 }
 324
 325 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 326 {
 327         void __iomem *reg_base = cqspi->iobase;
 328         int ret;
 329
 330         /* Write the CMDCTRL without start execution. */
 331         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 332         /* Start execute */
 333         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 334         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 335
 336         /* Polling for completion. */
 337         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 338                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 339         if (ret) {
 340                 dev_err(&cqspi->pdev->dev,
 341                         "Flash command execution timed out.\n");
 342                 return ret;
 343         }
 344
 345         /* Polling QSPI idle status. */
 346         return cqspi_wait_idle(cqspi);
 347 }
 348
 349 static int cqspi_command_read(struct spi_nor *nor,
 350                               const u8 *txbuf, const unsigned n_tx,
 351                               u8 *rxbuf, const unsigned n_rx)
 352 {
 353         struct cqspi_flash_pdata *f_pdata = nor->priv;
 354         struct cqspi_st *cqspi = f_pdata->cqspi;
 355         void __iomem *reg_base = cqspi->iobase;
 356         unsigned int rdreg;
 357         unsigned int reg;
 358         unsigned int read_len;
 359         int status;
 360
 361         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 362                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 363                         n_rx, rxbuf);
 364                 return -EINVAL;
 365         }
 366
 367         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 368
 369         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 370         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 371
 372         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 373
 374         /* 0 means 1 byte. */
 375         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 376                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 377         status = cqspi_exec_flash_cmd(cqspi, reg);
 378         if (status)
 379                 return status;
 380
 381         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 382
 383         /* Put the read value into rx_buf */
 384         read_len = (n_rx > 4) ? 4 : n_rx;
 385         memcpy(rxbuf, &reg, read_len);
 386         rxbuf += read_len;
 387
 388         if (n_rx > 4) {
 389                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 390
 391                 read_len = n_rx - read_len;
 392                 memcpy(rxbuf, &reg, read_len);
 393         }
 394
 395         return 0;
 396 }
 397
 398 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 399                                const u8 *txbuf, const unsigned n_tx)
 400 {
 401         struct cqspi_flash_pdata *f_pdata = nor->priv;
 402         struct cqspi_st *cqspi = f_pdata->cqspi;
 403         void __iomem *reg_base = cqspi->iobase;
 404         unsigned int reg;
 405         unsigned int data;
 406         int ret;
 407
 408         if (n_tx > 4 || (n_tx && !txbuf)) {
 409                 dev_err(nor->dev,
 410                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 411                         n_tx, txbuf);
 412                 return -EINVAL;
 413         }
 414
 415         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 416         if (n_tx) {
 417                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 418                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 419                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 420                 data = 0;
 421                 memcpy(&data, txbuf, n_tx);
 422                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 423         }
 424
 425         ret = cqspi_exec_flash_cmd(cqspi, reg);
 426         return ret;
 427 }
 428
 429 static int cqspi_command_write_addr(struct spi_nor *nor,
 430                                     const u8 opcode, const unsigned int addr)
 431 {
 432         struct cqspi_flash_pdata *f_pdata = nor->priv;
 433         struct cqspi_st *cqspi = f_pdata->cqspi;
 434         void __iomem *reg_base = cqspi->iobase;
 435         unsigned int reg;
 436
 437         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 438         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 439         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 440                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 441
 442         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 443
 444         return cqspi_exec_flash_cmd(cqspi, reg);
 445 }
 446
 447 static int cqspi_indirect_read_setup(struct spi_nor *nor,
 448                                      const unsigned int from_addr)
 449 {
 450         struct cqspi_flash_pdata *f_pdata = nor->priv;
 451         struct cqspi_st *cqspi = f_pdata->cqspi;
 452         void __iomem *reg_base = cqspi->iobase;
 453         unsigned int dummy_clk = 0;
 454         unsigned int reg;
 455
 456         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 457
 458         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 459         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 460
 461         /* Setup dummy clock cycles */
 462         dummy_clk = nor->read_dummy;
 463         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 464                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
 465
 466         if (dummy_clk / 8) {
 467                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 468                 /* Set mode bits high to ensure chip doesn't enter XIP */
 469                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 470
 471                 /* Need to subtract the mode byte (8 clocks). */
 472                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 473                         dummy_clk -= 8;
 474
 475                 if (dummy_clk)
 476                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 477                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 478         }
 479
 480         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 481
 482         /* Set address width */
 483         reg = readl(reg_base + CQSPI_REG_SIZE);
 484         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 485         reg |= (nor->addr_width - 1);
 486         writel(reg, reg_base + CQSPI_REG_SIZE);
 487         return 0;
 488 }
 489
 490 static int cqspi_indirect_read_execute(struct spi_nor *nor,
 491                                        u8 *rxbuf, const unsigned n_rx)
 492 {
 493         struct cqspi_flash_pdata *f_pdata = nor->priv;
 494         struct cqspi_st *cqspi = f_pdata->cqspi;
 495         void __iomem *reg_base = cqspi->iobase;
 496         void __iomem *ahb_base = cqspi->ahb_base;
 497         unsigned int remaining = n_rx;
 498         unsigned int bytes_to_read = 0;
 499         int ret = 0;
 500
 501         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 502
 503         /* Clear all interrupts. */
 504         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 505
 506         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 507
 508         reinit_completion(&cqspi->transfer_complete);
 509         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 510                reg_base + CQSPI_REG_INDIRECTRD);
 511
 512         while (remaining > 0) {
 513                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 514                                                   msecs_to_jiffies
 515                                                   (CQSPI_READ_TIMEOUT_MS));
 516
 517                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 518
 519                 if (!ret && bytes_to_read == 0) {
 520                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 521                         ret = -ETIMEDOUT;
 522                         goto failrd;
 523                 }
 524
 525                 while (bytes_to_read != 0) {
 526                         bytes_to_read *= cqspi->fifo_width;
 527                         bytes_to_read = bytes_to_read > remaining ?
 528                                         remaining : bytes_to_read;
 529                         ioread32_rep(ahb_base, rxbuf,
 530                                      DIV_ROUND_UP(bytes_to_read, 4));
 531                         rxbuf += bytes_to_read;
 532                         remaining -= bytes_to_read;
 533                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 534                 }
 535
 536                 if (remaining > 0)
 537                         reinit_completion(&cqspi->transfer_complete);
 538         }
 539
 540         /* Check indirect done status */
 541         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 542                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 543         if (ret) {
 544                 dev_err(nor->dev,
 545                         "Indirect read completion error (%i)\n", ret);
 546                 goto failrd;
 547         }
 548
 549         /* Disable interrupt */
 550         writel(0, reg_base + CQSPI_REG_IRQMASK);
 551
 552         /* Clear indirect completion status */
 553         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 554
 555         return 0;
 556
 557 failrd:
 558         /* Disable interrupt */
 559         writel(0, reg_base + CQSPI_REG_IRQMASK);
 560
 561         /* Cancel the indirect read */
 562         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 563                reg_base + CQSPI_REG_INDIRECTRD);
 564         return ret;
 565 }
 566
 567 static int cqspi_indirect_write_setup(struct spi_nor *nor,
 568                                       const unsigned int to_addr)
 569 {
 570         unsigned int reg;
 571         struct cqspi_flash_pdata *f_pdata = nor->priv;
 572         struct cqspi_st *cqspi = f_pdata->cqspi;
 573         void __iomem *reg_base = cqspi->iobase;
 574
 575         /* Set opcode. */
 576         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 577         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 578         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 579         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 580
 581         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 582
 583         reg = readl(reg_base + CQSPI_REG_SIZE);
 584         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 585         reg |= (nor->addr_width - 1);
 586         writel(reg, reg_base + CQSPI_REG_SIZE);
 587         return 0;
 588 }
 589
 590 static int cqspi_indirect_write_execute(struct spi_nor *nor,
 591                                         const u8 *txbuf, const unsigned n_tx)
 592 {
 593         const unsigned int page_size = nor->page_size;
 594         struct cqspi_flash_pdata *f_pdata = nor->priv;
 595         struct cqspi_st *cqspi = f_pdata->cqspi;
 596         void __iomem *reg_base = cqspi->iobase;
 597         unsigned int remaining = n_tx;
 598         unsigned int write_bytes;
 599         int ret;
 600
 601         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 602
 603         /* Clear all interrupts. */
 604         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 605
 606         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 607
 608         reinit_completion(&cqspi->transfer_complete);
 609         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 610                reg_base + CQSPI_REG_INDIRECTWR);
 611
 612         while (remaining > 0) {
 613                 write_bytes = remaining > page_size ? page_size : remaining;
 614                 iowrite32_rep(cqspi->ahb_base, txbuf,
 615                               DIV_ROUND_UP(write_bytes, 4));
 616
 617                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 618                                                   msecs_to_jiffies
 619                                                   (CQSPI_TIMEOUT_MS));
 620                 if (!ret) {
 621                         dev_err(nor->dev, "Indirect write timeout\n");
 622                         ret = -ETIMEDOUT;
 623                         goto failwr;
 624                 }
 625
 626                 txbuf += write_bytes;
 627                 remaining -= write_bytes;
 628
 629                 if (remaining > 0)
 630                         reinit_completion(&cqspi->transfer_complete);
 631         }
 632
 633         /* Check indirect done status */
 634         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 635                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 636         if (ret) {
 637                 dev_err(nor->dev,
 638                         "Indirect write completion error (%i)\n", ret);
 639                 goto failwr;
 640         }
 641
 642         /* Disable interrupt. */
 643         writel(0, reg_base + CQSPI_REG_IRQMASK);
 644
 645         /* Clear indirect completion status */
 646         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 647
 648         cqspi_wait_idle(cqspi);
 649
 650         return 0;
 651
 652 failwr:
 653         /* Disable interrupt. */
 654         writel(0, reg_base + CQSPI_REG_IRQMASK);
 655
 656         /* Cancel the indirect write */
 657         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 658                reg_base + CQSPI_REG_INDIRECTWR);
 659         return ret;
 660 }
 661
 662 static void cqspi_chipselect(struct spi_nor *nor)
 663 {
 664         struct cqspi_flash_pdata *f_pdata = nor->priv;
 665         struct cqspi_st *cqspi = f_pdata->cqspi;
 666         void __iomem *reg_base = cqspi->iobase;
 667         unsigned int chip_select = f_pdata->cs;
 668         unsigned int reg;
 669
 670         reg = readl(reg_base + CQSPI_REG_CONFIG);
 671         if (cqspi->is_decoded_cs) {
 672                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 673         } else {
 674                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 675
 676                 /* Convert CS if without decoder.
 677                  * CS0 to 4b'1110
 678                  * CS1 to 4b'1101
 679                  * CS2 to 4b'1011
 680                  * CS3 to 4b'0111
 681                  */
 682                 chip_select = 0xF & ~(1 << chip_select);
 683         }
 684
 685         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 686                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 687         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 688             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 689         writel(reg, reg_base + CQSPI_REG_CONFIG);
 690 }
 691
 692 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 693 {
 694         struct cqspi_flash_pdata *f_pdata = nor->priv;
 695         struct cqspi_st *cqspi = f_pdata->cqspi;
 696         void __iomem *iobase = cqspi->iobase;
 697         unsigned int reg;
 698
 699         /* configure page size and block size. */
 700         reg = readl(iobase + CQSPI_REG_SIZE);
 701         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 702         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 703         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 704         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 705         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 706         reg |= (nor->addr_width - 1);
 707         writel(reg, iobase + CQSPI_REG_SIZE);
 708
 709         /* configure the chip select */
 710         cqspi_chipselect(nor);
 711
 712         /* Store the new configuration of the controller */
 713         cqspi->current_page_size = nor->page_size;
 714         cqspi->current_erase_size = nor->mtd.erasesize;
 715         cqspi->current_addr_width = nor->addr_width;
 716 }
 717
 718 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 719                                            const unsigned int ns_val)
 720 {
 721         unsigned int ticks;
 722
 723         ticks = ref_clk_hz / 1000;      /* kHz */
 724         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 725
 726         return ticks;
 727 }
 728
 729 static void cqspi_delay(struct spi_nor *nor)
 730 {
 731         struct cqspi_flash_pdata *f_pdata = nor->priv;
 732         struct cqspi_st *cqspi = f_pdata->cqspi;
 733         void __iomem *iobase = cqspi->iobase;
 734         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 735         unsigned int tshsl, tchsh, tslch, tsd2d;
 736         unsigned int reg;
 737         unsigned int tsclk;
 738
 739         /* calculate the number of ref ticks for one sclk tick */
 740         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 741
 742         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 743         /* this particular value must be at least one sclk */
 744         if (tshsl < tsclk)
 745                 tshsl = tsclk;
 746
 747         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 748         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 749         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 750
 751         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 752                << CQSPI_REG_DELAY_TSHSL_LSB;
 753         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 754                 << CQSPI_REG_DELAY_TCHSH_LSB;
 755         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 756                 << CQSPI_REG_DELAY_TSLCH_LSB;
 757         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 758                 << CQSPI_REG_DELAY_TSD2D_LSB;
 759         writel(reg, iobase + CQSPI_REG_DELAY);
 760 }
 761
 762 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 763 {
 764         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 765         void __iomem *reg_base = cqspi->iobase;
 766         u32 reg, div;
 767
 768         /* Recalculate the baudrate divisor based on QSPI specification. */
 769         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 770
 771         reg = readl(reg_base + CQSPI_REG_CONFIG);
 772         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 773         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 774         writel(reg, reg_base + CQSPI_REG_CONFIG);
 775 }
 776
 777 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 778                                    const unsigned int bypass,
 779                                    const unsigned int delay)
 780 {
 781         void __iomem *reg_base = cqspi->iobase;
 782         unsigned int reg;
 783
 784         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 785
 786         if (bypass)
 787                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 788         else
 789                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 790
 791         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 792                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 793
 794         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 795                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 796
 797         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 798 }
 799
 800 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 801 {
 802         void __iomem *reg_base = cqspi->iobase;
 803         unsigned int reg;
 804
 805         reg = readl(reg_base + CQSPI_REG_CONFIG);
 806
 807         if (enable)
 808                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 809         else
 810                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 811
 812         writel(reg, reg_base + CQSPI_REG_CONFIG);
 813 }
 814
 815 static void cqspi_configure(struct spi_nor *nor)
 816 {
 817         struct cqspi_flash_pdata *f_pdata = nor->priv;
 818         struct cqspi_st *cqspi = f_pdata->cqspi;
 819         const unsigned int sclk = f_pdata->clk_rate;
 820         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 821         int switch_ck = (cqspi->sclk != sclk);
 822
 823         if ((cqspi->current_page_size != nor->page_size) ||
 824             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 825             (cqspi->current_addr_width != nor->addr_width))
 826                 switch_cs = 1;
 827
 828         if (switch_cs || switch_ck)
 829                 cqspi_controller_enable(cqspi, 0);
 830
 831         /* Switch chip select. */
 832         if (switch_cs) {
 833                 cqspi->current_cs = f_pdata->cs;
 834                 cqspi_configure_cs_and_sizes(nor);
 835         }
 836
 837         /* Setup baudrate divisor and delays */
 838         if (switch_ck) {
 839                 cqspi->sclk = sclk;
 840                 cqspi_config_baudrate_div(cqspi);
 841                 cqspi_delay(nor);
 842                 cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
 843         }
 844
 845         if (switch_cs || switch_ck)
 846                 cqspi_controller_enable(cqspi, 1);
 847 }
 848
 849 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 850 {
 851         struct cqspi_flash_pdata *f_pdata = nor->priv;
 852
 853         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 854         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 855         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 856
 857         if (read) {
 858                 switch (nor->read_proto) {
 859                 case SNOR_PROTO_1_1_1:
 860                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 861                         break;
 862                 case SNOR_PROTO_1_1_2:
 863                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 864                         break;
 865                 case SNOR_PROTO_1_1_4:
 866                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 867                         break;
 868                 default:
 869                         return -EINVAL;
 870                 }
 871         }
 872
 873         cqspi_configure(nor);
 874
 875         return 0;
 876 }
 877
 878 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 879                            size_t len, const u_char *buf)
 880 {
 881         int ret;
 882
 883         ret = cqspi_set_protocol(nor, 0);
 884         if (ret)
 885                 return ret;
 886
 887         ret = cqspi_indirect_write_setup(nor, to);
 888         if (ret)
 889                 return ret;
 890
 891         ret = cqspi_indirect_write_execute(nor, buf, len);
 892         if (ret)
 893                 return ret;
 894
 895         return len;
 896 }
 897
 898 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
 899                           size_t len, u_char *buf)
 900 {
 901         int ret;
 902
 903         ret = cqspi_set_protocol(nor, 1);
 904         if (ret)
 905                 return ret;
 906
 907         ret = cqspi_indirect_read_setup(nor, from);
 908         if (ret)
 909                 return ret;
 910
 911         ret = cqspi_indirect_read_execute(nor, buf, len);
 912         if (ret)
 913                 return ret;
 914
 915         return len;
 916 }
 917
 918 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
 919 {
 920         int ret;
 921
 922         ret = cqspi_set_protocol(nor, 0);
 923         if (ret)
 924                 return ret;
 925
 926         /* Send write enable, then erase commands. */
 927         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 928         if (ret)
 929                 return ret;
 930
 931         /* Set up command buffer. */
 932         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
 933         if (ret)
 934                 return ret;
 935
 936         return 0;
 937 }
 938
 939 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
 940 {
 941         struct cqspi_flash_pdata *f_pdata = nor->priv;
 942         struct cqspi_st *cqspi = f_pdata->cqspi;
 943
 944         mutex_lock(&cqspi->bus_mutex);
 945
 946         return 0;
 947 }
 948
 949 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
 950 {
 951         struct cqspi_flash_pdata *f_pdata = nor->priv;
 952         struct cqspi_st *cqspi = f_pdata->cqspi;
 953
 954         mutex_unlock(&cqspi->bus_mutex);
 955 }
 956
 957 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 958 {
 959         int ret;
 960
 961         ret = cqspi_set_protocol(nor, 0);
 962         if (!ret)
 963                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
 964
 965         return ret;
 966 }
 967
 968 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 969 {
 970         int ret;
 971
 972         ret = cqspi_set_protocol(nor, 0);
 973         if (!ret)
 974                 ret = cqspi_command_write(nor, opcode, buf, len);
 975
 976         return ret;
 977 }
 978
 979 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
 980                                     struct cqspi_flash_pdata *f_pdata,
 981                                     struct device_node *np)
 982 {
 983         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
 984                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
 985                 return -ENXIO;
 986         }
 987
 988         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
 989                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
 990                 return -ENXIO;
 991         }
 992
 993         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
 994                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
 995                 return -ENXIO;
 996         }
 997
 998         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
 999                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1000                 return -ENXIO;
1001         }
1002
1003         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1004                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1005                 return -ENXIO;
1006         }
1007
1008         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1009                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1010                 return -ENXIO;
1011         }
1012
1013         return 0;
1014 }
1015
1016 static int cqspi_of_get_pdata(struct platform_device *pdev)
1017 {
1018         struct device_node *np = pdev->dev.of_node;
1019         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1020
1021         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1022
1023         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1024                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1025                 return -ENXIO;
1026         }
1027
1028         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1029                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1030                 return -ENXIO;
1031         }
1032
1033         if (of_property_read_u32(np, "cdns,trigger-address",
1034                                  &cqspi->trigger_address)) {
1035                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1036                 return -ENXIO;
1037         }
1038
1039         return 0;
1040 }
1041
1042 static void cqspi_controller_init(struct cqspi_st *cqspi)
1043 {
1044         cqspi_controller_enable(cqspi, 0);
1045
1046         /* Configure the remap address register, no remap */
1047         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1048
1049         /* Disable all interrupts. */
1050         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1051
1052         /* Configure the SRAM split to 1:1 . */
1053         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1054
1055         /* Load indirect trigger address. */
1056         writel(cqspi->trigger_address,
1057                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1058
1059         /* Program read watermark -- 1/2 of the FIFO. */
1060         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1061                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1062         /* Program write watermark -- 1/8 of the FIFO. */
1063         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1064                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1065
1066         cqspi_controller_enable(cqspi, 1);
1067 }
1068
1069 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1070 {
1071         const struct spi_nor_hwcaps hwcaps = {
1072                 .mask = SNOR_HWCAPS_READ |
1073                         SNOR_HWCAPS_READ_FAST |
1074                         SNOR_HWCAPS_READ_1_1_2 |
1075                         SNOR_HWCAPS_READ_1_1_4 |
1076                         SNOR_HWCAPS_PP,
1077         };
1078         struct platform_device *pdev = cqspi->pdev;
1079         struct device *dev = &pdev->dev;
1080         struct cqspi_flash_pdata *f_pdata;
1081         struct spi_nor *nor;
1082         struct mtd_info *mtd;
1083         unsigned int cs;
1084         int i, ret;
1085
1086         /* Get flash device data */
1087         for_each_available_child_of_node(dev->of_node, np) {
1088                 ret = of_property_read_u32(np, "reg", &cs);
1089                 if (ret) {
1090                         dev_err(dev, "Couldn't determine chip select.\n");
1091                         goto err;
1092                 }
1093
1094                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1095                         ret = -EINVAL;
1096                         dev_err(dev, "Chip select %d out of range.\n", cs);
1097                         goto err;
1098                 }
1099
1100                 f_pdata = &cqspi->f_pdata[cs];
1101                 f_pdata->cqspi = cqspi;
1102                 f_pdata->cs = cs;
1103
1104                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1105                 if (ret)
1106                         goto err;
1107
1108                 nor = &f_pdata->nor;
1109                 mtd = &nor->mtd;
1110
1111                 mtd->priv = nor;
1112
1113                 nor->dev = dev;
1114                 spi_nor_set_flash_node(nor, np);
1115                 nor->priv = f_pdata;
1116
1117                 nor->read_reg = cqspi_read_reg;
1118                 nor->write_reg = cqspi_write_reg;
1119                 nor->read = cqspi_read;
1120                 nor->write = cqspi_write;
1121                 nor->erase = cqspi_erase;
1122                 nor->prepare = cqspi_prep;
1123                 nor->unprepare = cqspi_unprep;
1124
1125                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1126                                            dev_name(dev), cs);
1127                 if (!mtd->name) {
1128                         ret = -ENOMEM;
1129                         goto err;
1130                 }
1131
1132                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1133                 if (ret)
1134                         goto err;
1135
1136                 ret = mtd_device_register(mtd, NULL, 0);
1137                 if (ret)
1138                         goto err;
1139
1140                 f_pdata->registered = true;
1141         }
1142
1143         return 0;
1144
1145 err:
1146         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1147                 if (cqspi->f_pdata[i].registered)
1148                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1149         return ret;
1150 }
1151
1152 static int cqspi_probe(struct platform_device *pdev)
1153 {
1154         struct device_node *np = pdev->dev.of_node;
1155         struct device *dev = &pdev->dev;
1156         struct cqspi_st *cqspi;
1157         struct resource *res;
1158         struct resource *res_ahb;
1159         int ret;
1160         int irq;
1161
1162         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1163         if (!cqspi)
1164                 return -ENOMEM;
1165
1166         mutex_init(&cqspi->bus_mutex);
1167         cqspi->pdev = pdev;
1168         platform_set_drvdata(pdev, cqspi);
1169
1170         /* Obtain configuration from OF. */
1171         ret = cqspi_of_get_pdata(pdev);
1172         if (ret) {
1173                 dev_err(dev, "Cannot get mandatory OF data.\n");
1174                 return -ENODEV;
1175         }
1176
1177         /* Obtain QSPI clock. */
1178         cqspi->clk = devm_clk_get(dev, NULL);
1179         if (IS_ERR(cqspi->clk)) {
1180                 dev_err(dev, "Cannot claim QSPI clock.\n");
1181                 return PTR_ERR(cqspi->clk);
1182         }
1183
1184         /* Obtain and remap controller address. */
1185         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186         cqspi->iobase = devm_ioremap_resource(dev, res);
1187         if (IS_ERR(cqspi->iobase)) {
1188                 dev_err(dev, "Cannot remap controller address.\n");
1189                 return PTR_ERR(cqspi->iobase);
1190         }
1191
1192         /* Obtain and remap AHB address. */
1193         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1194         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1195         if (IS_ERR(cqspi->ahb_base)) {
1196                 dev_err(dev, "Cannot remap AHB address.\n");
1197                 return PTR_ERR(cqspi->ahb_base);
1198         }
1199
1200         init_completion(&cqspi->transfer_complete);
1201
1202         /* Obtain IRQ line. */
1203         irq = platform_get_irq(pdev, 0);
1204         if (irq < 0) {
1205                 dev_err(dev, "Cannot obtain IRQ.\n");
1206                 return -ENXIO;
1207         }
1208
1209         ret = clk_prepare_enable(cqspi->clk);
1210         if (ret) {
1211                 dev_err(dev, "Cannot enable QSPI clock.\n");
1212                 return ret;
1213         }
1214
1215         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1216
1217         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1218                                pdev->name, cqspi);
1219         if (ret) {
1220                 dev_err(dev, "Cannot request IRQ.\n");
1221                 goto probe_irq_failed;
1222         }
1223
1224         cqspi_wait_idle(cqspi);
1225         cqspi_controller_init(cqspi);
1226         cqspi->current_cs = -1;
1227         cqspi->sclk = 0;
1228
1229         ret = cqspi_setup_flash(cqspi, np);
1230         if (ret) {
1231                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1232                 goto probe_setup_failed;
1233         }
1234
1235         return ret;
1236 probe_irq_failed:
1237         cqspi_controller_enable(cqspi, 0);
1238 probe_setup_failed:
1239         clk_disable_unprepare(cqspi->clk);
1240         return ret;
1241 }
1242
1243 static int cqspi_remove(struct platform_device *pdev)
1244 {
1245         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1246         int i;
1247
1248         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1249                 if (cqspi->f_pdata[i].registered)
1250                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1251
1252         cqspi_controller_enable(cqspi, 0);
1253
1254         clk_disable_unprepare(cqspi->clk);
1255
1256         return 0;
1257 }
1258
1259 #ifdef CONFIG_PM_SLEEP
1260 static int cqspi_suspend(struct device *dev)
1261 {
1262         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1263
1264         cqspi_controller_enable(cqspi, 0);
1265         return 0;
1266 }
1267
1268 static int cqspi_resume(struct device *dev)
1269 {
1270         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1271
1272         cqspi_controller_enable(cqspi, 1);
1273         return 0;
1274 }
1275
1276 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1277         .suspend = cqspi_suspend,
1278         .resume = cqspi_resume,
1279 };
1280
1281 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1282 #else
1283 #define CQSPI_DEV_PM_OPS        NULL
1284 #endif
1285
1286 static const struct of_device_id cqspi_dt_ids[] = {
1287         {.compatible = "cdns,qspi-nor",},
1288         { /* end of table */ }
1289 };
1290
1291 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1292
1293 static struct platform_driver cqspi_platform_driver = {
1294         .probe = cqspi_probe,
1295         .remove = cqspi_remove,
1296         .driver = {
1297                 .name = CQSPI_NAME,
1298                 .pm = CQSPI_DEV_PM_OPS,
1299                 .of_match_table = cqspi_dt_ids,
1300         },
1301 };
1302
1303 module_platform_driver(cqspi_platform_driver);
1304
1305 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1306 MODULE_LICENSE("GPL v2");
1307 MODULE_ALIAS("platform:" CQSPI_NAME);
1308 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1309 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");