1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
6 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
8 #include <linux/delay.h>
10 #include <linux/slab.h>
12 #include "gpmi-nand.h"
13 #include "gpmi-regs.h"
16 /* Converts time to clock cycles */
17 #define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
19 #define MXS_SET_ADDR 0x4
20 #define MXS_CLR_ADDR 0x8
22 * Clear the bit and poll it cleared. This is usually called with
23 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
26 static int clear_poll_bit(void __iomem *addr, u32 mask)
31 writel(mask, addr + MXS_CLR_ADDR);
34 * SFTRST needs 3 GPMI clocks to settle, the reference manual
35 * recommends to wait 1us.
39 /* poll the bit becoming clear */
40 while ((readl(addr) & mask) && --timeout)
46 #define MODULE_CLKGATE (1 << 30)
47 #define MODULE_SFTRST (1 << 31)
49 * The current mxs_reset_block() will do two things:
50 * [1] enable the module.
51 * [2] reset the module.
53 * In most of the cases, it's ok.
54 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
55 * If you try to soft reset the BCH block, it becomes unusable until
56 * the next hard reset. This case occurs in the NAND boot mode. When the board
57 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
58 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
59 * You will see a DMA timeout in this case. The bug has been fixed
60 * in the following chips, such as MX28.
62 * To avoid this bug, just add a new parameter `just_enable` for
63 * the mxs_reset_block(), and rewrite it here.
65 static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
70 /* clear and poll SFTRST */
71 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
76 writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
79 /* set SFTRST to reset the block */
80 writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
83 /* poll CLKGATE becoming set */
84 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
86 if (unlikely(!timeout))
90 /* clear and poll SFTRST */
91 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
95 /* clear and poll CLKGATE */
96 ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
103 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
107 static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
113 for (i = 0; i < GPMI_CLK_MAX; i++) {
114 clk = this->resources.clock[i];
119 ret = clk_prepare_enable(clk);
123 clk_disable_unprepare(clk);
130 clk_disable_unprepare(this->resources.clock[i - 1]);
134 int gpmi_enable_clk(struct gpmi_nand_data *this)
136 return __gpmi_enable_clk(this, true);
139 int gpmi_disable_clk(struct gpmi_nand_data *this)
141 return __gpmi_enable_clk(this, false);
144 int gpmi_init(struct gpmi_nand_data *this)
146 struct resources *r = &this->resources;
149 ret = gpmi_enable_clk(this);
152 ret = gpmi_reset_block(r->gpmi_regs, false);
157 * Reset BCH here, too. We got failures otherwise :(
158 * See later BCH reset for explanation of MX23 handling
160 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
164 /* Choose NAND mode. */
165 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
167 /* Set the IRQ polarity. */
168 writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
169 r->gpmi_regs + HW_GPMI_CTRL1_SET);
171 /* Disable Write-Protection. */
172 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
174 /* Select BCH ECC. */
175 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
178 * Decouple the chip select from dma channel. We use dma0 for all
181 writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
183 gpmi_disable_clk(this);
186 gpmi_disable_clk(this);
190 /* This function is very useful. It is called only when the bug occur. */
191 void gpmi_dump_info(struct gpmi_nand_data *this)
193 struct resources *r = &this->resources;
194 struct bch_geometry *geo = &this->bch_geometry;
198 dev_err(this->dev, "Show GPMI registers :\n");
199 for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
200 reg = readl(r->gpmi_regs + i * 0x10);
201 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
204 /* start to print out the BCH info */
205 dev_err(this->dev, "Show BCH registers :\n");
206 for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) {
207 reg = readl(r->bch_regs + i * 0x10);
208 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
210 dev_err(this->dev, "BCH Geometry :\n"
212 "ECC Strength : %u\n"
213 "Page Size in Bytes : %u\n"
214 "Metadata Size in Bytes : %u\n"
215 "ECC Chunk Size in Bytes: %u\n"
216 "ECC Chunk Count : %u\n"
217 "Payload Size in Bytes : %u\n"
218 "Auxiliary Size in Bytes: %u\n"
219 "Auxiliary Status Offset: %u\n"
220 "Block Mark Byte Offset : %u\n"
221 "Block Mark Bit Offset : %u\n",
227 geo->ecc_chunk_count,
230 geo->auxiliary_status_offset,
231 geo->block_mark_byte_offset,
232 geo->block_mark_bit_offset);
235 /* Configures the geometry for BCH. */
236 int bch_set_geometry(struct gpmi_nand_data *this)
238 struct resources *r = &this->resources;
239 struct bch_geometry *bch_geo = &this->bch_geometry;
240 unsigned int block_count;
241 unsigned int block_size;
242 unsigned int metadata_size;
243 unsigned int ecc_strength;
244 unsigned int page_size;
248 ret = common_nfc_set_geometry(this);
252 block_count = bch_geo->ecc_chunk_count - 1;
253 block_size = bch_geo->ecc_chunk_size;
254 metadata_size = bch_geo->metadata_size;
255 ecc_strength = bch_geo->ecc_strength >> 1;
256 page_size = bch_geo->page_size;
257 gf_len = bch_geo->gf_len;
259 ret = gpmi_enable_clk(this);
264 * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
265 * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
266 * On the other hand, the MX28 needs the reset, because one case has been
267 * seen where the BCH produced ECC errors constantly after 10000
268 * consecutive reboots. The latter case has not been seen on the MX23
269 * yet, still we don't know if it could happen there as well.
271 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
275 /* Configure layout 0. */
276 writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
277 | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
278 | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
279 | BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
280 | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
281 r->bch_regs + HW_BCH_FLASH0LAYOUT0);
283 writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
284 | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
285 | BF_BCH_FLASH0LAYOUT1_GF(gf_len, this)
286 | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
287 r->bch_regs + HW_BCH_FLASH0LAYOUT1);
289 /* Set *all* chip selects to use layout 0. */
290 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
292 /* Enable interrupts. */
293 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
294 r->bch_regs + HW_BCH_CTRL_SET);
296 gpmi_disable_clk(this);
299 gpmi_disable_clk(this);
304 * <1> Firstly, we should know what's the GPMI-clock means.
305 * The GPMI-clock is the internal clock in the gpmi nand controller.
306 * If you set 100MHz to gpmi nand controller, the GPMI-clock's period
307 * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
309 * <2> Secondly, we should know what's the frequency on the nand chip pins.
310 * The frequency on the nand chip pins is derived from the GPMI-clock.
311 * We can get it from the following equation:
315 * F : the frequency on the nand chip pins.
316 * G : the GPMI clock, such as 100MHz.
317 * DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
318 * DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
320 * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
321 * the nand EDO(extended Data Out) timing could be applied.
322 * The GPMI implements a feedback read strobe to sample the read data.
323 * The feedback read strobe can be delayed to support the nand EDO timing
324 * where the read strobe may deasserts before the read data is valid, and
325 * read data is valid for some time after read strobe.
327 * The following figure illustrates some aspects of a NAND Flash read:
334 * __ ___|__________________________________
338 * Read Data --------------< >---------
342 * FeedbackRDN ________ ____________
345 * D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
348 * <4> Now, we begin to describe how to compute the right RDN_DELAY.
350 * 4.1) From the aspect of the nand chip pins:
351 * Delay = (tREA + C - tRP) {1}
353 * tREA : the maximum read access time.
354 * C : a constant to adjust the delay. default is 4000ps.
355 * tRP : the read pulse width, which is exactly:
356 * tRP = (GPMI-clock-period) * DATA_SETUP
358 * 4.2) From the aspect of the GPMI nand controller:
359 * Delay = RDN_DELAY * 0.125 * RP {2}
361 * RP : the DLL reference period.
362 * if (GPMI-clock-period > DLL_THRETHOLD)
363 * RP = GPMI-clock-period / 2;
365 * RP = GPMI-clock-period;
367 * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
368 * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
369 * is 16000ps, but in mx6q, we use 12000ps.
371 * 4.3) since {1} equals {2}, we get:
373 * (tREA + 4000 - tRP) * 8
374 * RDN_DELAY = ----------------------- {3}
377 static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
378 const struct nand_sdr_timings *sdr)
380 struct gpmi_nfc_hardware_timing *hw = &this->hw;
381 unsigned int dll_threshold_ps = this->devdata->max_chain_delay;
382 unsigned int period_ps, reference_period_ps;
383 unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles;
385 bool use_half_period;
386 int sample_delay_ps, sample_delay_factor;
387 u16 busy_timeout_cycles;
390 if (sdr->tRC_min >= 30000) {
391 /* ONFI non-EDO modes [0-3] */
392 hw->clk_rate = 22000000;
393 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
394 } else if (sdr->tRC_min >= 25000) {
395 /* ONFI EDO mode 4 */
396 hw->clk_rate = 80000000;
397 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
399 /* ONFI EDO mode 5 */
400 hw->clk_rate = 100000000;
401 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
404 /* SDR core timings are given in picoseconds */
405 period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate);
407 addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps);
408 data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps);
409 data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps);
410 busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps);
412 hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) |
413 BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles) |
414 BF_GPMI_TIMING0_DATA_SETUP(data_setup_cycles);
415 hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(busy_timeout_cycles * 4096);
418 * Derive NFC ideal delay from {3}:
420 * (tREA + 4000 - tRP) * 8
421 * RDN_DELAY = -----------------------
424 if (period_ps > dll_threshold_ps) {
425 use_half_period = true;
426 reference_period_ps = period_ps / 2;
428 use_half_period = false;
429 reference_period_ps = period_ps;
432 tRP_ps = data_setup_cycles * period_ps;
433 sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8;
434 if (sample_delay_ps > 0)
435 sample_delay_factor = sample_delay_ps / reference_period_ps;
437 sample_delay_factor = 0;
439 hw->ctrl1n = BF_GPMI_CTRL1_WRN_DLY_SEL(wrn_dly_sel);
440 if (sample_delay_factor)
441 hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) |
442 BM_GPMI_CTRL1_DLL_ENABLE |
443 (use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0);
446 void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
448 struct gpmi_nfc_hardware_timing *hw = &this->hw;
449 struct resources *r = &this->resources;
450 void __iomem *gpmi_regs = r->gpmi_regs;
451 unsigned int dll_wait_time_us;
453 clk_set_rate(r->clock[0], hw->clk_rate);
455 writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0);
456 writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1);
459 * Clear several CTRL1 fields, DLL must be disabled when setting
460 * RDN_DELAY or HALF_PERIOD.
462 writel(BM_GPMI_CTRL1_CLEAR_MASK, gpmi_regs + HW_GPMI_CTRL1_CLR);
463 writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET);
465 /* Wait 64 clock cycles before using the GPMI after enabling the DLL */
466 dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64;
467 if (!dll_wait_time_us)
468 dll_wait_time_us = 1;
470 /* Wait for the DLL to settle. */
471 udelay(dll_wait_time_us);
474 int gpmi_setup_data_interface(struct nand_chip *chip, int chipnr,
475 const struct nand_data_interface *conf)
477 struct gpmi_nand_data *this = nand_get_controller_data(chip);
478 const struct nand_sdr_timings *sdr;
480 /* Retrieve required NAND timings */
481 sdr = nand_get_sdr_timings(conf);
485 /* Only MX6 GPMI controller can reach EDO timings */
486 if (sdr->tRC_min <= 25000 && !GPMI_IS_MX6(this))
489 /* Stop here if this call was just a check */
493 /* Do the actual derivation of the controller timings */
494 gpmi_nfc_compute_timings(this, sdr);
496 this->hw.must_apply_timings = true;
501 /* Clears a BCH interrupt. */
502 void gpmi_clear_bch(struct gpmi_nand_data *this)
504 struct resources *r = &this->resources;
505 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
508 /* Returns the Ready/Busy status of the given chip. */
509 int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
511 struct resources *r = &this->resources;
515 if (GPMI_IS_MX23(this)) {
516 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
517 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
518 } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6(this)) {
520 * In the imx6, all the ready/busy pins are bound
521 * together. So we only need to check chip 0.
523 if (GPMI_IS_MX6(this))
526 /* MX28 shares the same R/B register as MX6Q. */
527 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
528 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
530 dev_err(this->dev, "unknown arch.\n");
534 int gpmi_send_command(struct gpmi_nand_data *this)
536 struct dma_chan *channel = get_dma_chan(this);
537 struct dma_async_tx_descriptor *desc;
538 struct scatterlist *sgl;
539 int chip = this->current_chip;
543 /* [1] send out the PIO words */
544 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
545 | BM_GPMI_CTRL0_WORD_LENGTH
546 | BF_GPMI_CTRL0_CS(chip, this)
547 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
548 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
549 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
550 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
552 desc = dmaengine_prep_slave_sg(channel,
553 (struct scatterlist *)pio,
554 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
558 /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
559 sgl = &this->cmd_sgl;
561 sg_init_one(sgl, this->cmd_buffer, this->command_length);
562 dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
563 desc = dmaengine_prep_slave_sg(channel,
564 sgl, 1, DMA_MEM_TO_DEV,
565 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
569 /* [3] submit the DMA */
570 ret = start_dma_without_bch_irq(this, desc);
572 dma_unmap_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
577 int gpmi_send_data(struct gpmi_nand_data *this, const void *buf, int len)
579 struct dma_async_tx_descriptor *desc;
580 struct dma_chan *channel = get_dma_chan(this);
581 int chip = this->current_chip;
583 uint32_t command_mode;
588 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
589 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
591 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
592 | BM_GPMI_CTRL0_WORD_LENGTH
593 | BF_GPMI_CTRL0_CS(chip, this)
594 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
595 | BF_GPMI_CTRL0_ADDRESS(address)
596 | BF_GPMI_CTRL0_XFER_COUNT(len);
598 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
599 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
603 /* [2] send DMA request */
604 prepare_data_dma(this, buf, len, DMA_TO_DEVICE);
605 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
607 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
611 /* [3] submit the DMA */
612 ret = start_dma_without_bch_irq(this, desc);
614 dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_TO_DEVICE);
619 int gpmi_read_data(struct gpmi_nand_data *this, void *buf, int len)
621 struct dma_async_tx_descriptor *desc;
622 struct dma_chan *channel = get_dma_chan(this);
623 int chip = this->current_chip;
629 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
630 | BM_GPMI_CTRL0_WORD_LENGTH
631 | BF_GPMI_CTRL0_CS(chip, this)
632 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
633 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
634 | BF_GPMI_CTRL0_XFER_COUNT(len);
636 desc = dmaengine_prep_slave_sg(channel,
637 (struct scatterlist *)pio,
638 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
642 /* [2] : send DMA request */
643 direct = prepare_data_dma(this, buf, len, DMA_FROM_DEVICE);
644 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
646 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
650 /* [3] : submit the DMA */
652 ret = start_dma_without_bch_irq(this, desc);
654 dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_FROM_DEVICE);
656 memcpy(buf, this->data_buffer_dma, len);
661 int gpmi_send_page(struct gpmi_nand_data *this,
662 dma_addr_t payload, dma_addr_t auxiliary)
664 struct bch_geometry *geo = &this->bch_geometry;
665 uint32_t command_mode;
667 uint32_t ecc_command;
668 uint32_t buffer_mask;
669 struct dma_async_tx_descriptor *desc;
670 struct dma_chan *channel = get_dma_chan(this);
671 int chip = this->current_chip;
674 /* A DMA descriptor that does an ECC page read. */
675 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
676 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
677 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
678 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
679 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
681 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
682 | BM_GPMI_CTRL0_WORD_LENGTH
683 | BF_GPMI_CTRL0_CS(chip, this)
684 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
685 | BF_GPMI_CTRL0_ADDRESS(address)
686 | BF_GPMI_CTRL0_XFER_COUNT(0);
688 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
689 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
690 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
691 pio[3] = geo->page_size;
695 desc = dmaengine_prep_slave_sg(channel,
696 (struct scatterlist *)pio,
697 ARRAY_SIZE(pio), DMA_TRANS_NONE,
702 return start_dma_with_bch_irq(this, desc);
705 int gpmi_read_page(struct gpmi_nand_data *this,
706 dma_addr_t payload, dma_addr_t auxiliary)
708 struct bch_geometry *geo = &this->bch_geometry;
709 uint32_t command_mode;
711 uint32_t ecc_command;
712 uint32_t buffer_mask;
713 struct dma_async_tx_descriptor *desc;
714 struct dma_chan *channel = get_dma_chan(this);
715 int chip = this->current_chip;
718 /* [1] Wait for the chip to report ready. */
719 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
720 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
722 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
723 | BM_GPMI_CTRL0_WORD_LENGTH
724 | BF_GPMI_CTRL0_CS(chip, this)
725 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
726 | BF_GPMI_CTRL0_ADDRESS(address)
727 | BF_GPMI_CTRL0_XFER_COUNT(0);
729 desc = dmaengine_prep_slave_sg(channel,
730 (struct scatterlist *)pio, 2,
735 /* [2] Enable the BCH block and read. */
736 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
737 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
738 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
739 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
740 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
742 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
743 | BM_GPMI_CTRL0_WORD_LENGTH
744 | BF_GPMI_CTRL0_CS(chip, this)
745 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
746 | BF_GPMI_CTRL0_ADDRESS(address)
747 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
750 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
751 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
752 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
753 pio[3] = geo->page_size;
756 desc = dmaengine_prep_slave_sg(channel,
757 (struct scatterlist *)pio,
758 ARRAY_SIZE(pio), DMA_TRANS_NONE,
759 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
763 /* [3] Disable the BCH block */
764 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
765 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
767 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
768 | BM_GPMI_CTRL0_WORD_LENGTH
769 | BF_GPMI_CTRL0_CS(chip, this)
770 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
771 | BF_GPMI_CTRL0_ADDRESS(address)
772 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
774 pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
775 desc = dmaengine_prep_slave_sg(channel,
776 (struct scatterlist *)pio, 3,
778 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
782 /* [4] submit the DMA */
783 return start_dma_with_bch_irq(this, desc);
787 * gpmi_copy_bits - copy bits from one memory region to another
788 * @dst: destination buffer
789 * @dst_bit_off: bit offset we're starting to write at
790 * @src: source buffer
791 * @src_bit_off: bit offset we're starting to read from
792 * @nbits: number of bits to copy
794 * This functions copies bits from one memory region to another, and is used by
795 * the GPMI driver to copy ECC sections which are not guaranteed to be byte
798 * src and dst should not overlap.
801 void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
802 const u8 *src, size_t src_bit_off,
808 size_t bits_in_src_buffer = 0;
814 * Move src and dst pointers to the closest byte pointer and store bit
815 * offsets within a byte.
817 src += src_bit_off / 8;
820 dst += dst_bit_off / 8;
824 * Initialize the src_buffer value with bits available in the first
825 * byte of data so that we end up with a byte aligned src pointer.
828 src_buffer = src[0] >> src_bit_off;
829 if (nbits >= (8 - src_bit_off)) {
830 bits_in_src_buffer += 8 - src_bit_off;
832 src_buffer &= GENMASK(nbits - 1, 0);
833 bits_in_src_buffer += nbits;
835 nbits -= bits_in_src_buffer;
839 /* Calculate the number of bytes that can be copied from src to dst. */
842 /* Try to align dst to a byte boundary. */
844 if (bits_in_src_buffer < (8 - dst_bit_off) && nbytes) {
845 src_buffer |= src[0] << bits_in_src_buffer;
846 bits_in_src_buffer += 8;
851 if (bits_in_src_buffer >= (8 - dst_bit_off)) {
852 dst[0] &= GENMASK(dst_bit_off - 1, 0);
853 dst[0] |= src_buffer << dst_bit_off;
854 src_buffer >>= (8 - dst_bit_off);
855 bits_in_src_buffer -= (8 - dst_bit_off);
858 if (bits_in_src_buffer > 7) {
859 bits_in_src_buffer -= 8;
867 if (!bits_in_src_buffer && !dst_bit_off) {
869 * Both src and dst pointers are byte aligned, thus we can
870 * just use the optimized memcpy function.
873 memcpy(dst, src, nbytes);
876 * src buffer is not byte aligned, hence we have to copy each
877 * src byte to the src_buffer variable before extracting a byte
880 for (i = 0; i < nbytes; i++) {
881 src_buffer |= src[i] << bits_in_src_buffer;
886 /* Update dst and src pointers */
891 * nbits is the number of remaining bits. It should not exceed 8 as
892 * we've already copied as much bytes as possible.
897 * If there's no more bits to copy to the destination and src buffer
898 * was already byte aligned, then we're done.
900 if (!nbits && !bits_in_src_buffer)
903 /* Copy the remaining bits to src_buffer */
905 src_buffer |= (*src & GENMASK(nbits - 1, 0)) <<
907 bits_in_src_buffer += nbits;
910 * In case there were not enough bits to get a byte aligned dst buffer
911 * prepare the src_buffer variable to match the dst organization (shift
912 * src_buffer by dst_bit_off and retrieve the least significant bits
916 src_buffer = (src_buffer << dst_bit_off) |
917 (*dst & GENMASK(dst_bit_off - 1, 0));
918 bits_in_src_buffer += dst_bit_off;
921 * Keep most significant bits from dst if we end up with an unaligned
924 nbytes = bits_in_src_buffer / 8;
925 if (bits_in_src_buffer % 8) {
926 src_buffer |= (dst[nbytes] &
927 GENMASK(7, bits_in_src_buffer % 8)) <<
932 /* Copy the remaining bytes to dst */
933 for (i = 0; i < nbytes; i++) {