1 // SPDX-License-Identifier: GPL-2.0
3 * NAND Flash Controller Device Driver for DT
5 * Copyright © 2011, Picochip.
11 #include <linux/ioport.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
21 struct denali_nand_info denali;
22 struct clk *clk; /* core clock */
23 struct clk *clk_x; /* bus interface clock */
24 struct clk *clk_ecc; /* ECC circuit clock */
27 struct denali_dt_data {
28 unsigned int revision;
30 const struct nand_ecc_caps *ecc_caps;
33 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
35 static const struct denali_dt_data denali_socfpga_data = {
36 .caps = DENALI_CAP_HW_ECC_FIXUP,
37 .ecc_caps = &denali_socfpga_ecc_caps,
40 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
42 static const struct denali_dt_data denali_uniphier_v5a_data = {
43 .caps = DENALI_CAP_HW_ECC_FIXUP |
45 .ecc_caps = &denali_uniphier_v5a_ecc_caps,
48 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
50 static const struct denali_dt_data denali_uniphier_v5b_data = {
52 .caps = DENALI_CAP_HW_ECC_FIXUP |
54 .ecc_caps = &denali_uniphier_v5b_ecc_caps,
57 static const struct of_device_id denali_nand_dt_ids[] = {
59 .compatible = "altr,socfpga-denali-nand",
60 .data = &denali_socfpga_data,
63 .compatible = "socionext,uniphier-denali-nand-v5a",
64 .data = &denali_uniphier_v5a_data,
67 .compatible = "socionext,uniphier-denali-nand-v5b",
68 .data = &denali_uniphier_v5b_data,
72 MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
74 static int denali_dt_probe(struct platform_device *pdev)
76 struct device *dev = &pdev->dev;
79 const struct denali_dt_data *data;
80 struct denali_nand_info *denali;
83 dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
88 data = of_device_get_match_data(dev);
90 denali->revision = data->revision;
91 denali->caps = data->caps;
92 denali->ecc_caps = data->ecc_caps;
96 denali->irq = platform_get_irq(pdev, 0);
97 if (denali->irq < 0) {
98 dev_err(dev, "no irq defined\n");
102 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg");
103 denali->reg = devm_ioremap_resource(dev, res);
104 if (IS_ERR(denali->reg))
105 return PTR_ERR(denali->reg);
107 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
108 denali->host = devm_ioremap_resource(dev, res);
109 if (IS_ERR(denali->host))
110 return PTR_ERR(denali->host);
113 * A single anonymous clock is supported for the backward compatibility.
114 * New platforms should support all the named clocks.
116 dt->clk = devm_clk_get(dev, "nand");
118 dt->clk = devm_clk_get(dev, NULL);
119 if (IS_ERR(dt->clk)) {
120 dev_err(dev, "no clk available\n");
121 return PTR_ERR(dt->clk);
124 dt->clk_x = devm_clk_get(dev, "nand_x");
125 if (IS_ERR(dt->clk_x))
128 dt->clk_ecc = devm_clk_get(dev, "ecc");
129 if (IS_ERR(dt->clk_ecc))
132 ret = clk_prepare_enable(dt->clk);
136 ret = clk_prepare_enable(dt->clk_x);
138 goto out_disable_clk;
140 ret = clk_prepare_enable(dt->clk_ecc);
142 goto out_disable_clk_x;
145 denali->clk_rate = clk_get_rate(dt->clk);
146 denali->clk_x_rate = clk_get_rate(dt->clk_x);
149 * Hardcode the clock rates for the backward compatibility.
150 * This works for both SOCFPGA and UniPhier.
153 "necessary clock is missing. default clock rates are used.\n");
154 denali->clk_rate = 50000000;
155 denali->clk_x_rate = 200000000;
158 ret = denali_init(denali);
160 goto out_disable_clk_ecc;
162 platform_set_drvdata(pdev, dt);
166 clk_disable_unprepare(dt->clk_ecc);
168 clk_disable_unprepare(dt->clk_x);
170 clk_disable_unprepare(dt->clk);
175 static int denali_dt_remove(struct platform_device *pdev)
177 struct denali_dt *dt = platform_get_drvdata(pdev);
179 denali_remove(&dt->denali);
180 clk_disable_unprepare(dt->clk_ecc);
181 clk_disable_unprepare(dt->clk_x);
182 clk_disable_unprepare(dt->clk);
187 static struct platform_driver denali_dt_driver = {
188 .probe = denali_dt_probe,
189 .remove = denali_dt_remove,
191 .name = "denali-nand-dt",
192 .of_match_table = denali_nand_dt_ids,
195 module_platform_driver(denali_dt_driver);
197 MODULE_LICENSE("GPL v2");
198 MODULE_AUTHOR("Jamie Iles");
199 MODULE_DESCRIPTION("DT driver for Denali NAND controller");