drivers/mtd/nand/raw/denali.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * NAND Flash Controller Device Driver
   4  * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
   5  */
   6
   7 #ifndef __DENALI_H__
   8 #define __DENALI_H__
   9
  10 #include <linux/bitops.h>
  11 #include <linux/completion.h>
  12 #include <linux/mtd/rawnand.h>
  13 #include <linux/spinlock_types.h>
  14 #include <linux/types.h>
  15
  16 #define DEVICE_RESET                            0x0
  17 #define     DEVICE_RESET__BANK(bank)                    BIT(bank)
  18
  19 #define TRANSFER_SPARE_REG                      0x10
  20 #define     TRANSFER_SPARE_REG__FLAG                    BIT(0)
  21
  22 #define LOAD_WAIT_CNT                           0x20
  23 #define     LOAD_WAIT_CNT__VALUE                        GENMASK(15, 0)
  24
  25 #define PROGRAM_WAIT_CNT                        0x30
  26 #define     PROGRAM_WAIT_CNT__VALUE                     GENMASK(15, 0)
  27
  28 #define ERASE_WAIT_CNT                          0x40
  29 #define     ERASE_WAIT_CNT__VALUE                       GENMASK(15, 0)
  30
  31 #define INT_MON_CYCCNT                          0x50
  32 #define     INT_MON_CYCCNT__VALUE                       GENMASK(15, 0)
  33
  34 #define RB_PIN_ENABLED                          0x60
  35 #define     RB_PIN_ENABLED__BANK(bank)                  BIT(bank)
  36
  37 #define MULTIPLANE_OPERATION                    0x70
  38 #define     MULTIPLANE_OPERATION__FLAG                  BIT(0)
  39
  40 #define MULTIPLANE_READ_ENABLE                  0x80
  41 #define     MULTIPLANE_READ_ENABLE__FLAG                BIT(0)
  42
  43 #define COPYBACK_DISABLE                        0x90
  44 #define     COPYBACK_DISABLE__FLAG                      BIT(0)
  45
  46 #define CACHE_WRITE_ENABLE                      0xa0
  47 #define     CACHE_WRITE_ENABLE__FLAG                    BIT(0)
  48
  49 #define CACHE_READ_ENABLE                       0xb0
  50 #define     CACHE_READ_ENABLE__FLAG                     BIT(0)
  51
  52 #define PREFETCH_MODE                           0xc0
  53 #define     PREFETCH_MODE__PREFETCH_EN                  BIT(0)
  54 #define     PREFETCH_MODE__PREFETCH_BURST_LENGTH        GENMASK(15, 4)
  55
  56 #define CHIP_ENABLE_DONT_CARE                   0xd0
  57 #define     CHIP_EN_DONT_CARE__FLAG                     BIT(0)
  58
  59 #define ECC_ENABLE                              0xe0
  60 #define     ECC_ENABLE__FLAG                            BIT(0)
  61
  62 #define GLOBAL_INT_ENABLE                       0xf0
  63 #define     GLOBAL_INT_EN_FLAG                          BIT(0)
  64
  65 #define TWHR2_AND_WE_2_RE                       0x100
  66 #define     TWHR2_AND_WE_2_RE__WE_2_RE                  GENMASK(5, 0)
  67 #define     TWHR2_AND_WE_2_RE__TWHR2                    GENMASK(13, 8)
  68
  69 #define TCWAW_AND_ADDR_2_DATA                   0x110
  70 /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
  71 #define     TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA          GENMASK(6, 0)
  72 #define     TCWAW_AND_ADDR_2_DATA__TCWAW                GENMASK(13, 8)
  73
  74 #define RE_2_WE                                 0x120
  75 #define     RE_2_WE__VALUE                              GENMASK(5, 0)
  76
  77 #define ACC_CLKS                                0x130
  78 #define     ACC_CLKS__VALUE                             GENMASK(3, 0)
  79
  80 #define NUMBER_OF_PLANES                        0x140
  81 #define     NUMBER_OF_PLANES__VALUE                     GENMASK(2, 0)
  82
  83 #define PAGES_PER_BLOCK                         0x150
  84 #define     PAGES_PER_BLOCK__VALUE                      GENMASK(15, 0)
  85
  86 #define DEVICE_WIDTH                            0x160
  87 #define     DEVICE_WIDTH__VALUE                         GENMASK(1, 0)
  88
  89 #define DEVICE_MAIN_AREA_SIZE                   0x170
  90 #define     DEVICE_MAIN_AREA_SIZE__VALUE                GENMASK(15, 0)
  91
  92 #define DEVICE_SPARE_AREA_SIZE                  0x180
  93 #define     DEVICE_SPARE_AREA_SIZE__VALUE               GENMASK(15, 0)
  94
  95 #define TWO_ROW_ADDR_CYCLES                     0x190
  96 #define     TWO_ROW_ADDR_CYCLES__FLAG                   BIT(0)
  97
  98 #define MULTIPLANE_ADDR_RESTRICT                0x1a0
  99 #define     MULTIPLANE_ADDR_RESTRICT__FLAG              BIT(0)
 100
 101 #define ECC_CORRECTION                          0x1b0
 102 #define     ECC_CORRECTION__VALUE                       GENMASK(4, 0)
 103 #define     ECC_CORRECTION__ERASE_THRESHOLD             GENMASK(31, 16)
 104
 105 #define READ_MODE                               0x1c0
 106 #define     READ_MODE__VALUE                            GENMASK(3, 0)
 107
 108 #define WRITE_MODE                              0x1d0
 109 #define     WRITE_MODE__VALUE                           GENMASK(3, 0)
 110
 111 #define COPYBACK_MODE                           0x1e0
 112 #define     COPYBACK_MODE__VALUE                        GENMASK(3, 0)
 113
 114 #define RDWR_EN_LO_CNT                          0x1f0
 115 #define     RDWR_EN_LO_CNT__VALUE                       GENMASK(4, 0)
 116
 117 #define RDWR_EN_HI_CNT                          0x200
 118 #define     RDWR_EN_HI_CNT__VALUE                       GENMASK(4, 0)
 119
 120 #define MAX_RD_DELAY                            0x210
 121 #define     MAX_RD_DELAY__VALUE                         GENMASK(3, 0)
 122
 123 #define CS_SETUP_CNT                            0x220
 124 #define     CS_SETUP_CNT__VALUE                         GENMASK(4, 0)
 125 #define     CS_SETUP_CNT__TWB                           GENMASK(17, 12)
 126
 127 #define SPARE_AREA_SKIP_BYTES                   0x230
 128 #define     SPARE_AREA_SKIP_BYTES__VALUE                GENMASK(5, 0)
 129
 130 #define SPARE_AREA_MARKER                       0x240
 131 #define     SPARE_AREA_MARKER__VALUE                    GENMASK(15, 0)
 132
 133 #define DEVICES_CONNECTED                       0x250
 134 #define     DEVICES_CONNECTED__VALUE                    GENMASK(2, 0)
 135
 136 #define DIE_MASK                                0x260
 137 #define     DIE_MASK__VALUE                             GENMASK(7, 0)
 138
 139 #define FIRST_BLOCK_OF_NEXT_PLANE               0x270
 140 #define     FIRST_BLOCK_OF_NEXT_PLANE__VALUE            GENMASK(15, 0)
 141
 142 #define WRITE_PROTECT                           0x280
 143 #define     WRITE_PROTECT__FLAG                         BIT(0)
 144
 145 #define RE_2_RE                                 0x290
 146 #define     RE_2_RE__VALUE                              GENMASK(5, 0)
 147
 148 #define MANUFACTURER_ID                         0x300
 149 #define     MANUFACTURER_ID__VALUE                      GENMASK(7, 0)
 150
 151 #define DEVICE_ID                               0x310
 152 #define     DEVICE_ID__VALUE                            GENMASK(7, 0)
 153
 154 #define DEVICE_PARAM_0                          0x320
 155 #define     DEVICE_PARAM_0__VALUE                       GENMASK(7, 0)
 156
 157 #define DEVICE_PARAM_1                          0x330
 158 #define     DEVICE_PARAM_1__VALUE                       GENMASK(7, 0)
 159
 160 #define DEVICE_PARAM_2                          0x340
 161 #define     DEVICE_PARAM_2__VALUE                       GENMASK(7, 0)
 162
 163 #define LOGICAL_PAGE_DATA_SIZE                  0x350
 164 #define     LOGICAL_PAGE_DATA_SIZE__VALUE               GENMASK(15, 0)
 165
 166 #define LOGICAL_PAGE_SPARE_SIZE                 0x360
 167 #define     LOGICAL_PAGE_SPARE_SIZE__VALUE              GENMASK(15, 0)
 168
 169 #define REVISION                                0x370
 170 #define     REVISION__VALUE                             GENMASK(15, 0)
 171
 172 #define ONFI_DEVICE_FEATURES                    0x380
 173 #define     ONFI_DEVICE_FEATURES__VALUE                 GENMASK(5, 0)
 174
 175 #define ONFI_OPTIONAL_COMMANDS                  0x390
 176 #define     ONFI_OPTIONAL_COMMANDS__VALUE               GENMASK(5, 0)
 177
 178 #define ONFI_TIMING_MODE                        0x3a0
 179 #define     ONFI_TIMING_MODE__VALUE                     GENMASK(5, 0)
 180
 181 #define ONFI_PGM_CACHE_TIMING_MODE              0x3b0
 182 #define     ONFI_PGM_CACHE_TIMING_MODE__VALUE           GENMASK(5, 0)
 183
 184 #define ONFI_DEVICE_NO_OF_LUNS                  0x3c0
 185 #define     ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS          GENMASK(7, 0)
 186 #define     ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE         BIT(8)
 187
 188 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L      0x3d0
 189 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE   GENMASK(15, 0)
 190
 191 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U      0x3e0
 192 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE   GENMASK(15, 0)
 193
 194 #define FEATURES                                0x3f0
 195 #define     FEATURES__N_BANKS                           GENMASK(1, 0)
 196 #define     FEATURES__ECC_MAX_ERR                       GENMASK(5, 2)
 197 #define     FEATURES__DMA                               BIT(6)
 198 #define     FEATURES__CMD_DMA                           BIT(7)
 199 #define     FEATURES__PARTITION                         BIT(8)
 200 #define     FEATURES__XDMA_SIDEBAND                     BIT(9)
 201 #define     FEATURES__GPREG                             BIT(10)
 202 #define     FEATURES__INDEX_ADDR                        BIT(11)
 203
 204 #define TRANSFER_MODE                           0x400
 205 #define     TRANSFER_MODE__VALUE                        GENMASK(1, 0)
 206
 207 #define INTR_STATUS(bank)                       (0x410 + (bank) * 0x50)
 208 #define INTR_EN(bank)                           (0x420 + (bank) * 0x50)
 209 /* bit[1:0] is used differently depending on IP version */
 210 #define     INTR__ECC_UNCOR_ERR                         BIT(0)  /* new IP */
 211 #define     INTR__ECC_TRANSACTION_DONE                  BIT(0)  /* old IP */
 212 #define     INTR__ECC_ERR                               BIT(1)  /* old IP */
 213 #define     INTR__DMA_CMD_COMP                          BIT(2)
 214 #define     INTR__TIME_OUT                              BIT(3)
 215 #define     INTR__PROGRAM_FAIL                          BIT(4)
 216 #define     INTR__ERASE_FAIL                            BIT(5)
 217 #define     INTR__LOAD_COMP                             BIT(6)
 218 #define     INTR__PROGRAM_COMP                          BIT(7)
 219 #define     INTR__ERASE_COMP                            BIT(8)
 220 #define     INTR__PIPE_CPYBCK_CMD_COMP                  BIT(9)
 221 #define     INTR__LOCKED_BLK                            BIT(10)
 222 #define     INTR__UNSUP_CMD                             BIT(11)
 223 #define     INTR__INT_ACT                               BIT(12)
 224 #define     INTR__RST_COMP                              BIT(13)
 225 #define     INTR__PIPE_CMD_ERR                          BIT(14)
 226 #define     INTR__PAGE_XFER_INC                         BIT(15)
 227 #define     INTR__ERASED_PAGE                           BIT(16)
 228
 229 #define PAGE_CNT(bank)                          (0x430 + (bank) * 0x50)
 230 #define ERR_PAGE_ADDR(bank)                     (0x440 + (bank) * 0x50)
 231 #define ERR_BLOCK_ADDR(bank)                    (0x450 + (bank) * 0x50)
 232
 233 #define ECC_THRESHOLD                           0x600
 234 #define     ECC_THRESHOLD__VALUE                        GENMASK(9, 0)
 235
 236 #define ECC_ERROR_BLOCK_ADDRESS                 0x610
 237 #define     ECC_ERROR_BLOCK_ADDRESS__VALUE              GENMASK(15, 0)
 238
 239 #define ECC_ERROR_PAGE_ADDRESS                  0x620
 240 #define     ECC_ERROR_PAGE_ADDRESS__VALUE               GENMASK(11, 0)
 241 #define     ECC_ERROR_PAGE_ADDRESS__BANK                GENMASK(15, 12)
 242
 243 #define ECC_ERROR_ADDRESS                       0x630
 244 #define     ECC_ERROR_ADDRESS__OFFSET                   GENMASK(11, 0)
 245 #define     ECC_ERROR_ADDRESS__SECTOR                   GENMASK(15, 12)
 246
 247 #define ERR_CORRECTION_INFO                     0x640
 248 #define     ERR_CORRECTION_INFO__BYTE                   GENMASK(7, 0)
 249 #define     ERR_CORRECTION_INFO__DEVICE                 GENMASK(11, 8)
 250 #define     ERR_CORRECTION_INFO__UNCOR                  BIT(14)
 251 #define     ERR_CORRECTION_INFO__LAST_ERR               BIT(15)
 252
 253 #define ECC_COR_INFO(bank)                      (0x650 + (bank) / 2 * 0x10)
 254 #define     ECC_COR_INFO__SHIFT(bank)                   ((bank) % 2 * 8)
 255 #define     ECC_COR_INFO__MAX_ERRORS                    GENMASK(6, 0)
 256 #define     ECC_COR_INFO__UNCOR_ERR                     BIT(7)
 257
 258 #define CFG_DATA_BLOCK_SIZE                     0x6b0
 259
 260 #define CFG_LAST_DATA_BLOCK_SIZE                0x6c0
 261
 262 #define CFG_NUM_DATA_BLOCKS                     0x6d0
 263
 264 #define CFG_META_DATA_SIZE                      0x6e0
 265
 266 #define DMA_ENABLE                              0x700
 267 #define     DMA_ENABLE__FLAG                            BIT(0)
 268
 269 #define IGNORE_ECC_DONE                         0x710
 270 #define     IGNORE_ECC_DONE__FLAG                       BIT(0)
 271
 272 #define DMA_INTR                                0x720
 273 #define DMA_INTR_EN                             0x730
 274 #define     DMA_INTR__TARGET_ERROR                      BIT(0)
 275 #define     DMA_INTR__DESC_COMP_CHANNEL0                BIT(1)
 276 #define     DMA_INTR__DESC_COMP_CHANNEL1                BIT(2)
 277 #define     DMA_INTR__DESC_COMP_CHANNEL2                BIT(3)
 278 #define     DMA_INTR__DESC_COMP_CHANNEL3                BIT(4)
 279 #define     DMA_INTR__MEMCOPY_DESC_COMP                 BIT(5)
 280
 281 #define TARGET_ERR_ADDR_LO                      0x740
 282 #define     TARGET_ERR_ADDR_LO__VALUE                   GENMASK(15, 0)
 283
 284 #define TARGET_ERR_ADDR_HI                      0x750
 285 #define     TARGET_ERR_ADDR_HI__VALUE                   GENMASK(15, 0)
 286
 287 #define CHNL_ACTIVE                             0x760
 288 #define     CHNL_ACTIVE__CHANNEL0                       BIT(0)
 289 #define     CHNL_ACTIVE__CHANNEL1                       BIT(1)
 290 #define     CHNL_ACTIVE__CHANNEL2                       BIT(2)
 291 #define     CHNL_ACTIVE__CHANNEL3                       BIT(3)
 292
 293 struct denali_nand_info {
 294         struct nand_chip nand;
 295         unsigned long clk_rate;         /* core clock rate */
 296         unsigned long clk_x_rate;       /* bus interface clock rate */
 297         int active_bank;                /* currently selected bank */
 298         struct device *dev;
 299         void __iomem *reg;              /* Register Interface */
 300         void __iomem *host;             /* Host Data/Command Interface */
 301         struct completion complete;
 302         spinlock_t irq_lock;            /* protect irq_mask and irq_status */
 303         u32 irq_mask;                   /* interrupts we are waiting for */
 304         u32 irq_status;                 /* interrupts that have happened */
 305         int irq;
 306         void *buf;                      /* for syndrome layout conversion */
 307         dma_addr_t dma_addr;
 308         int dma_avail;                  /* can support DMA? */
 309         int devs_per_cs;                /* devices connected in parallel */
 310         int oob_skip_bytes;             /* number of bytes reserved for BBM */
 311         int max_banks;
 312         unsigned int revision;          /* IP revision */
 313         unsigned int caps;              /* IP capability (or quirk) */
 314         const struct nand_ecc_caps *ecc_caps;
 315         u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
 316         void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
 317         void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
 318                           int page, int write);
 319 };
 320
 321 #define DENALI_CAP_HW_ECC_FIXUP                 BIT(0)
 322 #define DENALI_CAP_DMA_64BIT                    BIT(1)
 323
 324 int denali_calc_ecc_bytes(int step_size, int strength);
 325 int denali_init(struct denali_nand_info *denali);
 326 void denali_remove(struct denali_nand_info *denali);
 327
 328 #endif /* __DENALI_H__ */