e1ee62a17fe03f35b77f8e5115a0a1a65d679624
[sfrench/cifs-2.6.git] / drivers / mtd / nand / cafe.c
1 /*
2  * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3  *
4  * Copyright © 2006 Red Hat, Inc.
5  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
6  */
7
8 #define DEBUG
9
10 #include <linux/device.h>
11 #undef DEBUG
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/nand.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <asm/io.h>
18
19 #define CAFE_NAND_CTRL1         0x00
20 #define CAFE_NAND_CTRL2         0x04
21 #define CAFE_NAND_CTRL3         0x08
22 #define CAFE_NAND_STATUS        0x0c
23 #define CAFE_NAND_IRQ           0x10
24 #define CAFE_NAND_IRQ_MASK      0x14
25 #define CAFE_NAND_DATA_LEN      0x18
26 #define CAFE_NAND_ADDR1         0x1c
27 #define CAFE_NAND_ADDR2         0x20
28 #define CAFE_NAND_TIMING1       0x24
29 #define CAFE_NAND_TIMING2       0x28
30 #define CAFE_NAND_TIMING3       0x2c
31 #define CAFE_NAND_NONMEM        0x30
32 #define CAFE_NAND_ECC_RESULT    0x3C
33 #define CAFE_NAND_DMA_CTRL      0x40
34 #define CAFE_NAND_DMA_ADDR0     0x44
35 #define CAFE_NAND_DMA_ADDR1     0x48
36 #define CAFE_NAND_ECC_SYN01     0x50
37 #define CAFE_NAND_ECC_SYN23     0x54
38 #define CAFE_NAND_ECC_SYN45     0x58
39 #define CAFE_NAND_ECC_SYN67     0x5c
40 #define CAFE_NAND_READ_DATA     0x1000
41 #define CAFE_NAND_WRITE_DATA    0x2000
42
43 #define CAFE_GLOBAL_CTRL        0x3004
44 #define CAFE_GLOBAL_IRQ         0x3008
45 #define CAFE_GLOBAL_IRQ_MASK    0x300c
46 #define CAFE_NAND_RESET         0x3034
47
48 int cafe_correct_ecc(unsigned char *buf,
49                      unsigned short *chk_syndrome_list);
50
51 struct cafe_priv {
52         struct nand_chip nand;
53         struct pci_dev *pdev;
54         void __iomem *mmio;
55         uint32_t ctl1;
56         uint32_t ctl2;
57         int datalen;
58         int nr_data;
59         int data_pos;
60         int page_addr;
61         dma_addr_t dmaaddr;
62         unsigned char *dmabuf;
63 };
64
65 static int usedma = 1;
66 module_param(usedma, int, 0644);
67
68 static int skipbbt = 0;
69 module_param(skipbbt, int, 0644);
70
71 static int debug = 0;
72 module_param(debug, int, 0644);
73
74 static int regdebug = 0;
75 module_param(regdebug, int, 0644);
76
77 static int checkecc = 1;
78 module_param(checkecc, int, 0644);
79
80 static int numtimings;
81 static int timing[3];
82 module_param_array(timing, int, &numtimings, 0644);
83
84 /* Hrm. Why isn't this already conditional on something in the struct device? */
85 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
86
87 /* Make it easier to switch to PIO if we need to */
88 #define cafe_readl(cafe, addr)                  readl((cafe)->mmio + CAFE_##addr)
89 #define cafe_writel(cafe, datum, addr)          writel(datum, (cafe)->mmio + CAFE_##addr)
90
91 static int cafe_device_ready(struct mtd_info *mtd)
92 {
93         struct cafe_priv *cafe = mtd->priv;
94         int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
95         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
96
97         cafe_writel(cafe, irqs, NAND_IRQ);
98
99         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
100                 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
101                 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
102
103         return result;
104 }
105
106
107 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
108 {
109         struct cafe_priv *cafe = mtd->priv;
110
111         if (usedma)
112                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
113         else
114                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
115
116         cafe->datalen += len;
117
118         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
119                 len, cafe->datalen);
120 }
121
122 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
123 {
124         struct cafe_priv *cafe = mtd->priv;
125
126         if (usedma)
127                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
128         else
129                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
130
131         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
132                   len, cafe->datalen);
133         cafe->datalen += len;
134 }
135
136 static uint8_t cafe_read_byte(struct mtd_info *mtd)
137 {
138         struct cafe_priv *cafe = mtd->priv;
139         uint8_t d;
140
141         cafe_read_buf(mtd, &d, 1);
142         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
143
144         return d;
145 }
146
147 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
148                               int column, int page_addr)
149 {
150         struct cafe_priv *cafe = mtd->priv;
151         int adrbytes = 0;
152         uint32_t ctl1;
153         uint32_t doneint = 0x80000000;
154
155         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
156                 command, column, page_addr);
157
158         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
159                 /* Second half of a command we already calculated */
160                 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
161                 ctl1 = cafe->ctl1;
162                 cafe->ctl2 &= ~(1<<30);
163                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
164                           cafe->ctl1, cafe->nr_data);
165                 goto do_command;
166         }
167         /* Reset ECC engine */
168         cafe_writel(cafe, 0, NAND_CTRL2);
169
170         /* Emulate NAND_CMD_READOOB on large-page chips */
171         if (mtd->writesize > 512 &&
172             command == NAND_CMD_READOOB) {
173                 column += mtd->writesize;
174                 command = NAND_CMD_READ0;
175         }
176
177         /* FIXME: Do we need to send read command before sending data
178            for small-page chips, to position the buffer correctly? */
179
180         if (column != -1) {
181                 cafe_writel(cafe, column, NAND_ADDR1);
182                 adrbytes = 2;
183                 if (page_addr != -1)
184                         goto write_adr2;
185         } else if (page_addr != -1) {
186                 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
187                 page_addr >>= 16;
188         write_adr2:
189                 cafe_writel(cafe, page_addr, NAND_ADDR2);
190                 adrbytes += 2;
191                 if (mtd->size > mtd->writesize << 16)
192                         adrbytes++;
193         }
194
195         cafe->data_pos = cafe->datalen = 0;
196
197         /* Set command valid bit */
198         ctl1 = 0x80000000 | command;
199
200         /* Set RD or WR bits as appropriate */
201         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
202                 ctl1 |= (1<<26); /* rd */
203                 /* Always 5 bytes, for now */
204                 cafe->datalen = 4;
205                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
206                 adrbytes = 1;
207         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
208                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
209                 ctl1 |= 1<<26; /* rd */
210                 /* For now, assume just read to end of page */
211                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
212         } else if (command == NAND_CMD_SEQIN)
213                 ctl1 |= 1<<25; /* wr */
214
215         /* Set number of address bytes */
216         if (adrbytes)
217                 ctl1 |= ((adrbytes-1)|8) << 27;
218
219         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
220                 /* Ignore the first command of a pair; the hardware
221                    deals with them both at once, later */
222                 cafe->ctl1 = ctl1;
223                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
224                           cafe->ctl1, cafe->datalen);
225                 return;
226         }
227         /* RNDOUT and READ0 commands need a following byte */
228         if (command == NAND_CMD_RNDOUT)
229                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
230         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
231                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
232
233  do_command:
234         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
235                 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
236
237         /* NB: The datasheet lies -- we really should be subtracting 1 here */
238         cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
239         cafe_writel(cafe, 0x90000000, NAND_IRQ);
240         if (usedma && (ctl1 & (3<<25))) {
241                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
242                 /* If WR or RD bits set, set up DMA */
243                 if (ctl1 & (1<<26)) {
244                         /* It's a read */
245                         dmactl |= (1<<29);
246                         /* ... so it's done when the DMA is done, not just
247                            the command. */
248                         doneint = 0x10000000;
249                 }
250                 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
251         }
252         cafe->datalen = 0;
253
254         if (unlikely(regdebug)) {
255                 int i;
256                 printk("About to write command %08x to register 0\n", ctl1);
257                 for (i=4; i< 0x5c; i+=4)
258                         printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
259         }
260
261         cafe_writel(cafe, ctl1, NAND_CTRL1);
262         /* Apply this short delay always to ensure that we do wait tWB in
263          * any case on any machine. */
264         ndelay(100);
265
266         if (1) {
267                 int c = 500000;
268                 uint32_t irqs;
269
270                 while (c--) {
271                         irqs = cafe_readl(cafe, NAND_IRQ);
272                         if (irqs & doneint)
273                                 break;
274                         udelay(1);
275                         if (!(c % 100000))
276                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
277                         cpu_relax();
278                 }
279                 cafe_writel(cafe, doneint, NAND_IRQ);
280                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
281                              command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
282         }
283
284         WARN_ON(cafe->ctl2 & (1<<30));
285
286         switch (command) {
287
288         case NAND_CMD_CACHEDPROG:
289         case NAND_CMD_PAGEPROG:
290         case NAND_CMD_ERASE1:
291         case NAND_CMD_ERASE2:
292         case NAND_CMD_SEQIN:
293         case NAND_CMD_RNDIN:
294         case NAND_CMD_STATUS:
295         case NAND_CMD_DEPLETE1:
296         case NAND_CMD_RNDOUT:
297         case NAND_CMD_STATUS_ERROR:
298         case NAND_CMD_STATUS_ERROR0:
299         case NAND_CMD_STATUS_ERROR1:
300         case NAND_CMD_STATUS_ERROR2:
301         case NAND_CMD_STATUS_ERROR3:
302                 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
303                 return;
304         }
305         nand_wait_ready(mtd);
306         cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
307 }
308
309 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
310 {
311         //struct cafe_priv *cafe = mtd->priv;
312         //      cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
313 }
314
315 static int cafe_nand_interrupt(int irq, void *id)
316 {
317         struct mtd_info *mtd = id;
318         struct cafe_priv *cafe = mtd->priv;
319         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
320         cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
321         if (!irqs)
322                 return IRQ_NONE;
323
324         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
325         return IRQ_HANDLED;
326 }
327
328 static void cafe_nand_bug(struct mtd_info *mtd)
329 {
330         BUG();
331 }
332
333 static int cafe_nand_write_oob(struct mtd_info *mtd,
334                                struct nand_chip *chip, int page)
335 {
336         int status = 0;
337
338         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
339         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
340         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
341         status = chip->waitfunc(mtd, chip);
342
343         return status & NAND_STATUS_FAIL ? -EIO : 0;
344 }
345
346 /* Don't use -- use nand_read_oob_std for now */
347 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
348                               int page, int sndcmd)
349 {
350         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
351         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
352         return 1;
353 }
354 /**
355  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
356  * @mtd:        mtd info structure
357  * @chip:       nand chip info structure
358  * @buf:        buffer to store read data
359  *
360  * The hw generator calculates the error syndrome automatically. Therefor
361  * we need a special oob layout and handling.
362  */
363 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
364                                uint8_t *buf)
365 {
366         struct cafe_priv *cafe = mtd->priv;
367
368         cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
369                      cafe_readl(cafe, NAND_ECC_RESULT),
370                      cafe_readl(cafe, NAND_ECC_SYN01));
371
372         chip->read_buf(mtd, buf, mtd->writesize);
373         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
374
375         if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
376                 unsigned short syn[8];
377                 int i;
378
379                 for (i=0; i<8; i+=2) {
380                         uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
381                         syn[i] = tmp & 0xfff;
382                         syn[i+1] = (tmp >> 16) & 0xfff;
383                 }
384
385                 if ((i = cafe_correct_ecc(buf, syn)) < 0) {
386                         dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
387                                 cafe_readl(cafe, NAND_ADDR2) * 2048);
388                         for (i=0; i< 0x5c; i+=4)
389                                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
390                         mtd->ecc_stats.failed++;
391                 } else {
392                         dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i);
393                         mtd->ecc_stats.corrected += i;
394                 }
395         }
396
397
398         return 0;
399 }
400
401 static struct nand_ecclayout cafe_oobinfo_2048 = {
402         .eccbytes = 14,
403         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
404         .oobfree = {{14, 50}}
405 };
406
407 /* Ick. The BBT code really ought to be able to work this bit out
408    for itself from the above, at least for the 2KiB case */
409 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
410 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
411
412 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
413 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
414
415
416 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
417         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
418                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
419         .offs = 14,
420         .len = 4,
421         .veroffs = 18,
422         .maxblocks = 4,
423         .pattern = cafe_bbt_pattern_2048
424 };
425
426 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
427         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
428                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
429         .offs = 14,
430         .len = 4,
431         .veroffs = 18,
432         .maxblocks = 4,
433         .pattern = cafe_mirror_pattern_2048
434 };
435
436 static struct nand_ecclayout cafe_oobinfo_512 = {
437         .eccbytes = 14,
438         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
439         .oobfree = {{14, 2}}
440 };
441
442 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
443         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
444                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
445         .offs = 14,
446         .len = 1,
447         .veroffs = 15,
448         .maxblocks = 4,
449         .pattern = cafe_bbt_pattern_512
450 };
451
452 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
453         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
454                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
455         .offs = 14,
456         .len = 1,
457         .veroffs = 15,
458         .maxblocks = 4,
459         .pattern = cafe_mirror_pattern_512
460 };
461
462
463 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
464                                           struct nand_chip *chip, const uint8_t *buf)
465 {
466         struct cafe_priv *cafe = mtd->priv;
467
468         chip->write_buf(mtd, buf, mtd->writesize);
469         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
470
471         /* Set up ECC autogeneration */
472         cafe->ctl2 |= (1<<30);
473 }
474
475 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
476                                 const uint8_t *buf, int page, int cached, int raw)
477 {
478         int status;
479
480         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
481
482         if (unlikely(raw))
483                 chip->ecc.write_page_raw(mtd, chip, buf);
484         else
485                 chip->ecc.write_page(mtd, chip, buf);
486
487         /*
488          * Cached progamming disabled for now, Not sure if its worth the
489          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
490          */
491         cached = 0;
492
493         if (!cached || !(chip->options & NAND_CACHEPRG)) {
494
495                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
496                 status = chip->waitfunc(mtd, chip);
497                 /*
498                  * See if operation failed and additional status checks are
499                  * available
500                  */
501                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
502                         status = chip->errstat(mtd, chip, FL_WRITING, status,
503                                                page);
504
505                 if (status & NAND_STATUS_FAIL)
506                         return -EIO;
507         } else {
508                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
509                 status = chip->waitfunc(mtd, chip);
510         }
511
512 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
513         /* Send command to read back the data */
514         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
515
516         if (chip->verify_buf(mtd, buf, mtd->writesize))
517                 return -EIO;
518 #endif
519         return 0;
520 }
521
522 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
523 {
524         return 0;
525 }
526
527 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
528                                      const struct pci_device_id *ent)
529 {
530         struct mtd_info *mtd;
531         struct cafe_priv *cafe;
532         uint32_t timing1, timing2, timing3;
533         uint32_t ctrl;
534         int err = 0;
535
536         err = pci_enable_device(pdev);
537         if (err)
538                 return err;
539
540         pci_set_master(pdev);
541
542         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
543         if (!mtd) {
544                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
545                 return  -ENOMEM;
546         }
547         cafe = (void *)(&mtd[1]);
548
549         mtd->priv = cafe;
550         mtd->owner = THIS_MODULE;
551
552         cafe->pdev = pdev;
553         cafe->mmio = pci_iomap(pdev, 0, 0);
554         if (!cafe->mmio) {
555                 dev_warn(&pdev->dev, "failed to iomap\n");
556                 err = -ENOMEM;
557                 goto out_free_mtd;
558         }
559         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
560                                           &cafe->dmaaddr, GFP_KERNEL);
561         if (!cafe->dmabuf) {
562                 err = -ENOMEM;
563                 goto out_ior;
564         }
565         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
566
567         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
568         cafe->nand.dev_ready = cafe_device_ready;
569         cafe->nand.read_byte = cafe_read_byte;
570         cafe->nand.read_buf = cafe_read_buf;
571         cafe->nand.write_buf = cafe_write_buf;
572         cafe->nand.select_chip = cafe_select_chip;
573
574         cafe->nand.chip_delay = 0;
575
576         /* Enable the following for a flash based bad block table */
577         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
578
579         if (skipbbt) {
580                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
581                 cafe->nand.block_bad = cafe_nand_block_bad;
582         }
583
584         if (numtimings && numtimings != 3) {
585                 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
586         }
587
588         if (numtimings == 3) {
589                 timing1 = timing[0];
590                 timing2 = timing[1];
591                 timing3 = timing[2];
592                 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
593                              timing1, timing2, timing3);
594         } else {
595                 timing1 = cafe_readl(cafe, NAND_TIMING1);
596                 timing2 = cafe_readl(cafe, NAND_TIMING2);
597                 timing3 = cafe_readl(cafe, NAND_TIMING3);
598
599                 if (timing1 | timing2 | timing3) {
600                         cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", timing1, timing2, timing3);
601                 } else {
602                         dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
603                         timing1 = timing2 = timing3 = 0xffffffff;
604                 }
605         }
606
607         /* Start off by resetting the NAND controller completely */
608         cafe_writel(cafe, 1, NAND_RESET);
609         cafe_writel(cafe, 0, NAND_RESET);
610
611         cafe_writel(cafe, timing1, NAND_TIMING1);
612         cafe_writel(cafe, timing2, NAND_TIMING2);
613         cafe_writel(cafe, timing3, NAND_TIMING3);
614
615         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
616         err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
617         if (err) {
618                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
619                 goto out_free_dma;
620         }
621
622         /* Disable master reset, enable NAND clock */
623         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
624         ctrl &= 0xffffeff0;
625         ctrl |= 0x00007000;
626         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
627         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
628         cafe_writel(cafe, 0, NAND_DMA_CTRL);
629
630         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
631         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
632
633         /* Set up DMA address */
634         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
635         if (sizeof(cafe->dmaaddr) > 4)
636                 /* Shift in two parts to shut the compiler up */
637                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
638         else
639                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
640
641         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
642                 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
643
644         /* Enable NAND IRQ in global IRQ mask register */
645         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
646         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
647                 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
648
649         /* Scan to find existence of the device */
650         if (nand_scan_ident(mtd, 1)) {
651                 err = -ENXIO;
652                 goto out_irq;
653         }
654
655         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
656         if (mtd->writesize == 2048)
657                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
658
659         /* Set up ECC according to the type of chip we found */
660         if (mtd->writesize == 2048) {
661                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
662                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
663                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
664         } else if (mtd->writesize == 512) {
665                 cafe->nand.ecc.layout = &cafe_oobinfo_512;
666                 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
667                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
668         } else {
669                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
670                        mtd->writesize);
671                 goto out_irq;
672         }
673         cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
674         cafe->nand.ecc.size = mtd->writesize;
675         cafe->nand.ecc.bytes = 14;
676         cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
677         cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
678         cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
679         cafe->nand.write_page = cafe_nand_write_page;
680         cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
681         cafe->nand.ecc.write_oob = cafe_nand_write_oob;
682         cafe->nand.ecc.read_page = cafe_nand_read_page;
683         cafe->nand.ecc.read_oob = cafe_nand_read_oob;
684
685         err = nand_scan_tail(mtd);
686         if (err)
687                 goto out_irq;
688
689         pci_set_drvdata(pdev, mtd);
690         add_mtd_device(mtd);
691         goto out;
692
693  out_irq:
694         /* Disable NAND IRQ in global IRQ mask register */
695         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
696         free_irq(pdev->irq, mtd);
697  out_free_dma:
698         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
699  out_ior:
700         pci_iounmap(pdev, cafe->mmio);
701  out_free_mtd:
702         kfree(mtd);
703  out:
704         return err;
705 }
706
707 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
708 {
709         struct mtd_info *mtd = pci_get_drvdata(pdev);
710         struct cafe_priv *cafe = mtd->priv;
711
712         del_mtd_device(mtd);
713         /* Disable NAND IRQ in global IRQ mask register */
714         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
715         free_irq(pdev->irq, mtd);
716         nand_release(mtd);
717         pci_iounmap(pdev, cafe->mmio);
718         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
719         kfree(mtd);
720 }
721
722 static struct pci_device_id cafe_nand_tbl[] = {
723         { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
724 };
725
726 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
727
728 static struct pci_driver cafe_nand_pci_driver = {
729         .name = "CAFÉ NAND",
730         .id_table = cafe_nand_tbl,
731         .probe = cafe_nand_probe,
732         .remove = __devexit_p(cafe_nand_remove),
733 #ifdef CONFIG_PMx
734         .suspend = cafe_nand_suspend,
735         .resume = cafe_nand_resume,
736 #endif
737 };
738
739 static int cafe_nand_init(void)
740 {
741         return pci_register_driver(&cafe_nand_pci_driver);
742 }
743
744 static void cafe_nand_exit(void)
745 {
746         pci_unregister_driver(&cafe_nand_pci_driver);
747 }
748 module_init(cafe_nand_init);
749 module_exit(cafe_nand_exit);
750
751 MODULE_LICENSE("GPL");
752 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
753 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");