drivers/mtd/nand/cafe.c

   1 /*
   2  * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
   3  *
   4  * Copyright © 2006 Red Hat, Inc.
   5  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 #define DEBUG
   9
  10 #include <linux/device.h>
  11 #undef DEBUG
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/nand.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <asm/io.h>
  18
  19 #define CAFE_NAND_CTRL1         0x00
  20 #define CAFE_NAND_CTRL2         0x04
  21 #define CAFE_NAND_CTRL3         0x08
  22 #define CAFE_NAND_STATUS        0x0c
  23 #define CAFE_NAND_IRQ           0x10
  24 #define CAFE_NAND_IRQ_MASK      0x14
  25 #define CAFE_NAND_DATA_LEN      0x18
  26 #define CAFE_NAND_ADDR1         0x1c
  27 #define CAFE_NAND_ADDR2         0x20
  28 #define CAFE_NAND_TIMING1       0x24
  29 #define CAFE_NAND_TIMING2       0x28
  30 #define CAFE_NAND_TIMING3       0x2c
  31 #define CAFE_NAND_NONMEM        0x30
  32 #define CAFE_NAND_ECC_RESULT    0x3C
  33 #define CAFE_NAND_DMA_CTRL      0x40
  34 #define CAFE_NAND_DMA_ADDR0     0x44
  35 #define CAFE_NAND_DMA_ADDR1     0x48
  36 #define CAFE_NAND_ECC_SYN01     0x50
  37 #define CAFE_NAND_ECC_SYN23     0x54
  38 #define CAFE_NAND_ECC_SYN45     0x58
  39 #define CAFE_NAND_ECC_SYN67     0x5c
  40 #define CAFE_NAND_READ_DATA     0x1000
  41 #define CAFE_NAND_WRITE_DATA    0x2000
  42
  43 #define CAFE_GLOBAL_CTRL        0x3004
  44 #define CAFE_GLOBAL_IRQ         0x3008
  45 #define CAFE_GLOBAL_IRQ_MASK    0x300c
  46 #define CAFE_NAND_RESET         0x3034
  47
  48 int cafe_correct_ecc(unsigned char *buf,
  49                      unsigned short *chk_syndrome_list);
  50
  51 struct cafe_priv {
  52         struct nand_chip nand;
  53         struct pci_dev *pdev;
  54         void __iomem *mmio;
  55         uint32_t ctl1;
  56         uint32_t ctl2;
  57         int datalen;
  58         int nr_data;
  59         int data_pos;
  60         int page_addr;
  61         dma_addr_t dmaaddr;
  62         unsigned char *dmabuf;
  63 };
  64
  65 static int usedma = 1;
  66 module_param(usedma, int, 0644);
  67
  68 static int skipbbt = 0;
  69 module_param(skipbbt, int, 0644);
  70
  71 static int debug = 0;
  72 module_param(debug, int, 0644);
  73
  74 static int regdebug = 0;
  75 module_param(regdebug, int, 0644);
  76
  77 static int checkecc = 1;
  78 module_param(checkecc, int, 0644);
  79
  80 static int slowtiming = 0;
  81 module_param(slowtiming, int, 0644);
  82
  83 /* Hrm. Why isn't this already conditional on something in the struct device? */
  84 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
  85
  86 /* Make it easier to switch to PIO if we need to */
  87 #define cafe_readl(cafe, addr)                  readl((cafe)->mmio + CAFE_##addr)
  88 #define cafe_writel(cafe, datum, addr)          writel(datum, (cafe)->mmio + CAFE_##addr)
  89
  90 static int cafe_device_ready(struct mtd_info *mtd)
  91 {
  92         struct cafe_priv *cafe = mtd->priv;
  93         int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
  94         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
  95
  96         cafe_writel(cafe, irqs, NAND_IRQ);
  97
  98         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
  99                 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
 100                 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
 101
 102         return result;
 103 }
 104
 105
 106 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 107 {
 108         struct cafe_priv *cafe = mtd->priv;
 109
 110         if (usedma)
 111                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
 112         else
 113                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
 114
 115         cafe->datalen += len;
 116
 117         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
 118                 len, cafe->datalen);
 119 }
 120
 121 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 122 {
 123         struct cafe_priv *cafe = mtd->priv;
 124
 125         if (usedma)
 126                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
 127         else
 128                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
 129
 130         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
 131                   len, cafe->datalen);
 132         cafe->datalen += len;
 133 }
 134
 135 static uint8_t cafe_read_byte(struct mtd_info *mtd)
 136 {
 137         struct cafe_priv *cafe = mtd->priv;
 138         uint8_t d;
 139
 140         cafe_read_buf(mtd, &d, 1);
 141         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 142
 143         return d;
 144 }
 145
 146 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 147                               int column, int page_addr)
 148 {
 149         struct cafe_priv *cafe = mtd->priv;
 150         int adrbytes = 0;
 151         uint32_t ctl1;
 152         uint32_t doneint = 0x80000000;
 153
 154         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
 155                 command, column, page_addr);
 156
 157         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
 158                 /* Second half of a command we already calculated */
 159                 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
 160                 ctl1 = cafe->ctl1;
 161                 cafe->ctl2 &= ~(1<<30);
 162                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
 163                           cafe->ctl1, cafe->nr_data);
 164                 goto do_command;
 165         }
 166         /* Reset ECC engine */
 167         cafe_writel(cafe, 0, NAND_CTRL2);
 168
 169         /* Emulate NAND_CMD_READOOB on large-page chips */
 170         if (mtd->writesize > 512 &&
 171             command == NAND_CMD_READOOB) {
 172                 column += mtd->writesize;
 173                 command = NAND_CMD_READ0;
 174         }
 175
 176         /* FIXME: Do we need to send read command before sending data
 177            for small-page chips, to position the buffer correctly? */
 178
 179         if (column != -1) {
 180                 cafe_writel(cafe, column, NAND_ADDR1);
 181                 adrbytes = 2;
 182                 if (page_addr != -1)
 183                         goto write_adr2;
 184         } else if (page_addr != -1) {
 185                 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
 186                 page_addr >>= 16;
 187         write_adr2:
 188                 cafe_writel(cafe, page_addr, NAND_ADDR2);
 189                 adrbytes += 2;
 190                 if (mtd->size > mtd->writesize << 16)
 191                         adrbytes++;
 192         }
 193
 194         cafe->data_pos = cafe->datalen = 0;
 195
 196         /* Set command valid bit */
 197         ctl1 = 0x80000000 | command;
 198
 199         /* Set RD or WR bits as appropriate */
 200         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
 201                 ctl1 |= (1<<26); /* rd */
 202                 /* Always 5 bytes, for now */
 203                 cafe->datalen = 4;
 204                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
 205                 adrbytes = 1;
 206         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
 207                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
 208                 ctl1 |= 1<<26; /* rd */
 209                 /* For now, assume just read to end of page */
 210                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
 211         } else if (command == NAND_CMD_SEQIN)
 212                 ctl1 |= 1<<25; /* wr */
 213
 214         /* Set number of address bytes */
 215         if (adrbytes)
 216                 ctl1 |= ((adrbytes-1)|8) << 27;
 217
 218         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
 219                 /* Ignore the first command of a pair; the hardware
 220                    deals with them both at once, later */
 221                 cafe->ctl1 = ctl1;
 222                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
 223                           cafe->ctl1, cafe->datalen);
 224                 return;
 225         }
 226         /* RNDOUT and READ0 commands need a following byte */
 227         if (command == NAND_CMD_RNDOUT)
 228                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
 229         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
 230                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
 231
 232  do_command:
 233         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
 234                 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
 235
 236         /* NB: The datasheet lies -- we really should be subtracting 1 here */
 237         cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
 238         cafe_writel(cafe, 0x90000000, NAND_IRQ);
 239         if (usedma && (ctl1 & (3<<25))) {
 240                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
 241                 /* If WR or RD bits set, set up DMA */
 242                 if (ctl1 & (1<<26)) {
 243                         /* It's a read */
 244                         dmactl |= (1<<29);
 245                         /* ... so it's done when the DMA is done, not just
 246                            the command. */
 247                         doneint = 0x10000000;
 248                 }
 249                 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
 250         }
 251         cafe->datalen = 0;
 252
 253         if (unlikely(regdebug)) {
 254                 int i;
 255                 printk("About to write command %08x to register 0\n", ctl1);
 256                 for (i=4; i< 0x5c; i+=4)
 257                         printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 258         }
 259
 260         cafe_writel(cafe, ctl1, NAND_CTRL1);
 261         /* Apply this short delay always to ensure that we do wait tWB in
 262          * any case on any machine. */
 263         ndelay(100);
 264
 265         if (1) {
 266                 int c = 500000;
 267                 uint32_t irqs;
 268
 269                 while (c--) {
 270                         irqs = cafe_readl(cafe, NAND_IRQ);
 271                         if (irqs & doneint)
 272                                 break;
 273                         udelay(1);
 274                         if (!(c % 100000))
 275                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
 276                         cpu_relax();
 277                 }
 278                 cafe_writel(cafe, doneint, NAND_IRQ);
 279                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
 280                              command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
 281         }
 282
 283         WARN_ON(cafe->ctl2 & (1<<30));
 284
 285         switch (command) {
 286
 287         case NAND_CMD_CACHEDPROG:
 288         case NAND_CMD_PAGEPROG:
 289         case NAND_CMD_ERASE1:
 290         case NAND_CMD_ERASE2:
 291         case NAND_CMD_SEQIN:
 292         case NAND_CMD_RNDIN:
 293         case NAND_CMD_STATUS:
 294         case NAND_CMD_DEPLETE1:
 295         case NAND_CMD_RNDOUT:
 296         case NAND_CMD_STATUS_ERROR:
 297         case NAND_CMD_STATUS_ERROR0:
 298         case NAND_CMD_STATUS_ERROR1:
 299         case NAND_CMD_STATUS_ERROR2:
 300         case NAND_CMD_STATUS_ERROR3:
 301                 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
 302                 return;
 303         }
 304         nand_wait_ready(mtd);
 305         cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
 306 }
 307
 308 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
 309 {
 310         //struct cafe_priv *cafe = mtd->priv;
 311         //      cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
 312 }
 313
 314 static int cafe_nand_interrupt(int irq, void *id)
 315 {
 316         struct mtd_info *mtd = id;
 317         struct cafe_priv *cafe = mtd->priv;
 318         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
 319         cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
 320         if (!irqs)
 321                 return IRQ_NONE;
 322
 323         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
 324         return IRQ_HANDLED;
 325 }
 326
 327 static void cafe_nand_bug(struct mtd_info *mtd)
 328 {
 329         BUG();
 330 }
 331
 332 static int cafe_nand_write_oob(struct mtd_info *mtd,
 333                                struct nand_chip *chip, int page)
 334 {
 335         int status = 0;
 336
 337         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 338         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 339         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 340         status = chip->waitfunc(mtd, chip);
 341
 342         return status & NAND_STATUS_FAIL ? -EIO : 0;
 343 }
 344
 345 /* Don't use -- use nand_read_oob_std for now */
 346 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 347                               int page, int sndcmd)
 348 {
 349         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 350         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 351         return 1;
 352 }
 353 /**
 354  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 355  * @mtd:        mtd info structure
 356  * @chip:       nand chip info structure
 357  * @buf:        buffer to store read data
 358  *
 359  * The hw generator calculates the error syndrome automatically. Therefor
 360  * we need a special oob layout and handling.
 361  */
 362 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 363                                uint8_t *buf)
 364 {
 365         struct cafe_priv *cafe = mtd->priv;
 366
 367         cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
 368                      cafe_readl(cafe, NAND_ECC_RESULT),
 369                      cafe_readl(cafe, NAND_ECC_SYN01));
 370
 371         chip->read_buf(mtd, buf, mtd->writesize);
 372         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 373
 374         if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
 375                 unsigned short syn[8];
 376                 int i;
 377
 378                 for (i=0; i<8; i+=2) {
 379                         uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
 380                         syn[i] = tmp & 0xfff;
 381                         syn[i+1] = (tmp >> 16) & 0xfff;
 382                 }
 383
 384                 if ((i = cafe_correct_ecc(buf, syn)) < 0) {
 385                         dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
 386                                 cafe_readl(cafe, NAND_ADDR2) * 2048);
 387                         for (i=0; i< 0x5c; i+=4)
 388                                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 389                         mtd->ecc_stats.failed++;
 390                 } else {
 391                         dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i);
 392                         mtd->ecc_stats.corrected += i;
 393                 }
 394         }
 395
 396
 397         return 0;
 398 }
 399
 400 static struct nand_ecclayout cafe_oobinfo_2048 = {
 401         .eccbytes = 14,
 402         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 403         .oobfree = {{14, 50}}
 404 };
 405
 406 /* Ick. The BBT code really ought to be able to work this bit out
 407    for itself from the above, at least for the 2KiB case */
 408 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
 409 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
 410
 411 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
 412 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
 413
 414
 415 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
 416         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 417                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 418         .offs = 14,
 419         .len = 4,
 420         .veroffs = 18,
 421         .maxblocks = 4,
 422         .pattern = cafe_bbt_pattern_2048
 423 };
 424
 425 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
 426         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 427                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 428         .offs = 14,
 429         .len = 4,
 430         .veroffs = 18,
 431         .maxblocks = 4,
 432         .pattern = cafe_mirror_pattern_2048
 433 };
 434
 435 static struct nand_ecclayout cafe_oobinfo_512 = {
 436         .eccbytes = 14,
 437         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 438         .oobfree = {{14, 2}}
 439 };
 440
 441 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
 442         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 443                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 444         .offs = 14,
 445         .len = 1,
 446         .veroffs = 15,
 447         .maxblocks = 4,
 448         .pattern = cafe_bbt_pattern_512
 449 };
 450
 451 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
 452         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 453                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 454         .offs = 14,
 455         .len = 1,
 456         .veroffs = 15,
 457         .maxblocks = 4,
 458         .pattern = cafe_mirror_pattern_512
 459 };
 460
 461
 462 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 463                                           struct nand_chip *chip, const uint8_t *buf)
 464 {
 465         struct cafe_priv *cafe = mtd->priv;
 466
 467         chip->write_buf(mtd, buf, mtd->writesize);
 468         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 469
 470         /* Set up ECC autogeneration */
 471         cafe->ctl2 |= (1<<30);
 472 }
 473
 474 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 475                                 const uint8_t *buf, int page, int cached, int raw)
 476 {
 477         int status;
 478
 479         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 480
 481         if (unlikely(raw))
 482                 chip->ecc.write_page_raw(mtd, chip, buf);
 483         else
 484                 chip->ecc.write_page(mtd, chip, buf);
 485
 486         /*
 487          * Cached progamming disabled for now, Not sure if its worth the
 488          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
 489          */
 490         cached = 0;
 491
 492         if (!cached || !(chip->options & NAND_CACHEPRG)) {
 493
 494                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 495                 status = chip->waitfunc(mtd, chip);
 496                 /*
 497                  * See if operation failed and additional status checks are
 498                  * available
 499                  */
 500                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 501                         status = chip->errstat(mtd, chip, FL_WRITING, status,
 502                                                page);
 503
 504                 if (status & NAND_STATUS_FAIL)
 505                         return -EIO;
 506         } else {
 507                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
 508                 status = chip->waitfunc(mtd, chip);
 509         }
 510
 511 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 512         /* Send command to read back the data */
 513         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 514
 515         if (chip->verify_buf(mtd, buf, mtd->writesize))
 516                 return -EIO;
 517 #endif
 518         return 0;
 519 }
 520
 521 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 522 {
 523         return 0;
 524 }
 525
 526 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 527                                      const struct pci_device_id *ent)
 528 {
 529         struct mtd_info *mtd;
 530         struct cafe_priv *cafe;
 531         uint32_t ctrl;
 532         int err = 0;
 533
 534         err = pci_enable_device(pdev);
 535         if (err)
 536                 return err;
 537
 538         pci_set_master(pdev);
 539
 540         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
 541         if (!mtd) {
 542                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
 543                 return  -ENOMEM;
 544         }
 545         cafe = (void *)(&mtd[1]);
 546
 547         mtd->priv = cafe;
 548         mtd->owner = THIS_MODULE;
 549
 550         cafe->pdev = pdev;
 551         cafe->mmio = pci_iomap(pdev, 0, 0);
 552         if (!cafe->mmio) {
 553                 dev_warn(&pdev->dev, "failed to iomap\n");
 554                 err = -ENOMEM;
 555                 goto out_free_mtd;
 556         }
 557         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
 558                                           &cafe->dmaaddr, GFP_KERNEL);
 559         if (!cafe->dmabuf) {
 560                 err = -ENOMEM;
 561                 goto out_ior;
 562         }
 563         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
 564
 565         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
 566         cafe->nand.dev_ready = cafe_device_ready;
 567         cafe->nand.read_byte = cafe_read_byte;
 568         cafe->nand.read_buf = cafe_read_buf;
 569         cafe->nand.write_buf = cafe_write_buf;
 570         cafe->nand.select_chip = cafe_select_chip;
 571
 572         cafe->nand.chip_delay = 0;
 573
 574         /* Enable the following for a flash based bad block table */
 575         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
 576
 577         if (skipbbt) {
 578                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
 579                 cafe->nand.block_bad = cafe_nand_block_bad;
 580         }
 581
 582         /* Start off by resetting the NAND controller completely */
 583         cafe_writel(cafe, 1, NAND_RESET);
 584         cafe_writel(cafe, 0, NAND_RESET);
 585
 586         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
 587
 588         /* Timings from Marvell's test code (not verified or calculated by us) */
 589         if (!slowtiming) {
 590                 cafe_writel(cafe, 0x01010a0a, NAND_TIMING1);
 591                 cafe_writel(cafe, 0x24121212, NAND_TIMING2);
 592                 cafe_writel(cafe, 0x11000000, NAND_TIMING3);
 593         } else {
 594                 cafe_writel(cafe, 0xffffffff, NAND_TIMING1);
 595                 cafe_writel(cafe, 0xffffffff, NAND_TIMING2);
 596                 cafe_writel(cafe, 0xffffffff, NAND_TIMING3);
 597         }
 598         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
 599         err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
 600         if (err) {
 601                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
 602
 603                 goto out_free_dma;
 604         }
 605 #if 1
 606         /* Disable master reset, enable NAND clock */
 607         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
 608         ctrl &= 0xffffeff0;
 609         ctrl |= 0x00007000;
 610         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
 611         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
 612         cafe_writel(cafe, 0, NAND_DMA_CTRL);
 613
 614         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
 615         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
 616
 617         /* Set up DMA address */
 618         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
 619         if (sizeof(cafe->dmaaddr) > 4)
 620                 /* Shift in two parts to shut the compiler up */
 621                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
 622         else
 623                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
 624
 625         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
 626                 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
 627
 628         /* Enable NAND IRQ in global IRQ mask register */
 629         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
 630         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
 631                 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
 632 #endif
 633 #if 1
 634         mtd->writesize=2048;
 635         mtd->oobsize = 0x40;
 636         memset(cafe->dmabuf, 0x5a, 2112);
 637         cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1);
 638         cafe->nand.read_byte(mtd);
 639         cafe->nand.read_byte(mtd);
 640         cafe->nand.read_byte(mtd);
 641         cafe->nand.read_byte(mtd);
 642         cafe->nand.read_byte(mtd);
 643 #endif
 644 #if 0
 645         cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0);
 646         //      nand_wait_ready(mtd);
 647         cafe->nand.read_byte(mtd);
 648         cafe->nand.read_byte(mtd);
 649         cafe->nand.read_byte(mtd);
 650         cafe->nand.read_byte(mtd);
 651 #endif
 652 #if 0
 653         writel(0x84600070, cafe->mmio);
 654         udelay(10);
 655         cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", cafe_readl(cafe, NAND_NONMEM));
 656 #endif
 657         /* Scan to find existance of the device */
 658         if (nand_scan_ident(mtd, 1)) {
 659                 err = -ENXIO;
 660                 goto out_irq;
 661         }
 662
 663         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
 664         if (mtd->writesize == 2048)
 665                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
 666
 667         /* Set up ECC according to the type of chip we found */
 668         if (mtd->writesize == 2048) {
 669                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
 670                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
 671                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
 672         } else if (mtd->writesize == 512) {
 673                 cafe->nand.ecc.layout = &cafe_oobinfo_512;
 674                 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
 675                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
 676         } else {
 677                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
 678                        mtd->writesize);
 679                 goto out_irq;
 680         }
 681         cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 682         cafe->nand.ecc.size = mtd->writesize;
 683         cafe->nand.ecc.bytes = 14;
 684         cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
 685         cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
 686         cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
 687         cafe->nand.write_page = cafe_nand_write_page;
 688         cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
 689         cafe->nand.ecc.write_oob = cafe_nand_write_oob;
 690         cafe->nand.ecc.read_page = cafe_nand_read_page;
 691         cafe->nand.ecc.read_oob = cafe_nand_read_oob;
 692
 693         err = nand_scan_tail(mtd);
 694         if (err)
 695                 goto out_irq;
 696
 697         pci_set_drvdata(pdev, mtd);
 698         add_mtd_device(mtd);
 699         goto out;
 700
 701  out_irq:
 702         /* Disable NAND IRQ in global IRQ mask register */
 703         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
 704         free_irq(pdev->irq, mtd);
 705  out_free_dma:
 706         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 707  out_ior:
 708         pci_iounmap(pdev, cafe->mmio);
 709  out_free_mtd:
 710         kfree(mtd);
 711  out:
 712         return err;
 713 }
 714
 715 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
 716 {
 717         struct mtd_info *mtd = pci_get_drvdata(pdev);
 718         struct cafe_priv *cafe = mtd->priv;
 719
 720         del_mtd_device(mtd);
 721         /* Disable NAND IRQ in global IRQ mask register */
 722         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
 723         free_irq(pdev->irq, mtd);
 724         nand_release(mtd);
 725         pci_iounmap(pdev, cafe->mmio);
 726         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 727         kfree(mtd);
 728 }
 729
 730 static struct pci_device_id cafe_nand_tbl[] = {
 731         { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
 732 };
 733
 734 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
 735
 736 static struct pci_driver cafe_nand_pci_driver = {
 737         .name = "CAFÉ NAND",
 738         .id_table = cafe_nand_tbl,
 739         .probe = cafe_nand_probe,
 740         .remove = __devexit_p(cafe_nand_remove),
 741 #ifdef CONFIG_PMx
 742         .suspend = cafe_nand_suspend,
 743         .resume = cafe_nand_resume,
 744 #endif
 745 };
 746
 747 static int cafe_nand_init(void)
 748 {
 749         return pci_register_driver(&cafe_nand_pci_driver);
 750 }
 751
 752 static void cafe_nand_exit(void)
 753 {
 754         pci_unregister_driver(&cafe_nand_pci_driver);
 755 }
 756 module_init(cafe_nand_init);
 757 module_exit(cafe_nand_exit);
 758
 759 MODULE_LICENSE("GPL");
 760 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 761 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip");
 762
 763 /* Correct ECC for 2048 bytes of 0xff:
 764    41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */
 765
 766 /* dwmw2's B-test board, in case of completely screwing it:
 767 Bad eraseblock 2394 at 0x12b40000
 768 Bad eraseblock 2627 at 0x14860000
 769 Bad eraseblock 3349 at 0x1a2a0000
 770 */