drivers/mtd/nand/bf5xx_nand.c

   1 /* linux/drivers/mtd/nand/bf5xx_nand.c
   2  *
   3  * Copyright 2006-2008 Analog Devices Inc.
   4  *      http://blackfin.uclinux.org/
   5  *      Bryan Wu <bryan.wu@analog.com>
   6  *
   7  * Blackfin BF5xx on-chip NAND flash controller driver
   8  *
   9  * Derived from drivers/mtd/nand/s3c2410.c
  10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
  11  *
  12  * Derived from drivers/mtd/nand/cafe.c
  13  * Copyright © 2006 Red Hat, Inc.
  14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
  15  *
  16  * Changelog:
  17  *      12-Jun-2007  Bryan Wu:  Initial version
  18  *      18-Jul-2007  Bryan Wu:
  19  *              - ECC_HW and ECC_SW supported
  20  *              - DMA supported in ECC_HW
  21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
  22  *
  23  * TODO:
  24  *      Enable JFFS2 over NAND as rootfs
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License as published by
  28  * the Free Software Foundation; either version 2 of the License, or
  29  * (at your option) any later version.
  30  *
  31  * This program is distributed in the hope that it will be useful,
  32  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  * GNU General Public License for more details.
  35  *
  36  * You should have received a copy of the GNU General Public License
  37  * along with this program; if not, write to the Free Software
  38  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  39 */
  40
  41 #include <linux/module.h>
  42 #include <linux/types.h>
  43 #include <linux/init.h>
  44 #include <linux/kernel.h>
  45 #include <linux/string.h>
  46 #include <linux/ioport.h>
  47 #include <linux/platform_device.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/err.h>
  51 #include <linux/slab.h>
  52 #include <linux/io.h>
  53 #include <linux/bitops.h>
  54
  55 #include <linux/mtd/mtd.h>
  56 #include <linux/mtd/nand.h>
  57 #include <linux/mtd/nand_ecc.h>
  58 #include <linux/mtd/partitions.h>
  59
  60 #include <asm/blackfin.h>
  61 #include <asm/dma.h>
  62 #include <asm/cacheflush.h>
  63 #include <asm/nand.h>
  64 #include <asm/portmux.h>
  65
  66 #define DRV_NAME        "bf5xx-nand"
  67 #define DRV_VERSION     "1.2"
  68 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
  69 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
  70
  71 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
  72 static int hardware_ecc = 1;
  73 #else
  74 static int hardware_ecc;
  75 #endif
  76
  77 static const unsigned short bfin_nfc_pin_req[] =
  78         {P_NAND_CE,
  79          P_NAND_RB,
  80          P_NAND_D0,
  81          P_NAND_D1,
  82          P_NAND_D2,
  83          P_NAND_D3,
  84          P_NAND_D4,
  85          P_NAND_D5,
  86          P_NAND_D6,
  87          P_NAND_D7,
  88          P_NAND_WE,
  89          P_NAND_RE,
  90          P_NAND_CLE,
  91          P_NAND_ALE,
  92          0};
  93
  94 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
  95 static uint8_t bbt_pattern[] = { 0xff };
  96
  97 static struct nand_bbt_descr bootrom_bbt = {
  98         .options = 0,
  99         .offs = 63,
 100         .len = 1,
 101         .pattern = bbt_pattern,
 102 };
 103
 104 static struct nand_ecclayout bootrom_ecclayout = {
 105         .eccbytes = 24,
 106         .eccpos = {
 107                 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
 108                 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
 109                 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
 110                 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
 111                 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
 112                 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
 113                 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
 114                 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
 115         },
 116         .oobfree = {
 117                 { 0x8 * 0 + 3, 5 },
 118                 { 0x8 * 1 + 3, 5 },
 119                 { 0x8 * 2 + 3, 5 },
 120                 { 0x8 * 3 + 3, 5 },
 121                 { 0x8 * 4 + 3, 5 },
 122                 { 0x8 * 5 + 3, 5 },
 123                 { 0x8 * 6 + 3, 5 },
 124                 { 0x8 * 7 + 3, 5 },
 125         }
 126 };
 127 #endif
 128
 129 /*
 130  * Data structures for bf5xx nand flash controller driver
 131  */
 132
 133 /* bf5xx nand info */
 134 struct bf5xx_nand_info {
 135         /* mtd info */
 136         struct nand_hw_control          controller;
 137         struct mtd_info                 mtd;
 138         struct nand_chip                chip;
 139
 140         /* platform info */
 141         struct bf5xx_nand_platform      *platform;
 142
 143         /* device info */
 144         struct device                   *device;
 145
 146         /* DMA stuff */
 147         struct completion               dma_completion;
 148 };
 149
 150 /*
 151  * Conversion functions
 152  */
 153 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
 154 {
 155         return container_of(mtd, struct bf5xx_nand_info, mtd);
 156 }
 157
 158 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
 159 {
 160         return platform_get_drvdata(pdev);
 161 }
 162
 163 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
 164 {
 165         return pdev->dev.platform_data;
 166 }
 167
 168 /*
 169  * struct nand_chip interface function pointers
 170  */
 171
 172 /*
 173  * bf5xx_nand_hwcontrol
 174  *
 175  * Issue command and address cycles to the chip
 176  */
 177 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 178                                    unsigned int ctrl)
 179 {
 180         if (cmd == NAND_CMD_NONE)
 181                 return;
 182
 183         while (bfin_read_NFC_STAT() & WB_FULL)
 184                 cpu_relax();
 185
 186         if (ctrl & NAND_CLE)
 187                 bfin_write_NFC_CMD(cmd);
 188         else
 189                 bfin_write_NFC_ADDR(cmd);
 190         SSYNC();
 191 }
 192
 193 /*
 194  * bf5xx_nand_devready()
 195  *
 196  * returns 0 if the nand is busy, 1 if it is ready
 197  */
 198 static int bf5xx_nand_devready(struct mtd_info *mtd)
 199 {
 200         unsigned short val = bfin_read_NFC_IRQSTAT();
 201
 202         if ((val & NBUSYIRQ) == NBUSYIRQ)
 203                 return 1;
 204         else
 205                 return 0;
 206 }
 207
 208 /*
 209  * ECC functions
 210  * These allow the bf5xx to use the controller's ECC
 211  * generator block to ECC the data as it passes through
 212  */
 213
 214 /*
 215  * ECC error correction function
 216  */
 217 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
 218                                         u_char *read_ecc, u_char *calc_ecc)
 219 {
 220         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 221         u32 syndrome[5];
 222         u32 calced, stored;
 223         int i;
 224         unsigned short failing_bit, failing_byte;
 225         u_char data;
 226
 227         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
 228         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
 229
 230         syndrome[0] = (calced ^ stored);
 231
 232         /*
 233          * syndrome 0: all zero
 234          * No error in data
 235          * No action
 236          */
 237         if (!syndrome[0] || !calced || !stored)
 238                 return 0;
 239
 240         /*
 241          * sysdrome 0: only one bit is one
 242          * ECC data was incorrect
 243          * No action
 244          */
 245         if (hweight32(syndrome[0]) == 1) {
 246                 dev_err(info->device, "ECC data was incorrect!\n");
 247                 return 1;
 248         }
 249
 250         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
 251         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
 252         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
 253         syndrome[4] = syndrome[2] ^ syndrome[3];
 254
 255         for (i = 0; i < 5; i++)
 256                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
 257
 258         dev_info(info->device,
 259                 "calced[0x%08x], stored[0x%08x]\n",
 260                 calced, stored);
 261
 262         /*
 263          * sysdrome 0: exactly 11 bits are one, each parity
 264          * and parity' pair is 1 & 0 or 0 & 1.
 265          * 1-bit correctable error
 266          * Correct the error
 267          */
 268         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
 269                 dev_info(info->device,
 270                         "1-bit correctable error, correct it.\n");
 271                 dev_info(info->device,
 272                         "syndrome[1] 0x%08x\n", syndrome[1]);
 273
 274                 failing_bit = syndrome[1] & 0x7;
 275                 failing_byte = syndrome[1] >> 0x3;
 276                 data = *(dat + failing_byte);
 277                 data = data ^ (0x1 << failing_bit);
 278                 *(dat + failing_byte) = data;
 279
 280                 return 0;
 281         }
 282
 283         /*
 284          * sysdrome 0: random data
 285          * More than 1-bit error, non-correctable error
 286          * Discard data, mark bad block
 287          */
 288         dev_err(info->device,
 289                 "More than 1-bit error, non-correctable error.\n");
 290         dev_err(info->device,
 291                 "Please discard data, mark bad block\n");
 292
 293         return 1;
 294 }
 295
 296 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 297                                         u_char *read_ecc, u_char *calc_ecc)
 298 {
 299         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 300         struct bf5xx_nand_platform *plat = info->platform;
 301         unsigned short page_size = (plat->page_size ? 512 : 256);
 302         int ret;
 303
 304         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 305
 306         /* If page size is 512, correct second 256 bytes */
 307         if (page_size == 512) {
 308                 dat += 256;
 309                 read_ecc += 8;
 310                 calc_ecc += 8;
 311                 ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 312         }
 313
 314         return ret;
 315 }
 316
 317 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 318 {
 319         return;
 320 }
 321
 322 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
 323                 const u_char *dat, u_char *ecc_code)
 324 {
 325         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 326         struct bf5xx_nand_platform *plat = info->platform;
 327         u16 page_size = (plat->page_size ? 512 : 256);
 328         u16 ecc0, ecc1;
 329         u32 code[2];
 330         u8 *p;
 331
 332         /* first 4 bytes ECC code for 256 page size */
 333         ecc0 = bfin_read_NFC_ECC0();
 334         ecc1 = bfin_read_NFC_ECC1();
 335
 336         code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 337
 338         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
 339
 340         /* first 3 bytes in ecc_code for 256 page size */
 341         p = (u8 *) code;
 342         memcpy(ecc_code, p, 3);
 343
 344         /* second 4 bytes ECC code for 512 page size */
 345         if (page_size == 512) {
 346                 ecc0 = bfin_read_NFC_ECC2();
 347                 ecc1 = bfin_read_NFC_ECC3();
 348                 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 349
 350                 /* second 3 bytes in ecc_code for second 256
 351                  * bytes of 512 page size
 352                  */
 353                 p = (u8 *) (code + 1);
 354                 memcpy((ecc_code + 3), p, 3);
 355                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
 356         }
 357
 358         return 0;
 359 }
 360
 361 /*
 362  * PIO mode for buffer writing and reading
 363  */
 364 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 365 {
 366         int i;
 367         unsigned short val;
 368
 369         /*
 370          * Data reads are requested by first writing to NFC_DATA_RD
 371          * and then reading back from NFC_READ.
 372          */
 373         for (i = 0; i < len; i++) {
 374                 while (bfin_read_NFC_STAT() & WB_FULL)
 375                         cpu_relax();
 376
 377                 /* Contents do not matter */
 378                 bfin_write_NFC_DATA_RD(0x0000);
 379                 SSYNC();
 380
 381                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
 382                         cpu_relax();
 383
 384                 buf[i] = bfin_read_NFC_READ();
 385
 386                 val = bfin_read_NFC_IRQSTAT();
 387                 val |= RD_RDY;
 388                 bfin_write_NFC_IRQSTAT(val);
 389                 SSYNC();
 390         }
 391 }
 392
 393 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
 394 {
 395         uint8_t val;
 396
 397         bf5xx_nand_read_buf(mtd, &val, 1);
 398
 399         return val;
 400 }
 401
 402 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
 403                                 const uint8_t *buf, int len)
 404 {
 405         int i;
 406
 407         for (i = 0; i < len; i++) {
 408                 while (bfin_read_NFC_STAT() & WB_FULL)
 409                         cpu_relax();
 410
 411                 bfin_write_NFC_DATA_WR(buf[i]);
 412                 SSYNC();
 413         }
 414 }
 415
 416 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 417 {
 418         int i;
 419         u16 *p = (u16 *) buf;
 420         len >>= 1;
 421
 422         /*
 423          * Data reads are requested by first writing to NFC_DATA_RD
 424          * and then reading back from NFC_READ.
 425          */
 426         bfin_write_NFC_DATA_RD(0x5555);
 427
 428         SSYNC();
 429
 430         for (i = 0; i < len; i++)
 431                 p[i] = bfin_read_NFC_READ();
 432 }
 433
 434 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
 435                                 const uint8_t *buf, int len)
 436 {
 437         int i;
 438         u16 *p = (u16 *) buf;
 439         len >>= 1;
 440
 441         for (i = 0; i < len; i++)
 442                 bfin_write_NFC_DATA_WR(p[i]);
 443
 444         SSYNC();
 445 }
 446
 447 /*
 448  * DMA functions for buffer writing and reading
 449  */
 450 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
 451 {
 452         struct bf5xx_nand_info *info = dev_id;
 453
 454         clear_dma_irqstat(CH_NFC);
 455         disable_dma(CH_NFC);
 456         complete(&info->dma_completion);
 457
 458         return IRQ_HANDLED;
 459 }
 460
 461 static int bf5xx_nand_dma_rw(struct mtd_info *mtd,
 462                                 uint8_t *buf, int is_read)
 463 {
 464         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 465         struct bf5xx_nand_platform *plat = info->platform;
 466         unsigned short page_size = (plat->page_size ? 512 : 256);
 467         unsigned short val;
 468
 469         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
 470                         mtd, buf, is_read);
 471
 472         /*
 473          * Before starting a dma transfer, be sure to invalidate/flush
 474          * the cache over the address range of your DMA buffer to
 475          * prevent cache coherency problems. Otherwise very subtle bugs
 476          * can be introduced to your driver.
 477          */
 478         if (is_read)
 479                 invalidate_dcache_range((unsigned int)buf,
 480                                 (unsigned int)(buf + page_size));
 481         else
 482                 flush_dcache_range((unsigned int)buf,
 483                                 (unsigned int)(buf + page_size));
 484
 485         /*
 486          * This register must be written before each page is
 487          * transferred to generate the correct ECC register
 488          * values.
 489          */
 490         bfin_write_NFC_RST(0x1);
 491         SSYNC();
 492
 493         disable_dma(CH_NFC);
 494         clear_dma_irqstat(CH_NFC);
 495
 496         /* setup DMA register with Blackfin DMA API */
 497         set_dma_config(CH_NFC, 0x0);
 498         set_dma_start_addr(CH_NFC, (unsigned long) buf);
 499         set_dma_x_count(CH_NFC, (page_size >> 2));
 500         set_dma_x_modify(CH_NFC, 4);
 501
 502         /* setup write or read operation */
 503         val = DI_EN | WDSIZE_32;
 504         if (is_read)
 505                 val |= WNR;
 506         set_dma_config(CH_NFC, val);
 507         enable_dma(CH_NFC);
 508
 509         /* Start PAGE read/write operation */
 510         if (is_read)
 511                 bfin_write_NFC_PGCTL(0x1);
 512         else
 513                 bfin_write_NFC_PGCTL(0x2);
 514         wait_for_completion(&info->dma_completion);
 515
 516         return 0;
 517 }
 518
 519 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
 520                                         uint8_t *buf, int len)
 521 {
 522         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 523         struct bf5xx_nand_platform *plat = info->platform;
 524         unsigned short page_size = (plat->page_size ? 512 : 256);
 525
 526         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
 527
 528         if (len == page_size)
 529                 bf5xx_nand_dma_rw(mtd, buf, 1);
 530         else
 531                 bf5xx_nand_read_buf(mtd, buf, len);
 532 }
 533
 534 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
 535                                 const uint8_t *buf, int len)
 536 {
 537         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 538         struct bf5xx_nand_platform *plat = info->platform;
 539         unsigned short page_size = (plat->page_size ? 512 : 256);
 540
 541         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
 542
 543         if (len == page_size)
 544                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
 545         else
 546                 bf5xx_nand_write_buf(mtd, buf, len);
 547 }
 548
 549 /*
 550  * System initialization functions
 551  */
 552 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
 553 {
 554         int ret;
 555
 556         /* Do not use dma */
 557         if (!hardware_ecc)
 558                 return 0;
 559
 560         init_completion(&info->dma_completion);
 561
 562         /* Request NFC DMA channel */
 563         ret = request_dma(CH_NFC, "BF5XX NFC driver");
 564         if (ret < 0) {
 565                 dev_err(info->device, " unable to get DMA channel\n");
 566                 return ret;
 567         }
 568
 569 #ifdef CONFIG_BF54x
 570         /* Setup DMAC1 channel mux for NFC which shared with SDH */
 571         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
 572         SSYNC();
 573 #endif
 574
 575         set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
 576
 577         /* Turn off the DMA channel first */
 578         disable_dma(CH_NFC);
 579         return 0;
 580 }
 581
 582 static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
 583 {
 584         /* Free NFC DMA channel */
 585         if (hardware_ecc)
 586                 free_dma(CH_NFC);
 587 }
 588
 589 /*
 590  * BF5XX NFC hardware initialization
 591  *  - pin mux setup
 592  *  - clear interrupt status
 593  */
 594 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
 595 {
 596         int err = 0;
 597         unsigned short val;
 598         struct bf5xx_nand_platform *plat = info->platform;
 599
 600         /* setup NFC_CTL register */
 601         dev_info(info->device,
 602                 "page_size=%d, data_width=%d, wr_dly=%d, rd_dly=%d\n",
 603                 (plat->page_size ? 512 : 256),
 604                 (plat->data_width ? 16 : 8),
 605                 plat->wr_dly, plat->rd_dly);
 606
 607         val = (plat->page_size << NFC_PG_SIZE_OFFSET) |
 608                 (plat->data_width << NFC_NWIDTH_OFFSET) |
 609                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
 610                 (plat->rd_dly << NFC_WRDLY_OFFSET);
 611         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
 612
 613         bfin_write_NFC_CTL(val);
 614         SSYNC();
 615
 616         /* clear interrupt status */
 617         bfin_write_NFC_IRQMASK(0x0);
 618         SSYNC();
 619         val = bfin_read_NFC_IRQSTAT();
 620         bfin_write_NFC_IRQSTAT(val);
 621         SSYNC();
 622
 623         /* DMA initialization  */
 624         if (bf5xx_nand_dma_init(info))
 625                 err = -ENXIO;
 626
 627         return err;
 628 }
 629
 630 /*
 631  * Device management interface
 632  */
 633 static int __devinit bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
 634 {
 635         struct mtd_info *mtd = &info->mtd;
 636
 637 #ifdef CONFIG_MTD_PARTITIONS
 638         struct mtd_partition *parts = info->platform->partitions;
 639         int nr = info->platform->nr_partitions;
 640
 641         return add_mtd_partitions(mtd, parts, nr);
 642 #else
 643         return add_mtd_device(mtd);
 644 #endif
 645 }
 646
 647 static int __devexit bf5xx_nand_remove(struct platform_device *pdev)
 648 {
 649         struct bf5xx_nand_info *info = to_nand_info(pdev);
 650         struct mtd_info *mtd = NULL;
 651
 652         platform_set_drvdata(pdev, NULL);
 653
 654         /* first thing we need to do is release all our mtds
 655          * and their partitions, then go through freeing the
 656          * resources used
 657          */
 658         mtd = &info->mtd;
 659         if (mtd) {
 660                 nand_release(mtd);
 661                 kfree(mtd);
 662         }
 663
 664         peripheral_free_list(bfin_nfc_pin_req);
 665         bf5xx_nand_dma_remove(info);
 666
 667         /* free the common resources */
 668         kfree(info);
 669
 670         return 0;
 671 }
 672
 673 /*
 674  * bf5xx_nand_probe
 675  *
 676  * called by device layer when it finds a device matching
 677  * one our driver can handled. This code checks to see if
 678  * it can allocate all necessary resources then calls the
 679  * nand layer to look for devices
 680  */
 681 static int __devinit bf5xx_nand_probe(struct platform_device *pdev)
 682 {
 683         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
 684         struct bf5xx_nand_info *info = NULL;
 685         struct nand_chip *chip = NULL;
 686         struct mtd_info *mtd = NULL;
 687         int err = 0;
 688
 689         dev_dbg(&pdev->dev, "(%p)\n", pdev);
 690
 691         if (!plat) {
 692                 dev_err(&pdev->dev, "no platform specific information\n");
 693                 return -EINVAL;
 694         }
 695
 696         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
 697                 dev_err(&pdev->dev, "requesting Peripherals failed\n");
 698                 return -EFAULT;
 699         }
 700
 701         info = kzalloc(sizeof(*info), GFP_KERNEL);
 702         if (info == NULL) {
 703                 dev_err(&pdev->dev, "no memory for flash info\n");
 704                 err = -ENOMEM;
 705                 goto out_err_kzalloc;
 706         }
 707
 708         platform_set_drvdata(pdev, info);
 709
 710         spin_lock_init(&info->controller.lock);
 711         init_waitqueue_head(&info->controller.wq);
 712
 713         info->device     = &pdev->dev;
 714         info->platform   = plat;
 715
 716         /* initialise chip data struct */
 717         chip = &info->chip;
 718
 719         if (plat->data_width)
 720                 chip->options |= NAND_BUSWIDTH_16;
 721
 722         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
 723
 724         chip->read_buf = (plat->data_width) ?
 725                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
 726         chip->write_buf = (plat->data_width) ?
 727                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
 728
 729         chip->read_byte    = bf5xx_nand_read_byte;
 730
 731         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
 732         chip->dev_ready    = bf5xx_nand_devready;
 733
 734         chip->priv         = &info->mtd;
 735         chip->controller   = &info->controller;
 736
 737         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
 738         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
 739
 740         chip->chip_delay   = 0;
 741
 742         /* initialise mtd info data struct */
 743         mtd             = &info->mtd;
 744         mtd->priv       = chip;
 745         mtd->owner      = THIS_MODULE;
 746
 747         /* initialise the hardware */
 748         err = bf5xx_nand_hw_init(info);
 749         if (err)
 750                 goto out_err_hw_init;
 751
 752         /* setup hardware ECC data struct */
 753         if (hardware_ecc) {
 754 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 755                 chip->badblock_pattern = &bootrom_bbt;
 756                 chip->ecc.layout = &bootrom_ecclayout;
 757 #endif
 758
 759                 if (plat->page_size == NFC_PG_SIZE_256) {
 760                         chip->ecc.bytes = 3;
 761                         chip->ecc.size = 256;
 762                 } else if (plat->page_size == NFC_PG_SIZE_512) {
 763                         chip->ecc.bytes = 6;
 764                         chip->ecc.size = 512;
 765                 }
 766
 767                 chip->read_buf      = bf5xx_nand_dma_read_buf;
 768                 chip->write_buf     = bf5xx_nand_dma_write_buf;
 769                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
 770                 chip->ecc.correct   = bf5xx_nand_correct_data;
 771                 chip->ecc.mode      = NAND_ECC_HW;
 772                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
 773         } else {
 774                 chip->ecc.mode      = NAND_ECC_SOFT;
 775         }
 776
 777         /* scan hardware nand chip and setup mtd info data struct */
 778         if (nand_scan(mtd, 1)) {
 779                 err = -ENXIO;
 780                 goto out_err_nand_scan;
 781         }
 782
 783         /* add NAND partition */
 784         bf5xx_nand_add_partition(info);
 785
 786         dev_dbg(&pdev->dev, "initialised ok\n");
 787         return 0;
 788
 789 out_err_nand_scan:
 790         bf5xx_nand_dma_remove(info);
 791 out_err_hw_init:
 792         platform_set_drvdata(pdev, NULL);
 793         kfree(info);
 794 out_err_kzalloc:
 795         peripheral_free_list(bfin_nfc_pin_req);
 796
 797         return err;
 798 }
 799
 800 /* PM Support */
 801 #ifdef CONFIG_PM
 802
 803 static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
 804 {
 805         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 806
 807         return 0;
 808 }
 809
 810 static int bf5xx_nand_resume(struct platform_device *dev)
 811 {
 812         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 813
 814         return 0;
 815 }
 816
 817 #else
 818 #define bf5xx_nand_suspend NULL
 819 #define bf5xx_nand_resume NULL
 820 #endif
 821
 822 /* driver device registration */
 823 static struct platform_driver bf5xx_nand_driver = {
 824         .probe          = bf5xx_nand_probe,
 825         .remove         = __devexit_p(bf5xx_nand_remove),
 826         .suspend        = bf5xx_nand_suspend,
 827         .resume         = bf5xx_nand_resume,
 828         .driver         = {
 829                 .name   = DRV_NAME,
 830                 .owner  = THIS_MODULE,
 831         },
 832 };
 833
 834 static int __init bf5xx_nand_init(void)
 835 {
 836         printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n",
 837                 DRV_DESC, DRV_VERSION);
 838
 839         return platform_driver_register(&bf5xx_nand_driver);
 840 }
 841
 842 static void __exit bf5xx_nand_exit(void)
 843 {
 844         platform_driver_unregister(&bf5xx_nand_driver);
 845 }
 846
 847 module_init(bf5xx_nand_init);
 848 module_exit(bf5xx_nand_exit);
 849
 850 MODULE_LICENSE("GPL");
 851 MODULE_AUTHOR(DRV_AUTHOR);
 852 MODULE_DESCRIPTION(DRV_DESC);
 853 MODULE_ALIAS("platform:" DRV_NAME);