Merge tag 'for-linus-20170904' of git://git.infradead.org/linux-mtd
[sfrench/cifs-2.6.git] / drivers / mtd / nand / atmel / nand-controller.c
1 /*
2  * Copyright 2017 ATMEL
3  * Copyright 2017 Free Electrons
4  *
5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6  *
7  * Derived from the atmel_nand.c driver which contained the following
8  * copyrights:
9  *
10  *   Copyright 2003 Rick Bronson
11  *
12  *   Derived from drivers/mtd/nand/autcpu12.c
13  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
14  *
15  *   Derived from drivers/mtd/spia.c
16  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
17  *
18  *
19  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
21  *
22  *   Derived from Das U-Boot source code
23  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
25  *
26  *   Add Programmable Multibit ECC support for various AT91 SoC
27  *      Copyright 2012 ATMEL, Hong Xu
28  *
29  *   Add Nand Flash Controller support for SAMA5 SoC
30  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
31  *
32  * This program is free software; you can redistribute it and/or modify
33  * it under the terms of the GNU General Public License version 2 as
34  * published by the Free Software Foundation.
35  *
36  * A few words about the naming convention in this file. This convention
37  * applies to structure and function names.
38  *
39  * Prefixes:
40  *
41  * - atmel_nand_: all generic structures/functions
42  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43  *                    (at91sam9 and avr32 SoCs)
44  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45  *                     (sama5 SoCs and later)
46  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47  *               that is available in the HSMC block
48  * - <soc>_nand_: all SoC specific structures/functions
49  */
50
51 #include <linux/clk.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/dmaengine.h>
54 #include <linux/genalloc.h>
55 #include <linux/gpio.h>
56 #include <linux/gpio/consumer.h>
57 #include <linux/interrupt.h>
58 #include <linux/mfd/syscon.h>
59 #include <linux/mfd/syscon/atmel-matrix.h>
60 #include <linux/mfd/syscon/atmel-smc.h>
61 #include <linux/module.h>
62 #include <linux/mtd/rawnand.h>
63 #include <linux/of_address.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_platform.h>
66 #include <linux/iopoll.h>
67 #include <linux/platform_device.h>
68 #include <linux/regmap.h>
69
70 #include "pmecc.h"
71
72 #define ATMEL_HSMC_NFC_CFG                      0x0
73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
74 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
75 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
76 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
77 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
78 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
79 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
80 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
82 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
83
84 #define ATMEL_HSMC_NFC_CTRL                     0x4
85 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
86 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
87
88 #define ATMEL_HSMC_NFC_SR                       0x8
89 #define ATMEL_HSMC_NFC_IER                      0xc
90 #define ATMEL_HSMC_NFC_IDR                      0x10
91 #define ATMEL_HSMC_NFC_IMR                      0x14
92 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
93 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
94 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
95 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
96 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
97 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
98 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
99 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
100 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
101 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
102 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
103 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
104 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
105                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
106                                                  ATMEL_HSMC_NFC_SR_AWB | \
107                                                  ATMEL_HSMC_NFC_SR_NFCASE)
108 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
109
110 #define ATMEL_HSMC_NFC_ADDR                     0x18
111 #define ATMEL_HSMC_NFC_BANK                     0x1c
112
113 #define ATMEL_NFC_MAX_RB_ID                     7
114
115 #define ATMEL_NFC_SRAM_SIZE                     0x2400
116
117 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
118 #define ATMEL_NFC_VCMD2                         BIT(18)
119 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
120 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
121 #define ATMEL_NFC_DATAEN                        BIT(25)
122 #define ATMEL_NFC_NFCWR                         BIT(26)
123
124 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
125
126 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
127 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
128
129 #define DEFAULT_TIMEOUT_MS                      1000
130 #define MIN_DMA_LEN                             128
131
132 enum atmel_nand_rb_type {
133         ATMEL_NAND_NO_RB,
134         ATMEL_NAND_NATIVE_RB,
135         ATMEL_NAND_GPIO_RB,
136 };
137
138 struct atmel_nand_rb {
139         enum atmel_nand_rb_type type;
140         union {
141                 struct gpio_desc *gpio;
142                 int id;
143         };
144 };
145
146 struct atmel_nand_cs {
147         int id;
148         struct atmel_nand_rb rb;
149         struct gpio_desc *csgpio;
150         struct {
151                 void __iomem *virt;
152                 dma_addr_t dma;
153         } io;
154
155         struct atmel_smc_cs_conf smcconf;
156 };
157
158 struct atmel_nand {
159         struct list_head node;
160         struct device *dev;
161         struct nand_chip base;
162         struct atmel_nand_cs *activecs;
163         struct atmel_pmecc_user *pmecc;
164         struct gpio_desc *cdgpio;
165         int numcs;
166         struct atmel_nand_cs cs[];
167 };
168
169 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
170 {
171         return container_of(chip, struct atmel_nand, base);
172 }
173
174 enum atmel_nfc_data_xfer {
175         ATMEL_NFC_NO_DATA,
176         ATMEL_NFC_READ_DATA,
177         ATMEL_NFC_WRITE_DATA,
178 };
179
180 struct atmel_nfc_op {
181         u8 cs;
182         u8 ncmds;
183         u8 cmds[2];
184         u8 naddrs;
185         u8 addrs[5];
186         enum atmel_nfc_data_xfer data;
187         u32 wait;
188         u32 errors;
189 };
190
191 struct atmel_nand_controller;
192 struct atmel_nand_controller_caps;
193
194 struct atmel_nand_controller_ops {
195         int (*probe)(struct platform_device *pdev,
196                      const struct atmel_nand_controller_caps *caps);
197         int (*remove)(struct atmel_nand_controller *nc);
198         void (*nand_init)(struct atmel_nand_controller *nc,
199                           struct atmel_nand *nand);
200         int (*ecc_init)(struct atmel_nand *nand);
201         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
202                                     const struct nand_data_interface *conf);
203 };
204
205 struct atmel_nand_controller_caps {
206         bool has_dma;
207         bool legacy_of_bindings;
208         u32 ale_offs;
209         u32 cle_offs;
210         const struct atmel_nand_controller_ops *ops;
211 };
212
213 struct atmel_nand_controller {
214         struct nand_hw_control base;
215         const struct atmel_nand_controller_caps *caps;
216         struct device *dev;
217         struct regmap *smc;
218         struct dma_chan *dmac;
219         struct atmel_pmecc *pmecc;
220         struct list_head chips;
221         struct clk *mck;
222 };
223
224 static inline struct atmel_nand_controller *
225 to_nand_controller(struct nand_hw_control *ctl)
226 {
227         return container_of(ctl, struct atmel_nand_controller, base);
228 }
229
230 struct atmel_smc_nand_controller {
231         struct atmel_nand_controller base;
232         struct regmap *matrix;
233         unsigned int ebi_csa_offs;
234 };
235
236 static inline struct atmel_smc_nand_controller *
237 to_smc_nand_controller(struct nand_hw_control *ctl)
238 {
239         return container_of(to_nand_controller(ctl),
240                             struct atmel_smc_nand_controller, base);
241 }
242
243 struct atmel_hsmc_nand_controller {
244         struct atmel_nand_controller base;
245         struct {
246                 struct gen_pool *pool;
247                 void __iomem *virt;
248                 dma_addr_t dma;
249         } sram;
250         const struct atmel_hsmc_reg_layout *hsmc_layout;
251         struct regmap *io;
252         struct atmel_nfc_op op;
253         struct completion complete;
254         int irq;
255
256         /* Only used when instantiating from legacy DT bindings. */
257         struct clk *clk;
258 };
259
260 static inline struct atmel_hsmc_nand_controller *
261 to_hsmc_nand_controller(struct nand_hw_control *ctl)
262 {
263         return container_of(to_nand_controller(ctl),
264                             struct atmel_hsmc_nand_controller, base);
265 }
266
267 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
268 {
269         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
270         op->wait ^= status & op->wait;
271
272         return !op->wait || op->errors;
273 }
274
275 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
276 {
277         struct atmel_hsmc_nand_controller *nc = data;
278         u32 sr, rcvd;
279         bool done;
280
281         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
282
283         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
284         done = atmel_nfc_op_done(&nc->op, sr);
285
286         if (rcvd)
287                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
288
289         if (done)
290                 complete(&nc->complete);
291
292         return rcvd ? IRQ_HANDLED : IRQ_NONE;
293 }
294
295 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
296                           unsigned int timeout_ms)
297 {
298         int ret;
299
300         if (!timeout_ms)
301                 timeout_ms = DEFAULT_TIMEOUT_MS;
302
303         if (poll) {
304                 u32 status;
305
306                 ret = regmap_read_poll_timeout(nc->base.smc,
307                                                ATMEL_HSMC_NFC_SR, status,
308                                                atmel_nfc_op_done(&nc->op,
309                                                                  status),
310                                                0, timeout_ms * 1000);
311         } else {
312                 init_completion(&nc->complete);
313                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
314                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
315                 ret = wait_for_completion_timeout(&nc->complete,
316                                                 msecs_to_jiffies(timeout_ms));
317                 if (!ret)
318                         ret = -ETIMEDOUT;
319                 else
320                         ret = 0;
321
322                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
323         }
324
325         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
326                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
327                 ret = -ETIMEDOUT;
328         }
329
330         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
331                 dev_err(nc->base.dev, "Access to an undefined area\n");
332                 ret = -EIO;
333         }
334
335         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
336                 dev_err(nc->base.dev, "Access while busy\n");
337                 ret = -EIO;
338         }
339
340         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
341                 dev_err(nc->base.dev, "Wrong access size\n");
342                 ret = -EIO;
343         }
344
345         return ret;
346 }
347
348 static void atmel_nand_dma_transfer_finished(void *data)
349 {
350         struct completion *finished = data;
351
352         complete(finished);
353 }
354
355 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
356                                    void *buf, dma_addr_t dev_dma, size_t len,
357                                    enum dma_data_direction dir)
358 {
359         DECLARE_COMPLETION_ONSTACK(finished);
360         dma_addr_t src_dma, dst_dma, buf_dma;
361         struct dma_async_tx_descriptor *tx;
362         dma_cookie_t cookie;
363
364         buf_dma = dma_map_single(nc->dev, buf, len, dir);
365         if (dma_mapping_error(nc->dev, dev_dma)) {
366                 dev_err(nc->dev,
367                         "Failed to prepare a buffer for DMA access\n");
368                 goto err;
369         }
370
371         if (dir == DMA_FROM_DEVICE) {
372                 src_dma = dev_dma;
373                 dst_dma = buf_dma;
374         } else {
375                 src_dma = buf_dma;
376                 dst_dma = dev_dma;
377         }
378
379         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
380                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
381         if (!tx) {
382                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
383                 goto err_unmap;
384         }
385
386         tx->callback = atmel_nand_dma_transfer_finished;
387         tx->callback_param = &finished;
388
389         cookie = dmaengine_submit(tx);
390         if (dma_submit_error(cookie)) {
391                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
392                 goto err_unmap;
393         }
394
395         dma_async_issue_pending(nc->dmac);
396         wait_for_completion(&finished);
397
398         return 0;
399
400 err_unmap:
401         dma_unmap_single(nc->dev, buf_dma, len, dir);
402
403 err:
404         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
405
406         return -EIO;
407 }
408
409 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
410 {
411         struct nand_chip *chip = mtd_to_nand(mtd);
412         struct atmel_nand *nand = to_atmel_nand(chip);
413
414         return ioread8(nand->activecs->io.virt);
415 }
416
417 static u16 atmel_nand_read_word(struct mtd_info *mtd)
418 {
419         struct nand_chip *chip = mtd_to_nand(mtd);
420         struct atmel_nand *nand = to_atmel_nand(chip);
421
422         return ioread16(nand->activecs->io.virt);
423 }
424
425 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
426 {
427         struct nand_chip *chip = mtd_to_nand(mtd);
428         struct atmel_nand *nand = to_atmel_nand(chip);
429
430         if (chip->options & NAND_BUSWIDTH_16)
431                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
432         else
433                 iowrite8(byte, nand->activecs->io.virt);
434 }
435
436 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
437 {
438         struct nand_chip *chip = mtd_to_nand(mtd);
439         struct atmel_nand *nand = to_atmel_nand(chip);
440         struct atmel_nand_controller *nc;
441
442         nc = to_nand_controller(chip->controller);
443
444         /*
445          * If the controller supports DMA, the buffer address is DMA-able and
446          * len is long enough to make DMA transfers profitable, let's trigger
447          * a DMA transfer. If it fails, fallback to PIO mode.
448          */
449         if (nc->dmac && virt_addr_valid(buf) &&
450             len >= MIN_DMA_LEN &&
451             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
452                                      DMA_FROM_DEVICE))
453                 return;
454
455         if (chip->options & NAND_BUSWIDTH_16)
456                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
457         else
458                 ioread8_rep(nand->activecs->io.virt, buf, len);
459 }
460
461 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
462 {
463         struct nand_chip *chip = mtd_to_nand(mtd);
464         struct atmel_nand *nand = to_atmel_nand(chip);
465         struct atmel_nand_controller *nc;
466
467         nc = to_nand_controller(chip->controller);
468
469         /*
470          * If the controller supports DMA, the buffer address is DMA-able and
471          * len is long enough to make DMA transfers profitable, let's trigger
472          * a DMA transfer. If it fails, fallback to PIO mode.
473          */
474         if (nc->dmac && virt_addr_valid(buf) &&
475             len >= MIN_DMA_LEN &&
476             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
477                                      len, DMA_TO_DEVICE))
478                 return;
479
480         if (chip->options & NAND_BUSWIDTH_16)
481                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
482         else
483                 iowrite8_rep(nand->activecs->io.virt, buf, len);
484 }
485
486 static int atmel_nand_dev_ready(struct mtd_info *mtd)
487 {
488         struct nand_chip *chip = mtd_to_nand(mtd);
489         struct atmel_nand *nand = to_atmel_nand(chip);
490
491         return gpiod_get_value(nand->activecs->rb.gpio);
492 }
493
494 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
495 {
496         struct nand_chip *chip = mtd_to_nand(mtd);
497         struct atmel_nand *nand = to_atmel_nand(chip);
498
499         if (cs < 0 || cs >= nand->numcs) {
500                 nand->activecs = NULL;
501                 chip->dev_ready = NULL;
502                 return;
503         }
504
505         nand->activecs = &nand->cs[cs];
506
507         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
508                 chip->dev_ready = atmel_nand_dev_ready;
509 }
510
511 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
512 {
513         struct nand_chip *chip = mtd_to_nand(mtd);
514         struct atmel_nand *nand = to_atmel_nand(chip);
515         struct atmel_hsmc_nand_controller *nc;
516         u32 status;
517
518         nc = to_hsmc_nand_controller(chip->controller);
519
520         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
521
522         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
523 }
524
525 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
526 {
527         struct nand_chip *chip = mtd_to_nand(mtd);
528         struct atmel_nand *nand = to_atmel_nand(chip);
529         struct atmel_hsmc_nand_controller *nc;
530
531         nc = to_hsmc_nand_controller(chip->controller);
532
533         atmel_nand_select_chip(mtd, cs);
534
535         if (!nand->activecs) {
536                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
537                              ATMEL_HSMC_NFC_CTRL_DIS);
538                 return;
539         }
540
541         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
542                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
543
544         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
545                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
546                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
547                            ATMEL_HSMC_NFC_CFG_RSPARE |
548                            ATMEL_HSMC_NFC_CFG_WSPARE,
549                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
550                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
551                            ATMEL_HSMC_NFC_CFG_RSPARE);
552         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
553                      ATMEL_HSMC_NFC_CTRL_EN);
554 }
555
556 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
557 {
558         u8 *addrs = nc->op.addrs;
559         unsigned int op = 0;
560         u32 addr, val;
561         int i, ret;
562
563         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
564
565         for (i = 0; i < nc->op.ncmds; i++)
566                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
567
568         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
569                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
570
571         op |= ATMEL_NFC_CSID(nc->op.cs) |
572               ATMEL_NFC_ACYCLE(nc->op.naddrs);
573
574         if (nc->op.ncmds > 1)
575                 op |= ATMEL_NFC_VCMD2;
576
577         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
578                (addrs[3] << 24);
579
580         if (nc->op.data != ATMEL_NFC_NO_DATA) {
581                 op |= ATMEL_NFC_DATAEN;
582                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
583
584                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
585                         op |= ATMEL_NFC_NFCWR;
586         }
587
588         /* Clear all flags. */
589         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
590
591         /* Send the command. */
592         regmap_write(nc->io, op, addr);
593
594         ret = atmel_nfc_wait(nc, poll, 0);
595         if (ret)
596                 dev_err(nc->base.dev,
597                         "Failed to send NAND command (err = %d)!",
598                         ret);
599
600         /* Reset the op state. */
601         memset(&nc->op, 0, sizeof(nc->op));
602
603         return ret;
604 }
605
606 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
607                                      unsigned int ctrl)
608 {
609         struct nand_chip *chip = mtd_to_nand(mtd);
610         struct atmel_nand *nand = to_atmel_nand(chip);
611         struct atmel_hsmc_nand_controller *nc;
612
613         nc = to_hsmc_nand_controller(chip->controller);
614
615         if (ctrl & NAND_ALE) {
616                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
617                         return;
618
619                 nc->op.addrs[nc->op.naddrs++] = dat;
620         } else if (ctrl & NAND_CLE) {
621                 if (nc->op.ncmds > 1)
622                         return;
623
624                 nc->op.cmds[nc->op.ncmds++] = dat;
625         }
626
627         if (dat == NAND_CMD_NONE) {
628                 nc->op.cs = nand->activecs->id;
629                 atmel_nfc_exec_op(nc, true);
630         }
631 }
632
633 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
634                                 unsigned int ctrl)
635 {
636         struct nand_chip *chip = mtd_to_nand(mtd);
637         struct atmel_nand *nand = to_atmel_nand(chip);
638         struct atmel_nand_controller *nc;
639
640         nc = to_nand_controller(chip->controller);
641
642         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
643                 if (ctrl & NAND_NCE)
644                         gpiod_set_value(nand->activecs->csgpio, 0);
645                 else
646                         gpiod_set_value(nand->activecs->csgpio, 1);
647         }
648
649         if (ctrl & NAND_ALE)
650                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
651         else if (ctrl & NAND_CLE)
652                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
653 }
654
655 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
656                                    bool oob_required)
657 {
658         struct mtd_info *mtd = nand_to_mtd(chip);
659         struct atmel_hsmc_nand_controller *nc;
660         int ret = -EIO;
661
662         nc = to_hsmc_nand_controller(chip->controller);
663
664         if (nc->base.dmac)
665                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
666                                               nc->sram.dma, mtd->writesize,
667                                               DMA_TO_DEVICE);
668
669         /* Falling back to CPU copy. */
670         if (ret)
671                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
672
673         if (oob_required)
674                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
675                             mtd->oobsize);
676 }
677
678 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
679                                      bool oob_required)
680 {
681         struct mtd_info *mtd = nand_to_mtd(chip);
682         struct atmel_hsmc_nand_controller *nc;
683         int ret = -EIO;
684
685         nc = to_hsmc_nand_controller(chip->controller);
686
687         if (nc->base.dmac)
688                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
689                                               mtd->writesize, DMA_FROM_DEVICE);
690
691         /* Falling back to CPU copy. */
692         if (ret)
693                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
694
695         if (oob_required)
696                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
697                               mtd->oobsize);
698 }
699
700 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
701 {
702         struct mtd_info *mtd = nand_to_mtd(chip);
703         struct atmel_hsmc_nand_controller *nc;
704
705         nc = to_hsmc_nand_controller(chip->controller);
706
707         if (column >= 0) {
708                 nc->op.addrs[nc->op.naddrs++] = column;
709
710                 /*
711                  * 2 address cycles for the column offset on large page NANDs.
712                  */
713                 if (mtd->writesize > 512)
714                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
715         }
716
717         if (page >= 0) {
718                 nc->op.addrs[nc->op.naddrs++] = page;
719                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
720
721                 if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
722                     (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
723                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
724         }
725 }
726
727 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
728 {
729         struct atmel_nand *nand = to_atmel_nand(chip);
730         struct atmel_nand_controller *nc;
731         int ret;
732
733         nc = to_nand_controller(chip->controller);
734
735         if (raw)
736                 return 0;
737
738         ret = atmel_pmecc_enable(nand->pmecc, op);
739         if (ret)
740                 dev_err(nc->dev,
741                         "Failed to enable ECC engine (err = %d)\n", ret);
742
743         return ret;
744 }
745
746 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
747 {
748         struct atmel_nand *nand = to_atmel_nand(chip);
749
750         if (!raw)
751                 atmel_pmecc_disable(nand->pmecc);
752 }
753
754 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
755 {
756         struct atmel_nand *nand = to_atmel_nand(chip);
757         struct mtd_info *mtd = nand_to_mtd(chip);
758         struct atmel_nand_controller *nc;
759         struct mtd_oob_region oobregion;
760         void *eccbuf;
761         int ret, i;
762
763         nc = to_nand_controller(chip->controller);
764
765         if (raw)
766                 return 0;
767
768         ret = atmel_pmecc_wait_rdy(nand->pmecc);
769         if (ret) {
770                 dev_err(nc->dev,
771                         "Failed to transfer NAND page data (err = %d)\n",
772                         ret);
773                 return ret;
774         }
775
776         mtd_ooblayout_ecc(mtd, 0, &oobregion);
777         eccbuf = chip->oob_poi + oobregion.offset;
778
779         for (i = 0; i < chip->ecc.steps; i++) {
780                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
781                                                    eccbuf);
782                 eccbuf += chip->ecc.bytes;
783         }
784
785         return 0;
786 }
787
788 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
789                                          bool raw)
790 {
791         struct atmel_nand *nand = to_atmel_nand(chip);
792         struct mtd_info *mtd = nand_to_mtd(chip);
793         struct atmel_nand_controller *nc;
794         struct mtd_oob_region oobregion;
795         int ret, i, max_bitflips = 0;
796         void *databuf, *eccbuf;
797
798         nc = to_nand_controller(chip->controller);
799
800         if (raw)
801                 return 0;
802
803         ret = atmel_pmecc_wait_rdy(nand->pmecc);
804         if (ret) {
805                 dev_err(nc->dev,
806                         "Failed to read NAND page data (err = %d)\n",
807                         ret);
808                 return ret;
809         }
810
811         mtd_ooblayout_ecc(mtd, 0, &oobregion);
812         eccbuf = chip->oob_poi + oobregion.offset;
813         databuf = buf;
814
815         for (i = 0; i < chip->ecc.steps; i++) {
816                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
817                                                  eccbuf);
818                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
819                         ret = nand_check_erased_ecc_chunk(databuf,
820                                                           chip->ecc.size,
821                                                           eccbuf,
822                                                           chip->ecc.bytes,
823                                                           NULL, 0,
824                                                           chip->ecc.strength);
825
826                 if (ret >= 0)
827                         max_bitflips = max(ret, max_bitflips);
828                 else
829                         mtd->ecc_stats.failed++;
830
831                 databuf += chip->ecc.size;
832                 eccbuf += chip->ecc.bytes;
833         }
834
835         return max_bitflips;
836 }
837
838 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
839                                      bool oob_required, int page, bool raw)
840 {
841         struct mtd_info *mtd = nand_to_mtd(chip);
842         struct atmel_nand *nand = to_atmel_nand(chip);
843         int ret;
844
845         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
846         if (ret)
847                 return ret;
848
849         atmel_nand_write_buf(mtd, buf, mtd->writesize);
850
851         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
852         if (ret) {
853                 atmel_pmecc_disable(nand->pmecc);
854                 return ret;
855         }
856
857         atmel_nand_pmecc_disable(chip, raw);
858
859         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
860
861         return 0;
862 }
863
864 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
865                                        struct nand_chip *chip, const u8 *buf,
866                                        int oob_required, int page)
867 {
868         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
869 }
870
871 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
872                                            struct nand_chip *chip,
873                                            const u8 *buf, int oob_required,
874                                            int page)
875 {
876         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
877 }
878
879 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
880                                     bool oob_required, int page, bool raw)
881 {
882         struct mtd_info *mtd = nand_to_mtd(chip);
883         int ret;
884
885         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
886         if (ret)
887                 return ret;
888
889         atmel_nand_read_buf(mtd, buf, mtd->writesize);
890         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
891
892         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
893
894         atmel_nand_pmecc_disable(chip, raw);
895
896         return ret;
897 }
898
899 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
900                                       struct nand_chip *chip, u8 *buf,
901                                       int oob_required, int page)
902 {
903         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
904 }
905
906 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
907                                           struct nand_chip *chip, u8 *buf,
908                                           int oob_required, int page)
909 {
910         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
911 }
912
913 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
914                                           const u8 *buf, bool oob_required,
915                                           int page, bool raw)
916 {
917         struct mtd_info *mtd = nand_to_mtd(chip);
918         struct atmel_nand *nand = to_atmel_nand(chip);
919         struct atmel_hsmc_nand_controller *nc;
920         int ret, status;
921
922         nc = to_hsmc_nand_controller(chip->controller);
923
924         atmel_nfc_copy_to_sram(chip, buf, false);
925
926         nc->op.cmds[0] = NAND_CMD_SEQIN;
927         nc->op.ncmds = 1;
928         atmel_nfc_set_op_addr(chip, page, 0x0);
929         nc->op.cs = nand->activecs->id;
930         nc->op.data = ATMEL_NFC_WRITE_DATA;
931
932         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
933         if (ret)
934                 return ret;
935
936         ret = atmel_nfc_exec_op(nc, false);
937         if (ret) {
938                 atmel_nand_pmecc_disable(chip, raw);
939                 dev_err(nc->base.dev,
940                         "Failed to transfer NAND page data (err = %d)\n",
941                         ret);
942                 return ret;
943         }
944
945         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
946
947         atmel_nand_pmecc_disable(chip, raw);
948
949         if (ret)
950                 return ret;
951
952         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
953
954         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
955         nc->op.ncmds = 1;
956         nc->op.cs = nand->activecs->id;
957         ret = atmel_nfc_exec_op(nc, false);
958         if (ret)
959                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
960                         ret);
961
962         status = chip->waitfunc(mtd, chip);
963         if (status & NAND_STATUS_FAIL)
964                 return -EIO;
965
966         return ret;
967 }
968
969 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
970                                             struct nand_chip *chip,
971                                             const u8 *buf, int oob_required,
972                                             int page)
973 {
974         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
975                                               false);
976 }
977
978 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
979                                                 struct nand_chip *chip,
980                                                 const u8 *buf,
981                                                 int oob_required, int page)
982 {
983         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
984                                               true);
985 }
986
987 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
988                                          bool oob_required, int page,
989                                          bool raw)
990 {
991         struct mtd_info *mtd = nand_to_mtd(chip);
992         struct atmel_nand *nand = to_atmel_nand(chip);
993         struct atmel_hsmc_nand_controller *nc;
994         int ret;
995
996         nc = to_hsmc_nand_controller(chip->controller);
997
998         /*
999          * Optimized read page accessors only work when the NAND R/B pin is
1000          * connected to a native SoC R/B pin. If that's not the case, fallback
1001          * to the non-optimized one.
1002          */
1003         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1004                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1005
1006                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1007                                                 raw);
1008         }
1009
1010         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1011
1012         if (mtd->writesize > 512)
1013                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1014
1015         atmel_nfc_set_op_addr(chip, page, 0x0);
1016         nc->op.cs = nand->activecs->id;
1017         nc->op.data = ATMEL_NFC_READ_DATA;
1018
1019         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1020         if (ret)
1021                 return ret;
1022
1023         ret = atmel_nfc_exec_op(nc, false);
1024         if (ret) {
1025                 atmel_nand_pmecc_disable(chip, raw);
1026                 dev_err(nc->base.dev,
1027                         "Failed to load NAND page data (err = %d)\n",
1028                         ret);
1029                 return ret;
1030         }
1031
1032         atmel_nfc_copy_from_sram(chip, buf, true);
1033
1034         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1035
1036         atmel_nand_pmecc_disable(chip, raw);
1037
1038         return ret;
1039 }
1040
1041 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1042                                            struct nand_chip *chip, u8 *buf,
1043                                            int oob_required, int page)
1044 {
1045         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1046                                              false);
1047 }
1048
1049 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1050                                                struct nand_chip *chip,
1051                                                u8 *buf, int oob_required,
1052                                                int page)
1053 {
1054         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1055                                              true);
1056 }
1057
1058 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1059 {
1060         struct mtd_info *mtd = nand_to_mtd(chip);
1061         struct atmel_nand *nand = to_atmel_nand(chip);
1062         struct atmel_nand_controller *nc;
1063         struct atmel_pmecc_user_req req;
1064
1065         nc = to_nand_controller(chip->controller);
1066
1067         if (!nc->pmecc) {
1068                 dev_err(nc->dev, "HW ECC not supported\n");
1069                 return -ENOTSUPP;
1070         }
1071
1072         if (nc->caps->legacy_of_bindings) {
1073                 u32 val;
1074
1075                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1076                                           &val))
1077                         chip->ecc.strength = val;
1078
1079                 if (!of_property_read_u32(nc->dev->of_node,
1080                                           "atmel,pmecc-sector-size",
1081                                           &val))
1082                         chip->ecc.size = val;
1083         }
1084
1085         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1086                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1087         else if (chip->ecc.strength)
1088                 req.ecc.strength = chip->ecc.strength;
1089         else if (chip->ecc_strength_ds)
1090                 req.ecc.strength = chip->ecc_strength_ds;
1091         else
1092                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1093
1094         if (chip->ecc.size)
1095                 req.ecc.sectorsize = chip->ecc.size;
1096         else if (chip->ecc_step_ds)
1097                 req.ecc.sectorsize = chip->ecc_step_ds;
1098         else
1099                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1100
1101         req.pagesize = mtd->writesize;
1102         req.oobsize = mtd->oobsize;
1103
1104         if (mtd->writesize <= 512) {
1105                 req.ecc.bytes = 4;
1106                 req.ecc.ooboffset = 0;
1107         } else {
1108                 req.ecc.bytes = mtd->oobsize - 2;
1109                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1110         }
1111
1112         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1113         if (IS_ERR(nand->pmecc))
1114                 return PTR_ERR(nand->pmecc);
1115
1116         chip->ecc.algo = NAND_ECC_BCH;
1117         chip->ecc.size = req.ecc.sectorsize;
1118         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1119         chip->ecc.strength = req.ecc.strength;
1120
1121         chip->options |= NAND_NO_SUBPAGE_WRITE;
1122
1123         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1124
1125         return 0;
1126 }
1127
1128 static int atmel_nand_ecc_init(struct atmel_nand *nand)
1129 {
1130         struct nand_chip *chip = &nand->base;
1131         struct atmel_nand_controller *nc;
1132         int ret;
1133
1134         nc = to_nand_controller(chip->controller);
1135
1136         switch (chip->ecc.mode) {
1137         case NAND_ECC_NONE:
1138         case NAND_ECC_SOFT:
1139                 /*
1140                  * Nothing to do, the core will initialize everything for us.
1141                  */
1142                 break;
1143
1144         case NAND_ECC_HW:
1145                 ret = atmel_nand_pmecc_init(chip);
1146                 if (ret)
1147                         return ret;
1148
1149                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1150                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1151                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1152                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1153                 break;
1154
1155         default:
1156                 /* Other modes are not supported. */
1157                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1158                         chip->ecc.mode);
1159                 return -ENOTSUPP;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
1166 {
1167         struct nand_chip *chip = &nand->base;
1168         int ret;
1169
1170         ret = atmel_nand_ecc_init(nand);
1171         if (ret)
1172                 return ret;
1173
1174         if (chip->ecc.mode != NAND_ECC_HW)
1175                 return 0;
1176
1177         /* Adjust the ECC operations for the HSMC IP. */
1178         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1179         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1180         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1181         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1182         chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1183
1184         return 0;
1185 }
1186
1187 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1188                                         const struct nand_data_interface *conf,
1189                                         struct atmel_smc_cs_conf *smcconf)
1190 {
1191         u32 ncycles, totalcycles, timeps, mckperiodps;
1192         struct atmel_nand_controller *nc;
1193         int ret;
1194
1195         nc = to_nand_controller(nand->base.controller);
1196
1197         /* DDR interface not supported. */
1198         if (conf->type != NAND_SDR_IFACE)
1199                 return -ENOTSUPP;
1200
1201         /*
1202          * tRC < 30ns implies EDO mode. This controller does not support this
1203          * mode.
1204          */
1205         if (conf->timings.sdr.tRC_min < 30000)
1206                 return -ENOTSUPP;
1207
1208         atmel_smc_cs_conf_init(smcconf);
1209
1210         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1211         mckperiodps *= 1000;
1212
1213         /*
1214          * Set write pulse timing. This one is easy to extract:
1215          *
1216          * NWE_PULSE = tWP
1217          */
1218         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1219         totalcycles = ncycles;
1220         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1221                                           ncycles);
1222         if (ret)
1223                 return ret;
1224
1225         /*
1226          * The write setup timing depends on the operation done on the NAND.
1227          * All operations goes through the same data bus, but the operation
1228          * type depends on the address we are writing to (ALE/CLE address
1229          * lines).
1230          * Since we have no way to differentiate the different operations at
1231          * the SMC level, we must consider the worst case (the biggest setup
1232          * time among all operation types):
1233          *
1234          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1235          */
1236         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1237                       conf->timings.sdr.tALS_min);
1238         timeps = max(timeps, conf->timings.sdr.tDS_min);
1239         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1240         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1241         totalcycles += ncycles;
1242         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1243                                           ncycles);
1244         if (ret)
1245                 return ret;
1246
1247         /*
1248          * As for the write setup timing, the write hold timing depends on the
1249          * operation done on the NAND:
1250          *
1251          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1252          */
1253         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1254                       conf->timings.sdr.tALH_min);
1255         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1256                       conf->timings.sdr.tWH_min);
1257         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1258         totalcycles += ncycles;
1259
1260         /*
1261          * The write cycle timing is directly matching tWC, but is also
1262          * dependent on the other timings on the setup and hold timings we
1263          * calculated earlier, which gives:
1264          *
1265          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1266          */
1267         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1268         ncycles = max(totalcycles, ncycles);
1269         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1270                                           ncycles);
1271         if (ret)
1272                 return ret;
1273
1274         /*
1275          * We don't want the CS line to be toggled between each byte/word
1276          * transfer to the NAND. The only way to guarantee that is to have the
1277          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1278          *
1279          * NCS_WR_PULSE = NWE_CYCLE
1280          */
1281         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1282                                           ncycles);
1283         if (ret)
1284                 return ret;
1285
1286         /*
1287          * As for the write setup timing, the read hold timing depends on the
1288          * operation done on the NAND:
1289          *
1290          * NRD_HOLD = max(tREH, tRHOH)
1291          */
1292         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1293         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1294         totalcycles = ncycles;
1295
1296         /*
1297          * TDF = tRHZ - NRD_HOLD
1298          */
1299         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1300         ncycles -= totalcycles;
1301
1302         /*
1303          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1304          * we might end up with a config that does not fit in the TDF field.
1305          * Just take the max value in this case and hope that the NAND is more
1306          * tolerant than advertised.
1307          */
1308         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1309                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1310         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1311                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1312
1313         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1314                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1315
1316         /*
1317          * Read pulse timing directly matches tRP:
1318          *
1319          * NRD_PULSE = tRP
1320          */
1321         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1322         totalcycles += ncycles;
1323         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1324                                           ncycles);
1325         if (ret)
1326                 return ret;
1327
1328         /*
1329          * The write cycle timing is directly matching tWC, but is also
1330          * dependent on the setup and hold timings we calculated earlier,
1331          * which gives:
1332          *
1333          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1334          *
1335          * NRD_SETUP is always 0.
1336          */
1337         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1338         ncycles = max(totalcycles, ncycles);
1339         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1340                                           ncycles);
1341         if (ret)
1342                 return ret;
1343
1344         /*
1345          * We don't want the CS line to be toggled between each byte/word
1346          * transfer from the NAND. The only way to guarantee that is to have
1347          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1348          *
1349          * NCS_RD_PULSE = NRD_CYCLE
1350          */
1351         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1352                                           ncycles);
1353         if (ret)
1354                 return ret;
1355
1356         /* Txxx timings are directly matching tXXX ones. */
1357         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1358         ret = atmel_smc_cs_conf_set_timing(smcconf,
1359                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1360                                            ncycles);
1361         if (ret)
1362                 return ret;
1363
1364         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1365         ret = atmel_smc_cs_conf_set_timing(smcconf,
1366                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1367                                            ncycles);
1368         /*
1369          * Version 4 of the ONFI spec mandates that tADL be at least 400
1370          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1371          * fit in the tADL field of the SMC reg. We need to relax the check and
1372          * accept the -ERANGE return code.
1373          *
1374          * Note that previous versions of the ONFI spec had a lower tADL_min
1375          * (100 or 200 ns). It's not clear why this timing constraint got
1376          * increased but it seems most NANDs are fine with values lower than
1377          * 400ns, so we should be safe.
1378          */
1379         if (ret && ret != -ERANGE)
1380                 return ret;
1381
1382         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1383         ret = atmel_smc_cs_conf_set_timing(smcconf,
1384                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1385                                            ncycles);
1386         if (ret)
1387                 return ret;
1388
1389         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1390         ret = atmel_smc_cs_conf_set_timing(smcconf,
1391                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1392                                            ncycles);
1393         if (ret)
1394                 return ret;
1395
1396         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1397         ret = atmel_smc_cs_conf_set_timing(smcconf,
1398                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1399                                            ncycles);
1400         if (ret)
1401                 return ret;
1402
1403         /* Attach the CS line to the NFC logic. */
1404         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1405
1406         /* Set the appropriate data bus width. */
1407         if (nand->base.options & NAND_BUSWIDTH_16)
1408                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1409
1410         /* Operate in NRD/NWE READ/WRITEMODE. */
1411         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1412                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1413
1414         return 0;
1415 }
1416
1417 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1418                                         int csline,
1419                                         const struct nand_data_interface *conf)
1420 {
1421         struct atmel_nand_controller *nc;
1422         struct atmel_smc_cs_conf smcconf;
1423         struct atmel_nand_cs *cs;
1424         int ret;
1425
1426         nc = to_nand_controller(nand->base.controller);
1427
1428         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1429         if (ret)
1430                 return ret;
1431
1432         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1433                 return 0;
1434
1435         cs = &nand->cs[csline];
1436         cs->smcconf = smcconf;
1437         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1438
1439         return 0;
1440 }
1441
1442 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1443                                         int csline,
1444                                         const struct nand_data_interface *conf)
1445 {
1446         struct atmel_hsmc_nand_controller *nc;
1447         struct atmel_smc_cs_conf smcconf;
1448         struct atmel_nand_cs *cs;
1449         int ret;
1450
1451         nc = to_hsmc_nand_controller(nand->base.controller);
1452
1453         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1454         if (ret)
1455                 return ret;
1456
1457         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1458                 return 0;
1459
1460         cs = &nand->cs[csline];
1461         cs->smcconf = smcconf;
1462
1463         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1464                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1465
1466         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1467                                  &cs->smcconf);
1468
1469         return 0;
1470 }
1471
1472 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1473                                         const struct nand_data_interface *conf)
1474 {
1475         struct nand_chip *chip = mtd_to_nand(mtd);
1476         struct atmel_nand *nand = to_atmel_nand(chip);
1477         struct atmel_nand_controller *nc;
1478
1479         nc = to_nand_controller(nand->base.controller);
1480
1481         if (csline >= nand->numcs ||
1482             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1483                 return -EINVAL;
1484
1485         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1486 }
1487
1488 static void atmel_nand_init(struct atmel_nand_controller *nc,
1489                             struct atmel_nand *nand)
1490 {
1491         struct nand_chip *chip = &nand->base;
1492         struct mtd_info *mtd = nand_to_mtd(chip);
1493
1494         mtd->dev.parent = nc->dev;
1495         nand->base.controller = &nc->base;
1496
1497         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1498         chip->read_byte = atmel_nand_read_byte;
1499         chip->read_word = atmel_nand_read_word;
1500         chip->write_byte = atmel_nand_write_byte;
1501         chip->read_buf = atmel_nand_read_buf;
1502         chip->write_buf = atmel_nand_write_buf;
1503         chip->select_chip = atmel_nand_select_chip;
1504
1505         if (nc->mck && nc->caps->ops->setup_data_interface)
1506                 chip->setup_data_interface = atmel_nand_setup_data_interface;
1507
1508         /* Some NANDs require a longer delay than the default one (20us). */
1509         chip->chip_delay = 40;
1510
1511         /*
1512          * Use a bounce buffer when the buffer passed by the MTD user is not
1513          * suitable for DMA.
1514          */
1515         if (nc->dmac)
1516                 chip->options |= NAND_USE_BOUNCE_BUFFER;
1517
1518         /* Default to HW ECC if pmecc is available. */
1519         if (nc->pmecc)
1520                 chip->ecc.mode = NAND_ECC_HW;
1521 }
1522
1523 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1524                                 struct atmel_nand *nand)
1525 {
1526         struct nand_chip *chip = &nand->base;
1527         struct atmel_smc_nand_controller *smc_nc;
1528         int i;
1529
1530         atmel_nand_init(nc, nand);
1531
1532         smc_nc = to_smc_nand_controller(chip->controller);
1533         if (!smc_nc->matrix)
1534                 return;
1535
1536         /* Attach the CS to the NAND Flash logic. */
1537         for (i = 0; i < nand->numcs; i++)
1538                 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1539                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1540 }
1541
1542 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1543                                  struct atmel_nand *nand)
1544 {
1545         struct nand_chip *chip = &nand->base;
1546
1547         atmel_nand_init(nc, nand);
1548
1549         /* Overload some methods for the HSMC controller. */
1550         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1551         chip->select_chip = atmel_hsmc_nand_select_chip;
1552 }
1553
1554 static int atmel_nand_detect(struct atmel_nand *nand)
1555 {
1556         struct nand_chip *chip = &nand->base;
1557         struct mtd_info *mtd = nand_to_mtd(chip);
1558         struct atmel_nand_controller *nc;
1559         int ret;
1560
1561         nc = to_nand_controller(chip->controller);
1562
1563         ret = nand_scan_ident(mtd, nand->numcs, NULL);
1564         if (ret)
1565                 dev_err(nc->dev, "nand_scan_ident() failed: %d\n", ret);
1566
1567         return ret;
1568 }
1569
1570 static int atmel_nand_unregister(struct atmel_nand *nand)
1571 {
1572         struct nand_chip *chip = &nand->base;
1573         struct mtd_info *mtd = nand_to_mtd(chip);
1574         int ret;
1575
1576         ret = mtd_device_unregister(mtd);
1577         if (ret)
1578                 return ret;
1579
1580         nand_cleanup(chip);
1581         list_del(&nand->node);
1582
1583         return 0;
1584 }
1585
1586 static int atmel_nand_register(struct atmel_nand *nand)
1587 {
1588         struct nand_chip *chip = &nand->base;
1589         struct mtd_info *mtd = nand_to_mtd(chip);
1590         struct atmel_nand_controller *nc;
1591         int ret;
1592
1593         nc = to_nand_controller(chip->controller);
1594
1595         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1596                 /*
1597                  * We keep the MTD name unchanged to avoid breaking platforms
1598                  * where the MTD cmdline parser is used and the bootloader
1599                  * has not been updated to use the new naming scheme.
1600                  */
1601                 mtd->name = "atmel_nand";
1602         } else if (!mtd->name) {
1603                 /*
1604                  * If the new bindings are used and the bootloader has not been
1605                  * updated to pass a new mtdparts parameter on the cmdline, you
1606                  * should define the following property in your nand node:
1607                  *
1608                  *      label = "atmel_nand";
1609                  *
1610                  * This way, mtd->name will be set by the core when
1611                  * nand_set_flash_node() is called.
1612                  */
1613                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1614                                            "%s:nand.%d", dev_name(nc->dev),
1615                                            nand->cs[0].id);
1616                 if (!mtd->name) {
1617                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1618                         return -ENOMEM;
1619                 }
1620         }
1621
1622         ret = nand_scan_tail(mtd);
1623         if (ret) {
1624                 dev_err(nc->dev, "nand_scan_tail() failed: %d\n", ret);
1625                 return ret;
1626         }
1627
1628         ret = mtd_device_register(mtd, NULL, 0);
1629         if (ret) {
1630                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1631                 nand_cleanup(chip);
1632                 return ret;
1633         }
1634
1635         list_add_tail(&nand->node, &nc->chips);
1636
1637         return 0;
1638 }
1639
1640 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1641                                             struct device_node *np,
1642                                             int reg_cells)
1643 {
1644         struct atmel_nand *nand;
1645         struct gpio_desc *gpio;
1646         int numcs, ret, i;
1647
1648         numcs = of_property_count_elems_of_size(np, "reg",
1649                                                 reg_cells * sizeof(u32));
1650         if (numcs < 1) {
1651                 dev_err(nc->dev, "Missing or invalid reg property\n");
1652                 return ERR_PTR(-EINVAL);
1653         }
1654
1655         nand = devm_kzalloc(nc->dev,
1656                             sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1657                             GFP_KERNEL);
1658         if (!nand) {
1659                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1660                 return ERR_PTR(-ENOMEM);
1661         }
1662
1663         nand->numcs = numcs;
1664
1665         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1666                                                       &np->fwnode, GPIOD_IN,
1667                                                       "nand-det");
1668         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1669                 dev_err(nc->dev,
1670                         "Failed to get detect gpio (err = %ld)\n",
1671                         PTR_ERR(gpio));
1672                 return ERR_CAST(gpio);
1673         }
1674
1675         if (!IS_ERR(gpio))
1676                 nand->cdgpio = gpio;
1677
1678         for (i = 0; i < numcs; i++) {
1679                 struct resource res;
1680                 u32 val;
1681
1682                 ret = of_address_to_resource(np, 0, &res);
1683                 if (ret) {
1684                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1685                                 ret);
1686                         return ERR_PTR(ret);
1687                 }
1688
1689                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1690                                                  &val);
1691                 if (ret) {
1692                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1693                                 ret);
1694                         return ERR_PTR(ret);
1695                 }
1696
1697                 nand->cs[i].id = val;
1698
1699                 nand->cs[i].io.dma = res.start;
1700                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1701                 if (IS_ERR(nand->cs[i].io.virt))
1702                         return ERR_CAST(nand->cs[i].io.virt);
1703
1704                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1705                         if (val > ATMEL_NFC_MAX_RB_ID)
1706                                 return ERR_PTR(-EINVAL);
1707
1708                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1709                         nand->cs[i].rb.id = val;
1710                 } else {
1711                         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1712                                                         "rb", i, &np->fwnode,
1713                                                         GPIOD_IN, "nand-rb");
1714                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1715                                 dev_err(nc->dev,
1716                                         "Failed to get R/B gpio (err = %ld)\n",
1717                                         PTR_ERR(gpio));
1718                                 return ERR_CAST(gpio);
1719                         }
1720
1721                         if (!IS_ERR(gpio)) {
1722                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1723                                 nand->cs[i].rb.gpio = gpio;
1724                         }
1725                 }
1726
1727                 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1728                                                               i, &np->fwnode,
1729                                                               GPIOD_OUT_HIGH,
1730                                                               "nand-cs");
1731                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1732                         dev_err(nc->dev,
1733                                 "Failed to get CS gpio (err = %ld)\n",
1734                                 PTR_ERR(gpio));
1735                         return ERR_CAST(gpio);
1736                 }
1737
1738                 if (!IS_ERR(gpio))
1739                         nand->cs[i].csgpio = gpio;
1740         }
1741
1742         nand_set_flash_node(&nand->base, np);
1743
1744         return nand;
1745 }
1746
1747 static int
1748 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1749                                struct atmel_nand *nand)
1750 {
1751         int ret;
1752
1753         /* No card inserted, skip this NAND. */
1754         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1755                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1756                 return 0;
1757         }
1758
1759         nc->caps->ops->nand_init(nc, nand);
1760
1761         ret = atmel_nand_detect(nand);
1762         if (ret)
1763                 return ret;
1764
1765         ret = nc->caps->ops->ecc_init(nand);
1766         if (ret)
1767                 return ret;
1768
1769         return atmel_nand_register(nand);
1770 }
1771
1772 static int
1773 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1774 {
1775         struct atmel_nand *nand, *tmp;
1776         int ret;
1777
1778         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1779                 ret = atmel_nand_unregister(nand);
1780                 if (ret)
1781                         return ret;
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int
1788 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1789 {
1790         struct device *dev = nc->dev;
1791         struct platform_device *pdev = to_platform_device(dev);
1792         struct atmel_nand *nand;
1793         struct gpio_desc *gpio;
1794         struct resource *res;
1795
1796         /*
1797          * Legacy bindings only allow connecting a single NAND with a unique CS
1798          * line to the controller.
1799          */
1800         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1801                             GFP_KERNEL);
1802         if (!nand)
1803                 return -ENOMEM;
1804
1805         nand->numcs = 1;
1806
1807         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1808         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1809         if (IS_ERR(nand->cs[0].io.virt))
1810                 return PTR_ERR(nand->cs[0].io.virt);
1811
1812         nand->cs[0].io.dma = res->start;
1813
1814         /*
1815          * The old driver was hardcoding the CS id to 3 for all sama5
1816          * controllers. Since this id is only meaningful for the sama5
1817          * controller we can safely assign this id to 3 no matter the
1818          * controller.
1819          * If one wants to connect a NAND to a different CS line, he will
1820          * have to use the new bindings.
1821          */
1822         nand->cs[0].id = 3;
1823
1824         /* R/B GPIO. */
1825         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1826         if (IS_ERR(gpio)) {
1827                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1828                         PTR_ERR(gpio));
1829                 return PTR_ERR(gpio);
1830         }
1831
1832         if (gpio) {
1833                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1834                 nand->cs[0].rb.gpio = gpio;
1835         }
1836
1837         /* CS GPIO. */
1838         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1839         if (IS_ERR(gpio)) {
1840                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1841                         PTR_ERR(gpio));
1842                 return PTR_ERR(gpio);
1843         }
1844
1845         nand->cs[0].csgpio = gpio;
1846
1847         /* Card detect GPIO. */
1848         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1849         if (IS_ERR(gpio)) {
1850                 dev_err(dev,
1851                         "Failed to get detect gpio (err = %ld)\n",
1852                         PTR_ERR(gpio));
1853                 return PTR_ERR(gpio);
1854         }
1855
1856         nand->cdgpio = gpio;
1857
1858         nand_set_flash_node(&nand->base, nc->dev->of_node);
1859
1860         return atmel_nand_controller_add_nand(nc, nand);
1861 }
1862
1863 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1864 {
1865         struct device_node *np, *nand_np;
1866         struct device *dev = nc->dev;
1867         int ret, reg_cells;
1868         u32 val;
1869
1870         /* We do not retrieve the SMC syscon when parsing old DTs. */
1871         if (nc->caps->legacy_of_bindings)
1872                 return atmel_nand_controller_legacy_add_nands(nc);
1873
1874         np = dev->of_node;
1875
1876         ret = of_property_read_u32(np, "#address-cells", &val);
1877         if (ret) {
1878                 dev_err(dev, "missing #address-cells property\n");
1879                 return ret;
1880         }
1881
1882         reg_cells = val;
1883
1884         ret = of_property_read_u32(np, "#size-cells", &val);
1885         if (ret) {
1886                 dev_err(dev, "missing #address-cells property\n");
1887                 return ret;
1888         }
1889
1890         reg_cells += val;
1891
1892         for_each_child_of_node(np, nand_np) {
1893                 struct atmel_nand *nand;
1894
1895                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1896                 if (IS_ERR(nand)) {
1897                         ret = PTR_ERR(nand);
1898                         goto err;
1899                 }
1900
1901                 ret = atmel_nand_controller_add_nand(nc, nand);
1902                 if (ret)
1903                         goto err;
1904         }
1905
1906         return 0;
1907
1908 err:
1909         atmel_nand_controller_remove_nands(nc);
1910
1911         return ret;
1912 }
1913
1914 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1915 {
1916         if (nc->dmac)
1917                 dma_release_channel(nc->dmac);
1918
1919         clk_put(nc->mck);
1920 }
1921
1922 static const struct of_device_id atmel_matrix_of_ids[] = {
1923         {
1924                 .compatible = "atmel,at91sam9260-matrix",
1925                 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1926         },
1927         {
1928                 .compatible = "atmel,at91sam9261-matrix",
1929                 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1930         },
1931         {
1932                 .compatible = "atmel,at91sam9263-matrix",
1933                 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1934         },
1935         {
1936                 .compatible = "atmel,at91sam9rl-matrix",
1937                 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1938         },
1939         {
1940                 .compatible = "atmel,at91sam9g45-matrix",
1941                 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1942         },
1943         {
1944                 .compatible = "atmel,at91sam9n12-matrix",
1945                 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1946         },
1947         {
1948                 .compatible = "atmel,at91sam9x5-matrix",
1949                 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1950         },
1951         { /* sentinel */ },
1952 };
1953
1954 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1955                                 struct platform_device *pdev,
1956                                 const struct atmel_nand_controller_caps *caps)
1957 {
1958         struct device *dev = &pdev->dev;
1959         struct device_node *np = dev->of_node;
1960         int ret;
1961
1962         nand_hw_control_init(&nc->base);
1963         INIT_LIST_HEAD(&nc->chips);
1964         nc->dev = dev;
1965         nc->caps = caps;
1966
1967         platform_set_drvdata(pdev, nc);
1968
1969         nc->pmecc = devm_atmel_pmecc_get(dev);
1970         if (IS_ERR(nc->pmecc)) {
1971                 ret = PTR_ERR(nc->pmecc);
1972                 if (ret != -EPROBE_DEFER)
1973                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1974                                 ret);
1975                 return ret;
1976         }
1977
1978         if (nc->caps->has_dma) {
1979                 dma_cap_mask_t mask;
1980
1981                 dma_cap_zero(mask);
1982                 dma_cap_set(DMA_MEMCPY, mask);
1983
1984                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1985                 if (!nc->dmac)
1986                         dev_err(nc->dev, "Failed to request DMA channel\n");
1987         }
1988
1989         /* We do not retrieve the SMC syscon when parsing old DTs. */
1990         if (nc->caps->legacy_of_bindings)
1991                 return 0;
1992
1993         nc->mck = of_clk_get(dev->parent->of_node, 0);
1994         if (IS_ERR(nc->mck)) {
1995                 dev_err(dev, "Failed to retrieve MCK clk\n");
1996                 return PTR_ERR(nc->mck);
1997         }
1998
1999         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2000         if (!np) {
2001                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2002                 return -EINVAL;
2003         }
2004
2005         nc->smc = syscon_node_to_regmap(np);
2006         of_node_put(np);
2007         if (IS_ERR(nc->smc)) {
2008                 ret = PTR_ERR(nc->smc);
2009                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2010                 return ret;
2011         }
2012
2013         return 0;
2014 }
2015
2016 static int
2017 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2018 {
2019         struct device *dev = nc->base.dev;
2020         const struct of_device_id *match;
2021         struct device_node *np;
2022         int ret;
2023
2024         /* We do not retrieve the matrix syscon when parsing old DTs. */
2025         if (nc->base.caps->legacy_of_bindings)
2026                 return 0;
2027
2028         np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2029         if (!np)
2030                 return 0;
2031
2032         match = of_match_node(atmel_matrix_of_ids, np);
2033         if (!match) {
2034                 of_node_put(np);
2035                 return 0;
2036         }
2037
2038         nc->matrix = syscon_node_to_regmap(np);
2039         of_node_put(np);
2040         if (IS_ERR(nc->matrix)) {
2041                 ret = PTR_ERR(nc->matrix);
2042                 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2043                 return ret;
2044         }
2045
2046         nc->ebi_csa_offs = (unsigned int)match->data;
2047
2048         /*
2049          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2050          * add 4 to ->ebi_csa_offs.
2051          */
2052         if (of_device_is_compatible(dev->parent->of_node,
2053                                     "atmel,at91sam9263-ebi1"))
2054                 nc->ebi_csa_offs += 4;
2055
2056         return 0;
2057 }
2058
2059 static int
2060 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2061 {
2062         struct regmap_config regmap_conf = {
2063                 .reg_bits = 32,
2064                 .val_bits = 32,
2065                 .reg_stride = 4,
2066         };
2067
2068         struct device *dev = nc->base.dev;
2069         struct device_node *nand_np, *nfc_np;
2070         void __iomem *iomem;
2071         struct resource res;
2072         int ret;
2073
2074         nand_np = dev->of_node;
2075         nfc_np = of_find_compatible_node(dev->of_node, NULL,
2076                                          "atmel,sama5d3-nfc");
2077
2078         nc->clk = of_clk_get(nfc_np, 0);
2079         if (IS_ERR(nc->clk)) {
2080                 ret = PTR_ERR(nc->clk);
2081                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2082                         ret);
2083                 goto out;
2084         }
2085
2086         ret = clk_prepare_enable(nc->clk);
2087         if (ret) {
2088                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2089                         ret);
2090                 goto out;
2091         }
2092
2093         nc->irq = of_irq_get(nand_np, 0);
2094         if (nc->irq <= 0) {
2095                 ret = nc->irq ?: -ENXIO;
2096                 if (ret != -EPROBE_DEFER)
2097                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2098                                 ret);
2099                 goto out;
2100         }
2101
2102         ret = of_address_to_resource(nfc_np, 0, &res);
2103         if (ret) {
2104                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2105                         ret);
2106                 goto out;
2107         }
2108
2109         iomem = devm_ioremap_resource(dev, &res);
2110         if (IS_ERR(iomem)) {
2111                 ret = PTR_ERR(iomem);
2112                 goto out;
2113         }
2114
2115         regmap_conf.name = "nfc-io";
2116         regmap_conf.max_register = resource_size(&res) - 4;
2117         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2118         if (IS_ERR(nc->io)) {
2119                 ret = PTR_ERR(nc->io);
2120                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2121                         ret);
2122                 goto out;
2123         }
2124
2125         ret = of_address_to_resource(nfc_np, 1, &res);
2126         if (ret) {
2127                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2128                         ret);
2129                 goto out;
2130         }
2131
2132         iomem = devm_ioremap_resource(dev, &res);
2133         if (IS_ERR(iomem)) {
2134                 ret = PTR_ERR(iomem);
2135                 goto out;
2136         }
2137
2138         regmap_conf.name = "smc";
2139         regmap_conf.max_register = resource_size(&res) - 4;
2140         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2141         if (IS_ERR(nc->base.smc)) {
2142                 ret = PTR_ERR(nc->base.smc);
2143                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2144                         ret);
2145                 goto out;
2146         }
2147
2148         ret = of_address_to_resource(nfc_np, 2, &res);
2149         if (ret) {
2150                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2151                         ret);
2152                 goto out;
2153         }
2154
2155         nc->sram.virt = devm_ioremap_resource(dev, &res);
2156         if (IS_ERR(nc->sram.virt)) {
2157                 ret = PTR_ERR(nc->sram.virt);
2158                 goto out;
2159         }
2160
2161         nc->sram.dma = res.start;
2162
2163 out:
2164         of_node_put(nfc_np);
2165
2166         return ret;
2167 }
2168
2169 static int
2170 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2171 {
2172         struct device *dev = nc->base.dev;
2173         struct device_node *np;
2174         int ret;
2175
2176         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2177         if (!np) {
2178                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2179                 return -EINVAL;
2180         }
2181
2182         nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2183
2184         nc->irq = of_irq_get(np, 0);
2185         of_node_put(np);
2186         if (nc->irq <= 0) {
2187                 ret = nc->irq ?: -ENXIO;
2188                 if (ret != -EPROBE_DEFER)
2189                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2190                                 ret);
2191                 return ret;
2192         }
2193
2194         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2195         if (!np) {
2196                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2197                 return -EINVAL;
2198         }
2199
2200         nc->io = syscon_node_to_regmap(np);
2201         of_node_put(np);
2202         if (IS_ERR(nc->io)) {
2203                 ret = PTR_ERR(nc->io);
2204                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2205                 return ret;
2206         }
2207
2208         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2209                                          "atmel,nfc-sram", 0);
2210         if (!nc->sram.pool) {
2211                 dev_err(nc->base.dev, "Missing SRAM\n");
2212                 return -ENOMEM;
2213         }
2214
2215         nc->sram.virt = gen_pool_dma_alloc(nc->sram.pool,
2216                                             ATMEL_NFC_SRAM_SIZE,
2217                                             &nc->sram.dma);
2218         if (!nc->sram.virt) {
2219                 dev_err(nc->base.dev,
2220                         "Could not allocate memory from the NFC SRAM pool\n");
2221                 return -ENOMEM;
2222         }
2223
2224         return 0;
2225 }
2226
2227 static int
2228 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2229 {
2230         struct atmel_hsmc_nand_controller *hsmc_nc;
2231         int ret;
2232
2233         ret = atmel_nand_controller_remove_nands(nc);
2234         if (ret)
2235                 return ret;
2236
2237         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2238         if (hsmc_nc->sram.pool)
2239                 gen_pool_free(hsmc_nc->sram.pool,
2240                               (unsigned long)hsmc_nc->sram.virt,
2241                               ATMEL_NFC_SRAM_SIZE);
2242
2243         if (hsmc_nc->clk) {
2244                 clk_disable_unprepare(hsmc_nc->clk);
2245                 clk_put(hsmc_nc->clk);
2246         }
2247
2248         atmel_nand_controller_cleanup(nc);
2249
2250         return 0;
2251 }
2252
2253 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2254                                 const struct atmel_nand_controller_caps *caps)
2255 {
2256         struct device *dev = &pdev->dev;
2257         struct atmel_hsmc_nand_controller *nc;
2258         int ret;
2259
2260         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2261         if (!nc)
2262                 return -ENOMEM;
2263
2264         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2265         if (ret)
2266                 return ret;
2267
2268         if (caps->legacy_of_bindings)
2269                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2270         else
2271                 ret = atmel_hsmc_nand_controller_init(nc);
2272
2273         if (ret)
2274                 return ret;
2275
2276         /* Make sure all irqs are masked before registering our IRQ handler. */
2277         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2278         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2279                                IRQF_SHARED, "nfc", nc);
2280         if (ret) {
2281                 dev_err(dev,
2282                         "Could not get register NFC interrupt handler (err = %d)\n",
2283                         ret);
2284                 goto err;
2285         }
2286
2287         /* Initial NFC configuration. */
2288         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2289                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2290
2291         ret = atmel_nand_controller_add_nands(&nc->base);
2292         if (ret)
2293                 goto err;
2294
2295         return 0;
2296
2297 err:
2298         atmel_hsmc_nand_controller_remove(&nc->base);
2299
2300         return ret;
2301 }
2302
2303 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2304         .probe = atmel_hsmc_nand_controller_probe,
2305         .remove = atmel_hsmc_nand_controller_remove,
2306         .ecc_init = atmel_hsmc_nand_ecc_init,
2307         .nand_init = atmel_hsmc_nand_init,
2308         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2309 };
2310
2311 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2312         .has_dma = true,
2313         .ale_offs = BIT(21),
2314         .cle_offs = BIT(22),
2315         .ops = &atmel_hsmc_nc_ops,
2316 };
2317
2318 /* Only used to parse old bindings. */
2319 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2320         .has_dma = true,
2321         .ale_offs = BIT(21),
2322         .cle_offs = BIT(22),
2323         .ops = &atmel_hsmc_nc_ops,
2324         .legacy_of_bindings = true,
2325 };
2326
2327 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2328                                 const struct atmel_nand_controller_caps *caps)
2329 {
2330         struct device *dev = &pdev->dev;
2331         struct atmel_smc_nand_controller *nc;
2332         int ret;
2333
2334         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2335         if (!nc)
2336                 return -ENOMEM;
2337
2338         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2339         if (ret)
2340                 return ret;
2341
2342         ret = atmel_smc_nand_controller_init(nc);
2343         if (ret)
2344                 return ret;
2345
2346         return atmel_nand_controller_add_nands(&nc->base);
2347 }
2348
2349 static int
2350 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2351 {
2352         int ret;
2353
2354         ret = atmel_nand_controller_remove_nands(nc);
2355         if (ret)
2356                 return ret;
2357
2358         atmel_nand_controller_cleanup(nc);
2359
2360         return 0;
2361 }
2362
2363 /*
2364  * The SMC reg layout of at91rm9200 is completely different which prevents us
2365  * from re-using atmel_smc_nand_setup_data_interface() for the
2366  * ->setup_data_interface() hook.
2367  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2368  * ->setup_data_interface() unassigned.
2369  */
2370 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2371         .probe = atmel_smc_nand_controller_probe,
2372         .remove = atmel_smc_nand_controller_remove,
2373         .ecc_init = atmel_nand_ecc_init,
2374         .nand_init = atmel_smc_nand_init,
2375 };
2376
2377 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2378         .ale_offs = BIT(21),
2379         .cle_offs = BIT(22),
2380         .ops = &at91rm9200_nc_ops,
2381 };
2382
2383 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2384         .probe = atmel_smc_nand_controller_probe,
2385         .remove = atmel_smc_nand_controller_remove,
2386         .ecc_init = atmel_nand_ecc_init,
2387         .nand_init = atmel_smc_nand_init,
2388         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2389 };
2390
2391 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2392         .ale_offs = BIT(21),
2393         .cle_offs = BIT(22),
2394         .ops = &atmel_smc_nc_ops,
2395 };
2396
2397 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2398         .ale_offs = BIT(22),
2399         .cle_offs = BIT(21),
2400         .ops = &atmel_smc_nc_ops,
2401 };
2402
2403 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2404         .has_dma = true,
2405         .ale_offs = BIT(21),
2406         .cle_offs = BIT(22),
2407         .ops = &atmel_smc_nc_ops,
2408 };
2409
2410 /* Only used to parse old bindings. */
2411 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2412         .ale_offs = BIT(21),
2413         .cle_offs = BIT(22),
2414         .ops = &atmel_smc_nc_ops,
2415         .legacy_of_bindings = true,
2416 };
2417
2418 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2419         .ale_offs = BIT(22),
2420         .cle_offs = BIT(21),
2421         .ops = &atmel_smc_nc_ops,
2422         .legacy_of_bindings = true,
2423 };
2424
2425 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2426         .has_dma = true,
2427         .ale_offs = BIT(21),
2428         .cle_offs = BIT(22),
2429         .ops = &atmel_smc_nc_ops,
2430         .legacy_of_bindings = true,
2431 };
2432
2433 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2434         {
2435                 .compatible = "atmel,at91rm9200-nand-controller",
2436                 .data = &atmel_rm9200_nc_caps,
2437         },
2438         {
2439                 .compatible = "atmel,at91sam9260-nand-controller",
2440                 .data = &atmel_sam9260_nc_caps,
2441         },
2442         {
2443                 .compatible = "atmel,at91sam9261-nand-controller",
2444                 .data = &atmel_sam9261_nc_caps,
2445         },
2446         {
2447                 .compatible = "atmel,at91sam9g45-nand-controller",
2448                 .data = &atmel_sam9g45_nc_caps,
2449         },
2450         {
2451                 .compatible = "atmel,sama5d3-nand-controller",
2452                 .data = &atmel_sama5_nc_caps,
2453         },
2454         /* Support for old/deprecated bindings: */
2455         {
2456                 .compatible = "atmel,at91rm9200-nand",
2457                 .data = &atmel_rm9200_nand_caps,
2458         },
2459         {
2460                 .compatible = "atmel,sama5d4-nand",
2461                 .data = &atmel_rm9200_nand_caps,
2462         },
2463         {
2464                 .compatible = "atmel,sama5d2-nand",
2465                 .data = &atmel_rm9200_nand_caps,
2466         },
2467         { /* sentinel */ },
2468 };
2469 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2470
2471 static int atmel_nand_controller_probe(struct platform_device *pdev)
2472 {
2473         const struct atmel_nand_controller_caps *caps;
2474
2475         if (pdev->id_entry)
2476                 caps = (void *)pdev->id_entry->driver_data;
2477         else
2478                 caps = of_device_get_match_data(&pdev->dev);
2479
2480         if (!caps) {
2481                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2482                 return -EINVAL;
2483         }
2484
2485         if (caps->legacy_of_bindings) {
2486                 u32 ale_offs = 21;
2487
2488                 /*
2489                  * If we are parsing legacy DT props and the DT contains a
2490                  * valid NFC node, forward the request to the sama5 logic.
2491                  */
2492                 if (of_find_compatible_node(pdev->dev.of_node, NULL,
2493                                             "atmel,sama5d3-nfc"))
2494                         caps = &atmel_sama5_nand_caps;
2495
2496                 /*
2497                  * Even if the compatible says we are dealing with an
2498                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2499                  * this controller supports DMA, which means we are in fact
2500                  * dealing with an at91sam9g45+ controller.
2501                  */
2502                 if (!caps->has_dma &&
2503                     of_property_read_bool(pdev->dev.of_node,
2504                                           "atmel,nand-has-dma"))
2505                         caps = &atmel_sam9g45_nand_caps;
2506
2507                 /*
2508                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2509                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2510                  * actually dealing with an at91sam9261 controller.
2511                  */
2512                 of_property_read_u32(pdev->dev.of_node,
2513                                      "atmel,nand-addr-offset", &ale_offs);
2514                 if (ale_offs != 21)
2515                         caps = &atmel_sam9261_nand_caps;
2516         }
2517
2518         return caps->ops->probe(pdev, caps);
2519 }
2520
2521 static int atmel_nand_controller_remove(struct platform_device *pdev)
2522 {
2523         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2524
2525         return nc->caps->ops->remove(nc);
2526 }
2527
2528 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2529 {
2530         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2531         struct atmel_nand *nand;
2532
2533         list_for_each_entry(nand, &nc->chips, node) {
2534                 int i;
2535
2536                 for (i = 0; i < nand->numcs; i++)
2537                         nand_reset(&nand->base, i);
2538         }
2539
2540         return 0;
2541 }
2542
2543 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2544                          atmel_nand_controller_resume);
2545
2546 static struct platform_driver atmel_nand_controller_driver = {
2547         .driver = {
2548                 .name = "atmel-nand-controller",
2549                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2550         },
2551         .probe = atmel_nand_controller_probe,
2552         .remove = atmel_nand_controller_remove,
2553 };
2554 module_platform_driver(atmel_nand_controller_driver);
2555
2556 MODULE_LICENSE("GPL");
2557 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2558 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2559 MODULE_ALIAS("platform:atmel-nand-controller");