Merge tag 'nand/for-4.14' of git://git.infradead.org/l2-mtd into mtd/next
[sfrench/cifs-2.6.git] / drivers / mtd / nand / atmel / nand-controller.c
1 /*
2  * Copyright 2017 ATMEL
3  * Copyright 2017 Free Electrons
4  *
5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6  *
7  * Derived from the atmel_nand.c driver which contained the following
8  * copyrights:
9  *
10  *   Copyright 2003 Rick Bronson
11  *
12  *   Derived from drivers/mtd/nand/autcpu12.c
13  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
14  *
15  *   Derived from drivers/mtd/spia.c
16  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
17  *
18  *
19  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
21  *
22  *   Derived from Das U-Boot source code
23  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
25  *
26  *   Add Programmable Multibit ECC support for various AT91 SoC
27  *      Copyright 2012 ATMEL, Hong Xu
28  *
29  *   Add Nand Flash Controller support for SAMA5 SoC
30  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
31  *
32  * This program is free software; you can redistribute it and/or modify
33  * it under the terms of the GNU General Public License version 2 as
34  * published by the Free Software Foundation.
35  *
36  * A few words about the naming convention in this file. This convention
37  * applies to structure and function names.
38  *
39  * Prefixes:
40  *
41  * - atmel_nand_: all generic structures/functions
42  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43  *                    (at91sam9 and avr32 SoCs)
44  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45  *                     (sama5 SoCs and later)
46  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47  *               that is available in the HSMC block
48  * - <soc>_nand_: all SoC specific structures/functions
49  */
50
51 #include <linux/clk.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/dmaengine.h>
54 #include <linux/genalloc.h>
55 #include <linux/gpio.h>
56 #include <linux/gpio/consumer.h>
57 #include <linux/interrupt.h>
58 #include <linux/mfd/syscon.h>
59 #include <linux/mfd/syscon/atmel-matrix.h>
60 #include <linux/mfd/syscon/atmel-smc.h>
61 #include <linux/module.h>
62 #include <linux/mtd/rawnand.h>
63 #include <linux/of_address.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_platform.h>
66 #include <linux/iopoll.h>
67 #include <linux/platform_device.h>
68 #include <linux/regmap.h>
69
70 #include "pmecc.h"
71
72 #define ATMEL_HSMC_NFC_CFG                      0x0
73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
74 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
75 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
76 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
77 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
78 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
79 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
80 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
82 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
83
84 #define ATMEL_HSMC_NFC_CTRL                     0x4
85 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
86 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
87
88 #define ATMEL_HSMC_NFC_SR                       0x8
89 #define ATMEL_HSMC_NFC_IER                      0xc
90 #define ATMEL_HSMC_NFC_IDR                      0x10
91 #define ATMEL_HSMC_NFC_IMR                      0x14
92 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
93 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
94 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
95 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
96 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
97 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
98 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
99 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
100 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
101 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
102 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
103 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
104 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
105                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
106                                                  ATMEL_HSMC_NFC_SR_AWB | \
107                                                  ATMEL_HSMC_NFC_SR_NFCASE)
108 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
109
110 #define ATMEL_HSMC_NFC_ADDR                     0x18
111 #define ATMEL_HSMC_NFC_BANK                     0x1c
112
113 #define ATMEL_NFC_MAX_RB_ID                     7
114
115 #define ATMEL_NFC_SRAM_SIZE                     0x2400
116
117 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
118 #define ATMEL_NFC_VCMD2                         BIT(18)
119 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
120 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
121 #define ATMEL_NFC_DATAEN                        BIT(25)
122 #define ATMEL_NFC_NFCWR                         BIT(26)
123
124 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
125
126 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
127 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
128
129 #define DEFAULT_TIMEOUT_MS                      1000
130 #define MIN_DMA_LEN                             128
131
132 enum atmel_nand_rb_type {
133         ATMEL_NAND_NO_RB,
134         ATMEL_NAND_NATIVE_RB,
135         ATMEL_NAND_GPIO_RB,
136 };
137
138 struct atmel_nand_rb {
139         enum atmel_nand_rb_type type;
140         union {
141                 struct gpio_desc *gpio;
142                 int id;
143         };
144 };
145
146 struct atmel_nand_cs {
147         int id;
148         struct atmel_nand_rb rb;
149         struct gpio_desc *csgpio;
150         struct {
151                 void __iomem *virt;
152                 dma_addr_t dma;
153         } io;
154
155         struct atmel_smc_cs_conf smcconf;
156 };
157
158 struct atmel_nand {
159         struct list_head node;
160         struct device *dev;
161         struct nand_chip base;
162         struct atmel_nand_cs *activecs;
163         struct atmel_pmecc_user *pmecc;
164         struct gpio_desc *cdgpio;
165         int numcs;
166         struct atmel_nand_cs cs[];
167 };
168
169 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
170 {
171         return container_of(chip, struct atmel_nand, base);
172 }
173
174 enum atmel_nfc_data_xfer {
175         ATMEL_NFC_NO_DATA,
176         ATMEL_NFC_READ_DATA,
177         ATMEL_NFC_WRITE_DATA,
178 };
179
180 struct atmel_nfc_op {
181         u8 cs;
182         u8 ncmds;
183         u8 cmds[2];
184         u8 naddrs;
185         u8 addrs[5];
186         enum atmel_nfc_data_xfer data;
187         u32 wait;
188         u32 errors;
189 };
190
191 struct atmel_nand_controller;
192 struct atmel_nand_controller_caps;
193
194 struct atmel_nand_controller_ops {
195         int (*probe)(struct platform_device *pdev,
196                      const struct atmel_nand_controller_caps *caps);
197         int (*remove)(struct atmel_nand_controller *nc);
198         void (*nand_init)(struct atmel_nand_controller *nc,
199                           struct atmel_nand *nand);
200         int (*ecc_init)(struct atmel_nand *nand);
201         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
202                                     const struct nand_data_interface *conf);
203 };
204
205 struct atmel_nand_controller_caps {
206         bool has_dma;
207         bool legacy_of_bindings;
208         u32 ale_offs;
209         u32 cle_offs;
210         const struct atmel_nand_controller_ops *ops;
211 };
212
213 struct atmel_nand_controller {
214         struct nand_hw_control base;
215         const struct atmel_nand_controller_caps *caps;
216         struct device *dev;
217         struct regmap *smc;
218         struct dma_chan *dmac;
219         struct atmel_pmecc *pmecc;
220         struct list_head chips;
221         struct clk *mck;
222 };
223
224 static inline struct atmel_nand_controller *
225 to_nand_controller(struct nand_hw_control *ctl)
226 {
227         return container_of(ctl, struct atmel_nand_controller, base);
228 }
229
230 struct atmel_smc_nand_controller {
231         struct atmel_nand_controller base;
232         struct regmap *matrix;
233         unsigned int ebi_csa_offs;
234 };
235
236 static inline struct atmel_smc_nand_controller *
237 to_smc_nand_controller(struct nand_hw_control *ctl)
238 {
239         return container_of(to_nand_controller(ctl),
240                             struct atmel_smc_nand_controller, base);
241 }
242
243 struct atmel_hsmc_nand_controller {
244         struct atmel_nand_controller base;
245         struct {
246                 struct gen_pool *pool;
247                 void __iomem *virt;
248                 dma_addr_t dma;
249         } sram;
250         struct regmap *io;
251         struct atmel_nfc_op op;
252         struct completion complete;
253         int irq;
254
255         /* Only used when instantiating from legacy DT bindings. */
256         struct clk *clk;
257 };
258
259 static inline struct atmel_hsmc_nand_controller *
260 to_hsmc_nand_controller(struct nand_hw_control *ctl)
261 {
262         return container_of(to_nand_controller(ctl),
263                             struct atmel_hsmc_nand_controller, base);
264 }
265
266 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
267 {
268         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
269         op->wait ^= status & op->wait;
270
271         return !op->wait || op->errors;
272 }
273
274 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
275 {
276         struct atmel_hsmc_nand_controller *nc = data;
277         u32 sr, rcvd;
278         bool done;
279
280         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
281
282         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
283         done = atmel_nfc_op_done(&nc->op, sr);
284
285         if (rcvd)
286                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
287
288         if (done)
289                 complete(&nc->complete);
290
291         return rcvd ? IRQ_HANDLED : IRQ_NONE;
292 }
293
294 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
295                           unsigned int timeout_ms)
296 {
297         int ret;
298
299         if (!timeout_ms)
300                 timeout_ms = DEFAULT_TIMEOUT_MS;
301
302         if (poll) {
303                 u32 status;
304
305                 ret = regmap_read_poll_timeout(nc->base.smc,
306                                                ATMEL_HSMC_NFC_SR, status,
307                                                atmel_nfc_op_done(&nc->op,
308                                                                  status),
309                                                0, timeout_ms * 1000);
310         } else {
311                 init_completion(&nc->complete);
312                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
313                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
314                 ret = wait_for_completion_timeout(&nc->complete,
315                                                 msecs_to_jiffies(timeout_ms));
316                 if (!ret)
317                         ret = -ETIMEDOUT;
318                 else
319                         ret = 0;
320
321                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
322         }
323
324         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
325                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
326                 ret = -ETIMEDOUT;
327         }
328
329         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
330                 dev_err(nc->base.dev, "Access to an undefined area\n");
331                 ret = -EIO;
332         }
333
334         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
335                 dev_err(nc->base.dev, "Access while busy\n");
336                 ret = -EIO;
337         }
338
339         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
340                 dev_err(nc->base.dev, "Wrong access size\n");
341                 ret = -EIO;
342         }
343
344         return ret;
345 }
346
347 static void atmel_nand_dma_transfer_finished(void *data)
348 {
349         struct completion *finished = data;
350
351         complete(finished);
352 }
353
354 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
355                                    void *buf, dma_addr_t dev_dma, size_t len,
356                                    enum dma_data_direction dir)
357 {
358         DECLARE_COMPLETION_ONSTACK(finished);
359         dma_addr_t src_dma, dst_dma, buf_dma;
360         struct dma_async_tx_descriptor *tx;
361         dma_cookie_t cookie;
362
363         buf_dma = dma_map_single(nc->dev, buf, len, dir);
364         if (dma_mapping_error(nc->dev, dev_dma)) {
365                 dev_err(nc->dev,
366                         "Failed to prepare a buffer for DMA access\n");
367                 goto err;
368         }
369
370         if (dir == DMA_FROM_DEVICE) {
371                 src_dma = dev_dma;
372                 dst_dma = buf_dma;
373         } else {
374                 src_dma = buf_dma;
375                 dst_dma = dev_dma;
376         }
377
378         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
379                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
380         if (!tx) {
381                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
382                 goto err_unmap;
383         }
384
385         tx->callback = atmel_nand_dma_transfer_finished;
386         tx->callback_param = &finished;
387
388         cookie = dmaengine_submit(tx);
389         if (dma_submit_error(cookie)) {
390                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
391                 goto err_unmap;
392         }
393
394         dma_async_issue_pending(nc->dmac);
395         wait_for_completion(&finished);
396
397         return 0;
398
399 err_unmap:
400         dma_unmap_single(nc->dev, buf_dma, len, dir);
401
402 err:
403         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
404
405         return -EIO;
406 }
407
408 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
409 {
410         struct nand_chip *chip = mtd_to_nand(mtd);
411         struct atmel_nand *nand = to_atmel_nand(chip);
412
413         return ioread8(nand->activecs->io.virt);
414 }
415
416 static u16 atmel_nand_read_word(struct mtd_info *mtd)
417 {
418         struct nand_chip *chip = mtd_to_nand(mtd);
419         struct atmel_nand *nand = to_atmel_nand(chip);
420
421         return ioread16(nand->activecs->io.virt);
422 }
423
424 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
425 {
426         struct nand_chip *chip = mtd_to_nand(mtd);
427         struct atmel_nand *nand = to_atmel_nand(chip);
428
429         if (chip->options & NAND_BUSWIDTH_16)
430                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
431         else
432                 iowrite8(byte, nand->activecs->io.virt);
433 }
434
435 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
436 {
437         struct nand_chip *chip = mtd_to_nand(mtd);
438         struct atmel_nand *nand = to_atmel_nand(chip);
439         struct atmel_nand_controller *nc;
440
441         nc = to_nand_controller(chip->controller);
442
443         /*
444          * If the controller supports DMA, the buffer address is DMA-able and
445          * len is long enough to make DMA transfers profitable, let's trigger
446          * a DMA transfer. If it fails, fallback to PIO mode.
447          */
448         if (nc->dmac && virt_addr_valid(buf) &&
449             len >= MIN_DMA_LEN &&
450             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
451                                      DMA_FROM_DEVICE))
452                 return;
453
454         if (chip->options & NAND_BUSWIDTH_16)
455                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
456         else
457                 ioread8_rep(nand->activecs->io.virt, buf, len);
458 }
459
460 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
461 {
462         struct nand_chip *chip = mtd_to_nand(mtd);
463         struct atmel_nand *nand = to_atmel_nand(chip);
464         struct atmel_nand_controller *nc;
465
466         nc = to_nand_controller(chip->controller);
467
468         /*
469          * If the controller supports DMA, the buffer address is DMA-able and
470          * len is long enough to make DMA transfers profitable, let's trigger
471          * a DMA transfer. If it fails, fallback to PIO mode.
472          */
473         if (nc->dmac && virt_addr_valid(buf) &&
474             len >= MIN_DMA_LEN &&
475             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
476                                      len, DMA_TO_DEVICE))
477                 return;
478
479         if (chip->options & NAND_BUSWIDTH_16)
480                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
481         else
482                 iowrite8_rep(nand->activecs->io.virt, buf, len);
483 }
484
485 static int atmel_nand_dev_ready(struct mtd_info *mtd)
486 {
487         struct nand_chip *chip = mtd_to_nand(mtd);
488         struct atmel_nand *nand = to_atmel_nand(chip);
489
490         return gpiod_get_value(nand->activecs->rb.gpio);
491 }
492
493 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
494 {
495         struct nand_chip *chip = mtd_to_nand(mtd);
496         struct atmel_nand *nand = to_atmel_nand(chip);
497
498         if (cs < 0 || cs >= nand->numcs) {
499                 nand->activecs = NULL;
500                 chip->dev_ready = NULL;
501                 return;
502         }
503
504         nand->activecs = &nand->cs[cs];
505
506         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
507                 chip->dev_ready = atmel_nand_dev_ready;
508 }
509
510 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
511 {
512         struct nand_chip *chip = mtd_to_nand(mtd);
513         struct atmel_nand *nand = to_atmel_nand(chip);
514         struct atmel_hsmc_nand_controller *nc;
515         u32 status;
516
517         nc = to_hsmc_nand_controller(chip->controller);
518
519         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
520
521         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
522 }
523
524 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
525 {
526         struct nand_chip *chip = mtd_to_nand(mtd);
527         struct atmel_nand *nand = to_atmel_nand(chip);
528         struct atmel_hsmc_nand_controller *nc;
529
530         nc = to_hsmc_nand_controller(chip->controller);
531
532         atmel_nand_select_chip(mtd, cs);
533
534         if (!nand->activecs) {
535                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
536                              ATMEL_HSMC_NFC_CTRL_DIS);
537                 return;
538         }
539
540         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
541                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
542
543         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
544                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
545                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
546                            ATMEL_HSMC_NFC_CFG_RSPARE |
547                            ATMEL_HSMC_NFC_CFG_WSPARE,
548                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
549                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
550                            ATMEL_HSMC_NFC_CFG_RSPARE);
551         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
552                      ATMEL_HSMC_NFC_CTRL_EN);
553 }
554
555 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
556 {
557         u8 *addrs = nc->op.addrs;
558         unsigned int op = 0;
559         u32 addr, val;
560         int i, ret;
561
562         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
563
564         for (i = 0; i < nc->op.ncmds; i++)
565                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
566
567         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
568                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
569
570         op |= ATMEL_NFC_CSID(nc->op.cs) |
571               ATMEL_NFC_ACYCLE(nc->op.naddrs);
572
573         if (nc->op.ncmds > 1)
574                 op |= ATMEL_NFC_VCMD2;
575
576         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
577                (addrs[3] << 24);
578
579         if (nc->op.data != ATMEL_NFC_NO_DATA) {
580                 op |= ATMEL_NFC_DATAEN;
581                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
582
583                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
584                         op |= ATMEL_NFC_NFCWR;
585         }
586
587         /* Clear all flags. */
588         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
589
590         /* Send the command. */
591         regmap_write(nc->io, op, addr);
592
593         ret = atmel_nfc_wait(nc, poll, 0);
594         if (ret)
595                 dev_err(nc->base.dev,
596                         "Failed to send NAND command (err = %d)!",
597                         ret);
598
599         /* Reset the op state. */
600         memset(&nc->op, 0, sizeof(nc->op));
601
602         return ret;
603 }
604
605 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
606                                      unsigned int ctrl)
607 {
608         struct nand_chip *chip = mtd_to_nand(mtd);
609         struct atmel_nand *nand = to_atmel_nand(chip);
610         struct atmel_hsmc_nand_controller *nc;
611
612         nc = to_hsmc_nand_controller(chip->controller);
613
614         if (ctrl & NAND_ALE) {
615                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
616                         return;
617
618                 nc->op.addrs[nc->op.naddrs++] = dat;
619         } else if (ctrl & NAND_CLE) {
620                 if (nc->op.ncmds > 1)
621                         return;
622
623                 nc->op.cmds[nc->op.ncmds++] = dat;
624         }
625
626         if (dat == NAND_CMD_NONE) {
627                 nc->op.cs = nand->activecs->id;
628                 atmel_nfc_exec_op(nc, true);
629         }
630 }
631
632 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
633                                 unsigned int ctrl)
634 {
635         struct nand_chip *chip = mtd_to_nand(mtd);
636         struct atmel_nand *nand = to_atmel_nand(chip);
637         struct atmel_nand_controller *nc;
638
639         nc = to_nand_controller(chip->controller);
640
641         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
642                 if (ctrl & NAND_NCE)
643                         gpiod_set_value(nand->activecs->csgpio, 0);
644                 else
645                         gpiod_set_value(nand->activecs->csgpio, 1);
646         }
647
648         if (ctrl & NAND_ALE)
649                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
650         else if (ctrl & NAND_CLE)
651                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
652 }
653
654 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
655                                    bool oob_required)
656 {
657         struct mtd_info *mtd = nand_to_mtd(chip);
658         struct atmel_hsmc_nand_controller *nc;
659         int ret = -EIO;
660
661         nc = to_hsmc_nand_controller(chip->controller);
662
663         if (nc->base.dmac)
664                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
665                                               nc->sram.dma, mtd->writesize,
666                                               DMA_TO_DEVICE);
667
668         /* Falling back to CPU copy. */
669         if (ret)
670                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
671
672         if (oob_required)
673                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
674                             mtd->oobsize);
675 }
676
677 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
678                                      bool oob_required)
679 {
680         struct mtd_info *mtd = nand_to_mtd(chip);
681         struct atmel_hsmc_nand_controller *nc;
682         int ret = -EIO;
683
684         nc = to_hsmc_nand_controller(chip->controller);
685
686         if (nc->base.dmac)
687                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
688                                               mtd->writesize, DMA_FROM_DEVICE);
689
690         /* Falling back to CPU copy. */
691         if (ret)
692                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
693
694         if (oob_required)
695                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
696                               mtd->oobsize);
697 }
698
699 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
700 {
701         struct mtd_info *mtd = nand_to_mtd(chip);
702         struct atmel_hsmc_nand_controller *nc;
703
704         nc = to_hsmc_nand_controller(chip->controller);
705
706         if (column >= 0) {
707                 nc->op.addrs[nc->op.naddrs++] = column;
708
709                 /*
710                  * 2 address cycles for the column offset on large page NANDs.
711                  */
712                 if (mtd->writesize > 512)
713                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
714         }
715
716         if (page >= 0) {
717                 nc->op.addrs[nc->op.naddrs++] = page;
718                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
719
720                 if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
721                     (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
722                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
723         }
724 }
725
726 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
727 {
728         struct atmel_nand *nand = to_atmel_nand(chip);
729         struct atmel_nand_controller *nc;
730         int ret;
731
732         nc = to_nand_controller(chip->controller);
733
734         if (raw)
735                 return 0;
736
737         ret = atmel_pmecc_enable(nand->pmecc, op);
738         if (ret)
739                 dev_err(nc->dev,
740                         "Failed to enable ECC engine (err = %d)\n", ret);
741
742         return ret;
743 }
744
745 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
746 {
747         struct atmel_nand *nand = to_atmel_nand(chip);
748
749         if (!raw)
750                 atmel_pmecc_disable(nand->pmecc);
751 }
752
753 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
754 {
755         struct atmel_nand *nand = to_atmel_nand(chip);
756         struct mtd_info *mtd = nand_to_mtd(chip);
757         struct atmel_nand_controller *nc;
758         struct mtd_oob_region oobregion;
759         void *eccbuf;
760         int ret, i;
761
762         nc = to_nand_controller(chip->controller);
763
764         if (raw)
765                 return 0;
766
767         ret = atmel_pmecc_wait_rdy(nand->pmecc);
768         if (ret) {
769                 dev_err(nc->dev,
770                         "Failed to transfer NAND page data (err = %d)\n",
771                         ret);
772                 return ret;
773         }
774
775         mtd_ooblayout_ecc(mtd, 0, &oobregion);
776         eccbuf = chip->oob_poi + oobregion.offset;
777
778         for (i = 0; i < chip->ecc.steps; i++) {
779                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
780                                                    eccbuf);
781                 eccbuf += chip->ecc.bytes;
782         }
783
784         return 0;
785 }
786
787 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
788                                          bool raw)
789 {
790         struct atmel_nand *nand = to_atmel_nand(chip);
791         struct mtd_info *mtd = nand_to_mtd(chip);
792         struct atmel_nand_controller *nc;
793         struct mtd_oob_region oobregion;
794         int ret, i, max_bitflips = 0;
795         void *databuf, *eccbuf;
796
797         nc = to_nand_controller(chip->controller);
798
799         if (raw)
800                 return 0;
801
802         ret = atmel_pmecc_wait_rdy(nand->pmecc);
803         if (ret) {
804                 dev_err(nc->dev,
805                         "Failed to read NAND page data (err = %d)\n",
806                         ret);
807                 return ret;
808         }
809
810         mtd_ooblayout_ecc(mtd, 0, &oobregion);
811         eccbuf = chip->oob_poi + oobregion.offset;
812         databuf = buf;
813
814         for (i = 0; i < chip->ecc.steps; i++) {
815                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
816                                                  eccbuf);
817                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
818                         ret = nand_check_erased_ecc_chunk(databuf,
819                                                           chip->ecc.size,
820                                                           eccbuf,
821                                                           chip->ecc.bytes,
822                                                           NULL, 0,
823                                                           chip->ecc.strength);
824
825                 if (ret >= 0)
826                         max_bitflips = max(ret, max_bitflips);
827                 else
828                         mtd->ecc_stats.failed++;
829
830                 databuf += chip->ecc.size;
831                 eccbuf += chip->ecc.bytes;
832         }
833
834         return max_bitflips;
835 }
836
837 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
838                                      bool oob_required, int page, bool raw)
839 {
840         struct mtd_info *mtd = nand_to_mtd(chip);
841         struct atmel_nand *nand = to_atmel_nand(chip);
842         int ret;
843
844         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
845         if (ret)
846                 return ret;
847
848         atmel_nand_write_buf(mtd, buf, mtd->writesize);
849
850         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
851         if (ret) {
852                 atmel_pmecc_disable(nand->pmecc);
853                 return ret;
854         }
855
856         atmel_nand_pmecc_disable(chip, raw);
857
858         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
859
860         return 0;
861 }
862
863 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
864                                        struct nand_chip *chip, const u8 *buf,
865                                        int oob_required, int page)
866 {
867         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
868 }
869
870 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
871                                            struct nand_chip *chip,
872                                            const u8 *buf, int oob_required,
873                                            int page)
874 {
875         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
876 }
877
878 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
879                                     bool oob_required, int page, bool raw)
880 {
881         struct mtd_info *mtd = nand_to_mtd(chip);
882         int ret;
883
884         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
885         if (ret)
886                 return ret;
887
888         atmel_nand_read_buf(mtd, buf, mtd->writesize);
889         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
890
891         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
892
893         atmel_nand_pmecc_disable(chip, raw);
894
895         return ret;
896 }
897
898 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
899                                       struct nand_chip *chip, u8 *buf,
900                                       int oob_required, int page)
901 {
902         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
903 }
904
905 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
906                                           struct nand_chip *chip, u8 *buf,
907                                           int oob_required, int page)
908 {
909         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
910 }
911
912 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
913                                           const u8 *buf, bool oob_required,
914                                           int page, bool raw)
915 {
916         struct mtd_info *mtd = nand_to_mtd(chip);
917         struct atmel_nand *nand = to_atmel_nand(chip);
918         struct atmel_hsmc_nand_controller *nc;
919         int ret, status;
920
921         nc = to_hsmc_nand_controller(chip->controller);
922
923         atmel_nfc_copy_to_sram(chip, buf, false);
924
925         nc->op.cmds[0] = NAND_CMD_SEQIN;
926         nc->op.ncmds = 1;
927         atmel_nfc_set_op_addr(chip, page, 0x0);
928         nc->op.cs = nand->activecs->id;
929         nc->op.data = ATMEL_NFC_WRITE_DATA;
930
931         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
932         if (ret)
933                 return ret;
934
935         ret = atmel_nfc_exec_op(nc, false);
936         if (ret) {
937                 atmel_nand_pmecc_disable(chip, raw);
938                 dev_err(nc->base.dev,
939                         "Failed to transfer NAND page data (err = %d)\n",
940                         ret);
941                 return ret;
942         }
943
944         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
945
946         atmel_nand_pmecc_disable(chip, raw);
947
948         if (ret)
949                 return ret;
950
951         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
952
953         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
954         nc->op.ncmds = 1;
955         nc->op.cs = nand->activecs->id;
956         ret = atmel_nfc_exec_op(nc, false);
957         if (ret)
958                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
959                         ret);
960
961         status = chip->waitfunc(mtd, chip);
962         if (status & NAND_STATUS_FAIL)
963                 return -EIO;
964
965         return ret;
966 }
967
968 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
969                                             struct nand_chip *chip,
970                                             const u8 *buf, int oob_required,
971                                             int page)
972 {
973         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
974                                               false);
975 }
976
977 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
978                                                 struct nand_chip *chip,
979                                                 const u8 *buf,
980                                                 int oob_required, int page)
981 {
982         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
983                                               true);
984 }
985
986 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
987                                          bool oob_required, int page,
988                                          bool raw)
989 {
990         struct mtd_info *mtd = nand_to_mtd(chip);
991         struct atmel_nand *nand = to_atmel_nand(chip);
992         struct atmel_hsmc_nand_controller *nc;
993         int ret;
994
995         nc = to_hsmc_nand_controller(chip->controller);
996
997         /*
998          * Optimized read page accessors only work when the NAND R/B pin is
999          * connected to a native SoC R/B pin. If that's not the case, fallback
1000          * to the non-optimized one.
1001          */
1002         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1003                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1004
1005                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1006                                                 raw);
1007         }
1008
1009         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1010
1011         if (mtd->writesize > 512)
1012                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1013
1014         atmel_nfc_set_op_addr(chip, page, 0x0);
1015         nc->op.cs = nand->activecs->id;
1016         nc->op.data = ATMEL_NFC_READ_DATA;
1017
1018         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1019         if (ret)
1020                 return ret;
1021
1022         ret = atmel_nfc_exec_op(nc, false);
1023         if (ret) {
1024                 atmel_nand_pmecc_disable(chip, raw);
1025                 dev_err(nc->base.dev,
1026                         "Failed to load NAND page data (err = %d)\n",
1027                         ret);
1028                 return ret;
1029         }
1030
1031         atmel_nfc_copy_from_sram(chip, buf, true);
1032
1033         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1034
1035         atmel_nand_pmecc_disable(chip, raw);
1036
1037         return ret;
1038 }
1039
1040 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1041                                            struct nand_chip *chip, u8 *buf,
1042                                            int oob_required, int page)
1043 {
1044         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1045                                              false);
1046 }
1047
1048 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1049                                                struct nand_chip *chip,
1050                                                u8 *buf, int oob_required,
1051                                                int page)
1052 {
1053         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1054                                              true);
1055 }
1056
1057 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1058 {
1059         struct mtd_info *mtd = nand_to_mtd(chip);
1060         struct atmel_nand *nand = to_atmel_nand(chip);
1061         struct atmel_nand_controller *nc;
1062         struct atmel_pmecc_user_req req;
1063
1064         nc = to_nand_controller(chip->controller);
1065
1066         if (!nc->pmecc) {
1067                 dev_err(nc->dev, "HW ECC not supported\n");
1068                 return -ENOTSUPP;
1069         }
1070
1071         if (nc->caps->legacy_of_bindings) {
1072                 u32 val;
1073
1074                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1075                                           &val))
1076                         chip->ecc.strength = val;
1077
1078                 if (!of_property_read_u32(nc->dev->of_node,
1079                                           "atmel,pmecc-sector-size",
1080                                           &val))
1081                         chip->ecc.size = val;
1082         }
1083
1084         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1085                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1086         else if (chip->ecc.strength)
1087                 req.ecc.strength = chip->ecc.strength;
1088         else if (chip->ecc_strength_ds)
1089                 req.ecc.strength = chip->ecc_strength_ds;
1090         else
1091                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1092
1093         if (chip->ecc.size)
1094                 req.ecc.sectorsize = chip->ecc.size;
1095         else if (chip->ecc_step_ds)
1096                 req.ecc.sectorsize = chip->ecc_step_ds;
1097         else
1098                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1099
1100         req.pagesize = mtd->writesize;
1101         req.oobsize = mtd->oobsize;
1102
1103         if (mtd->writesize <= 512) {
1104                 req.ecc.bytes = 4;
1105                 req.ecc.ooboffset = 0;
1106         } else {
1107                 req.ecc.bytes = mtd->oobsize - 2;
1108                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1109         }
1110
1111         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1112         if (IS_ERR(nand->pmecc))
1113                 return PTR_ERR(nand->pmecc);
1114
1115         chip->ecc.algo = NAND_ECC_BCH;
1116         chip->ecc.size = req.ecc.sectorsize;
1117         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1118         chip->ecc.strength = req.ecc.strength;
1119
1120         chip->options |= NAND_NO_SUBPAGE_WRITE;
1121
1122         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1123
1124         return 0;
1125 }
1126
1127 static int atmel_nand_ecc_init(struct atmel_nand *nand)
1128 {
1129         struct nand_chip *chip = &nand->base;
1130         struct atmel_nand_controller *nc;
1131         int ret;
1132
1133         nc = to_nand_controller(chip->controller);
1134
1135         switch (chip->ecc.mode) {
1136         case NAND_ECC_NONE:
1137         case NAND_ECC_SOFT:
1138                 /*
1139                  * Nothing to do, the core will initialize everything for us.
1140                  */
1141                 break;
1142
1143         case NAND_ECC_HW:
1144                 ret = atmel_nand_pmecc_init(chip);
1145                 if (ret)
1146                         return ret;
1147
1148                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1149                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1150                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1151                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1152                 break;
1153
1154         default:
1155                 /* Other modes are not supported. */
1156                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1157                         chip->ecc.mode);
1158                 return -ENOTSUPP;
1159         }
1160
1161         return 0;
1162 }
1163
1164 static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
1165 {
1166         struct nand_chip *chip = &nand->base;
1167         int ret;
1168
1169         ret = atmel_nand_ecc_init(nand);
1170         if (ret)
1171                 return ret;
1172
1173         if (chip->ecc.mode != NAND_ECC_HW)
1174                 return 0;
1175
1176         /* Adjust the ECC operations for the HSMC IP. */
1177         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1178         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1179         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1180         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1181         chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1182
1183         return 0;
1184 }
1185
1186 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1187                                         const struct nand_data_interface *conf,
1188                                         struct atmel_smc_cs_conf *smcconf)
1189 {
1190         u32 ncycles, totalcycles, timeps, mckperiodps;
1191         struct atmel_nand_controller *nc;
1192         int ret;
1193
1194         nc = to_nand_controller(nand->base.controller);
1195
1196         /* DDR interface not supported. */
1197         if (conf->type != NAND_SDR_IFACE)
1198                 return -ENOTSUPP;
1199
1200         /*
1201          * tRC < 30ns implies EDO mode. This controller does not support this
1202          * mode.
1203          */
1204         if (conf->timings.sdr.tRC_min < 30000)
1205                 return -ENOTSUPP;
1206
1207         atmel_smc_cs_conf_init(smcconf);
1208
1209         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1210         mckperiodps *= 1000;
1211
1212         /*
1213          * Set write pulse timing. This one is easy to extract:
1214          *
1215          * NWE_PULSE = tWP
1216          */
1217         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1218         totalcycles = ncycles;
1219         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1220                                           ncycles);
1221         if (ret)
1222                 return ret;
1223
1224         /*
1225          * The write setup timing depends on the operation done on the NAND.
1226          * All operations goes through the same data bus, but the operation
1227          * type depends on the address we are writing to (ALE/CLE address
1228          * lines).
1229          * Since we have no way to differentiate the different operations at
1230          * the SMC level, we must consider the worst case (the biggest setup
1231          * time among all operation types):
1232          *
1233          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1234          */
1235         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1236                       conf->timings.sdr.tALS_min);
1237         timeps = max(timeps, conf->timings.sdr.tDS_min);
1238         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1239         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1240         totalcycles += ncycles;
1241         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1242                                           ncycles);
1243         if (ret)
1244                 return ret;
1245
1246         /*
1247          * As for the write setup timing, the write hold timing depends on the
1248          * operation done on the NAND:
1249          *
1250          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1251          */
1252         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1253                       conf->timings.sdr.tALH_min);
1254         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1255                       conf->timings.sdr.tWH_min);
1256         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1257         totalcycles += ncycles;
1258
1259         /*
1260          * The write cycle timing is directly matching tWC, but is also
1261          * dependent on the other timings on the setup and hold timings we
1262          * calculated earlier, which gives:
1263          *
1264          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1265          */
1266         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1267         ncycles = max(totalcycles, ncycles);
1268         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1269                                           ncycles);
1270         if (ret)
1271                 return ret;
1272
1273         /*
1274          * We don't want the CS line to be toggled between each byte/word
1275          * transfer to the NAND. The only way to guarantee that is to have the
1276          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1277          *
1278          * NCS_WR_PULSE = NWE_CYCLE
1279          */
1280         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1281                                           ncycles);
1282         if (ret)
1283                 return ret;
1284
1285         /*
1286          * As for the write setup timing, the read hold timing depends on the
1287          * operation done on the NAND:
1288          *
1289          * NRD_HOLD = max(tREH, tRHOH)
1290          */
1291         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1292         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1293         totalcycles = ncycles;
1294
1295         /*
1296          * TDF = tRHZ - NRD_HOLD
1297          */
1298         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1299         ncycles -= totalcycles;
1300
1301         /*
1302          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1303          * we might end up with a config that does not fit in the TDF field.
1304          * Just take the max value in this case and hope that the NAND is more
1305          * tolerant than advertised.
1306          */
1307         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1308                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1309         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1310                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1311
1312         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1313                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1314
1315         /*
1316          * Read pulse timing directly matches tRP:
1317          *
1318          * NRD_PULSE = tRP
1319          */
1320         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1321         totalcycles += ncycles;
1322         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1323                                           ncycles);
1324         if (ret)
1325                 return ret;
1326
1327         /*
1328          * The write cycle timing is directly matching tWC, but is also
1329          * dependent on the setup and hold timings we calculated earlier,
1330          * which gives:
1331          *
1332          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1333          *
1334          * NRD_SETUP is always 0.
1335          */
1336         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1337         ncycles = max(totalcycles, ncycles);
1338         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1339                                           ncycles);
1340         if (ret)
1341                 return ret;
1342
1343         /*
1344          * We don't want the CS line to be toggled between each byte/word
1345          * transfer from the NAND. The only way to guarantee that is to have
1346          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1347          *
1348          * NCS_RD_PULSE = NRD_CYCLE
1349          */
1350         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1351                                           ncycles);
1352         if (ret)
1353                 return ret;
1354
1355         /* Txxx timings are directly matching tXXX ones. */
1356         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1357         ret = atmel_smc_cs_conf_set_timing(smcconf,
1358                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1359                                            ncycles);
1360         if (ret)
1361                 return ret;
1362
1363         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1364         ret = atmel_smc_cs_conf_set_timing(smcconf,
1365                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1366                                            ncycles);
1367         /*
1368          * Version 4 of the ONFI spec mandates that tADL be at least 400
1369          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1370          * fit in the tADL field of the SMC reg. We need to relax the check and
1371          * accept the -ERANGE return code.
1372          *
1373          * Note that previous versions of the ONFI spec had a lower tADL_min
1374          * (100 or 200 ns). It's not clear why this timing constraint got
1375          * increased but it seems most NANDs are fine with values lower than
1376          * 400ns, so we should be safe.
1377          */
1378         if (ret && ret != -ERANGE)
1379                 return ret;
1380
1381         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1382         ret = atmel_smc_cs_conf_set_timing(smcconf,
1383                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1384                                            ncycles);
1385         if (ret)
1386                 return ret;
1387
1388         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1389         ret = atmel_smc_cs_conf_set_timing(smcconf,
1390                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1391                                            ncycles);
1392         if (ret)
1393                 return ret;
1394
1395         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1396         ret = atmel_smc_cs_conf_set_timing(smcconf,
1397                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1398                                            ncycles);
1399         if (ret)
1400                 return ret;
1401
1402         /* Attach the CS line to the NFC logic. */
1403         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1404
1405         /* Set the appropriate data bus width. */
1406         if (nand->base.options & NAND_BUSWIDTH_16)
1407                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1408
1409         /* Operate in NRD/NWE READ/WRITEMODE. */
1410         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1411                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1412
1413         return 0;
1414 }
1415
1416 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1417                                         int csline,
1418                                         const struct nand_data_interface *conf)
1419 {
1420         struct atmel_nand_controller *nc;
1421         struct atmel_smc_cs_conf smcconf;
1422         struct atmel_nand_cs *cs;
1423         int ret;
1424
1425         nc = to_nand_controller(nand->base.controller);
1426
1427         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1428         if (ret)
1429                 return ret;
1430
1431         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1432                 return 0;
1433
1434         cs = &nand->cs[csline];
1435         cs->smcconf = smcconf;
1436         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1437
1438         return 0;
1439 }
1440
1441 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1442                                         int csline,
1443                                         const struct nand_data_interface *conf)
1444 {
1445         struct atmel_nand_controller *nc;
1446         struct atmel_smc_cs_conf smcconf;
1447         struct atmel_nand_cs *cs;
1448         int ret;
1449
1450         nc = to_nand_controller(nand->base.controller);
1451
1452         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1453         if (ret)
1454                 return ret;
1455
1456         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1457                 return 0;
1458
1459         cs = &nand->cs[csline];
1460         cs->smcconf = smcconf;
1461
1462         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1463                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1464
1465         atmel_hsmc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1466
1467         return 0;
1468 }
1469
1470 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1471                                         const struct nand_data_interface *conf)
1472 {
1473         struct nand_chip *chip = mtd_to_nand(mtd);
1474         struct atmel_nand *nand = to_atmel_nand(chip);
1475         struct atmel_nand_controller *nc;
1476
1477         nc = to_nand_controller(nand->base.controller);
1478
1479         if (csline >= nand->numcs ||
1480             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1481                 return -EINVAL;
1482
1483         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1484 }
1485
1486 static void atmel_nand_init(struct atmel_nand_controller *nc,
1487                             struct atmel_nand *nand)
1488 {
1489         struct nand_chip *chip = &nand->base;
1490         struct mtd_info *mtd = nand_to_mtd(chip);
1491
1492         mtd->dev.parent = nc->dev;
1493         nand->base.controller = &nc->base;
1494
1495         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1496         chip->read_byte = atmel_nand_read_byte;
1497         chip->read_word = atmel_nand_read_word;
1498         chip->write_byte = atmel_nand_write_byte;
1499         chip->read_buf = atmel_nand_read_buf;
1500         chip->write_buf = atmel_nand_write_buf;
1501         chip->select_chip = atmel_nand_select_chip;
1502
1503         if (nc->mck && nc->caps->ops->setup_data_interface)
1504                 chip->setup_data_interface = atmel_nand_setup_data_interface;
1505
1506         /* Some NANDs require a longer delay than the default one (20us). */
1507         chip->chip_delay = 40;
1508
1509         /*
1510          * Use a bounce buffer when the buffer passed by the MTD user is not
1511          * suitable for DMA.
1512          */
1513         if (nc->dmac)
1514                 chip->options |= NAND_USE_BOUNCE_BUFFER;
1515
1516         /* Default to HW ECC if pmecc is available. */
1517         if (nc->pmecc)
1518                 chip->ecc.mode = NAND_ECC_HW;
1519 }
1520
1521 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1522                                 struct atmel_nand *nand)
1523 {
1524         struct nand_chip *chip = &nand->base;
1525         struct atmel_smc_nand_controller *smc_nc;
1526         int i;
1527
1528         atmel_nand_init(nc, nand);
1529
1530         smc_nc = to_smc_nand_controller(chip->controller);
1531         if (!smc_nc->matrix)
1532                 return;
1533
1534         /* Attach the CS to the NAND Flash logic. */
1535         for (i = 0; i < nand->numcs; i++)
1536                 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1537                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1538 }
1539
1540 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1541                                  struct atmel_nand *nand)
1542 {
1543         struct nand_chip *chip = &nand->base;
1544
1545         atmel_nand_init(nc, nand);
1546
1547         /* Overload some methods for the HSMC controller. */
1548         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1549         chip->select_chip = atmel_hsmc_nand_select_chip;
1550 }
1551
1552 static int atmel_nand_detect(struct atmel_nand *nand)
1553 {
1554         struct nand_chip *chip = &nand->base;
1555         struct mtd_info *mtd = nand_to_mtd(chip);
1556         struct atmel_nand_controller *nc;
1557         int ret;
1558
1559         nc = to_nand_controller(chip->controller);
1560
1561         ret = nand_scan_ident(mtd, nand->numcs, NULL);
1562         if (ret)
1563                 dev_err(nc->dev, "nand_scan_ident() failed: %d\n", ret);
1564
1565         return ret;
1566 }
1567
1568 static int atmel_nand_unregister(struct atmel_nand *nand)
1569 {
1570         struct nand_chip *chip = &nand->base;
1571         struct mtd_info *mtd = nand_to_mtd(chip);
1572         int ret;
1573
1574         ret = mtd_device_unregister(mtd);
1575         if (ret)
1576                 return ret;
1577
1578         nand_cleanup(chip);
1579         list_del(&nand->node);
1580
1581         return 0;
1582 }
1583
1584 static int atmel_nand_register(struct atmel_nand *nand)
1585 {
1586         struct nand_chip *chip = &nand->base;
1587         struct mtd_info *mtd = nand_to_mtd(chip);
1588         struct atmel_nand_controller *nc;
1589         int ret;
1590
1591         nc = to_nand_controller(chip->controller);
1592
1593         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1594                 /*
1595                  * We keep the MTD name unchanged to avoid breaking platforms
1596                  * where the MTD cmdline parser is used and the bootloader
1597                  * has not been updated to use the new naming scheme.
1598                  */
1599                 mtd->name = "atmel_nand";
1600         } else if (!mtd->name) {
1601                 /*
1602                  * If the new bindings are used and the bootloader has not been
1603                  * updated to pass a new mtdparts parameter on the cmdline, you
1604                  * should define the following property in your nand node:
1605                  *
1606                  *      label = "atmel_nand";
1607                  *
1608                  * This way, mtd->name will be set by the core when
1609                  * nand_set_flash_node() is called.
1610                  */
1611                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1612                                            "%s:nand.%d", dev_name(nc->dev),
1613                                            nand->cs[0].id);
1614                 if (!mtd->name) {
1615                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1616                         return -ENOMEM;
1617                 }
1618         }
1619
1620         ret = nand_scan_tail(mtd);
1621         if (ret) {
1622                 dev_err(nc->dev, "nand_scan_tail() failed: %d\n", ret);
1623                 return ret;
1624         }
1625
1626         ret = mtd_device_register(mtd, NULL, 0);
1627         if (ret) {
1628                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1629                 nand_cleanup(chip);
1630                 return ret;
1631         }
1632
1633         list_add_tail(&nand->node, &nc->chips);
1634
1635         return 0;
1636 }
1637
1638 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1639                                             struct device_node *np,
1640                                             int reg_cells)
1641 {
1642         struct atmel_nand *nand;
1643         struct gpio_desc *gpio;
1644         int numcs, ret, i;
1645
1646         numcs = of_property_count_elems_of_size(np, "reg",
1647                                                 reg_cells * sizeof(u32));
1648         if (numcs < 1) {
1649                 dev_err(nc->dev, "Missing or invalid reg property\n");
1650                 return ERR_PTR(-EINVAL);
1651         }
1652
1653         nand = devm_kzalloc(nc->dev,
1654                             sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1655                             GFP_KERNEL);
1656         if (!nand) {
1657                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1658                 return ERR_PTR(-ENOMEM);
1659         }
1660
1661         nand->numcs = numcs;
1662
1663         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1664                                                       &np->fwnode, GPIOD_IN,
1665                                                       "nand-det");
1666         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1667                 dev_err(nc->dev,
1668                         "Failed to get detect gpio (err = %ld)\n",
1669                         PTR_ERR(gpio));
1670                 return ERR_CAST(gpio);
1671         }
1672
1673         if (!IS_ERR(gpio))
1674                 nand->cdgpio = gpio;
1675
1676         for (i = 0; i < numcs; i++) {
1677                 struct resource res;
1678                 u32 val;
1679
1680                 ret = of_address_to_resource(np, 0, &res);
1681                 if (ret) {
1682                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1683                                 ret);
1684                         return ERR_PTR(ret);
1685                 }
1686
1687                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1688                                                  &val);
1689                 if (ret) {
1690                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1691                                 ret);
1692                         return ERR_PTR(ret);
1693                 }
1694
1695                 nand->cs[i].id = val;
1696
1697                 nand->cs[i].io.dma = res.start;
1698                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1699                 if (IS_ERR(nand->cs[i].io.virt))
1700                         return ERR_CAST(nand->cs[i].io.virt);
1701
1702                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1703                         if (val > ATMEL_NFC_MAX_RB_ID)
1704                                 return ERR_PTR(-EINVAL);
1705
1706                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1707                         nand->cs[i].rb.id = val;
1708                 } else {
1709                         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1710                                                         "rb", i, &np->fwnode,
1711                                                         GPIOD_IN, "nand-rb");
1712                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1713                                 dev_err(nc->dev,
1714                                         "Failed to get R/B gpio (err = %ld)\n",
1715                                         PTR_ERR(gpio));
1716                                 return ERR_CAST(gpio);
1717                         }
1718
1719                         if (!IS_ERR(gpio)) {
1720                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1721                                 nand->cs[i].rb.gpio = gpio;
1722                         }
1723                 }
1724
1725                 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1726                                                               i, &np->fwnode,
1727                                                               GPIOD_OUT_HIGH,
1728                                                               "nand-cs");
1729                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1730                         dev_err(nc->dev,
1731                                 "Failed to get CS gpio (err = %ld)\n",
1732                                 PTR_ERR(gpio));
1733                         return ERR_CAST(gpio);
1734                 }
1735
1736                 if (!IS_ERR(gpio))
1737                         nand->cs[i].csgpio = gpio;
1738         }
1739
1740         nand_set_flash_node(&nand->base, np);
1741
1742         return nand;
1743 }
1744
1745 static int
1746 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1747                                struct atmel_nand *nand)
1748 {
1749         int ret;
1750
1751         /* No card inserted, skip this NAND. */
1752         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1753                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1754                 return 0;
1755         }
1756
1757         nc->caps->ops->nand_init(nc, nand);
1758
1759         ret = atmel_nand_detect(nand);
1760         if (ret)
1761                 return ret;
1762
1763         ret = nc->caps->ops->ecc_init(nand);
1764         if (ret)
1765                 return ret;
1766
1767         return atmel_nand_register(nand);
1768 }
1769
1770 static int
1771 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1772 {
1773         struct atmel_nand *nand, *tmp;
1774         int ret;
1775
1776         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1777                 ret = atmel_nand_unregister(nand);
1778                 if (ret)
1779                         return ret;
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int
1786 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1787 {
1788         struct device *dev = nc->dev;
1789         struct platform_device *pdev = to_platform_device(dev);
1790         struct atmel_nand *nand;
1791         struct gpio_desc *gpio;
1792         struct resource *res;
1793
1794         /*
1795          * Legacy bindings only allow connecting a single NAND with a unique CS
1796          * line to the controller.
1797          */
1798         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1799                             GFP_KERNEL);
1800         if (!nand)
1801                 return -ENOMEM;
1802
1803         nand->numcs = 1;
1804
1805         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1806         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1807         if (IS_ERR(nand->cs[0].io.virt))
1808                 return PTR_ERR(nand->cs[0].io.virt);
1809
1810         nand->cs[0].io.dma = res->start;
1811
1812         /*
1813          * The old driver was hardcoding the CS id to 3 for all sama5
1814          * controllers. Since this id is only meaningful for the sama5
1815          * controller we can safely assign this id to 3 no matter the
1816          * controller.
1817          * If one wants to connect a NAND to a different CS line, he will
1818          * have to use the new bindings.
1819          */
1820         nand->cs[0].id = 3;
1821
1822         /* R/B GPIO. */
1823         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1824         if (IS_ERR(gpio)) {
1825                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1826                         PTR_ERR(gpio));
1827                 return PTR_ERR(gpio);
1828         }
1829
1830         if (gpio) {
1831                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1832                 nand->cs[0].rb.gpio = gpio;
1833         }
1834
1835         /* CS GPIO. */
1836         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1837         if (IS_ERR(gpio)) {
1838                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1839                         PTR_ERR(gpio));
1840                 return PTR_ERR(gpio);
1841         }
1842
1843         nand->cs[0].csgpio = gpio;
1844
1845         /* Card detect GPIO. */
1846         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1847         if (IS_ERR(gpio)) {
1848                 dev_err(dev,
1849                         "Failed to get detect gpio (err = %ld)\n",
1850                         PTR_ERR(gpio));
1851                 return PTR_ERR(gpio);
1852         }
1853
1854         nand->cdgpio = gpio;
1855
1856         nand_set_flash_node(&nand->base, nc->dev->of_node);
1857
1858         return atmel_nand_controller_add_nand(nc, nand);
1859 }
1860
1861 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1862 {
1863         struct device_node *np, *nand_np;
1864         struct device *dev = nc->dev;
1865         int ret, reg_cells;
1866         u32 val;
1867
1868         /* We do not retrieve the SMC syscon when parsing old DTs. */
1869         if (nc->caps->legacy_of_bindings)
1870                 return atmel_nand_controller_legacy_add_nands(nc);
1871
1872         np = dev->of_node;
1873
1874         ret = of_property_read_u32(np, "#address-cells", &val);
1875         if (ret) {
1876                 dev_err(dev, "missing #address-cells property\n");
1877                 return ret;
1878         }
1879
1880         reg_cells = val;
1881
1882         ret = of_property_read_u32(np, "#size-cells", &val);
1883         if (ret) {
1884                 dev_err(dev, "missing #address-cells property\n");
1885                 return ret;
1886         }
1887
1888         reg_cells += val;
1889
1890         for_each_child_of_node(np, nand_np) {
1891                 struct atmel_nand *nand;
1892
1893                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1894                 if (IS_ERR(nand)) {
1895                         ret = PTR_ERR(nand);
1896                         goto err;
1897                 }
1898
1899                 ret = atmel_nand_controller_add_nand(nc, nand);
1900                 if (ret)
1901                         goto err;
1902         }
1903
1904         return 0;
1905
1906 err:
1907         atmel_nand_controller_remove_nands(nc);
1908
1909         return ret;
1910 }
1911
1912 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1913 {
1914         if (nc->dmac)
1915                 dma_release_channel(nc->dmac);
1916
1917         clk_put(nc->mck);
1918 }
1919
1920 static const struct of_device_id atmel_matrix_of_ids[] = {
1921         {
1922                 .compatible = "atmel,at91sam9260-matrix",
1923                 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1924         },
1925         {
1926                 .compatible = "atmel,at91sam9261-matrix",
1927                 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1928         },
1929         {
1930                 .compatible = "atmel,at91sam9263-matrix",
1931                 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1932         },
1933         {
1934                 .compatible = "atmel,at91sam9rl-matrix",
1935                 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1936         },
1937         {
1938                 .compatible = "atmel,at91sam9g45-matrix",
1939                 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1940         },
1941         {
1942                 .compatible = "atmel,at91sam9n12-matrix",
1943                 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1944         },
1945         {
1946                 .compatible = "atmel,at91sam9x5-matrix",
1947                 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1948         },
1949         { /* sentinel */ },
1950 };
1951
1952 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1953                                 struct platform_device *pdev,
1954                                 const struct atmel_nand_controller_caps *caps)
1955 {
1956         struct device *dev = &pdev->dev;
1957         struct device_node *np = dev->of_node;
1958         int ret;
1959
1960         nand_hw_control_init(&nc->base);
1961         INIT_LIST_HEAD(&nc->chips);
1962         nc->dev = dev;
1963         nc->caps = caps;
1964
1965         platform_set_drvdata(pdev, nc);
1966
1967         nc->pmecc = devm_atmel_pmecc_get(dev);
1968         if (IS_ERR(nc->pmecc)) {
1969                 ret = PTR_ERR(nc->pmecc);
1970                 if (ret != -EPROBE_DEFER)
1971                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1972                                 ret);
1973                 return ret;
1974         }
1975
1976         if (nc->caps->has_dma) {
1977                 dma_cap_mask_t mask;
1978
1979                 dma_cap_zero(mask);
1980                 dma_cap_set(DMA_MEMCPY, mask);
1981
1982                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1983                 if (!nc->dmac)
1984                         dev_err(nc->dev, "Failed to request DMA channel\n");
1985         }
1986
1987         /* We do not retrieve the SMC syscon when parsing old DTs. */
1988         if (nc->caps->legacy_of_bindings)
1989                 return 0;
1990
1991         nc->mck = of_clk_get(dev->parent->of_node, 0);
1992         if (IS_ERR(nc->mck)) {
1993                 dev_err(dev, "Failed to retrieve MCK clk\n");
1994                 return PTR_ERR(nc->mck);
1995         }
1996
1997         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1998         if (!np) {
1999                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2000                 return -EINVAL;
2001         }
2002
2003         nc->smc = syscon_node_to_regmap(np);
2004         of_node_put(np);
2005         if (IS_ERR(nc->smc)) {
2006                 ret = PTR_ERR(nc->smc);
2007                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2008                 return ret;
2009         }
2010
2011         return 0;
2012 }
2013
2014 static int
2015 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2016 {
2017         struct device *dev = nc->base.dev;
2018         const struct of_device_id *match;
2019         struct device_node *np;
2020         int ret;
2021
2022         /* We do not retrieve the matrix syscon when parsing old DTs. */
2023         if (nc->base.caps->legacy_of_bindings)
2024                 return 0;
2025
2026         np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2027         if (!np)
2028                 return 0;
2029
2030         match = of_match_node(atmel_matrix_of_ids, np);
2031         if (!match) {
2032                 of_node_put(np);
2033                 return 0;
2034         }
2035
2036         nc->matrix = syscon_node_to_regmap(np);
2037         of_node_put(np);
2038         if (IS_ERR(nc->matrix)) {
2039                 ret = PTR_ERR(nc->matrix);
2040                 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2041                 return ret;
2042         }
2043
2044         nc->ebi_csa_offs = (unsigned int)match->data;
2045
2046         /*
2047          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2048          * add 4 to ->ebi_csa_offs.
2049          */
2050         if (of_device_is_compatible(dev->parent->of_node,
2051                                     "atmel,at91sam9263-ebi1"))
2052                 nc->ebi_csa_offs += 4;
2053
2054         return 0;
2055 }
2056
2057 static int
2058 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2059 {
2060         struct regmap_config regmap_conf = {
2061                 .reg_bits = 32,
2062                 .val_bits = 32,
2063                 .reg_stride = 4,
2064         };
2065
2066         struct device *dev = nc->base.dev;
2067         struct device_node *nand_np, *nfc_np;
2068         void __iomem *iomem;
2069         struct resource res;
2070         int ret;
2071
2072         nand_np = dev->of_node;
2073         nfc_np = of_find_compatible_node(dev->of_node, NULL,
2074                                          "atmel,sama5d3-nfc");
2075
2076         nc->clk = of_clk_get(nfc_np, 0);
2077         if (IS_ERR(nc->clk)) {
2078                 ret = PTR_ERR(nc->clk);
2079                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2080                         ret);
2081                 goto out;
2082         }
2083
2084         ret = clk_prepare_enable(nc->clk);
2085         if (ret) {
2086                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2087                         ret);
2088                 goto out;
2089         }
2090
2091         nc->irq = of_irq_get(nand_np, 0);
2092         if (nc->irq <= 0) {
2093                 ret = nc->irq ?: -ENXIO;
2094                 if (ret != -EPROBE_DEFER)
2095                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2096                                 ret);
2097                 goto out;
2098         }
2099
2100         ret = of_address_to_resource(nfc_np, 0, &res);
2101         if (ret) {
2102                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2103                         ret);
2104                 goto out;
2105         }
2106
2107         iomem = devm_ioremap_resource(dev, &res);
2108         if (IS_ERR(iomem)) {
2109                 ret = PTR_ERR(iomem);
2110                 goto out;
2111         }
2112
2113         regmap_conf.name = "nfc-io";
2114         regmap_conf.max_register = resource_size(&res) - 4;
2115         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2116         if (IS_ERR(nc->io)) {
2117                 ret = PTR_ERR(nc->io);
2118                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2119                         ret);
2120                 goto out;
2121         }
2122
2123         ret = of_address_to_resource(nfc_np, 1, &res);
2124         if (ret) {
2125                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2126                         ret);
2127                 goto out;
2128         }
2129
2130         iomem = devm_ioremap_resource(dev, &res);
2131         if (IS_ERR(iomem)) {
2132                 ret = PTR_ERR(iomem);
2133                 goto out;
2134         }
2135
2136         regmap_conf.name = "smc";
2137         regmap_conf.max_register = resource_size(&res) - 4;
2138         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2139         if (IS_ERR(nc->base.smc)) {
2140                 ret = PTR_ERR(nc->base.smc);
2141                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2142                         ret);
2143                 goto out;
2144         }
2145
2146         ret = of_address_to_resource(nfc_np, 2, &res);
2147         if (ret) {
2148                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2149                         ret);
2150                 goto out;
2151         }
2152
2153         nc->sram.virt = devm_ioremap_resource(dev, &res);
2154         if (IS_ERR(nc->sram.virt)) {
2155                 ret = PTR_ERR(nc->sram.virt);
2156                 goto out;
2157         }
2158
2159         nc->sram.dma = res.start;
2160
2161 out:
2162         of_node_put(nfc_np);
2163
2164         return ret;
2165 }
2166
2167 static int
2168 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2169 {
2170         struct device *dev = nc->base.dev;
2171         struct device_node *np;
2172         int ret;
2173
2174         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2175         if (!np) {
2176                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2177                 return -EINVAL;
2178         }
2179
2180         nc->irq = of_irq_get(np, 0);
2181         of_node_put(np);
2182         if (nc->irq <= 0) {
2183                 ret = nc->irq ?: -ENXIO;
2184                 if (ret != -EPROBE_DEFER)
2185                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2186                                 ret);
2187                 return ret;
2188         }
2189
2190         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2191         if (!np) {
2192                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2193                 return -EINVAL;
2194         }
2195
2196         nc->io = syscon_node_to_regmap(np);
2197         of_node_put(np);
2198         if (IS_ERR(nc->io)) {
2199                 ret = PTR_ERR(nc->io);
2200                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2201                 return ret;
2202         }
2203
2204         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2205                                          "atmel,nfc-sram", 0);
2206         if (!nc->sram.pool) {
2207                 dev_err(nc->base.dev, "Missing SRAM\n");
2208                 return -ENOMEM;
2209         }
2210
2211         nc->sram.virt = gen_pool_dma_alloc(nc->sram.pool,
2212                                             ATMEL_NFC_SRAM_SIZE,
2213                                             &nc->sram.dma);
2214         if (!nc->sram.virt) {
2215                 dev_err(nc->base.dev,
2216                         "Could not allocate memory from the NFC SRAM pool\n");
2217                 return -ENOMEM;
2218         }
2219
2220         return 0;
2221 }
2222
2223 static int
2224 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2225 {
2226         struct atmel_hsmc_nand_controller *hsmc_nc;
2227         int ret;
2228
2229         ret = atmel_nand_controller_remove_nands(nc);
2230         if (ret)
2231                 return ret;
2232
2233         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2234         if (hsmc_nc->sram.pool)
2235                 gen_pool_free(hsmc_nc->sram.pool,
2236                               (unsigned long)hsmc_nc->sram.virt,
2237                               ATMEL_NFC_SRAM_SIZE);
2238
2239         if (hsmc_nc->clk) {
2240                 clk_disable_unprepare(hsmc_nc->clk);
2241                 clk_put(hsmc_nc->clk);
2242         }
2243
2244         atmel_nand_controller_cleanup(nc);
2245
2246         return 0;
2247 }
2248
2249 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2250                                 const struct atmel_nand_controller_caps *caps)
2251 {
2252         struct device *dev = &pdev->dev;
2253         struct atmel_hsmc_nand_controller *nc;
2254         int ret;
2255
2256         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2257         if (!nc)
2258                 return -ENOMEM;
2259
2260         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2261         if (ret)
2262                 return ret;
2263
2264         if (caps->legacy_of_bindings)
2265                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2266         else
2267                 ret = atmel_hsmc_nand_controller_init(nc);
2268
2269         if (ret)
2270                 return ret;
2271
2272         /* Make sure all irqs are masked before registering our IRQ handler. */
2273         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2274         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2275                                IRQF_SHARED, "nfc", nc);
2276         if (ret) {
2277                 dev_err(dev,
2278                         "Could not get register NFC interrupt handler (err = %d)\n",
2279                         ret);
2280                 goto err;
2281         }
2282
2283         /* Initial NFC configuration. */
2284         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2285                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2286
2287         ret = atmel_nand_controller_add_nands(&nc->base);
2288         if (ret)
2289                 goto err;
2290
2291         return 0;
2292
2293 err:
2294         atmel_hsmc_nand_controller_remove(&nc->base);
2295
2296         return ret;
2297 }
2298
2299 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2300         .probe = atmel_hsmc_nand_controller_probe,
2301         .remove = atmel_hsmc_nand_controller_remove,
2302         .ecc_init = atmel_hsmc_nand_ecc_init,
2303         .nand_init = atmel_hsmc_nand_init,
2304         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2305 };
2306
2307 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2308         .has_dma = true,
2309         .ale_offs = BIT(21),
2310         .cle_offs = BIT(22),
2311         .ops = &atmel_hsmc_nc_ops,
2312 };
2313
2314 /* Only used to parse old bindings. */
2315 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2316         .has_dma = true,
2317         .ale_offs = BIT(21),
2318         .cle_offs = BIT(22),
2319         .ops = &atmel_hsmc_nc_ops,
2320         .legacy_of_bindings = true,
2321 };
2322
2323 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2324                                 const struct atmel_nand_controller_caps *caps)
2325 {
2326         struct device *dev = &pdev->dev;
2327         struct atmel_smc_nand_controller *nc;
2328         int ret;
2329
2330         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2331         if (!nc)
2332                 return -ENOMEM;
2333
2334         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2335         if (ret)
2336                 return ret;
2337
2338         ret = atmel_smc_nand_controller_init(nc);
2339         if (ret)
2340                 return ret;
2341
2342         return atmel_nand_controller_add_nands(&nc->base);
2343 }
2344
2345 static int
2346 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2347 {
2348         int ret;
2349
2350         ret = atmel_nand_controller_remove_nands(nc);
2351         if (ret)
2352                 return ret;
2353
2354         atmel_nand_controller_cleanup(nc);
2355
2356         return 0;
2357 }
2358
2359 /*
2360  * The SMC reg layout of at91rm9200 is completely different which prevents us
2361  * from re-using atmel_smc_nand_setup_data_interface() for the
2362  * ->setup_data_interface() hook.
2363  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2364  * ->setup_data_interface() unassigned.
2365  */
2366 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2367         .probe = atmel_smc_nand_controller_probe,
2368         .remove = atmel_smc_nand_controller_remove,
2369         .ecc_init = atmel_nand_ecc_init,
2370         .nand_init = atmel_smc_nand_init,
2371 };
2372
2373 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2374         .ale_offs = BIT(21),
2375         .cle_offs = BIT(22),
2376         .ops = &at91rm9200_nc_ops,
2377 };
2378
2379 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2380         .probe = atmel_smc_nand_controller_probe,
2381         .remove = atmel_smc_nand_controller_remove,
2382         .ecc_init = atmel_nand_ecc_init,
2383         .nand_init = atmel_smc_nand_init,
2384         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2385 };
2386
2387 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2388         .ale_offs = BIT(21),
2389         .cle_offs = BIT(22),
2390         .ops = &atmel_smc_nc_ops,
2391 };
2392
2393 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2394         .ale_offs = BIT(22),
2395         .cle_offs = BIT(21),
2396         .ops = &atmel_smc_nc_ops,
2397 };
2398
2399 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2400         .has_dma = true,
2401         .ale_offs = BIT(21),
2402         .cle_offs = BIT(22),
2403         .ops = &atmel_smc_nc_ops,
2404 };
2405
2406 /* Only used to parse old bindings. */
2407 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2408         .ale_offs = BIT(21),
2409         .cle_offs = BIT(22),
2410         .ops = &atmel_smc_nc_ops,
2411         .legacy_of_bindings = true,
2412 };
2413
2414 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2415         .ale_offs = BIT(22),
2416         .cle_offs = BIT(21),
2417         .ops = &atmel_smc_nc_ops,
2418         .legacy_of_bindings = true,
2419 };
2420
2421 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2422         .has_dma = true,
2423         .ale_offs = BIT(21),
2424         .cle_offs = BIT(22),
2425         .ops = &atmel_smc_nc_ops,
2426         .legacy_of_bindings = true,
2427 };
2428
2429 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2430         {
2431                 .compatible = "atmel,at91rm9200-nand-controller",
2432                 .data = &atmel_rm9200_nc_caps,
2433         },
2434         {
2435                 .compatible = "atmel,at91sam9260-nand-controller",
2436                 .data = &atmel_sam9260_nc_caps,
2437         },
2438         {
2439                 .compatible = "atmel,at91sam9261-nand-controller",
2440                 .data = &atmel_sam9261_nc_caps,
2441         },
2442         {
2443                 .compatible = "atmel,at91sam9g45-nand-controller",
2444                 .data = &atmel_sam9g45_nc_caps,
2445         },
2446         {
2447                 .compatible = "atmel,sama5d3-nand-controller",
2448                 .data = &atmel_sama5_nc_caps,
2449         },
2450         /* Support for old/deprecated bindings: */
2451         {
2452                 .compatible = "atmel,at91rm9200-nand",
2453                 .data = &atmel_rm9200_nand_caps,
2454         },
2455         {
2456                 .compatible = "atmel,sama5d4-nand",
2457                 .data = &atmel_rm9200_nand_caps,
2458         },
2459         {
2460                 .compatible = "atmel,sama5d2-nand",
2461                 .data = &atmel_rm9200_nand_caps,
2462         },
2463         { /* sentinel */ },
2464 };
2465 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2466
2467 static int atmel_nand_controller_probe(struct platform_device *pdev)
2468 {
2469         const struct atmel_nand_controller_caps *caps;
2470
2471         if (pdev->id_entry)
2472                 caps = (void *)pdev->id_entry->driver_data;
2473         else
2474                 caps = of_device_get_match_data(&pdev->dev);
2475
2476         if (!caps) {
2477                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2478                 return -EINVAL;
2479         }
2480
2481         if (caps->legacy_of_bindings) {
2482                 u32 ale_offs = 21;
2483
2484                 /*
2485                  * If we are parsing legacy DT props and the DT contains a
2486                  * valid NFC node, forward the request to the sama5 logic.
2487                  */
2488                 if (of_find_compatible_node(pdev->dev.of_node, NULL,
2489                                             "atmel,sama5d3-nfc"))
2490                         caps = &atmel_sama5_nand_caps;
2491
2492                 /*
2493                  * Even if the compatible says we are dealing with an
2494                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2495                  * this controller supports DMA, which means we are in fact
2496                  * dealing with an at91sam9g45+ controller.
2497                  */
2498                 if (!caps->has_dma &&
2499                     of_property_read_bool(pdev->dev.of_node,
2500                                           "atmel,nand-has-dma"))
2501                         caps = &atmel_sam9g45_nand_caps;
2502
2503                 /*
2504                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2505                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2506                  * actually dealing with an at91sam9261 controller.
2507                  */
2508                 of_property_read_u32(pdev->dev.of_node,
2509                                      "atmel,nand-addr-offset", &ale_offs);
2510                 if (ale_offs != 21)
2511                         caps = &atmel_sam9261_nand_caps;
2512         }
2513
2514         return caps->ops->probe(pdev, caps);
2515 }
2516
2517 static int atmel_nand_controller_remove(struct platform_device *pdev)
2518 {
2519         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2520
2521         return nc->caps->ops->remove(nc);
2522 }
2523
2524 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2525 {
2526         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2527         struct atmel_nand *nand;
2528
2529         list_for_each_entry(nand, &nc->chips, node) {
2530                 int i;
2531
2532                 for (i = 0; i < nand->numcs; i++)
2533                         nand_reset(&nand->base, i);
2534         }
2535
2536         return 0;
2537 }
2538
2539 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2540                          atmel_nand_controller_resume);
2541
2542 static struct platform_driver atmel_nand_controller_driver = {
2543         .driver = {
2544                 .name = "atmel-nand-controller",
2545                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2546         },
2547         .probe = atmel_nand_controller_probe,
2548         .remove = atmel_nand_controller_remove,
2549 };
2550 module_platform_driver(atmel_nand_controller_driver);
2551
2552 MODULE_LICENSE("GPL");
2553 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2554 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2555 MODULE_ALIAS("platform:atmel-nand-controller");