drivers/mmc/host/sdhci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2010 Google, Inc.
   4  */
   5
   6 #include <linux/delay.h>
   7 #include <linux/err.h>
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19 #include <linux/mmc/card.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/mmc/slot-gpio.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/ktime.h>
  25
  26 #include "sdhci-pltfm.h"
  27 #include "cqhci.h"
  28
  29 /* Tegra SDHOST controller vendor register definitions */
  30 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL                   0x100
  31 #define SDHCI_CLOCK_CTRL_TAP_MASK                       0x00ff0000
  32 #define SDHCI_CLOCK_CTRL_TAP_SHIFT                      16
  33 #define SDHCI_CLOCK_CTRL_TRIM_MASK                      0x1f000000
  34 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT                     24
  35 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE          BIT(5)
  36 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE         BIT(3)
  37 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE        BIT(2)
  38
  39 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL                  0x104
  40 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE         BIT(31)
  41
  42 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES                0x10c
  43 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK         0x00003f00
  44 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT        8
  45
  46 #define SDHCI_TEGRA_VENDOR_MISC_CTRL                    0x120
  47 #define SDHCI_MISC_CTRL_ENABLE_SDR104                   0x8
  48 #define SDHCI_MISC_CTRL_ENABLE_SDR50                    0x10
  49 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300           0x20
  50 #define SDHCI_MISC_CTRL_ENABLE_DDR50                    0x200
  51
  52 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG                   0x1b0
  53 #define SDHCI_TEGRA_DLLCAL_CALIBRATE                    BIT(31)
  54
  55 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA                   0x1bc
  56 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE                   BIT(31)
  57
  58 #define SDHCI_VNDR_TUN_CTRL0_0                          0x1c0
  59 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP                 0x20000
  60 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK         0x03fc0000
  61 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT        18
  62 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK                 0x00001fc0
  63 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT                6
  64 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK              0x000e000
  65 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT             13
  66 #define TRIES_128                                       2
  67 #define TRIES_256                                       4
  68 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK          0x7
  69
  70 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0                    0x1c4
  71 #define SDHCI_TEGRA_VNDR_TUN_STATUS0                    0x1C8
  72 #define SDHCI_TEGRA_VNDR_TUN_STATUS1                    0x1CC
  73 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK           0xFF
  74 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT      0x8
  75 #define TUNING_WORD_BIT_SIZE                            32
  76
  77 #define SDHCI_TEGRA_AUTO_CAL_CONFIG                     0x1e4
  78 #define SDHCI_AUTO_CAL_START                            BIT(31)
  79 #define SDHCI_AUTO_CAL_ENABLE                           BIT(29)
  80 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK                 0x0000ffff
  81
  82 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL                  0x1e0
  83 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK    0x0000000f
  84 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL     0x7
  85 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD   BIT(31)
  86 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK          0x07FFF000
  87
  88 #define SDHCI_TEGRA_AUTO_CAL_STATUS                     0x1ec
  89 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE                     BIT(31)
  90
  91 #define NVQUIRK_FORCE_SDHCI_SPEC_200                    BIT(0)
  92 #define NVQUIRK_ENABLE_BLOCK_GAP_DET                    BIT(1)
  93 #define NVQUIRK_ENABLE_SDHCI_SPEC_300                   BIT(2)
  94 #define NVQUIRK_ENABLE_SDR50                            BIT(3)
  95 #define NVQUIRK_ENABLE_SDR104                           BIT(4)
  96 #define NVQUIRK_ENABLE_DDR50                            BIT(5)
  97 #define NVQUIRK_HAS_PADCALIB                            BIT(6)
  98 #define NVQUIRK_NEEDS_PAD_CONTROL                       BIT(7)
  99 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP                 BIT(8)
 100 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING               BIT(9)
 101
 102 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
 103 #define SDHCI_TEGRA_CQE_BASE_ADDR                       0xF000
 104
 105 struct sdhci_tegra_soc_data {
 106         const struct sdhci_pltfm_data *pdata;
 107         u32 nvquirks;
 108         u8 min_tap_delay;
 109         u8 max_tap_delay;
 110 };
 111
 112 /* Magic pull up and pull down pad calibration offsets */
 113 struct sdhci_tegra_autocal_offsets {
 114         u32 pull_up_3v3;
 115         u32 pull_down_3v3;
 116         u32 pull_up_3v3_timeout;
 117         u32 pull_down_3v3_timeout;
 118         u32 pull_up_1v8;
 119         u32 pull_down_1v8;
 120         u32 pull_up_1v8_timeout;
 121         u32 pull_down_1v8_timeout;
 122         u32 pull_up_sdr104;
 123         u32 pull_down_sdr104;
 124         u32 pull_up_hs400;
 125         u32 pull_down_hs400;
 126 };
 127
 128 struct sdhci_tegra {
 129         const struct sdhci_tegra_soc_data *soc_data;
 130         struct gpio_desc *power_gpio;
 131         bool ddr_signaling;
 132         bool pad_calib_required;
 133         bool pad_control_available;
 134
 135         struct reset_control *rst;
 136         struct pinctrl *pinctrl_sdmmc;
 137         struct pinctrl_state *pinctrl_state_3v3;
 138         struct pinctrl_state *pinctrl_state_1v8;
 139         struct pinctrl_state *pinctrl_state_3v3_drv;
 140         struct pinctrl_state *pinctrl_state_1v8_drv;
 141
 142         struct sdhci_tegra_autocal_offsets autocal_offsets;
 143         ktime_t last_calib;
 144
 145         u32 default_tap;
 146         u32 default_trim;
 147         u32 dqs_trim;
 148         bool enable_hwcq;
 149         unsigned long curr_clk_rate;
 150         u8 tuned_tap_delay;
 151 };
 152
 153 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
 154 {
 155         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 156         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 157         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 158
 159         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
 160                         (reg == SDHCI_HOST_VERSION))) {
 161                 /* Erratum: Version register is invalid in HW. */
 162                 return SDHCI_SPEC_200;
 163         }
 164
 165         return readw(host->ioaddr + reg);
 166 }
 167
 168 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 169 {
 170         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 171
 172         switch (reg) {
 173         case SDHCI_TRANSFER_MODE:
 174                 /*
 175                  * Postpone this write, we must do it together with a
 176                  * command write that is down below.
 177                  */
 178                 pltfm_host->xfer_mode_shadow = val;
 179                 return;
 180         case SDHCI_COMMAND:
 181                 writel((val << 16) | pltfm_host->xfer_mode_shadow,
 182                         host->ioaddr + SDHCI_TRANSFER_MODE);
 183                 return;
 184         }
 185
 186         writew(val, host->ioaddr + reg);
 187 }
 188
 189 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 190 {
 191         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 192         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 193         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 194
 195         /* Seems like we're getting spurious timeout and crc errors, so
 196          * disable signalling of them. In case of real errors software
 197          * timers should take care of eventually detecting them.
 198          */
 199         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
 200                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
 201
 202         writel(val, host->ioaddr + reg);
 203
 204         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
 205                         (reg == SDHCI_INT_ENABLE))) {
 206                 /* Erratum: Must enable block gap interrupt detection */
 207                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 208                 if (val & SDHCI_INT_CARD_INT)
 209                         gap_ctrl |= 0x8;
 210                 else
 211                         gap_ctrl &= ~0x8;
 212                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 213         }
 214 }
 215
 216 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
 217 {
 218         bool status;
 219         u32 reg;
 220
 221         reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 222         status = !!(reg & SDHCI_CLOCK_CARD_EN);
 223
 224         if (status == enable)
 225                 return status;
 226
 227         if (enable)
 228                 reg |= SDHCI_CLOCK_CARD_EN;
 229         else
 230                 reg &= ~SDHCI_CLOCK_CARD_EN;
 231
 232         sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
 233
 234         return status;
 235 }
 236
 237 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 238 {
 239         bool is_tuning_cmd = 0;
 240         bool clk_enabled;
 241         u8 cmd;
 242
 243         if (reg == SDHCI_COMMAND) {
 244                 cmd = SDHCI_GET_CMD(val);
 245                 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK ||
 246                                 cmd == MMC_SEND_TUNING_BLOCK_HS200;
 247         }
 248
 249         if (is_tuning_cmd)
 250                 clk_enabled = tegra_sdhci_configure_card_clk(host, 0);
 251
 252         writew(val, host->ioaddr + reg);
 253
 254         if (is_tuning_cmd) {
 255                 udelay(1);
 256                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 257                 tegra_sdhci_configure_card_clk(host, clk_enabled);
 258         }
 259 }
 260
 261 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
 262 {
 263         /*
 264          * Write-enable shall be assumed if GPIO is missing in a board's
 265          * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
 266          * Tegra.
 267          */
 268         return mmc_gpio_get_ro(host->mmc);
 269 }
 270
 271 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
 272 {
 273         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 274         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 275         int has_1v8, has_3v3;
 276
 277         /*
 278          * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad
 279          * voltage configuration in order to perform voltage switching. This
 280          * means that valid pinctrl info is required on SDHCI instances capable
 281          * of performing voltage switching. Whether or not an SDHCI instance is
 282          * capable of voltage switching is determined based on the regulator.
 283          */
 284
 285         if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
 286                 return true;
 287
 288         if (IS_ERR(host->mmc->supply.vqmmc))
 289                 return false;
 290
 291         has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
 292                                                  1700000, 1950000);
 293
 294         has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
 295                                                  2700000, 3600000);
 296
 297         if (has_1v8 == 1 && has_3v3 == 1)
 298                 return tegra_host->pad_control_available;
 299
 300         /* Fixed voltage, no pad control required. */
 301         return true;
 302 }
 303
 304 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
 305 {
 306         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 307         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 308         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 309         bool card_clk_enabled = false;
 310         u32 reg;
 311
 312         /*
 313          * Touching the tap values is a bit tricky on some SoC generations.
 314          * The quirk enables a workaround for a glitch that sometimes occurs if
 315          * the tap values are changed.
 316          */
 317
 318         if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
 319                 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
 320
 321         reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 322         reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
 323         reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
 324         sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 325
 326         if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
 327             card_clk_enabled) {
 328                 udelay(1);
 329                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 330                 tegra_sdhci_configure_card_clk(host, card_clk_enabled);
 331         }
 332 }
 333
 334 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
 335                                               struct mmc_ios *ios)
 336 {
 337         struct sdhci_host *host = mmc_priv(mmc);
 338         u32 val;
 339
 340         val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
 341
 342         if (ios->enhanced_strobe)
 343                 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
 344         else
 345                 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
 346
 347         sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
 348
 349 }
 350
 351 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
 352 {
 353         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 354         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 355         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 356         u32 misc_ctrl, clk_ctrl, pad_ctrl;
 357
 358         sdhci_reset(host, mask);
 359
 360         if (!(mask & SDHCI_RESET_ALL))
 361                 return;
 362
 363         tegra_sdhci_set_tap(host, tegra_host->default_tap);
 364
 365         misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 366         clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 367
 368         misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
 369                        SDHCI_MISC_CTRL_ENABLE_SDR50 |
 370                        SDHCI_MISC_CTRL_ENABLE_DDR50 |
 371                        SDHCI_MISC_CTRL_ENABLE_SDR104);
 372
 373         clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
 374                       SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE);
 375
 376         if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
 377                 /* Erratum: Enable SDHCI spec v3.00 support */
 378                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
 379                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
 380                 /* Advertise UHS modes as supported by host */
 381                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
 382                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
 383                 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
 384                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
 385                 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
 386                         misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
 387                 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
 388                         clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
 389         }
 390
 391         clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
 392
 393         sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
 394         sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 395
 396         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
 397                 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 398                 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK;
 399                 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL;
 400                 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 401
 402                 tegra_host->pad_calib_required = true;
 403         }
 404
 405         tegra_host->ddr_signaling = false;
 406 }
 407
 408 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
 409 {
 410         u32 val;
 411
 412         /*
 413          * Enable or disable the additional I/O pad used by the drive strength
 414          * calibration process.
 415          */
 416         val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 417
 418         if (enable)
 419                 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
 420         else
 421                 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
 422
 423         sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 424
 425         if (enable)
 426                 usleep_range(1, 2);
 427 }
 428
 429 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
 430                                                u16 pdpu)
 431 {
 432         u32 reg;
 433
 434         reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 435         reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
 436         reg |= pdpu;
 437         sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 438 }
 439
 440 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
 441                                    bool state_drvupdn)
 442 {
 443         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 444         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 445         struct sdhci_tegra_autocal_offsets *offsets =
 446                                                 &tegra_host->autocal_offsets;
 447         struct pinctrl_state *pinctrl_drvupdn = NULL;
 448         int ret = 0;
 449         u8 drvup = 0, drvdn = 0;
 450         u32 reg;
 451
 452         if (!state_drvupdn) {
 453                 /* PADS Drive Strength */
 454                 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
 455                         if (tegra_host->pinctrl_state_1v8_drv) {
 456                                 pinctrl_drvupdn =
 457                                         tegra_host->pinctrl_state_1v8_drv;
 458                         } else {
 459                                 drvup = offsets->pull_up_1v8_timeout;
 460                                 drvdn = offsets->pull_down_1v8_timeout;
 461                         }
 462                 } else {
 463                         if (tegra_host->pinctrl_state_3v3_drv) {
 464                                 pinctrl_drvupdn =
 465                                         tegra_host->pinctrl_state_3v3_drv;
 466                         } else {
 467                                 drvup = offsets->pull_up_3v3_timeout;
 468                                 drvdn = offsets->pull_down_3v3_timeout;
 469                         }
 470                 }
 471
 472                 if (pinctrl_drvupdn != NULL) {
 473                         ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
 474                                                         pinctrl_drvupdn);
 475                         if (ret < 0)
 476                                 dev_err(mmc_dev(host->mmc),
 477                                         "failed pads drvupdn, ret: %d\n", ret);
 478                 } else if ((drvup) || (drvdn)) {
 479                         reg = sdhci_readl(host,
 480                                         SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 481                         reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
 482                         reg |= (drvup << 20) | (drvdn << 12);
 483                         sdhci_writel(host, reg,
 484                                         SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
 485                 }
 486
 487         } else {
 488                 /* Dual Voltage PADS Voltage selection */
 489                 if (!tegra_host->pad_control_available)
 490                         return 0;
 491
 492                 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
 493                         ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
 494                                                 tegra_host->pinctrl_state_1v8);
 495                         if (ret < 0)
 496                                 dev_err(mmc_dev(host->mmc),
 497                                         "setting 1.8V failed, ret: %d\n", ret);
 498                 } else {
 499                         ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
 500                                                 tegra_host->pinctrl_state_3v3);
 501                         if (ret < 0)
 502                                 dev_err(mmc_dev(host->mmc),
 503                                         "setting 3.3V failed, ret: %d\n", ret);
 504                 }
 505         }
 506
 507         return ret;
 508 }
 509
 510 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
 511 {
 512         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 513         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 514         struct sdhci_tegra_autocal_offsets offsets =
 515                         tegra_host->autocal_offsets;
 516         struct mmc_ios *ios = &host->mmc->ios;
 517         bool card_clk_enabled;
 518         u16 pdpu;
 519         u32 reg;
 520         int ret;
 521
 522         switch (ios->timing) {
 523         case MMC_TIMING_UHS_SDR104:
 524                 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
 525                 break;
 526         case MMC_TIMING_MMC_HS400:
 527                 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
 528                 break;
 529         default:
 530                 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
 531                         pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
 532                 else
 533                         pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
 534         }
 535
 536         /* Set initial offset before auto-calibration */
 537         tegra_sdhci_set_pad_autocal_offset(host, pdpu);
 538
 539         card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
 540
 541         tegra_sdhci_configure_cal_pad(host, true);
 542
 543         reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 544         reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
 545         sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 546
 547         usleep_range(1, 2);
 548         /* 10 ms timeout */
 549         ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
 550                                  reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE),
 551                                  1000, 10000);
 552
 553         tegra_sdhci_configure_cal_pad(host, false);
 554
 555         tegra_sdhci_configure_card_clk(host, card_clk_enabled);
 556
 557         if (ret) {
 558                 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
 559
 560                 /* Disable automatic cal and use fixed Drive Strengths */
 561                 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 562                 reg &= ~SDHCI_AUTO_CAL_ENABLE;
 563                 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 564
 565                 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
 566                 if (ret < 0)
 567                         dev_err(mmc_dev(host->mmc),
 568                                 "Setting drive strengths failed: %d\n", ret);
 569         }
 570 }
 571
 572 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
 573 {
 574         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 575         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 576         struct sdhci_tegra_autocal_offsets *autocal =
 577                         &tegra_host->autocal_offsets;
 578         int err;
 579
 580         err = device_property_read_u32(host->mmc->parent,
 581                         "nvidia,pad-autocal-pull-up-offset-3v3",
 582                         &autocal->pull_up_3v3);
 583         if (err)
 584                 autocal->pull_up_3v3 = 0;
 585
 586         err = device_property_read_u32(host->mmc->parent,
 587                         "nvidia,pad-autocal-pull-down-offset-3v3",
 588                         &autocal->pull_down_3v3);
 589         if (err)
 590                 autocal->pull_down_3v3 = 0;
 591
 592         err = device_property_read_u32(host->mmc->parent,
 593                         "nvidia,pad-autocal-pull-up-offset-1v8",
 594                         &autocal->pull_up_1v8);
 595         if (err)
 596                 autocal->pull_up_1v8 = 0;
 597
 598         err = device_property_read_u32(host->mmc->parent,
 599                         "nvidia,pad-autocal-pull-down-offset-1v8",
 600                         &autocal->pull_down_1v8);
 601         if (err)
 602                 autocal->pull_down_1v8 = 0;
 603
 604         err = device_property_read_u32(host->mmc->parent,
 605                         "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
 606                         &autocal->pull_up_3v3_timeout);
 607         if (err) {
 608                 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
 609                         (tegra_host->pinctrl_state_3v3_drv == NULL))
 610                         pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
 611                                 mmc_hostname(host->mmc));
 612                 autocal->pull_up_3v3_timeout = 0;
 613         }
 614
 615         err = device_property_read_u32(host->mmc->parent,
 616                         "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
 617                         &autocal->pull_down_3v3_timeout);
 618         if (err) {
 619                 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
 620                         (tegra_host->pinctrl_state_3v3_drv == NULL))
 621                         pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
 622                                 mmc_hostname(host->mmc));
 623                 autocal->pull_down_3v3_timeout = 0;
 624         }
 625
 626         err = device_property_read_u32(host->mmc->parent,
 627                         "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
 628                         &autocal->pull_up_1v8_timeout);
 629         if (err) {
 630                 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
 631                         (tegra_host->pinctrl_state_1v8_drv == NULL))
 632                         pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
 633                                 mmc_hostname(host->mmc));
 634                 autocal->pull_up_1v8_timeout = 0;
 635         }
 636
 637         err = device_property_read_u32(host->mmc->parent,
 638                         "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
 639                         &autocal->pull_down_1v8_timeout);
 640         if (err) {
 641                 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
 642                         (tegra_host->pinctrl_state_1v8_drv == NULL))
 643                         pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
 644                                 mmc_hostname(host->mmc));
 645                 autocal->pull_down_1v8_timeout = 0;
 646         }
 647
 648         err = device_property_read_u32(host->mmc->parent,
 649                         "nvidia,pad-autocal-pull-up-offset-sdr104",
 650                         &autocal->pull_up_sdr104);
 651         if (err)
 652                 autocal->pull_up_sdr104 = autocal->pull_up_1v8;
 653
 654         err = device_property_read_u32(host->mmc->parent,
 655                         "nvidia,pad-autocal-pull-down-offset-sdr104",
 656                         &autocal->pull_down_sdr104);
 657         if (err)
 658                 autocal->pull_down_sdr104 = autocal->pull_down_1v8;
 659
 660         err = device_property_read_u32(host->mmc->parent,
 661                         "nvidia,pad-autocal-pull-up-offset-hs400",
 662                         &autocal->pull_up_hs400);
 663         if (err)
 664                 autocal->pull_up_hs400 = autocal->pull_up_1v8;
 665
 666         err = device_property_read_u32(host->mmc->parent,
 667                         "nvidia,pad-autocal-pull-down-offset-hs400",
 668                         &autocal->pull_down_hs400);
 669         if (err)
 670                 autocal->pull_down_hs400 = autocal->pull_down_1v8;
 671 }
 672
 673 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 674 {
 675         struct sdhci_host *host = mmc_priv(mmc);
 676         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 677         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 678         ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib);
 679
 680         /* 100 ms calibration interval is specified in the TRM */
 681         if (ktime_to_ms(since_calib) > 100) {
 682                 tegra_sdhci_pad_autocalib(host);
 683                 tegra_host->last_calib = ktime_get();
 684         }
 685
 686         sdhci_request(mmc, mrq);
 687 }
 688
 689 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
 690 {
 691         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 692         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 693         int err;
 694
 695         err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap",
 696                                        &tegra_host->default_tap);
 697         if (err)
 698                 tegra_host->default_tap = 0;
 699
 700         err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim",
 701                                        &tegra_host->default_trim);
 702         if (err)
 703                 tegra_host->default_trim = 0;
 704
 705         err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim",
 706                                        &tegra_host->dqs_trim);
 707         if (err)
 708                 tegra_host->dqs_trim = 0x11;
 709 }
 710
 711 static void tegra_sdhci_parse_dt(struct sdhci_host *host)
 712 {
 713         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 714         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 715
 716         if (device_property_read_bool(host->mmc->parent, "supports-cqe"))
 717                 tegra_host->enable_hwcq = true;
 718         else
 719                 tegra_host->enable_hwcq = false;
 720
 721         tegra_sdhci_parse_pad_autocal_dt(host);
 722         tegra_sdhci_parse_tap_and_trim(host);
 723 }
 724
 725 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 726 {
 727         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 728         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 729         unsigned long host_clk;
 730
 731         if (!clock)
 732                 return sdhci_set_clock(host, clock);
 733
 734         /*
 735          * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
 736          * divider to be configured to divided the host clock by two. The SDHCI
 737          * clock divider is calculated as part of sdhci_set_clock() by
 738          * sdhci_calc_clk(). The divider is calculated from host->max_clk and
 739          * the requested clock rate.
 740          *
 741          * By setting the host->max_clk to clock * 2 the divider calculation
 742          * will always result in the correct value for DDR50/52 modes,
 743          * regardless of clock rate rounding, which may happen if the value
 744          * from clk_get_rate() is used.
 745          */
 746         host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
 747         clk_set_rate(pltfm_host->clk, host_clk);
 748         tegra_host->curr_clk_rate = host_clk;
 749         if (tegra_host->ddr_signaling)
 750                 host->max_clk = host_clk;
 751         else
 752                 host->max_clk = clk_get_rate(pltfm_host->clk);
 753
 754         sdhci_set_clock(host, clock);
 755
 756         if (tegra_host->pad_calib_required) {
 757                 tegra_sdhci_pad_autocalib(host);
 758                 tegra_host->pad_calib_required = false;
 759         }
 760 }
 761
 762 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
 763 {
 764         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 765
 766         return clk_round_rate(pltfm_host->clk, UINT_MAX);
 767 }
 768
 769 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
 770 {
 771         u32 val;
 772
 773         val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
 774         val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK;
 775         val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT;
 776         sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
 777 }
 778
 779 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
 780 {
 781         u32 reg;
 782         int err;
 783
 784         reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
 785         reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
 786         sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
 787
 788         /* 1 ms sleep, 5 ms timeout */
 789         err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
 790                                  reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE),
 791                                  1000, 5000);
 792         if (err)
 793                 dev_err(mmc_dev(host->mmc),
 794                         "HS400 delay line calibration timed out\n");
 795 }
 796
 797 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up,
 798                                        u8 thd_low, u8 fixed_tap)
 799 {
 800         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 801         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 802         u32 val, tun_status;
 803         u8 word, bit, edge1, tap, window;
 804         bool tap_result;
 805         bool start_fail = false;
 806         bool start_pass = false;
 807         bool end_pass = false;
 808         bool first_fail = false;
 809         bool first_pass = false;
 810         u8 start_pass_tap = 0;
 811         u8 end_pass_tap = 0;
 812         u8 first_fail_tap = 0;
 813         u8 first_pass_tap = 0;
 814         u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE;
 815
 816         /*
 817          * Read auto-tuned results and extract good valid passing window by
 818          * filtering out un-wanted bubble/partial/merged windows.
 819          */
 820         for (word = 0; word < total_tuning_words; word++) {
 821                 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
 822                 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK;
 823                 val |= word;
 824                 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
 825                 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);
 826                 bit = 0;
 827                 while (bit < TUNING_WORD_BIT_SIZE) {
 828                         tap = word * TUNING_WORD_BIT_SIZE + bit;
 829                         tap_result = tun_status & (1 << bit);
 830                         if (!tap_result && !start_fail) {
 831                                 start_fail = true;
 832                                 if (!first_fail) {
 833                                         first_fail_tap = tap;
 834                                         first_fail = true;
 835                                 }
 836
 837                         } else if (tap_result && start_fail && !start_pass) {
 838                                 start_pass_tap = tap;
 839                                 start_pass = true;
 840                                 if (!first_pass) {
 841                                         first_pass_tap = tap;
 842                                         first_pass = true;
 843                                 }
 844
 845                         } else if (!tap_result && start_fail && start_pass &&
 846                                    !end_pass) {
 847                                 end_pass_tap = tap - 1;
 848                                 end_pass = true;
 849                         } else if (tap_result && start_pass && start_fail &&
 850                                    end_pass) {
 851                                 window = end_pass_tap - start_pass_tap;
 852                                 /* discard merged window and bubble window */
 853                                 if (window >= thd_up || window < thd_low) {
 854                                         start_pass_tap = tap;
 855                                         end_pass = false;
 856                                 } else {
 857                                         /* set tap at middle of valid window */
 858                                         tap = start_pass_tap + window / 2;
 859                                         tegra_host->tuned_tap_delay = tap;
 860                                         return;
 861                                 }
 862                         }
 863
 864                         bit++;
 865                 }
 866         }
 867
 868         if (!first_fail) {
 869                 WARN(1, "no edge detected, continue with hw tuned delay.\n");
 870         } else if (first_pass) {
 871                 /* set tap location at fixed tap relative to the first edge */
 872                 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2;
 873                 if (edge1 - 1 > fixed_tap)
 874                         tegra_host->tuned_tap_delay = edge1 - fixed_tap;
 875                 else
 876                         tegra_host->tuned_tap_delay = edge1 + fixed_tap;
 877         }
 878 }
 879
 880 static void tegra_sdhci_post_tuning(struct sdhci_host *host)
 881 {
 882         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 883         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 884         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 885         u32 avg_tap_dly, val, min_tap_dly, max_tap_dly;
 886         u8 fixed_tap, start_tap, end_tap, window_width;
 887         u8 thdupper, thdlower;
 888         u8 num_iter;
 889         u32 clk_rate_mhz, period_ps, bestcase, worstcase;
 890
 891         /* retain HW tuned tap to use incase if no correction is needed */
 892         val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
 893         tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >>
 894                                       SDHCI_CLOCK_CTRL_TAP_SHIFT;
 895         if (soc_data->min_tap_delay && soc_data->max_tap_delay) {
 896                 min_tap_dly = soc_data->min_tap_delay;
 897                 max_tap_dly = soc_data->max_tap_delay;
 898                 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC;
 899                 period_ps = USEC_PER_SEC / clk_rate_mhz;
 900                 bestcase = period_ps / min_tap_dly;
 901                 worstcase = period_ps / max_tap_dly;
 902                 /*
 903                  * Upper and Lower bound thresholds used to detect merged and
 904                  * bubble windows
 905                  */
 906                 thdupper = (2 * worstcase + bestcase) / 2;
 907                 thdlower = worstcase / 4;
 908                 /*
 909                  * fixed tap is used when HW tuning result contains single edge
 910                  * and tap is set at fixed tap delay relative to the first edge
 911                  */
 912                 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly);
 913                 fixed_tap = avg_tap_dly / 2;
 914
 915                 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);
 916                 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
 917                 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) &
 918                           SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
 919                 window_width = end_tap - start_tap;
 920                 num_iter = host->tuning_loop_count;
 921                 /*
 922                  * partial window includes edges of the tuning range.
 923                  * merged window includes more taps so window width is higher
 924                  * than upper threshold.
 925                  */
 926                 if (start_tap == 0 || (end_tap == (num_iter - 1)) ||
 927                     (end_tap == num_iter - 2) || window_width >= thdupper) {
 928                         pr_debug("%s: Apply tuning correction\n",
 929                                  mmc_hostname(host->mmc));
 930                         tegra_sdhci_tap_correction(host, thdupper, thdlower,
 931                                                    fixed_tap);
 932                 }
 933         }
 934
 935         tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
 936 }
 937
 938 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
 939 {
 940         struct sdhci_host *host = mmc_priv(mmc);
 941         int err;
 942
 943         err = sdhci_execute_tuning(mmc, opcode);
 944         if (!err && !host->tuning_err)
 945                 tegra_sdhci_post_tuning(host);
 946
 947         return err;
 948 }
 949
 950 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 951                                           unsigned timing)
 952 {
 953         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 954         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 955         bool set_default_tap = false;
 956         bool set_dqs_trim = false;
 957         bool do_hs400_dll_cal = false;
 958         u8 iter = TRIES_256;
 959         u32 val;
 960
 961         tegra_host->ddr_signaling = false;
 962         switch (timing) {
 963         case MMC_TIMING_UHS_SDR50:
 964                 break;
 965         case MMC_TIMING_UHS_SDR104:
 966         case MMC_TIMING_MMC_HS200:
 967                 /* Don't set default tap on tunable modes. */
 968                 iter = TRIES_128;
 969                 break;
 970         case MMC_TIMING_MMC_HS400:
 971                 set_dqs_trim = true;
 972                 do_hs400_dll_cal = true;
 973                 iter = TRIES_128;
 974                 break;
 975         case MMC_TIMING_MMC_DDR52:
 976         case MMC_TIMING_UHS_DDR50:
 977                 tegra_host->ddr_signaling = true;
 978                 set_default_tap = true;
 979                 break;
 980         default:
 981                 set_default_tap = true;
 982                 break;
 983         }
 984
 985         val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
 986         val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK |
 987                  SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK |
 988                  SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK);
 989         val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT |
 990                 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT |
 991                 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT);
 992         sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
 993         sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0);
 994
 995         host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256;
 996
 997         sdhci_set_uhs_signaling(host, timing);
 998
 999         tegra_sdhci_pad_autocalib(host);
1000
1001         if (tegra_host->tuned_tap_delay && !set_default_tap)
1002                 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
1003         else
1004                 tegra_sdhci_set_tap(host, tegra_host->default_tap);
1005
1006         if (set_dqs_trim)
1007                 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
1008
1009         if (do_hs400_dll_cal)
1010                 tegra_sdhci_hs400_dll_cal(host);
1011 }
1012
1013 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
1014 {
1015         unsigned int min, max;
1016
1017         /*
1018          * Start search for minimum tap value at 10, as smaller values are
1019          * may wrongly be reported as working but fail at higher speeds,
1020          * according to the TRM.
1021          */
1022         min = 10;
1023         while (min < 255) {
1024                 tegra_sdhci_set_tap(host, min);
1025                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1026                         break;
1027                 min++;
1028         }
1029
1030         /* Find the maximum tap value that still passes. */
1031         max = min + 1;
1032         while (max < 255) {
1033                 tegra_sdhci_set_tap(host, max);
1034                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1035                         max--;
1036                         break;
1037                 }
1038                 max++;
1039         }
1040
1041         /* The TRM states the ideal tap value is at 75% in the passing range. */
1042         tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
1043
1044         return mmc_send_tuning(host->mmc, opcode, NULL);
1045 }
1046
1047 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
1048                                                    struct mmc_ios *ios)
1049 {
1050         struct sdhci_host *host = mmc_priv(mmc);
1051         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1052         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1053         int ret = 0;
1054
1055         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1056                 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1057                 if (ret < 0)
1058                         return ret;
1059                 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1060         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1061                 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1062                 if (ret < 0)
1063                         return ret;
1064                 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1065         }
1066
1067         if (tegra_host->pad_calib_required)
1068                 tegra_sdhci_pad_autocalib(host);
1069
1070         return ret;
1071 }
1072
1073 static int tegra_sdhci_init_pinctrl_info(struct device *dev,
1074                                          struct sdhci_tegra *tegra_host)
1075 {
1076         tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
1077         if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
1078                 dev_dbg(dev, "No pinctrl info, err: %ld\n",
1079                         PTR_ERR(tegra_host->pinctrl_sdmmc));
1080                 return -1;
1081         }
1082
1083         tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
1084                                 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
1085         if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
1086                 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
1087                         tegra_host->pinctrl_state_1v8_drv = NULL;
1088         }
1089
1090         tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
1091                                 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
1092         if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
1093                 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
1094                         tegra_host->pinctrl_state_3v3_drv = NULL;
1095         }
1096
1097         tegra_host->pinctrl_state_3v3 =
1098                 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
1099         if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
1100                 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n",
1101                          PTR_ERR(tegra_host->pinctrl_state_3v3));
1102                 return -1;
1103         }
1104
1105         tegra_host->pinctrl_state_1v8 =
1106                 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
1107         if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
1108                 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n",
1109                          PTR_ERR(tegra_host->pinctrl_state_1v8));
1110                 return -1;
1111         }
1112
1113         tegra_host->pad_control_available = true;
1114
1115         return 0;
1116 }
1117
1118 static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
1119 {
1120         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1121         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1122         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1123
1124         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1125                 tegra_host->pad_calib_required = true;
1126 }
1127
1128 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg)
1129 {
1130         struct mmc_host *mmc = cq_host->mmc;
1131         u8 ctrl;
1132         ktime_t timeout;
1133         bool timed_out;
1134
1135         /*
1136          * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to
1137          * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need
1138          * to be re-configured.
1139          * Tegra CQHCI/SDHCI prevents write access to block size register when
1140          * CQE is unhalted. So handling CQE resume sequence here to configure
1141          * SDHCI block registers prior to exiting CQE halt state.
1142          */
1143         if (reg == CQHCI_CTL && !(val & CQHCI_HALT) &&
1144             cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) {
1145                 sdhci_cqe_enable(mmc);
1146                 writel(val, cq_host->mmio + reg);
1147                 timeout = ktime_add_us(ktime_get(), 50);
1148                 while (1) {
1149                         timed_out = ktime_compare(ktime_get(), timeout) > 0;
1150                         ctrl = cqhci_readl(cq_host, CQHCI_CTL);
1151                         if (!(ctrl & CQHCI_HALT) || timed_out)
1152                                 break;
1153                 }
1154                 /*
1155                  * CQE usually resumes very quick, but incase if Tegra CQE
1156                  * doesn't resume retry unhalt.
1157                  */
1158                 if (timed_out)
1159                         writel(val, cq_host->mmio + reg);
1160         } else {
1161                 writel(val, cq_host->mmio + reg);
1162         }
1163 }
1164
1165 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc,
1166                                          struct mmc_request *mrq, u64 *data)
1167 {
1168         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc));
1169         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1170         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1171
1172         if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&
1173             mrq->cmd->flags & MMC_RSP_R1B)
1174                 *data |= CQHCI_CMD_TIMING(1);
1175 }
1176
1177 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
1178 {
1179         struct cqhci_host *cq_host = mmc->cqe_private;
1180         u32 val;
1181
1182         /*
1183          * Tegra CQHCI/SDMMC design prevents write access to sdhci block size
1184          * register when CQE is enabled and unhalted.
1185          * CQHCI driver enables CQE prior to activation, so disable CQE before
1186          * programming block size in sdhci controller and enable it back.
1187          */
1188         if (!cq_host->activated) {
1189                 val = cqhci_readl(cq_host, CQHCI_CFG);
1190                 if (val & CQHCI_ENABLE)
1191                         cqhci_writel(cq_host, (val & ~CQHCI_ENABLE),
1192                                      CQHCI_CFG);
1193                 sdhci_cqe_enable(mmc);
1194                 if (val & CQHCI_ENABLE)
1195                         cqhci_writel(cq_host, val, CQHCI_CFG);
1196         }
1197
1198         /*
1199          * CMD CRC errors are seen sometimes with some eMMC devices when status
1200          * command is sent during transfer of last data block which is the
1201          * default case as send status command block counter (CBC) is 1.
1202          * Recommended fix to set CBC to 0 allowing send status command only
1203          * when data lines are idle.
1204          */
1205         val = cqhci_readl(cq_host, CQHCI_SSC1);
1206         val &= ~CQHCI_SSC1_CBC_MASK;
1207         cqhci_writel(cq_host, val, CQHCI_SSC1);
1208 }
1209
1210 static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
1211 {
1212         sdhci_dumpregs(mmc_priv(mmc));
1213 }
1214
1215 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
1216 {
1217         int cmd_error = 0;
1218         int data_error = 0;
1219
1220         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1221                 return intmask;
1222
1223         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1224
1225         return 0;
1226 }
1227
1228 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
1229         .write_l    = tegra_cqhci_writel,
1230         .enable = sdhci_tegra_cqe_enable,
1231         .disable = sdhci_cqe_disable,
1232         .dumpregs = sdhci_tegra_dumpregs,
1233         .update_dcmd_desc = sdhci_tegra_update_dcmd_desc,
1234 };
1235
1236 static const struct sdhci_ops tegra_sdhci_ops = {
1237         .get_ro     = tegra_sdhci_get_ro,
1238         .read_w     = tegra_sdhci_readw,
1239         .write_l    = tegra_sdhci_writel,
1240         .set_clock  = tegra_sdhci_set_clock,
1241         .set_bus_width = sdhci_set_bus_width,
1242         .reset      = tegra_sdhci_reset,
1243         .platform_execute_tuning = tegra_sdhci_execute_tuning,
1244         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1245         .voltage_switch = tegra_sdhci_voltage_switch,
1246         .get_max_clock = tegra_sdhci_get_max_clock,
1247 };
1248
1249 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1250         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1251                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1252                   SDHCI_QUIRK_NO_HISPD_BIT |
1253                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1254                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1255         .ops  = &tegra_sdhci_ops,
1256 };
1257
1258 static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
1259         .pdata = &sdhci_tegra20_pdata,
1260         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1261                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
1262 };
1263
1264 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1265         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1266                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1267                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1268                   SDHCI_QUIRK_NO_HISPD_BIT |
1269                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1270                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1271         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1272                    SDHCI_QUIRK2_BROKEN_HS200 |
1273                    /*
1274                     * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1275                     * though no command operation was in progress."
1276                     *
1277                     * The exact reason is unknown, as the same hardware seems
1278                     * to support Auto CMD23 on a downstream 3.1 kernel.
1279                     */
1280                    SDHCI_QUIRK2_ACMD23_BROKEN,
1281         .ops  = &tegra_sdhci_ops,
1282 };
1283
1284 static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
1285         .pdata = &sdhci_tegra30_pdata,
1286         .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
1287                     NVQUIRK_ENABLE_SDR50 |
1288                     NVQUIRK_ENABLE_SDR104 |
1289                     NVQUIRK_HAS_PADCALIB,
1290 };
1291
1292 static const struct sdhci_ops tegra114_sdhci_ops = {
1293         .get_ro     = tegra_sdhci_get_ro,
1294         .read_w     = tegra_sdhci_readw,
1295         .write_w    = tegra_sdhci_writew,
1296         .write_l    = tegra_sdhci_writel,
1297         .set_clock  = tegra_sdhci_set_clock,
1298         .set_bus_width = sdhci_set_bus_width,
1299         .reset      = tegra_sdhci_reset,
1300         .platform_execute_tuning = tegra_sdhci_execute_tuning,
1301         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1302         .voltage_switch = tegra_sdhci_voltage_switch,
1303         .get_max_clock = tegra_sdhci_get_max_clock,
1304 };
1305
1306 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
1307         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1308                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1309                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1310                   SDHCI_QUIRK_NO_HISPD_BIT |
1311                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1312                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1313         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1314         .ops  = &tegra114_sdhci_ops,
1315 };
1316
1317 static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
1318         .pdata = &sdhci_tegra114_pdata,
1319 };
1320
1321 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
1322         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1323                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1324                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1325                   SDHCI_QUIRK_NO_HISPD_BIT |
1326                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1327                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1328         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1329                    /*
1330                     * The TRM states that the SD/MMC controller found on
1331                     * Tegra124 can address 34 bits (the maximum supported by
1332                     * the Tegra memory controller), but tests show that DMA
1333                     * to or from above 4 GiB doesn't work. This is possibly
1334                     * caused by missing programming, though it's not obvious
1335                     * what sequence is required. Mark 64-bit DMA broken for
1336                     * now to fix this for existing users (e.g. Nyan boards).
1337                     */
1338                    SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1339         .ops  = &tegra114_sdhci_ops,
1340 };
1341
1342 static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
1343         .pdata = &sdhci_tegra124_pdata,
1344 };
1345
1346 static const struct sdhci_ops tegra210_sdhci_ops = {
1347         .get_ro     = tegra_sdhci_get_ro,
1348         .read_w     = tegra_sdhci_readw,
1349         .write_w    = tegra210_sdhci_writew,
1350         .write_l    = tegra_sdhci_writel,
1351         .set_clock  = tegra_sdhci_set_clock,
1352         .set_bus_width = sdhci_set_bus_width,
1353         .reset      = tegra_sdhci_reset,
1354         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1355         .voltage_switch = tegra_sdhci_voltage_switch,
1356         .get_max_clock = tegra_sdhci_get_max_clock,
1357 };
1358
1359 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
1360         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1361                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1362                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1363                   SDHCI_QUIRK_NO_HISPD_BIT |
1364                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1365                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1366         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1367         .ops  = &tegra210_sdhci_ops,
1368 };
1369
1370 static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
1371         .pdata = &sdhci_tegra210_pdata,
1372         .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1373                     NVQUIRK_HAS_PADCALIB |
1374                     NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1375                     NVQUIRK_ENABLE_SDR50 |
1376                     NVQUIRK_ENABLE_SDR104,
1377         .min_tap_delay = 106,
1378         .max_tap_delay = 185,
1379 };
1380
1381 static const struct sdhci_ops tegra186_sdhci_ops = {
1382         .get_ro     = tegra_sdhci_get_ro,
1383         .read_w     = tegra_sdhci_readw,
1384         .write_l    = tegra_sdhci_writel,
1385         .set_clock  = tegra_sdhci_set_clock,
1386         .set_bus_width = sdhci_set_bus_width,
1387         .reset      = tegra_sdhci_reset,
1388         .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1389         .voltage_switch = tegra_sdhci_voltage_switch,
1390         .get_max_clock = tegra_sdhci_get_max_clock,
1391         .irq = sdhci_tegra_cqhci_irq,
1392 };
1393
1394 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
1395         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1396                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1397                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1398                   SDHCI_QUIRK_NO_HISPD_BIT |
1399                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1400                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1401         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1402                    /* SDHCI controllers on Tegra186 support 40-bit addressing.
1403                     * IOVA addresses are 48-bit wide on Tegra186.
1404                     * With 64-bit dma mask used for SDHCI, accesses can
1405                     * be broken. Disable 64-bit dma, which would fall back
1406                     * to 32-bit dma mask. Ideally 40-bit dma mask would work,
1407                     * But it is not supported as of now.
1408                     */
1409                    SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1410         .ops  = &tegra186_sdhci_ops,
1411 };
1412
1413 static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
1414         .pdata = &sdhci_tegra186_pdata,
1415         .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1416                     NVQUIRK_HAS_PADCALIB |
1417                     NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1418                     NVQUIRK_ENABLE_SDR50 |
1419                     NVQUIRK_ENABLE_SDR104 |
1420                     NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING,
1421         .min_tap_delay = 84,
1422         .max_tap_delay = 136,
1423 };
1424
1425 static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
1426         .pdata = &sdhci_tegra186_pdata,
1427         .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1428                     NVQUIRK_HAS_PADCALIB |
1429                     NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1430                     NVQUIRK_ENABLE_SDR50 |
1431                     NVQUIRK_ENABLE_SDR104,
1432         .min_tap_delay = 96,
1433         .max_tap_delay = 139,
1434 };
1435
1436 static const struct of_device_id sdhci_tegra_dt_match[] = {
1437         { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1438         { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1439         { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1440         { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1441         { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1442         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1443         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1444         {}
1445 };
1446 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
1447
1448 static int sdhci_tegra_add_host(struct sdhci_host *host)
1449 {
1450         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1451         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1452         struct cqhci_host *cq_host;
1453         bool dma64;
1454         int ret;
1455
1456         if (!tegra_host->enable_hwcq)
1457                 return sdhci_add_host(host);
1458
1459         sdhci_enable_v4_mode(host);
1460
1461         ret = sdhci_setup_host(host);
1462         if (ret)
1463                 return ret;
1464
1465         host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1466
1467         cq_host = devm_kzalloc(host->mmc->parent,
1468                                 sizeof(*cq_host), GFP_KERNEL);
1469         if (!cq_host) {
1470                 ret = -ENOMEM;
1471                 goto cleanup;
1472         }
1473
1474         cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
1475         cq_host->ops = &sdhci_tegra_cqhci_ops;
1476
1477         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1478         if (dma64)
1479                 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1480
1481         ret = cqhci_init(cq_host, host->mmc, dma64);
1482         if (ret)
1483                 goto cleanup;
1484
1485         ret = __sdhci_add_host(host);
1486         if (ret)
1487                 goto cleanup;
1488
1489         return 0;
1490
1491 cleanup:
1492         sdhci_cleanup_host(host);
1493         return ret;
1494 }
1495
1496 static int sdhci_tegra_probe(struct platform_device *pdev)
1497 {
1498         const struct of_device_id *match;
1499         const struct sdhci_tegra_soc_data *soc_data;
1500         struct sdhci_host *host;
1501         struct sdhci_pltfm_host *pltfm_host;
1502         struct sdhci_tegra *tegra_host;
1503         struct clk *clk;
1504         int rc;
1505
1506         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1507         if (!match)
1508                 return -EINVAL;
1509         soc_data = match->data;
1510
1511         host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1512         if (IS_ERR(host))
1513                 return PTR_ERR(host);
1514         pltfm_host = sdhci_priv(host);
1515
1516         tegra_host = sdhci_pltfm_priv(pltfm_host);
1517         tegra_host->ddr_signaling = false;
1518         tegra_host->pad_calib_required = false;
1519         tegra_host->pad_control_available = false;
1520         tegra_host->soc_data = soc_data;
1521
1522         if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1523                 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1524                 if (rc == 0)
1525                         host->mmc_host_ops.start_signal_voltage_switch =
1526                                 sdhci_tegra_start_signal_voltage_switch;
1527         }
1528
1529         /* Hook to periodically rerun pad calibration */
1530         if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1531                 host->mmc_host_ops.request = tegra_sdhci_request;
1532
1533         host->mmc_host_ops.hs400_enhanced_strobe =
1534                         tegra_sdhci_hs400_enhanced_strobe;
1535
1536         if (!host->ops->platform_execute_tuning)
1537                 host->mmc_host_ops.execute_tuning =
1538                                 tegra_sdhci_execute_hw_tuning;
1539
1540         rc = mmc_of_parse(host->mmc);
1541         if (rc)
1542                 goto err_parse_dt;
1543
1544         if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1545                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1546
1547         tegra_sdhci_parse_dt(host);
1548
1549         tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1550                                                          GPIOD_OUT_HIGH);
1551         if (IS_ERR(tegra_host->power_gpio)) {
1552                 rc = PTR_ERR(tegra_host->power_gpio);
1553                 goto err_power_req;
1554         }
1555
1556         clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1557         if (IS_ERR(clk)) {
1558                 rc = PTR_ERR(clk);
1559
1560                 if (rc != -EPROBE_DEFER)
1561                         dev_err(&pdev->dev, "failed to get clock: %d\n", rc);
1562
1563                 goto err_clk_get;
1564         }
1565         clk_prepare_enable(clk);
1566         pltfm_host->clk = clk;
1567
1568         tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1569                                                            "sdhci");
1570         if (IS_ERR(tegra_host->rst)) {
1571                 rc = PTR_ERR(tegra_host->rst);
1572                 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1573                 goto err_rst_get;
1574         }
1575
1576         rc = reset_control_assert(tegra_host->rst);
1577         if (rc)
1578                 goto err_rst_get;
1579
1580         usleep_range(2000, 4000);
1581
1582         rc = reset_control_deassert(tegra_host->rst);
1583         if (rc)
1584                 goto err_rst_get;
1585
1586         usleep_range(2000, 4000);
1587
1588         rc = sdhci_tegra_add_host(host);
1589         if (rc)
1590                 goto err_add_host;
1591
1592         return 0;
1593
1594 err_add_host:
1595         reset_control_assert(tegra_host->rst);
1596 err_rst_get:
1597         clk_disable_unprepare(pltfm_host->clk);
1598 err_clk_get:
1599 err_power_req:
1600 err_parse_dt:
1601         sdhci_pltfm_free(pdev);
1602         return rc;
1603 }
1604
1605 static int sdhci_tegra_remove(struct platform_device *pdev)
1606 {
1607         struct sdhci_host *host = platform_get_drvdata(pdev);
1608         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1609         struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1610
1611         sdhci_remove_host(host, 0);
1612
1613         reset_control_assert(tegra_host->rst);
1614         usleep_range(2000, 4000);
1615         clk_disable_unprepare(pltfm_host->clk);
1616
1617         sdhci_pltfm_free(pdev);
1618
1619         return 0;
1620 }
1621
1622 #ifdef CONFIG_PM_SLEEP
1623 static int __maybe_unused sdhci_tegra_suspend(struct device *dev)
1624 {
1625         struct sdhci_host *host = dev_get_drvdata(dev);
1626         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1627         int ret;
1628
1629         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1630                 ret = cqhci_suspend(host->mmc);
1631                 if (ret)
1632                         return ret;
1633         }
1634
1635         ret = sdhci_suspend_host(host);
1636         if (ret) {
1637                 cqhci_resume(host->mmc);
1638                 return ret;
1639         }
1640
1641         clk_disable_unprepare(pltfm_host->clk);
1642         return 0;
1643 }
1644
1645 static int __maybe_unused sdhci_tegra_resume(struct device *dev)
1646 {
1647         struct sdhci_host *host = dev_get_drvdata(dev);
1648         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1649         int ret;
1650
1651         ret = clk_prepare_enable(pltfm_host->clk);
1652         if (ret)
1653                 return ret;
1654
1655         ret = sdhci_resume_host(host);
1656         if (ret)
1657                 goto disable_clk;
1658
1659         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1660                 ret = cqhci_resume(host->mmc);
1661                 if (ret)
1662                         goto suspend_host;
1663         }
1664
1665         return 0;
1666
1667 suspend_host:
1668         sdhci_suspend_host(host);
1669 disable_clk:
1670         clk_disable_unprepare(pltfm_host->clk);
1671         return ret;
1672 }
1673 #endif
1674
1675 static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend,
1676                          sdhci_tegra_resume);
1677
1678 static struct platform_driver sdhci_tegra_driver = {
1679         .driver         = {
1680                 .name   = "sdhci-tegra",
1681                 .of_match_table = sdhci_tegra_dt_match,
1682                 .pm     = &sdhci_tegra_dev_pm_ops,
1683         },
1684         .probe          = sdhci_tegra_probe,
1685         .remove         = sdhci_tegra_remove,
1686 };
1687
1688 module_platform_driver(sdhci_tegra_driver);
1689
1690 MODULE_DESCRIPTION("SDHCI driver for Tegra");
1691 MODULE_AUTHOR("Google, Inc.");
1692 MODULE_LICENSE("GPL v2");