drivers/mmc/host/sdhci-omap.c

   1 /**
   2  * SDHCI Controller driver for TI's OMAP SoCs
   3  *
   4  * Copyright (C) 2017 Texas Instruments
   5  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 of
   9  * the License as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/mmc/slot-gpio.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/sys_soc.h>
  30 #include <linux/thermal.h>
  31
  32 #include "sdhci-pltfm.h"
  33
  34 #define SDHCI_OMAP_CON          0x12c
  35 #define CON_DW8                 BIT(5)
  36 #define CON_DMA_MASTER          BIT(20)
  37 #define CON_DDR                 BIT(19)
  38 #define CON_CLKEXTFREE          BIT(16)
  39 #define CON_PADEN               BIT(15)
  40 #define CON_CTPL                BIT(11)
  41 #define CON_INIT                BIT(1)
  42 #define CON_OD                  BIT(0)
  43
  44 #define SDHCI_OMAP_DLL          0x0134
  45 #define DLL_SWT                 BIT(20)
  46 #define DLL_FORCE_SR_C_SHIFT    13
  47 #define DLL_FORCE_SR_C_MASK     (0x7f << DLL_FORCE_SR_C_SHIFT)
  48 #define DLL_FORCE_VALUE         BIT(12)
  49 #define DLL_CALIB               BIT(1)
  50
  51 #define SDHCI_OMAP_CMD          0x20c
  52
  53 #define SDHCI_OMAP_PSTATE       0x0224
  54 #define PSTATE_DLEV_DAT0        BIT(20)
  55 #define PSTATE_DATI             BIT(1)
  56
  57 #define SDHCI_OMAP_HCTL         0x228
  58 #define HCTL_SDBP               BIT(8)
  59 #define HCTL_SDVS_SHIFT         9
  60 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  61 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  62 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  63 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  64
  65 #define SDHCI_OMAP_SYSCTL       0x22c
  66 #define SYSCTL_CEN              BIT(2)
  67 #define SYSCTL_CLKD_SHIFT       6
  68 #define SYSCTL_CLKD_MASK        0x3ff
  69
  70 #define SDHCI_OMAP_STAT         0x230
  71
  72 #define SDHCI_OMAP_IE           0x234
  73 #define INT_CC_EN               BIT(0)
  74
  75 #define SDHCI_OMAP_AC12         0x23c
  76 #define AC12_V1V8_SIGEN         BIT(19)
  77 #define AC12_SCLK_SEL           BIT(23)
  78
  79 #define SDHCI_OMAP_CAPA         0x240
  80 #define CAPA_VS33               BIT(24)
  81 #define CAPA_VS30               BIT(25)
  82 #define CAPA_VS18               BIT(26)
  83
  84 #define SDHCI_OMAP_CAPA2        0x0244
  85 #define CAPA2_TSDR50            BIT(13)
  86
  87 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  88
  89 #define SYSCTL_CLKD_MAX         0x3FF
  90
  91 #define IOV_1V8                 1800000         /* 180000 uV */
  92 #define IOV_3V0                 3000000         /* 300000 uV */
  93 #define IOV_3V3                 3300000         /* 330000 uV */
  94
  95 #define MAX_PHASE_DELAY         0x7C
  96
  97 /* sdhci-omap controller flags */
  98 #define SDHCI_OMAP_REQUIRE_IODELAY      BIT(0)
  99
 100 struct sdhci_omap_data {
 101         u32 offset;
 102         u8 flags;
 103 };
 104
 105 struct sdhci_omap_host {
 106         char                    *version;
 107         void __iomem            *base;
 108         struct device           *dev;
 109         struct  regulator       *pbias;
 110         bool                    pbias_enabled;
 111         struct sdhci_host       *host;
 112         u8                      bus_mode;
 113         u8                      power_mode;
 114         u8                      timing;
 115         u8                      flags;
 116
 117         struct pinctrl          *pinctrl;
 118         struct pinctrl_state    **pinctrl_state;
 119         bool                    is_tuning;
 120 };
 121
 122 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
 123 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
 124
 125 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
 126                                    unsigned int offset)
 127 {
 128         return readl(host->base + offset);
 129 }
 130
 131 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 132                                      unsigned int offset, u32 data)
 133 {
 134         writel(data, host->base + offset);
 135 }
 136
 137 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 138                                 bool power_on, unsigned int iov)
 139 {
 140         int ret;
 141         struct device *dev = omap_host->dev;
 142
 143         if (IS_ERR(omap_host->pbias))
 144                 return 0;
 145
 146         if (power_on) {
 147                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 148                 if (ret) {
 149                         dev_err(dev, "pbias set voltage failed\n");
 150                         return ret;
 151                 }
 152
 153                 if (omap_host->pbias_enabled)
 154                         return 0;
 155
 156                 ret = regulator_enable(omap_host->pbias);
 157                 if (ret) {
 158                         dev_err(dev, "pbias reg enable fail\n");
 159                         return ret;
 160                 }
 161
 162                 omap_host->pbias_enabled = true;
 163         } else {
 164                 if (!omap_host->pbias_enabled)
 165                         return 0;
 166
 167                 ret = regulator_disable(omap_host->pbias);
 168                 if (ret) {
 169                         dev_err(dev, "pbias reg disable fail\n");
 170                         return ret;
 171                 }
 172                 omap_host->pbias_enabled = false;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 179                                  unsigned int iov)
 180 {
 181         int ret;
 182         struct sdhci_host *host = omap_host->host;
 183         struct mmc_host *mmc = host->mmc;
 184
 185         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 186         if (ret)
 187                 return ret;
 188
 189         if (!IS_ERR(mmc->supply.vqmmc)) {
 190                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 191                 if (ret) {
 192                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 193                         return ret;
 194                 }
 195         }
 196
 197         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 198         if (ret)
 199                 return ret;
 200
 201         return 0;
 202 }
 203
 204 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 205                                       unsigned char signal_voltage)
 206 {
 207         u32 reg;
 208         ktime_t timeout;
 209
 210         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 211         reg &= ~HCTL_SDVS_MASK;
 212
 213         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 214                 reg |= HCTL_SDVS_33;
 215         else
 216                 reg |= HCTL_SDVS_18;
 217
 218         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 219
 220         reg |= HCTL_SDBP;
 221         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 222
 223         /* wait 1ms */
 224         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 225         while (1) {
 226                 bool timedout = ktime_after(ktime_get(), timeout);
 227
 228                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
 229                         break;
 230                 if (WARN_ON(timedout))
 231                         return;
 232                 usleep_range(5, 10);
 233         }
 234 }
 235
 236 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
 237 {
 238         struct sdhci_host *host = mmc_priv(mmc);
 239         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 240         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 241         u32 reg;
 242
 243         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 244         if (enable)
 245                 reg |= (CON_CTPL | CON_CLKEXTFREE);
 246         else
 247                 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
 248         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 249
 250         sdhci_enable_sdio_irq(mmc, enable);
 251 }
 252
 253 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
 254                                       int count)
 255 {
 256         int i;
 257         u32 reg;
 258
 259         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 260         reg |= DLL_FORCE_VALUE;
 261         reg &= ~DLL_FORCE_SR_C_MASK;
 262         reg |= (count << DLL_FORCE_SR_C_SHIFT);
 263         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 264
 265         reg |= DLL_CALIB;
 266         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 267         for (i = 0; i < 1000; i++) {
 268                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 269                 if (reg & DLL_CALIB)
 270                         break;
 271         }
 272         reg &= ~DLL_CALIB;
 273         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 274 }
 275
 276 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
 277 {
 278         u32 reg;
 279
 280         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 281         reg &= ~AC12_SCLK_SEL;
 282         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 283
 284         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 285         reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
 286         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 287 }
 288
 289 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
 290 {
 291         struct sdhci_host *host = mmc_priv(mmc);
 292         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 293         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 294         struct thermal_zone_device *thermal_dev;
 295         struct device *dev = omap_host->dev;
 296         struct mmc_ios *ios = &mmc->ios;
 297         u32 start_window = 0, max_window = 0;
 298         bool single_point_failure = false;
 299         bool dcrc_was_enabled = false;
 300         u8 cur_match, prev_match = 0;
 301         u32 length = 0, max_len = 0;
 302         u32 phase_delay = 0;
 303         int temperature;
 304         int ret = 0;
 305         u32 reg;
 306         int i;
 307
 308         /* clock tuning is not needed for upto 52MHz */
 309         if (ios->clock <= 52000000)
 310                 return 0;
 311
 312         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
 313         if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
 314                 return 0;
 315
 316         thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
 317         if (IS_ERR(thermal_dev)) {
 318                 dev_err(dev, "Unable to get thermal zone for tuning\n");
 319                 return PTR_ERR(thermal_dev);
 320         }
 321
 322         ret = thermal_zone_get_temp(thermal_dev, &temperature);
 323         if (ret)
 324                 return ret;
 325
 326         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 327         reg |= DLL_SWT;
 328         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 329
 330         /*
 331          * OMAP5/DRA74X/DRA72x Errata i802:
 332          * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
 333          * during the tuning procedure. So disable it during the
 334          * tuning procedure.
 335          */
 336         if (host->ier & SDHCI_INT_DATA_CRC) {
 337                 host->ier &= ~SDHCI_INT_DATA_CRC;
 338                 dcrc_was_enabled = true;
 339         }
 340
 341         omap_host->is_tuning = true;
 342
 343         /*
 344          * Stage 1: Search for a maximum pass window ignoring any
 345          * any single point failures. If the tuning value ends up
 346          * near it, move away from it in stage 2 below
 347          */
 348         while (phase_delay <= MAX_PHASE_DELAY) {
 349                 sdhci_omap_set_dll(omap_host, phase_delay);
 350
 351                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 352                 if (cur_match) {
 353                         if (prev_match) {
 354                                 length++;
 355                         } else if (single_point_failure) {
 356                                 /* ignore single point failure */
 357                                 length++;
 358                         } else {
 359                                 start_window = phase_delay;
 360                                 length = 1;
 361                         }
 362                 } else {
 363                         single_point_failure = prev_match;
 364                 }
 365
 366                 if (length > max_len) {
 367                         max_window = start_window;
 368                         max_len = length;
 369                 }
 370
 371                 prev_match = cur_match;
 372                 phase_delay += 4;
 373         }
 374
 375         if (!max_len) {
 376                 dev_err(dev, "Unable to find match\n");
 377                 ret = -EIO;
 378                 goto tuning_error;
 379         }
 380
 381         /*
 382          * Assign tuning value as a ratio of maximum pass window based
 383          * on temperature
 384          */
 385         if (temperature < -20000)
 386                 phase_delay = min(max_window + 4 * max_len - 24,
 387                                   max_window +
 388                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 389         else if (temperature < 20000)
 390                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 391         else if (temperature < 40000)
 392                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 393         else if (temperature < 70000)
 394                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 395         else if (temperature < 90000)
 396                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 397         else if (temperature < 120000)
 398                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 399         else
 400                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 401
 402         /*
 403          * Stage 2: Search for a single point failure near the chosen tuning
 404          * value in two steps. First in the +3 to +10 range and then in the
 405          * +2 to -10 range. If found, move away from it in the appropriate
 406          * direction by the appropriate amount depending on the temperature.
 407          */
 408         for (i = 3; i <= 10; i++) {
 409                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 410
 411                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 412                         if (temperature < 10000)
 413                                 phase_delay += i + 6;
 414                         else if (temperature < 20000)
 415                                 phase_delay += i - 12;
 416                         else if (temperature < 70000)
 417                                 phase_delay += i - 8;
 418                         else
 419                                 phase_delay += i - 6;
 420
 421                         goto single_failure_found;
 422                 }
 423         }
 424
 425         for (i = 2; i >= -10; i--) {
 426                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 427
 428                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 429                         if (temperature < 10000)
 430                                 phase_delay += i + 12;
 431                         else if (temperature < 20000)
 432                                 phase_delay += i + 8;
 433                         else if (temperature < 70000)
 434                                 phase_delay += i + 8;
 435                         else if (temperature < 90000)
 436                                 phase_delay += i + 10;
 437                         else
 438                                 phase_delay += i + 12;
 439
 440                         goto single_failure_found;
 441                 }
 442         }
 443
 444 single_failure_found:
 445         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 446         if (!(reg & AC12_SCLK_SEL)) {
 447                 ret = -EIO;
 448                 goto tuning_error;
 449         }
 450
 451         sdhci_omap_set_dll(omap_host, phase_delay);
 452
 453         omap_host->is_tuning = false;
 454
 455         goto ret;
 456
 457 tuning_error:
 458         omap_host->is_tuning = false;
 459         dev_err(dev, "Tuning failed\n");
 460         sdhci_omap_disable_tuning(omap_host);
 461
 462 ret:
 463         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 464         /* Reenable forbidden interrupt */
 465         if (dcrc_was_enabled)
 466                 host->ier |= SDHCI_INT_DATA_CRC;
 467         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 468         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 469         return ret;
 470 }
 471
 472 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 473 {
 474         u32 reg, ac12;
 475         int ret = false;
 476         struct sdhci_host *host = mmc_priv(mmc);
 477         struct sdhci_pltfm_host *pltfm_host;
 478         struct sdhci_omap_host *omap_host;
 479         u32 ier = host->ier;
 480
 481         pltfm_host = sdhci_priv(host);
 482         omap_host = sdhci_pltfm_priv(pltfm_host);
 483
 484         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 485         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 486         reg &= ~CON_CLKEXTFREE;
 487         if (ac12 & AC12_V1V8_SIGEN)
 488                 reg |= CON_CLKEXTFREE;
 489         reg |= CON_PADEN;
 490         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 491
 492         disable_irq(host->irq);
 493         ier |= SDHCI_INT_CARD_INT;
 494         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 495         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 496
 497         /*
 498          * Delay is required for PSTATE to correctly reflect
 499          * DLEV/CLEV values after PADEN is set.
 500          */
 501         usleep_range(50, 100);
 502         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 503         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 504                 ret = true;
 505
 506         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 507         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 508         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 509
 510         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 511         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 512         enable_irq(host->irq);
 513
 514         return ret;
 515 }
 516
 517 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 518                                                   struct mmc_ios *ios)
 519 {
 520         u32 reg;
 521         int ret;
 522         unsigned int iov;
 523         struct sdhci_host *host = mmc_priv(mmc);
 524         struct sdhci_pltfm_host *pltfm_host;
 525         struct sdhci_omap_host *omap_host;
 526         struct device *dev;
 527
 528         pltfm_host = sdhci_priv(host);
 529         omap_host = sdhci_pltfm_priv(pltfm_host);
 530         dev = omap_host->dev;
 531
 532         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 533                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 534                 if (!(reg & CAPA_VS33))
 535                         return -EOPNOTSUPP;
 536
 537                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 538
 539                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 540                 reg &= ~AC12_V1V8_SIGEN;
 541                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 542
 543                 iov = IOV_3V3;
 544         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 545                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 546                 if (!(reg & CAPA_VS18))
 547                         return -EOPNOTSUPP;
 548
 549                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 550
 551                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 552                 reg |= AC12_V1V8_SIGEN;
 553                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 554
 555                 iov = IOV_1V8;
 556         } else {
 557                 return -EOPNOTSUPP;
 558         }
 559
 560         ret = sdhci_omap_enable_iov(omap_host, iov);
 561         if (ret) {
 562                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 563                 return ret;
 564         }
 565
 566         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 567         return 0;
 568 }
 569
 570 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
 571 {
 572         int ret;
 573         struct pinctrl_state *pinctrl_state;
 574         struct device *dev = omap_host->dev;
 575
 576         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 577                 return;
 578
 579         if (omap_host->timing == timing)
 580                 return;
 581
 582         sdhci_omap_stop_clock(omap_host);
 583
 584         pinctrl_state = omap_host->pinctrl_state[timing];
 585         ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
 586         if (ret) {
 587                 dev_err(dev, "failed to select pinctrl state\n");
 588                 return;
 589         }
 590
 591         sdhci_omap_start_clock(omap_host);
 592         omap_host->timing = timing;
 593 }
 594
 595 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 596                                       u8 power_mode)
 597 {
 598         if (omap_host->bus_mode == MMC_POWER_OFF)
 599                 sdhci_omap_disable_tuning(omap_host);
 600         omap_host->power_mode = power_mode;
 601 }
 602
 603 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 604                                     unsigned int mode)
 605 {
 606         u32 reg;
 607
 608         if (omap_host->bus_mode == mode)
 609                 return;
 610
 611         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 612         if (mode == MMC_BUSMODE_OPENDRAIN)
 613                 reg |= CON_OD;
 614         else
 615                 reg &= ~CON_OD;
 616         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 617
 618         omap_host->bus_mode = mode;
 619 }
 620
 621 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 622 {
 623         struct sdhci_host *host = mmc_priv(mmc);
 624         struct sdhci_pltfm_host *pltfm_host;
 625         struct sdhci_omap_host *omap_host;
 626
 627         pltfm_host = sdhci_priv(host);
 628         omap_host = sdhci_pltfm_priv(pltfm_host);
 629
 630         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 631         sdhci_omap_set_timing(omap_host, ios->timing);
 632         sdhci_set_ios(mmc, ios);
 633         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 634 }
 635
 636 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 637                                    unsigned int clock)
 638 {
 639         u16 dsor;
 640
 641         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 642         if (dsor > SYSCTL_CLKD_MAX)
 643                 dsor = SYSCTL_CLKD_MAX;
 644
 645         return dsor;
 646 }
 647
 648 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 649 {
 650         u32 reg;
 651
 652         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 653         reg |= SYSCTL_CEN;
 654         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 655 }
 656
 657 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 658 {
 659         u32 reg;
 660
 661         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 662         reg &= ~SYSCTL_CEN;
 663         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 664 }
 665
 666 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 667 {
 668         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 669         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 670         unsigned long clkdiv;
 671
 672         sdhci_omap_stop_clock(omap_host);
 673
 674         if (!clock)
 675                 return;
 676
 677         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 678         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 679         sdhci_enable_clk(host, clkdiv);
 680
 681         sdhci_omap_start_clock(omap_host);
 682 }
 683
 684 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 685                           unsigned short vdd)
 686 {
 687         struct mmc_host *mmc = host->mmc;
 688
 689         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 690 }
 691
 692 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 693 {
 694         u32 reg;
 695         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 696         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 697
 698         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 699         reg |= CON_DMA_MASTER;
 700         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 701
 702         return 0;
 703 }
 704
 705 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 706 {
 707         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 708
 709         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 710 }
 711
 712 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 713 {
 714         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 715         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 716         u32 reg;
 717
 718         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 719         if (width == MMC_BUS_WIDTH_8)
 720                 reg |= CON_DW8;
 721         else
 722                 reg &= ~CON_DW8;
 723         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 724
 725         sdhci_set_bus_width(host, width);
 726 }
 727
 728 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 729 {
 730         u32 reg;
 731         ktime_t timeout;
 732         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 733         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 734
 735         if (omap_host->power_mode == power_mode)
 736                 return;
 737
 738         if (power_mode != MMC_POWER_ON)
 739                 return;
 740
 741         disable_irq(host->irq);
 742
 743         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 744         reg |= CON_INIT;
 745         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 746         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 747
 748         /* wait 1ms */
 749         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 750         while (1) {
 751                 bool timedout = ktime_after(ktime_get(), timeout);
 752
 753                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
 754                         break;
 755                 if (WARN_ON(timedout))
 756                         return;
 757                 usleep_range(5, 10);
 758         }
 759
 760         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 761         reg &= ~CON_INIT;
 762         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 763         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 764
 765         enable_irq(host->irq);
 766 }
 767
 768 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 769                                          unsigned int timing)
 770 {
 771         u32 reg;
 772         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 773         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 774
 775         sdhci_omap_stop_clock(omap_host);
 776
 777         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 778         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 779                 reg |= CON_DDR;
 780         else
 781                 reg &= ~CON_DDR;
 782         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 783
 784         sdhci_set_uhs_signaling(host, timing);
 785         sdhci_omap_start_clock(omap_host);
 786 }
 787
 788 void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
 789 {
 790         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 791         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 792
 793         /* Don't reset data lines during tuning operation */
 794         if (omap_host->is_tuning)
 795                 mask &= ~SDHCI_RESET_DATA;
 796
 797         sdhci_reset(host, mask);
 798 }
 799
 800 static struct sdhci_ops sdhci_omap_ops = {
 801         .set_clock = sdhci_omap_set_clock,
 802         .set_power = sdhci_omap_set_power,
 803         .enable_dma = sdhci_omap_enable_dma,
 804         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 805         .get_min_clock = sdhci_omap_get_min_clock,
 806         .set_bus_width = sdhci_omap_set_bus_width,
 807         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 808         .reset = sdhci_omap_reset,
 809         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 810 };
 811
 812 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 813 {
 814         u32 reg;
 815         int ret = 0;
 816         struct device *dev = omap_host->dev;
 817         struct regulator *vqmmc;
 818
 819         vqmmc = regulator_get(dev, "vqmmc");
 820         if (IS_ERR(vqmmc)) {
 821                 ret = PTR_ERR(vqmmc);
 822                 goto reg_put;
 823         }
 824
 825         /* voltage capabilities might be set by boot loader, clear it */
 826         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 827         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 828
 829         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 830                 reg |= CAPA_VS33;
 831         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 832                 reg |= CAPA_VS18;
 833
 834         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 835
 836 reg_put:
 837         regulator_put(vqmmc);
 838
 839         return ret;
 840 }
 841
 842 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 843         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 844                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 845                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 846                   SDHCI_QUIRK_NO_HISPD_BIT |
 847                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 848         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
 849                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 850                    SDHCI_QUIRK2_RSP_136_HAS_CRC |
 851                    SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
 852         .ops = &sdhci_omap_ops,
 853 };
 854
 855 static const struct sdhci_omap_data k2g_data = {
 856         .offset = 0x200,
 857 };
 858
 859 static const struct sdhci_omap_data dra7_data = {
 860         .offset = 0x200,
 861         .flags  = SDHCI_OMAP_REQUIRE_IODELAY,
 862 };
 863
 864 static const struct of_device_id omap_sdhci_match[] = {
 865         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 866         { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
 867         {},
 868 };
 869 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 870
 871 static struct pinctrl_state
 872 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
 873                                   u32 *caps, u32 capmask)
 874 {
 875         struct device *dev = omap_host->dev;
 876         char *version = omap_host->version;
 877         struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
 878         char str[20];
 879
 880         if (!(*caps & capmask))
 881                 goto ret;
 882
 883         if (version) {
 884                 snprintf(str, 20, "%s-%s", mode, version);
 885                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
 886         }
 887
 888         if (IS_ERR(pinctrl_state))
 889                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
 890
 891         if (IS_ERR(pinctrl_state)) {
 892                 dev_err(dev, "no pinctrl state for %s mode", mode);
 893                 *caps &= ~capmask;
 894         }
 895
 896 ret:
 897         return pinctrl_state;
 898 }
 899
 900 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
 901                                                    *omap_host)
 902 {
 903         struct device *dev = omap_host->dev;
 904         struct sdhci_host *host = omap_host->host;
 905         struct mmc_host *mmc = host->mmc;
 906         u32 *caps = &mmc->caps;
 907         u32 *caps2 = &mmc->caps2;
 908         struct pinctrl_state *state;
 909         struct pinctrl_state **pinctrl_state;
 910
 911         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 912                 return 0;
 913
 914         pinctrl_state = devm_kcalloc(dev,
 915                                      MMC_TIMING_MMC_HS200 + 1,
 916                                      sizeof(*pinctrl_state),
 917                                      GFP_KERNEL);
 918         if (!pinctrl_state)
 919                 return -ENOMEM;
 920
 921         omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
 922         if (IS_ERR(omap_host->pinctrl)) {
 923                 dev_err(dev, "Cannot get pinctrl\n");
 924                 return PTR_ERR(omap_host->pinctrl);
 925         }
 926
 927         state = pinctrl_lookup_state(omap_host->pinctrl, "default");
 928         if (IS_ERR(state)) {
 929                 dev_err(dev, "no pinctrl state for default mode\n");
 930                 return PTR_ERR(state);
 931         }
 932         pinctrl_state[MMC_TIMING_LEGACY] = state;
 933
 934         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
 935                                                  MMC_CAP_UHS_SDR104);
 936         if (!IS_ERR(state))
 937                 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
 938
 939         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
 940                                                  MMC_CAP_UHS_DDR50);
 941         if (!IS_ERR(state))
 942                 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
 943
 944         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
 945                                                  MMC_CAP_UHS_SDR50);
 946         if (!IS_ERR(state))
 947                 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
 948
 949         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
 950                                                  MMC_CAP_UHS_SDR25);
 951         if (!IS_ERR(state))
 952                 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
 953
 954         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
 955                                                  MMC_CAP_UHS_SDR12);
 956         if (!IS_ERR(state))
 957                 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
 958
 959         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
 960                                                  MMC_CAP_1_8V_DDR);
 961         if (!IS_ERR(state)) {
 962                 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
 963         } else {
 964                 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
 965                                                          caps,
 966                                                          MMC_CAP_3_3V_DDR);
 967                 if (!IS_ERR(state))
 968                         pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
 969         }
 970
 971         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
 972                                                  MMC_CAP_SD_HIGHSPEED);
 973         if (!IS_ERR(state))
 974                 pinctrl_state[MMC_TIMING_SD_HS] = state;
 975
 976         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
 977                                                  MMC_CAP_MMC_HIGHSPEED);
 978         if (!IS_ERR(state))
 979                 pinctrl_state[MMC_TIMING_MMC_HS] = state;
 980
 981         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
 982                                                  MMC_CAP2_HS200_1_8V_SDR);
 983         if (!IS_ERR(state))
 984                 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
 985
 986         omap_host->pinctrl_state = pinctrl_state;
 987
 988         return 0;
 989 }
 990
 991 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
 992         {
 993                 .machine = "DRA7[45]*",
 994                 .revision = "ES1.[01]",
 995         },
 996         {
 997                 /* sentinel */
 998         }
 999 };
1000
1001 static int sdhci_omap_probe(struct platform_device *pdev)
1002 {
1003         int ret;
1004         u32 offset;
1005         struct device *dev = &pdev->dev;
1006         struct sdhci_host *host;
1007         struct sdhci_pltfm_host *pltfm_host;
1008         struct sdhci_omap_host *omap_host;
1009         struct mmc_host *mmc;
1010         const struct of_device_id *match;
1011         struct sdhci_omap_data *data;
1012         const struct soc_device_attribute *soc;
1013
1014         match = of_match_device(omap_sdhci_match, dev);
1015         if (!match)
1016                 return -EINVAL;
1017
1018         data = (struct sdhci_omap_data *)match->data;
1019         if (!data) {
1020                 dev_err(dev, "no sdhci omap data\n");
1021                 return -EINVAL;
1022         }
1023         offset = data->offset;
1024
1025         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1026                                 sizeof(*omap_host));
1027         if (IS_ERR(host)) {
1028                 dev_err(dev, "Failed sdhci_pltfm_init\n");
1029                 return PTR_ERR(host);
1030         }
1031
1032         pltfm_host = sdhci_priv(host);
1033         omap_host = sdhci_pltfm_priv(pltfm_host);
1034         omap_host->host = host;
1035         omap_host->base = host->ioaddr;
1036         omap_host->dev = dev;
1037         omap_host->power_mode = MMC_POWER_UNDEFINED;
1038         omap_host->timing = MMC_TIMING_LEGACY;
1039         omap_host->flags = data->flags;
1040         host->ioaddr += offset;
1041
1042         mmc = host->mmc;
1043         sdhci_get_of_property(pdev);
1044         ret = mmc_of_parse(mmc);
1045         if (ret)
1046                 goto err_pltfm_free;
1047
1048         soc = soc_device_match(sdhci_omap_soc_devices);
1049         if (soc) {
1050                 omap_host->version = "rev11";
1051                 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1052                         mmc->f_max = 96000000;
1053                 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1054                         mmc->f_max = 48000000;
1055                 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1056                         mmc->f_max = 48000000;
1057         }
1058
1059         pltfm_host->clk = devm_clk_get(dev, "fck");
1060         if (IS_ERR(pltfm_host->clk)) {
1061                 ret = PTR_ERR(pltfm_host->clk);
1062                 goto err_pltfm_free;
1063         }
1064
1065         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1066         if (ret) {
1067                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1068                 goto err_pltfm_free;
1069         }
1070
1071         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1072         if (IS_ERR(omap_host->pbias)) {
1073                 ret = PTR_ERR(omap_host->pbias);
1074                 if (ret != -ENODEV)
1075                         goto err_pltfm_free;
1076                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1077         }
1078         omap_host->pbias_enabled = false;
1079
1080         /*
1081          * omap_device_pm_domain has callbacks to enable the main
1082          * functional clock, interface clock and also configure the
1083          * SYSCONFIG register of omap devices. The callback will be invoked
1084          * as part of pm_runtime_get_sync.
1085          */
1086         pm_runtime_enable(dev);
1087         ret = pm_runtime_get_sync(dev);
1088         if (ret < 0) {
1089                 dev_err(dev, "pm_runtime_get_sync failed\n");
1090                 pm_runtime_put_noidle(dev);
1091                 goto err_rpm_disable;
1092         }
1093
1094         ret = sdhci_omap_set_capabilities(omap_host);
1095         if (ret) {
1096                 dev_err(dev, "failed to set system capabilities\n");
1097                 goto err_put_sync;
1098         }
1099
1100         host->mmc_host_ops.start_signal_voltage_switch =
1101                                         sdhci_omap_start_signal_voltage_switch;
1102         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1103         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1104         host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1105         host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1106
1107         ret = sdhci_setup_host(host);
1108         if (ret)
1109                 goto err_put_sync;
1110
1111         ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1112         if (ret)
1113                 goto err_cleanup_host;
1114
1115         ret = __sdhci_add_host(host);
1116         if (ret)
1117                 goto err_cleanup_host;
1118
1119         return 0;
1120
1121 err_cleanup_host:
1122         sdhci_cleanup_host(host);
1123
1124 err_put_sync:
1125         pm_runtime_put_sync(dev);
1126
1127 err_rpm_disable:
1128         pm_runtime_disable(dev);
1129
1130 err_pltfm_free:
1131         sdhci_pltfm_free(pdev);
1132         return ret;
1133 }
1134
1135 static int sdhci_omap_remove(struct platform_device *pdev)
1136 {
1137         struct device *dev = &pdev->dev;
1138         struct sdhci_host *host = platform_get_drvdata(pdev);
1139
1140         sdhci_remove_host(host, true);
1141         pm_runtime_put_sync(dev);
1142         pm_runtime_disable(dev);
1143         sdhci_pltfm_free(pdev);
1144
1145         return 0;
1146 }
1147
1148 static struct platform_driver sdhci_omap_driver = {
1149         .probe = sdhci_omap_probe,
1150         .remove = sdhci_omap_remove,
1151         .driver = {
1152                    .name = "sdhci-omap",
1153                    .of_match_table = omap_sdhci_match,
1154                   },
1155 };
1156
1157 module_platform_driver(sdhci_omap_driver);
1158
1159 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1160 MODULE_AUTHOR("Texas Instruments Inc.");
1161 MODULE_LICENSE("GPL v2");
1162 MODULE_ALIAS("platform:sdhci_omap");