drivers/mmc/host/s3cmci.c

   1 /*
   2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3  *
   4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5  *
   6  * Current driver maintained by Ben Dooks and Simtec Electronics
   7  *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/clk.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/gpio.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25
  26 #include <mach/dma.h>
  27 #include <mach/gpio-samsung.h>
  28
  29 #include <linux/platform_data/mmc-s3cmci.h>
  30
  31 #include "s3cmci.h"
  32
  33 #define DRIVER_NAME "s3c-mci"
  34
  35 #define S3C2410_SDICON                  (0x00)
  36 #define S3C2410_SDIPRE                  (0x04)
  37 #define S3C2410_SDICMDARG               (0x08)
  38 #define S3C2410_SDICMDCON               (0x0C)
  39 #define S3C2410_SDICMDSTAT              (0x10)
  40 #define S3C2410_SDIRSP0                 (0x14)
  41 #define S3C2410_SDIRSP1                 (0x18)
  42 #define S3C2410_SDIRSP2                 (0x1C)
  43 #define S3C2410_SDIRSP3                 (0x20)
  44 #define S3C2410_SDITIMER                (0x24)
  45 #define S3C2410_SDIBSIZE                (0x28)
  46 #define S3C2410_SDIDCON                 (0x2C)
  47 #define S3C2410_SDIDCNT                 (0x30)
  48 #define S3C2410_SDIDSTA                 (0x34)
  49 #define S3C2410_SDIFSTA                 (0x38)
  50
  51 #define S3C2410_SDIDATA                 (0x3C)
  52 #define S3C2410_SDIIMSK                 (0x40)
  53
  54 #define S3C2440_SDIDATA                 (0x40)
  55 #define S3C2440_SDIIMSK                 (0x3C)
  56
  57 #define S3C2440_SDICON_SDRESET          (1 << 8)
  58 #define S3C2410_SDICON_SDIOIRQ          (1 << 3)
  59 #define S3C2410_SDICON_FIFORESET        (1 << 1)
  60 #define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
  61
  62 #define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
  63 #define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
  64 #define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
  65 #define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
  66 #define S3C2410_SDICMDCON_INDEX         (0x3f)
  67
  68 #define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
  69 #define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
  70 #define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
  71 #define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
  72
  73 #define S3C2440_SDIDCON_DS_WORD         (2 << 22)
  74 #define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
  75 #define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
  76 #define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
  77 #define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
  78 #define S3C2410_SDIDCON_DMAEN           (1 << 15)
  79 #define S3C2410_SDIDCON_STOP            (1 << 14)
  80 #define S3C2440_SDIDCON_DATSTART        (1 << 14)
  81
  82 #define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
  83 #define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
  84
  85 #define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
  86
  87 #define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
  88 #define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
  89 #define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
  90 #define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
  91 #define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
  92 #define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
  93 #define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
  94 #define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
  95
  96 #define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
  97 #define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
  98 #define S3C2410_SDIFSTA_TFDET           (1 << 13)
  99 #define S3C2410_SDIFSTA_RFDET           (1 << 12)
 100 #define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
 101
 102 #define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
 103 #define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
 104 #define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
 105 #define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
 106 #define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
 107 #define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
 108 #define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
 109 #define S3C2410_SDIIMSK_DATACRC         (1 << 9)
 110 #define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
 111 #define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
 112 #define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
 113 #define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
 114 #define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
 115
 116 enum dbg_channels {
 117         dbg_err   = (1 << 0),
 118         dbg_debug = (1 << 1),
 119         dbg_info  = (1 << 2),
 120         dbg_irq   = (1 << 3),
 121         dbg_sg    = (1 << 4),
 122         dbg_dma   = (1 << 5),
 123         dbg_pio   = (1 << 6),
 124         dbg_fail  = (1 << 7),
 125         dbg_conf  = (1 << 8),
 126 };
 127
 128 static const int dbgmap_err   = dbg_fail;
 129 static const int dbgmap_info  = dbg_info | dbg_conf;
 130 static const int dbgmap_debug = dbg_err | dbg_debug;
 131
 132 #define dbg(host, channels, args...)              \
 133         do {                                      \
 134         if (dbgmap_err & channels)                \
 135                 dev_err(&host->pdev->dev, args);  \
 136         else if (dbgmap_info & channels)          \
 137                 dev_info(&host->pdev->dev, args); \
 138         else if (dbgmap_debug & channels)         \
 139                 dev_dbg(&host->pdev->dev, args);  \
 140         } while (0)
 141
 142 static struct s3c2410_dma_client s3cmci_dma_client = {
 143         .name           = "s3c-mci",
 144 };
 145
 146 static void finalize_request(struct s3cmci_host *host);
 147 static void s3cmci_send_request(struct mmc_host *mmc);
 148 static void s3cmci_reset(struct s3cmci_host *host);
 149
 150 #ifdef CONFIG_MMC_DEBUG
 151
 152 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
 153 {
 154         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
 155         u32 datcon, datcnt, datsta, fsta, imask;
 156
 157         con     = readl(host->base + S3C2410_SDICON);
 158         pre     = readl(host->base + S3C2410_SDIPRE);
 159         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
 160         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
 161         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
 162         r0      = readl(host->base + S3C2410_SDIRSP0);
 163         r1      = readl(host->base + S3C2410_SDIRSP1);
 164         r2      = readl(host->base + S3C2410_SDIRSP2);
 165         r3      = readl(host->base + S3C2410_SDIRSP3);
 166         timer   = readl(host->base + S3C2410_SDITIMER);
 167         bsize   = readl(host->base + S3C2410_SDIBSIZE);
 168         datcon  = readl(host->base + S3C2410_SDIDCON);
 169         datcnt  = readl(host->base + S3C2410_SDIDCNT);
 170         datsta  = readl(host->base + S3C2410_SDIDSTA);
 171         fsta    = readl(host->base + S3C2410_SDIFSTA);
 172         imask   = readl(host->base + host->sdiimsk);
 173
 174         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
 175                                 prefix, con, pre, timer);
 176
 177         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
 178                                 prefix, cmdcon, cmdarg, cmdsta);
 179
 180         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 181                                " DSTA:[%08x] DCNT:[%08x]\n",
 182                                 prefix, datcon, fsta, datsta, datcnt);
 183
 184         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 185                                "   R2:[%08x]   R3:[%08x]\n",
 186                                 prefix, r0, r1, r2, r3);
 187 }
 188
 189 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 190                            int stop)
 191 {
 192         snprintf(host->dbgmsg_cmd, 300,
 193                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 194                  host->ccnt, (stop ? " (STOP)" : ""),
 195                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 196
 197         if (cmd->data) {
 198                 snprintf(host->dbgmsg_dat, 300,
 199                          "#%u bsize:%u blocks:%u bytes:%u",
 200                          host->dcnt, cmd->data->blksz,
 201                          cmd->data->blocks,
 202                          cmd->data->blocks * cmd->data->blksz);
 203         } else {
 204                 host->dbgmsg_dat[0] = '\0';
 205         }
 206 }
 207
 208 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 209                         int fail)
 210 {
 211         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 212
 213         if (!cmd)
 214                 return;
 215
 216         if (cmd->error == 0) {
 217                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 218                         host->dbgmsg_cmd, cmd->resp[0]);
 219         } else {
 220                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 221                         cmd->error, host->dbgmsg_cmd, host->status);
 222         }
 223
 224         if (!cmd->data)
 225                 return;
 226
 227         if (cmd->data->error == 0) {
 228                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 229         } else {
 230                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 231                         cmd->data->error, host->dbgmsg_dat,
 232                         readl(host->base + S3C2410_SDIDCNT));
 233         }
 234 }
 235 #else
 236 static void dbg_dumpcmd(struct s3cmci_host *host,
 237                         struct mmc_command *cmd, int fail) { }
 238
 239 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 240                            int stop) { }
 241
 242 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 243
 244 #endif /* CONFIG_MMC_DEBUG */
 245
 246 /**
 247  * s3cmci_host_usedma - return whether the host is using dma or pio
 248  * @host: The host state
 249  *
 250  * Return true if the host is using DMA to transfer data, else false
 251  * to use PIO mode. Will return static data depending on the driver
 252  * configuration.
 253  */
 254 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 255 {
 256 #ifdef CONFIG_MMC_S3C_PIO
 257         return false;
 258 #elif defined(CONFIG_MMC_S3C_DMA)
 259         return true;
 260 #else
 261         return host->dodma;
 262 #endif
 263 }
 264
 265 /**
 266  * s3cmci_host_canpio - return true if host has pio code available
 267  *
 268  * Return true if the driver has been compiled with the PIO support code
 269  * available.
 270  */
 271 static inline bool s3cmci_host_canpio(void)
 272 {
 273 #ifdef CONFIG_MMC_S3C_PIO
 274         return true;
 275 #else
 276         return false;
 277 #endif
 278 }
 279
 280 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 281 {
 282         u32 newmask;
 283
 284         newmask = readl(host->base + host->sdiimsk);
 285         newmask |= imask;
 286
 287         writel(newmask, host->base + host->sdiimsk);
 288
 289         return newmask;
 290 }
 291
 292 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 293 {
 294         u32 newmask;
 295
 296         newmask = readl(host->base + host->sdiimsk);
 297         newmask &= ~imask;
 298
 299         writel(newmask, host->base + host->sdiimsk);
 300
 301         return newmask;
 302 }
 303
 304 static inline void clear_imask(struct s3cmci_host *host)
 305 {
 306         u32 mask = readl(host->base + host->sdiimsk);
 307
 308         /* preserve the SDIO IRQ mask state */
 309         mask &= S3C2410_SDIIMSK_SDIOIRQ;
 310         writel(mask, host->base + host->sdiimsk);
 311 }
 312
 313 /**
 314  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 315  * @host: The host to check.
 316  *
 317  * Test to see if the SDIO interrupt is being signalled in case the
 318  * controller has failed to re-detect a card interrupt. Read GPE8 and
 319  * see if it is low and if so, signal a SDIO interrupt.
 320  *
 321  * This is currently called if a request is finished (we assume that the
 322  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 323  * already being indicated.
 324 */
 325 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 326 {
 327         if (host->sdio_irqen) {
 328                 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
 329                         pr_debug("%s: signalling irq\n", __func__);
 330                         mmc_signal_sdio_irq(host->mmc);
 331                 }
 332         }
 333 }
 334
 335 static inline int get_data_buffer(struct s3cmci_host *host,
 336                                   u32 *bytes, u32 **pointer)
 337 {
 338         struct scatterlist *sg;
 339
 340         if (host->pio_active == XFER_NONE)
 341                 return -EINVAL;
 342
 343         if ((!host->mrq) || (!host->mrq->data))
 344                 return -EINVAL;
 345
 346         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 347                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 348                       host->pio_sgptr, host->mrq->data->sg_len);
 349                 return -EBUSY;
 350         }
 351         sg = &host->mrq->data->sg[host->pio_sgptr];
 352
 353         *bytes = sg->length;
 354         *pointer = sg_virt(sg);
 355
 356         host->pio_sgptr++;
 357
 358         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 359             host->pio_sgptr, host->mrq->data->sg_len);
 360
 361         return 0;
 362 }
 363
 364 static inline u32 fifo_count(struct s3cmci_host *host)
 365 {
 366         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 367
 368         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 369         return fifostat;
 370 }
 371
 372 static inline u32 fifo_free(struct s3cmci_host *host)
 373 {
 374         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 375
 376         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 377         return 63 - fifostat;
 378 }
 379
 380 /**
 381  * s3cmci_enable_irq - enable IRQ, after having disabled it.
 382  * @host: The device state.
 383  * @more: True if more IRQs are expected from transfer.
 384  *
 385  * Enable the main IRQ if needed after it has been disabled.
 386  *
 387  * The IRQ can be one of the following states:
 388  *      - disabled during IDLE
 389  *      - disabled whilst processing data
 390  *      - enabled during transfer
 391  *      - enabled whilst awaiting SDIO interrupt detection
 392  */
 393 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 394 {
 395         unsigned long flags;
 396         bool enable = false;
 397
 398         local_irq_save(flags);
 399
 400         host->irq_enabled = more;
 401         host->irq_disabled = false;
 402
 403         enable = more | host->sdio_irqen;
 404
 405         if (host->irq_state != enable) {
 406                 host->irq_state = enable;
 407
 408                 if (enable)
 409                         enable_irq(host->irq);
 410                 else
 411                         disable_irq(host->irq);
 412         }
 413
 414         local_irq_restore(flags);
 415 }
 416
 417 /**
 418  *
 419  */
 420 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 421 {
 422         unsigned long flags;
 423
 424         local_irq_save(flags);
 425
 426         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 427
 428         host->irq_disabled = transfer;
 429
 430         if (transfer && host->irq_state) {
 431                 host->irq_state = false;
 432                 disable_irq(host->irq);
 433         }
 434
 435         local_irq_restore(flags);
 436 }
 437
 438 static void do_pio_read(struct s3cmci_host *host)
 439 {
 440         int res;
 441         u32 fifo;
 442         u32 *ptr;
 443         u32 fifo_words;
 444         void __iomem *from_ptr;
 445
 446         /* write real prescaler to host, it might be set slow to fix */
 447         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 448
 449         from_ptr = host->base + host->sdidata;
 450
 451         while ((fifo = fifo_count(host))) {
 452                 if (!host->pio_bytes) {
 453                         res = get_data_buffer(host, &host->pio_bytes,
 454                                               &host->pio_ptr);
 455                         if (res) {
 456                                 host->pio_active = XFER_NONE;
 457                                 host->complete_what = COMPLETION_FINALIZE;
 458
 459                                 dbg(host, dbg_pio, "pio_read(): "
 460                                     "complete (no more data).\n");
 461                                 return;
 462                         }
 463
 464                         dbg(host, dbg_pio,
 465                             "pio_read(): new target: [%i]@[%p]\n",
 466                             host->pio_bytes, host->pio_ptr);
 467                 }
 468
 469                 dbg(host, dbg_pio,
 470                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 471                     fifo, host->pio_bytes,
 472                     readl(host->base + S3C2410_SDIDCNT));
 473
 474                 /* If we have reached the end of the block, we can
 475                  * read a word and get 1 to 3 bytes.  If we in the
 476                  * middle of the block, we have to read full words,
 477                  * otherwise we will write garbage, so round down to
 478                  * an even multiple of 4. */
 479                 if (fifo >= host->pio_bytes)
 480                         fifo = host->pio_bytes;
 481                 else
 482                         fifo -= fifo & 3;
 483
 484                 host->pio_bytes -= fifo;
 485                 host->pio_count += fifo;
 486
 487                 fifo_words = fifo >> 2;
 488                 ptr = host->pio_ptr;
 489                 while (fifo_words--)
 490                         *ptr++ = readl(from_ptr);
 491                 host->pio_ptr = ptr;
 492
 493                 if (fifo & 3) {
 494                         u32 n = fifo & 3;
 495                         u32 data = readl(from_ptr);
 496                         u8 *p = (u8 *)host->pio_ptr;
 497
 498                         while (n--) {
 499                                 *p++ = data;
 500                                 data >>= 8;
 501                         }
 502                 }
 503         }
 504
 505         if (!host->pio_bytes) {
 506                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 507                 if (res) {
 508                         dbg(host, dbg_pio,
 509                             "pio_read(): complete (no more buffers).\n");
 510                         host->pio_active = XFER_NONE;
 511                         host->complete_what = COMPLETION_FINALIZE;
 512
 513                         return;
 514                 }
 515         }
 516
 517         enable_imask(host,
 518                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 519 }
 520
 521 static void do_pio_write(struct s3cmci_host *host)
 522 {
 523         void __iomem *to_ptr;
 524         int res;
 525         u32 fifo;
 526         u32 *ptr;
 527
 528         to_ptr = host->base + host->sdidata;
 529
 530         while ((fifo = fifo_free(host)) > 3) {
 531                 if (!host->pio_bytes) {
 532                         res = get_data_buffer(host, &host->pio_bytes,
 533                                                         &host->pio_ptr);
 534                         if (res) {
 535                                 dbg(host, dbg_pio,
 536                                     "pio_write(): complete (no more data).\n");
 537                                 host->pio_active = XFER_NONE;
 538
 539                                 return;
 540                         }
 541
 542                         dbg(host, dbg_pio,
 543                             "pio_write(): new source: [%i]@[%p]\n",
 544                             host->pio_bytes, host->pio_ptr);
 545
 546                 }
 547
 548                 /* If we have reached the end of the block, we have to
 549                  * write exactly the remaining number of bytes.  If we
 550                  * in the middle of the block, we have to write full
 551                  * words, so round down to an even multiple of 4. */
 552                 if (fifo >= host->pio_bytes)
 553                         fifo = host->pio_bytes;
 554                 else
 555                         fifo -= fifo & 3;
 556
 557                 host->pio_bytes -= fifo;
 558                 host->pio_count += fifo;
 559
 560                 fifo = (fifo + 3) >> 2;
 561                 ptr = host->pio_ptr;
 562                 while (fifo--)
 563                         writel(*ptr++, to_ptr);
 564                 host->pio_ptr = ptr;
 565         }
 566
 567         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 568 }
 569
 570 static void pio_tasklet(unsigned long data)
 571 {
 572         struct s3cmci_host *host = (struct s3cmci_host *) data;
 573
 574         s3cmci_disable_irq(host, true);
 575
 576         if (host->pio_active == XFER_WRITE)
 577                 do_pio_write(host);
 578
 579         if (host->pio_active == XFER_READ)
 580                 do_pio_read(host);
 581
 582         if (host->complete_what == COMPLETION_FINALIZE) {
 583                 clear_imask(host);
 584                 if (host->pio_active != XFER_NONE) {
 585                         dbg(host, dbg_err, "unfinished %s "
 586                             "- pio_count:[%u] pio_bytes:[%u]\n",
 587                             (host->pio_active == XFER_READ) ? "read" : "write",
 588                             host->pio_count, host->pio_bytes);
 589
 590                         if (host->mrq->data)
 591                                 host->mrq->data->error = -EINVAL;
 592                 }
 593
 594                 s3cmci_enable_irq(host, false);
 595                 finalize_request(host);
 596         } else
 597                 s3cmci_enable_irq(host, true);
 598 }
 599
 600 /*
 601  * ISR for SDI Interface IRQ
 602  * Communication between driver and ISR works as follows:
 603  *   host->mrq                  points to current request
 604  *   host->complete_what        Indicates when the request is considered done
 605  *     COMPLETION_CMDSENT         when the command was sent
 606  *     COMPLETION_RSPFIN          when a response was received
 607  *     COMPLETION_XFERFINISH      when the data transfer is finished
 608  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 609  *   host->complete_request     is the completion-object the driver waits for
 610  *
 611  * 1) Driver sets up host->mrq and host->complete_what
 612  * 2) Driver prepares the transfer
 613  * 3) Driver enables interrupts
 614  * 4) Driver starts transfer
 615  * 5) Driver waits for host->complete_rquest
 616  * 6) ISR checks for request status (errors and success)
 617  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 618  * 7) ISR completes host->complete_request
 619  * 8) ISR disables interrupts
 620  * 9) Driver wakes up and takes care of the request
 621  *
 622  * Note: "->error"-fields are expected to be set to 0 before the request
 623  *       was issued by mmc.c - therefore they are only set, when an error
 624  *       contition comes up
 625  */
 626
 627 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 628 {
 629         struct s3cmci_host *host = dev_id;
 630         struct mmc_command *cmd;
 631         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 632         u32 mci_cclear = 0, mci_dclear;
 633         unsigned long iflags;
 634
 635         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 636         mci_imsk = readl(host->base + host->sdiimsk);
 637
 638         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 639                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 640                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 641                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 642
 643                         mmc_signal_sdio_irq(host->mmc);
 644                         return IRQ_HANDLED;
 645                 }
 646         }
 647
 648         spin_lock_irqsave(&host->complete_lock, iflags);
 649
 650         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 651         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 652         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 653         mci_dclear = 0;
 654
 655         if ((host->complete_what == COMPLETION_NONE) ||
 656             (host->complete_what == COMPLETION_FINALIZE)) {
 657                 host->status = "nothing to complete";
 658                 clear_imask(host);
 659                 goto irq_out;
 660         }
 661
 662         if (!host->mrq) {
 663                 host->status = "no active mrq";
 664                 clear_imask(host);
 665                 goto irq_out;
 666         }
 667
 668         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 669
 670         if (!cmd) {
 671                 host->status = "no active cmd";
 672                 clear_imask(host);
 673                 goto irq_out;
 674         }
 675
 676         if (!s3cmci_host_usedma(host)) {
 677                 if ((host->pio_active == XFER_WRITE) &&
 678                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 679
 680                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 681                         tasklet_schedule(&host->pio_tasklet);
 682                         host->status = "pio tx";
 683                 }
 684
 685                 if ((host->pio_active == XFER_READ) &&
 686                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 687
 688                         disable_imask(host,
 689                                       S3C2410_SDIIMSK_RXFIFOHALF |
 690                                       S3C2410_SDIIMSK_RXFIFOLAST);
 691
 692                         tasklet_schedule(&host->pio_tasklet);
 693                         host->status = "pio rx";
 694                 }
 695         }
 696
 697         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 698                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 699                 cmd->error = -ETIMEDOUT;
 700                 host->status = "error: command timeout";
 701                 goto fail_transfer;
 702         }
 703
 704         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 705                 if (host->complete_what == COMPLETION_CMDSENT) {
 706                         host->status = "ok: command sent";
 707                         goto close_transfer;
 708                 }
 709
 710                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 711         }
 712
 713         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 714                 if (cmd->flags & MMC_RSP_CRC) {
 715                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 716                                 dbg(host, dbg_irq,
 717                                     "fixup: ignore CRC fail with long rsp\n");
 718                         } else {
 719                                 /* note, we used to fail the transfer
 720                                  * here, but it seems that this is just
 721                                  * the hardware getting it wrong.
 722                                  *
 723                                  * cmd->error = -EILSEQ;
 724                                  * host->status = "error: bad command crc";
 725                                  * goto fail_transfer;
 726                                 */
 727                         }
 728                 }
 729
 730                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 731         }
 732
 733         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 734                 if (host->complete_what == COMPLETION_RSPFIN) {
 735                         host->status = "ok: command response received";
 736                         goto close_transfer;
 737                 }
 738
 739                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 740                         host->complete_what = COMPLETION_XFERFINISH;
 741
 742                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 743         }
 744
 745         /* errors handled after this point are only relevant
 746            when a data transfer is in progress */
 747
 748         if (!cmd->data)
 749                 goto clear_status_bits;
 750
 751         /* Check for FIFO failure */
 752         if (host->is2440) {
 753                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 754                         dbg(host, dbg_err, "FIFO failure\n");
 755                         host->mrq->data->error = -EILSEQ;
 756                         host->status = "error: 2440 fifo failure";
 757                         goto fail_transfer;
 758                 }
 759         } else {
 760                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 761                         dbg(host, dbg_err, "FIFO failure\n");
 762                         cmd->data->error = -EILSEQ;
 763                         host->status = "error:  fifo failure";
 764                         goto fail_transfer;
 765                 }
 766         }
 767
 768         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 769                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 770                 cmd->data->error = -EILSEQ;
 771                 host->status = "error: bad data crc (outgoing)";
 772                 goto fail_transfer;
 773         }
 774
 775         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 776                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 777                 cmd->data->error = -EILSEQ;
 778                 host->status = "error: bad data crc (incoming)";
 779                 goto fail_transfer;
 780         }
 781
 782         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 783                 dbg(host, dbg_err, "data timeout\n");
 784                 cmd->data->error = -ETIMEDOUT;
 785                 host->status = "error: data timeout";
 786                 goto fail_transfer;
 787         }
 788
 789         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 790                 if (host->complete_what == COMPLETION_XFERFINISH) {
 791                         host->status = "ok: data transfer completed";
 792                         goto close_transfer;
 793                 }
 794
 795                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 796                         host->complete_what = COMPLETION_RSPFIN;
 797
 798                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 799         }
 800
 801 clear_status_bits:
 802         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 803         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 804
 805         goto irq_out;
 806
 807 fail_transfer:
 808         host->pio_active = XFER_NONE;
 809
 810 close_transfer:
 811         host->complete_what = COMPLETION_FINALIZE;
 812
 813         clear_imask(host);
 814         tasklet_schedule(&host->pio_tasklet);
 815
 816         goto irq_out;
 817
 818 irq_out:
 819         dbg(host, dbg_irq,
 820             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 821             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 822
 823         spin_unlock_irqrestore(&host->complete_lock, iflags);
 824         return IRQ_HANDLED;
 825
 826 }
 827
 828 /*
 829  * ISR for the CardDetect Pin
 830 */
 831
 832 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
 833 {
 834         struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
 835
 836         dbg(host, dbg_irq, "card detect\n");
 837
 838         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 839
 840         return IRQ_HANDLED;
 841 }
 842
 843 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
 844                                      void *buf_id, int size,
 845                                      enum s3c2410_dma_buffresult result)
 846 {
 847         struct s3cmci_host *host = buf_id;
 848         unsigned long iflags;
 849         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
 850
 851         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 852         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 853         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 854         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 855
 856         BUG_ON(!host->mrq);
 857         BUG_ON(!host->mrq->data);
 858         BUG_ON(!host->dmatogo);
 859
 860         spin_lock_irqsave(&host->complete_lock, iflags);
 861
 862         if (result != S3C2410_RES_OK) {
 863                 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
 864                         "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
 865                         mci_csta, mci_dsta, mci_fsta,
 866                         mci_dcnt, result, host->dmatogo);
 867
 868                 goto fail_request;
 869         }
 870
 871         host->dmatogo--;
 872         if (host->dmatogo) {
 873                 dbg(host, dbg_dma, "DMA DONE  Size:%i DSTA:[%08x] "
 874                         "DCNT:[%08x] toGo:%u\n",
 875                         size, mci_dsta, mci_dcnt, host->dmatogo);
 876
 877                 goto out;
 878         }
 879
 880         dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
 881                 size, mci_dsta, mci_dcnt);
 882
 883         host->dma_complete = 1;
 884         host->complete_what = COMPLETION_FINALIZE;
 885
 886 out:
 887         tasklet_schedule(&host->pio_tasklet);
 888         spin_unlock_irqrestore(&host->complete_lock, iflags);
 889         return;
 890
 891 fail_request:
 892         host->mrq->data->error = -EINVAL;
 893         host->complete_what = COMPLETION_FINALIZE;
 894         clear_imask(host);
 895
 896         goto out;
 897 }
 898
 899 static void finalize_request(struct s3cmci_host *host)
 900 {
 901         struct mmc_request *mrq = host->mrq;
 902         struct mmc_command *cmd;
 903         int debug_as_failure = 0;
 904
 905         if (host->complete_what != COMPLETION_FINALIZE)
 906                 return;
 907
 908         if (!mrq)
 909                 return;
 910         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 911
 912         if (cmd->data && (cmd->error == 0) &&
 913             (cmd->data->error == 0)) {
 914                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 915                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 916                             host->dma_complete);
 917                         return;
 918                 }
 919         }
 920
 921         /* Read response from controller. */
 922         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 923         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 924         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 925         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 926
 927         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 928
 929         if (cmd->error)
 930                 debug_as_failure = 1;
 931
 932         if (cmd->data && cmd->data->error)
 933                 debug_as_failure = 1;
 934
 935         dbg_dumpcmd(host, cmd, debug_as_failure);
 936
 937         /* Cleanup controller */
 938         writel(0, host->base + S3C2410_SDICMDARG);
 939         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 940         writel(0, host->base + S3C2410_SDICMDCON);
 941         clear_imask(host);
 942
 943         if (cmd->data && cmd->error)
 944                 cmd->data->error = cmd->error;
 945
 946         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 947                 host->cmd_is_stop = 1;
 948                 s3cmci_send_request(host->mmc);
 949                 return;
 950         }
 951
 952         /* If we have no data transfer we are finished here */
 953         if (!mrq->data)
 954                 goto request_done;
 955
 956         /* Calculate the amout of bytes transfer if there was no error */
 957         if (mrq->data->error == 0) {
 958                 mrq->data->bytes_xfered =
 959                         (mrq->data->blocks * mrq->data->blksz);
 960         } else {
 961                 mrq->data->bytes_xfered = 0;
 962         }
 963
 964         /* If we had an error while transferring data we flush the
 965          * DMA channel and the fifo to clear out any garbage. */
 966         if (mrq->data->error != 0) {
 967                 if (s3cmci_host_usedma(host))
 968                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 969
 970                 if (host->is2440) {
 971                         /* Clear failure register and reset fifo. */
 972                         writel(S3C2440_SDIFSTA_FIFORESET |
 973                                S3C2440_SDIFSTA_FIFOFAIL,
 974                                host->base + S3C2410_SDIFSTA);
 975                 } else {
 976                         u32 mci_con;
 977
 978                         /* reset fifo */
 979                         mci_con = readl(host->base + S3C2410_SDICON);
 980                         mci_con |= S3C2410_SDICON_FIFORESET;
 981
 982                         writel(mci_con, host->base + S3C2410_SDICON);
 983                 }
 984         }
 985
 986 request_done:
 987         host->complete_what = COMPLETION_NONE;
 988         host->mrq = NULL;
 989
 990         s3cmci_check_sdio_irq(host);
 991         mmc_request_done(host->mmc, mrq);
 992 }
 993
 994 static void s3cmci_dma_setup(struct s3cmci_host *host,
 995                              enum dma_data_direction source)
 996 {
 997         static enum dma_data_direction last_source = -1;
 998         static int setup_ok;
 999
1000         if (last_source == source)
1001                 return;
1002
1003         last_source = source;
1004
1005         s3c2410_dma_devconfig(host->dma, source,
1006                               host->mem->start + host->sdidata);
1007
1008         if (!setup_ok) {
1009                 s3c2410_dma_config(host->dma, 4);
1010                 s3c2410_dma_set_buffdone_fn(host->dma,
1011                                             s3cmci_dma_done_callback);
1012                 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
1013                 setup_ok = 1;
1014         }
1015 }
1016
1017 static void s3cmci_send_command(struct s3cmci_host *host,
1018                                         struct mmc_command *cmd)
1019 {
1020         u32 ccon, imsk;
1021
1022         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
1023                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
1024                 S3C2410_SDIIMSK_RESPONSECRC;
1025
1026         enable_imask(host, imsk);
1027
1028         if (cmd->data)
1029                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
1030         else if (cmd->flags & MMC_RSP_PRESENT)
1031                 host->complete_what = COMPLETION_RSPFIN;
1032         else
1033                 host->complete_what = COMPLETION_CMDSENT;
1034
1035         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
1036
1037         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
1038         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
1039
1040         if (cmd->flags & MMC_RSP_PRESENT)
1041                 ccon |= S3C2410_SDICMDCON_WAITRSP;
1042
1043         if (cmd->flags & MMC_RSP_136)
1044                 ccon |= S3C2410_SDICMDCON_LONGRSP;
1045
1046         writel(ccon, host->base + S3C2410_SDICMDCON);
1047 }
1048
1049 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
1050 {
1051         u32 dcon, imsk, stoptries = 3;
1052
1053         /* write DCON register */
1054
1055         if (!data) {
1056                 writel(0, host->base + S3C2410_SDIDCON);
1057                 return 0;
1058         }
1059
1060         if ((data->blksz & 3) != 0) {
1061                 /* We cannot deal with unaligned blocks with more than
1062                  * one block being transferred. */
1063
1064                 if (data->blocks > 1) {
1065                         pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
1066                         return -EINVAL;
1067                 }
1068         }
1069
1070         while (readl(host->base + S3C2410_SDIDSTA) &
1071                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
1072
1073                 dbg(host, dbg_err,
1074                     "mci_setup_data() transfer stillin progress.\n");
1075
1076                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1077                 s3cmci_reset(host);
1078
1079                 if ((stoptries--) == 0) {
1080                         dbg_dumpregs(host, "DRF");
1081                         return -EINVAL;
1082                 }
1083         }
1084
1085         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1086
1087         if (s3cmci_host_usedma(host))
1088                 dcon |= S3C2410_SDIDCON_DMAEN;
1089
1090         if (host->bus_width == MMC_BUS_WIDTH_4)
1091                 dcon |= S3C2410_SDIDCON_WIDEBUS;
1092
1093         if (!(data->flags & MMC_DATA_STREAM))
1094                 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1095
1096         if (data->flags & MMC_DATA_WRITE) {
1097                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1098                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1099         }
1100
1101         if (data->flags & MMC_DATA_READ) {
1102                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1103                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1104         }
1105
1106         if (host->is2440) {
1107                 dcon |= S3C2440_SDIDCON_DS_WORD;
1108                 dcon |= S3C2440_SDIDCON_DATSTART;
1109         }
1110
1111         writel(dcon, host->base + S3C2410_SDIDCON);
1112
1113         /* write BSIZE register */
1114
1115         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1116
1117         /* add to IMASK register */
1118         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1119                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1120
1121         enable_imask(host, imsk);
1122
1123         /* write TIMER register */
1124
1125         if (host->is2440) {
1126                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1127         } else {
1128                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1129
1130                 /* FIX: set slow clock to prevent timeouts on read */
1131                 if (data->flags & MMC_DATA_READ)
1132                         writel(0xFF, host->base + S3C2410_SDIPRE);
1133         }
1134
1135         return 0;
1136 }
1137
1138 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1139
1140 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1141 {
1142         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1143
1144         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1145
1146         host->pio_sgptr = 0;
1147         host->pio_bytes = 0;
1148         host->pio_count = 0;
1149         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1150
1151         if (rw) {
1152                 do_pio_write(host);
1153                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1154         } else {
1155                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1156                              | S3C2410_SDIIMSK_RXFIFOLAST);
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1163 {
1164         int dma_len, i;
1165         int rw = data->flags & MMC_DATA_WRITE;
1166
1167         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1168
1169         s3cmci_dma_setup(host, rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1170         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1171
1172         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1173                              rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1174
1175         if (dma_len == 0)
1176                 return -ENOMEM;
1177
1178         host->dma_complete = 0;
1179         host->dmatogo = dma_len;
1180
1181         for (i = 0; i < dma_len; i++) {
1182                 int res;
1183
1184                 dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
1185                     sg_dma_address(&data->sg[i]),
1186                     sg_dma_len(&data->sg[i]));
1187
1188                 res = s3c2410_dma_enqueue(host->dma, host,
1189                                           sg_dma_address(&data->sg[i]),
1190                                           sg_dma_len(&data->sg[i]));
1191
1192                 if (res) {
1193                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1194                         return -EBUSY;
1195                 }
1196         }
1197
1198         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
1199
1200         return 0;
1201 }
1202
1203 static void s3cmci_send_request(struct mmc_host *mmc)
1204 {
1205         struct s3cmci_host *host = mmc_priv(mmc);
1206         struct mmc_request *mrq = host->mrq;
1207         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1208
1209         host->ccnt++;
1210         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1211
1212         /* Clear command, data and fifo status registers
1213            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1214         */
1215         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1216         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1217         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1218
1219         if (cmd->data) {
1220                 int res = s3cmci_setup_data(host, cmd->data);
1221
1222                 host->dcnt++;
1223
1224                 if (res) {
1225                         dbg(host, dbg_err, "setup data error %d\n", res);
1226                         cmd->error = res;
1227                         cmd->data->error = res;
1228
1229                         mmc_request_done(mmc, mrq);
1230                         return;
1231                 }
1232
1233                 if (s3cmci_host_usedma(host))
1234                         res = s3cmci_prepare_dma(host, cmd->data);
1235                 else
1236                         res = s3cmci_prepare_pio(host, cmd->data);
1237
1238                 if (res) {
1239                         dbg(host, dbg_err, "data prepare error %d\n", res);
1240                         cmd->error = res;
1241                         cmd->data->error = res;
1242
1243                         mmc_request_done(mmc, mrq);
1244                         return;
1245                 }
1246         }
1247
1248         /* Send command */
1249         s3cmci_send_command(host, cmd);
1250
1251         /* Enable Interrupt */
1252         s3cmci_enable_irq(host, true);
1253 }
1254
1255 static int s3cmci_card_present(struct mmc_host *mmc)
1256 {
1257         struct s3cmci_host *host = mmc_priv(mmc);
1258         struct s3c24xx_mci_pdata *pdata = host->pdata;
1259         int ret;
1260
1261         if (pdata->no_detect)
1262                 return -ENOSYS;
1263
1264         ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1265         return ret ^ pdata->detect_invert;
1266 }
1267
1268 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1269 {
1270         struct s3cmci_host *host = mmc_priv(mmc);
1271
1272         host->status = "mmc request";
1273         host->cmd_is_stop = 0;
1274         host->mrq = mrq;
1275
1276         if (s3cmci_card_present(mmc) == 0) {
1277                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1278                 host->mrq->cmd->error = -ENOMEDIUM;
1279                 mmc_request_done(mmc, mrq);
1280         } else
1281                 s3cmci_send_request(mmc);
1282 }
1283
1284 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1285 {
1286         u32 mci_psc;
1287
1288         /* Set clock */
1289         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1290                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1291
1292                 if (host->real_rate <= ios->clock)
1293                         break;
1294         }
1295
1296         if (mci_psc > 255)
1297                 mci_psc = 255;
1298
1299         host->prescaler = mci_psc;
1300         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1301
1302         /* If requested clock is 0, real_rate will be 0, too */
1303         if (ios->clock == 0)
1304                 host->real_rate = 0;
1305 }
1306
1307 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1308 {
1309         struct s3cmci_host *host = mmc_priv(mmc);
1310         u32 mci_con;
1311
1312         /* Set the power state */
1313
1314         mci_con = readl(host->base + S3C2410_SDICON);
1315
1316         switch (ios->power_mode) {
1317         case MMC_POWER_ON:
1318         case MMC_POWER_UP:
1319                 /* Configure GPE5...GPE10 pins in SD mode */
1320                 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1321                                       S3C_GPIO_PULL_NONE);
1322
1323                 if (host->pdata->set_power)
1324                         host->pdata->set_power(ios->power_mode, ios->vdd);
1325
1326                 if (!host->is2440)
1327                         mci_con |= S3C2410_SDICON_FIFORESET;
1328
1329                 break;
1330
1331         case MMC_POWER_OFF:
1332         default:
1333                 gpio_direction_output(S3C2410_GPE(5), 0);
1334
1335                 if (host->is2440)
1336                         mci_con |= S3C2440_SDICON_SDRESET;
1337
1338                 if (host->pdata->set_power)
1339                         host->pdata->set_power(ios->power_mode, ios->vdd);
1340
1341                 break;
1342         }
1343
1344         s3cmci_set_clk(host, ios);
1345
1346         /* Set CLOCK_ENABLE */
1347         if (ios->clock)
1348                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1349         else
1350                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1351
1352         writel(mci_con, host->base + S3C2410_SDICON);
1353
1354         if ((ios->power_mode == MMC_POWER_ON) ||
1355             (ios->power_mode == MMC_POWER_UP)) {
1356                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1357                         host->real_rate/1000, ios->clock/1000);
1358         } else {
1359                 dbg(host, dbg_conf, "powered down.\n");
1360         }
1361
1362         host->bus_width = ios->bus_width;
1363 }
1364
1365 static void s3cmci_reset(struct s3cmci_host *host)
1366 {
1367         u32 con = readl(host->base + S3C2410_SDICON);
1368
1369         con |= S3C2440_SDICON_SDRESET;
1370         writel(con, host->base + S3C2410_SDICON);
1371 }
1372
1373 static int s3cmci_get_ro(struct mmc_host *mmc)
1374 {
1375         struct s3cmci_host *host = mmc_priv(mmc);
1376         struct s3c24xx_mci_pdata *pdata = host->pdata;
1377         int ret;
1378
1379         if (pdata->no_wprotect)
1380                 return 0;
1381
1382         ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1383         ret ^= pdata->wprotect_invert;
1384
1385         return ret;
1386 }
1387
1388 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1389 {
1390         struct s3cmci_host *host = mmc_priv(mmc);
1391         unsigned long flags;
1392         u32 con;
1393
1394         local_irq_save(flags);
1395
1396         con = readl(host->base + S3C2410_SDICON);
1397         host->sdio_irqen = enable;
1398
1399         if (enable == host->sdio_irqen)
1400                 goto same_state;
1401
1402         if (enable) {
1403                 con |= S3C2410_SDICON_SDIOIRQ;
1404                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1405
1406                 if (!host->irq_state && !host->irq_disabled) {
1407                         host->irq_state = true;
1408                         enable_irq(host->irq);
1409                 }
1410         } else {
1411                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1412                 con &= ~S3C2410_SDICON_SDIOIRQ;
1413
1414                 if (!host->irq_enabled && host->irq_state) {
1415                         disable_irq_nosync(host->irq);
1416                         host->irq_state = false;
1417                 }
1418         }
1419
1420         writel(con, host->base + S3C2410_SDICON);
1421
1422  same_state:
1423         local_irq_restore(flags);
1424
1425         s3cmci_check_sdio_irq(host);
1426 }
1427
1428 static struct mmc_host_ops s3cmci_ops = {
1429         .request        = s3cmci_request,
1430         .set_ios        = s3cmci_set_ios,
1431         .get_ro         = s3cmci_get_ro,
1432         .get_cd         = s3cmci_card_present,
1433         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1434 };
1435
1436 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1437         /* This is currently here to avoid a number of if (host->pdata)
1438          * checks. Any zero fields to ensure reasonable defaults are picked. */
1439          .no_wprotect = 1,
1440          .no_detect = 1,
1441 };
1442
1443 #ifdef CONFIG_CPU_FREQ
1444
1445 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1446                                      unsigned long val, void *data)
1447 {
1448         struct s3cmci_host *host;
1449         struct mmc_host *mmc;
1450         unsigned long newclk;
1451         unsigned long flags;
1452
1453         host = container_of(nb, struct s3cmci_host, freq_transition);
1454         newclk = clk_get_rate(host->clk);
1455         mmc = host->mmc;
1456
1457         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1458             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1459                 spin_lock_irqsave(&mmc->lock, flags);
1460
1461                 host->clk_rate = newclk;
1462
1463                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1464                     mmc->ios.clock != 0)
1465                         s3cmci_set_clk(host, &mmc->ios);
1466
1467                 spin_unlock_irqrestore(&mmc->lock, flags);
1468         }
1469
1470         return 0;
1471 }
1472
1473 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1474 {
1475         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1476
1477         return cpufreq_register_notifier(&host->freq_transition,
1478                                          CPUFREQ_TRANSITION_NOTIFIER);
1479 }
1480
1481 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1482 {
1483         cpufreq_unregister_notifier(&host->freq_transition,
1484                                     CPUFREQ_TRANSITION_NOTIFIER);
1485 }
1486
1487 #else
1488 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1489 {
1490         return 0;
1491 }
1492
1493 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1494 {
1495 }
1496 #endif
1497
1498
1499 #ifdef CONFIG_DEBUG_FS
1500
1501 static int s3cmci_state_show(struct seq_file *seq, void *v)
1502 {
1503         struct s3cmci_host *host = seq->private;
1504
1505         seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1506         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1507         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1508         seq_printf(seq, "is2440 = %d\n", host->is2440);
1509         seq_printf(seq, "IRQ = %d\n", host->irq);
1510         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1511         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1512         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1513         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1514         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1515         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1516         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1517
1518         return 0;
1519 }
1520
1521 static int s3cmci_state_open(struct inode *inode, struct file *file)
1522 {
1523         return single_open(file, s3cmci_state_show, inode->i_private);
1524 }
1525
1526 static const struct file_operations s3cmci_fops_state = {
1527         .owner          = THIS_MODULE,
1528         .open           = s3cmci_state_open,
1529         .read           = seq_read,
1530         .llseek         = seq_lseek,
1531         .release        = single_release,
1532 };
1533
1534 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1535
1536 struct s3cmci_reg {
1537         unsigned short  addr;
1538         unsigned char   *name;
1539 } debug_regs[] = {
1540         DBG_REG(CON),
1541         DBG_REG(PRE),
1542         DBG_REG(CMDARG),
1543         DBG_REG(CMDCON),
1544         DBG_REG(CMDSTAT),
1545         DBG_REG(RSP0),
1546         DBG_REG(RSP1),
1547         DBG_REG(RSP2),
1548         DBG_REG(RSP3),
1549         DBG_REG(TIMER),
1550         DBG_REG(BSIZE),
1551         DBG_REG(DCON),
1552         DBG_REG(DCNT),
1553         DBG_REG(DSTA),
1554         DBG_REG(FSTA),
1555         {}
1556 };
1557
1558 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1559 {
1560         struct s3cmci_host *host = seq->private;
1561         struct s3cmci_reg *rptr = debug_regs;
1562
1563         for (; rptr->name; rptr++)
1564                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1565                            readl(host->base + rptr->addr));
1566
1567         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1568
1569         return 0;
1570 }
1571
1572 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1573 {
1574         return single_open(file, s3cmci_regs_show, inode->i_private);
1575 }
1576
1577 static const struct file_operations s3cmci_fops_regs = {
1578         .owner          = THIS_MODULE,
1579         .open           = s3cmci_regs_open,
1580         .read           = seq_read,
1581         .llseek         = seq_lseek,
1582         .release        = single_release,
1583 };
1584
1585 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1586 {
1587         struct device *dev = &host->pdev->dev;
1588
1589         host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1590         if (IS_ERR(host->debug_root)) {
1591                 dev_err(dev, "failed to create debugfs root\n");
1592                 return;
1593         }
1594
1595         host->debug_state = debugfs_create_file("state", 0444,
1596                                                 host->debug_root, host,
1597                                                 &s3cmci_fops_state);
1598
1599         if (IS_ERR(host->debug_state))
1600                 dev_err(dev, "failed to create debug state file\n");
1601
1602         host->debug_regs = debugfs_create_file("regs", 0444,
1603                                                host->debug_root, host,
1604                                                &s3cmci_fops_regs);
1605
1606         if (IS_ERR(host->debug_regs))
1607                 dev_err(dev, "failed to create debug regs file\n");
1608 }
1609
1610 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1611 {
1612         debugfs_remove(host->debug_regs);
1613         debugfs_remove(host->debug_state);
1614         debugfs_remove(host->debug_root);
1615 }
1616
1617 #else
1618 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1619 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1620
1621 #endif /* CONFIG_DEBUG_FS */
1622
1623 static int s3cmci_probe(struct platform_device *pdev)
1624 {
1625         struct s3cmci_host *host;
1626         struct mmc_host *mmc;
1627         int ret;
1628         int is2440;
1629         int i;
1630
1631         is2440 = platform_get_device_id(pdev)->driver_data;
1632
1633         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1634         if (!mmc) {
1635                 ret = -ENOMEM;
1636                 goto probe_out;
1637         }
1638
1639         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1640                 ret = gpio_request(i, dev_name(&pdev->dev));
1641                 if (ret) {
1642                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1643
1644                         for (i--; i >= S3C2410_GPE(5); i--)
1645                                 gpio_free(i);
1646
1647                         goto probe_free_host;
1648                 }
1649         }
1650
1651         host = mmc_priv(mmc);
1652         host->mmc       = mmc;
1653         host->pdev      = pdev;
1654         host->is2440    = is2440;
1655
1656         host->pdata = pdev->dev.platform_data;
1657         if (!host->pdata) {
1658                 pdev->dev.platform_data = &s3cmci_def_pdata;
1659                 host->pdata = &s3cmci_def_pdata;
1660         }
1661
1662         spin_lock_init(&host->complete_lock);
1663         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1664
1665         if (is2440) {
1666                 host->sdiimsk   = S3C2440_SDIIMSK;
1667                 host->sdidata   = S3C2440_SDIDATA;
1668                 host->clk_div   = 1;
1669         } else {
1670                 host->sdiimsk   = S3C2410_SDIIMSK;
1671                 host->sdidata   = S3C2410_SDIDATA;
1672                 host->clk_div   = 2;
1673         }
1674
1675         host->complete_what     = COMPLETION_NONE;
1676         host->pio_active        = XFER_NONE;
1677
1678 #ifdef CONFIG_MMC_S3C_PIODMA
1679         host->dodma             = host->pdata->use_dma;
1680 #endif
1681
1682         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1683         if (!host->mem) {
1684                 dev_err(&pdev->dev,
1685                         "failed to get io memory region resource.\n");
1686
1687                 ret = -ENOENT;
1688                 goto probe_free_gpio;
1689         }
1690
1691         host->mem = request_mem_region(host->mem->start,
1692                                        resource_size(host->mem), pdev->name);
1693
1694         if (!host->mem) {
1695                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1696                 ret = -ENOENT;
1697                 goto probe_free_gpio;
1698         }
1699
1700         host->base = ioremap(host->mem->start, resource_size(host->mem));
1701         if (!host->base) {
1702                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1703                 ret = -EINVAL;
1704                 goto probe_free_mem_region;
1705         }
1706
1707         host->irq = platform_get_irq(pdev, 0);
1708         if (host->irq == 0) {
1709                 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1710                 ret = -EINVAL;
1711                 goto probe_iounmap;
1712         }
1713
1714         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1715                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1716                 ret = -ENOENT;
1717                 goto probe_iounmap;
1718         }
1719
1720         /* We get spurious interrupts even when we have set the IMSK
1721          * register to ignore everything, so use disable_irq() to make
1722          * ensure we don't lock the system with un-serviceable requests. */
1723
1724         disable_irq(host->irq);
1725         host->irq_state = false;
1726
1727         if (!host->pdata->no_detect) {
1728                 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1729                 if (ret) {
1730                         dev_err(&pdev->dev, "failed to get detect gpio\n");
1731                         goto probe_free_irq;
1732                 }
1733
1734                 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1735
1736                 if (host->irq_cd >= 0) {
1737                         if (request_irq(host->irq_cd, s3cmci_irq_cd,
1738                                         IRQF_TRIGGER_RISING |
1739                                         IRQF_TRIGGER_FALLING,
1740                                         DRIVER_NAME, host)) {
1741                                 dev_err(&pdev->dev,
1742                                         "can't get card detect irq.\n");
1743                                 ret = -ENOENT;
1744                                 goto probe_free_gpio_cd;
1745                         }
1746                 } else {
1747                         dev_warn(&pdev->dev,
1748                                  "host detect has no irq available\n");
1749                         gpio_direction_input(host->pdata->gpio_detect);
1750                 }
1751         } else
1752                 host->irq_cd = -1;
1753
1754         if (!host->pdata->no_wprotect) {
1755                 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1756                 if (ret) {
1757                         dev_err(&pdev->dev, "failed to get writeprotect\n");
1758                         goto probe_free_irq_cd;
1759                 }
1760
1761                 gpio_direction_input(host->pdata->gpio_wprotect);
1762         }
1763
1764         /* depending on the dma state, get a dma channel to use. */
1765
1766         if (s3cmci_host_usedma(host)) {
1767                 host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
1768                                                 host);
1769                 if (host->dma < 0) {
1770                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1771                         if (!s3cmci_host_canpio()) {
1772                                 ret = -EBUSY;
1773                                 goto probe_free_gpio_wp;
1774                         } else {
1775                                 dev_warn(&pdev->dev, "falling back to PIO.\n");
1776                                 host->dodma = 0;
1777                         }
1778                 }
1779         }
1780
1781         host->clk = clk_get(&pdev->dev, "sdi");
1782         if (IS_ERR(host->clk)) {
1783                 dev_err(&pdev->dev, "failed to find clock source.\n");
1784                 ret = PTR_ERR(host->clk);
1785                 host->clk = NULL;
1786                 goto probe_free_dma;
1787         }
1788
1789         ret = clk_enable(host->clk);
1790         if (ret) {
1791                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1792                 goto clk_free;
1793         }
1794
1795         host->clk_rate = clk_get_rate(host->clk);
1796
1797         mmc->ops        = &s3cmci_ops;
1798         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1799 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1800         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1801 #else
1802         mmc->caps       = MMC_CAP_4_BIT_DATA;
1803 #endif
1804         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1805         mmc->f_max      = host->clk_rate / host->clk_div;
1806
1807         if (host->pdata->ocr_avail)
1808                 mmc->ocr_avail = host->pdata->ocr_avail;
1809
1810         mmc->max_blk_count      = 4095;
1811         mmc->max_blk_size       = 4095;
1812         mmc->max_req_size       = 4095 * 512;
1813         mmc->max_seg_size       = mmc->max_req_size;
1814
1815         mmc->max_segs           = 128;
1816
1817         dbg(host, dbg_debug,
1818             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1819             (host->is2440?"2440":""),
1820             host->base, host->irq, host->irq_cd, host->dma);
1821
1822         ret = s3cmci_cpufreq_register(host);
1823         if (ret) {
1824                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1825                 goto free_dmabuf;
1826         }
1827
1828         ret = mmc_add_host(mmc);
1829         if (ret) {
1830                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1831                 goto free_cpufreq;
1832         }
1833
1834         s3cmci_debugfs_attach(host);
1835
1836         platform_set_drvdata(pdev, mmc);
1837         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1838                  s3cmci_host_usedma(host) ? "dma" : "pio",
1839                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1840
1841         return 0;
1842
1843  free_cpufreq:
1844         s3cmci_cpufreq_deregister(host);
1845
1846  free_dmabuf:
1847         clk_disable(host->clk);
1848
1849  clk_free:
1850         clk_put(host->clk);
1851
1852  probe_free_dma:
1853         if (s3cmci_host_usedma(host))
1854                 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1855
1856  probe_free_gpio_wp:
1857         if (!host->pdata->no_wprotect)
1858                 gpio_free(host->pdata->gpio_wprotect);
1859
1860  probe_free_gpio_cd:
1861         if (!host->pdata->no_detect)
1862                 gpio_free(host->pdata->gpio_detect);
1863
1864  probe_free_irq_cd:
1865         if (host->irq_cd >= 0)
1866                 free_irq(host->irq_cd, host);
1867
1868  probe_free_irq:
1869         free_irq(host->irq, host);
1870
1871  probe_iounmap:
1872         iounmap(host->base);
1873
1874  probe_free_mem_region:
1875         release_mem_region(host->mem->start, resource_size(host->mem));
1876
1877  probe_free_gpio:
1878         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1879                 gpio_free(i);
1880
1881  probe_free_host:
1882         mmc_free_host(mmc);
1883
1884  probe_out:
1885         return ret;
1886 }
1887
1888 static void s3cmci_shutdown(struct platform_device *pdev)
1889 {
1890         struct mmc_host *mmc = platform_get_drvdata(pdev);
1891         struct s3cmci_host *host = mmc_priv(mmc);
1892
1893         if (host->irq_cd >= 0)
1894                 free_irq(host->irq_cd, host);
1895
1896         s3cmci_debugfs_remove(host);
1897         s3cmci_cpufreq_deregister(host);
1898         mmc_remove_host(mmc);
1899         clk_disable(host->clk);
1900 }
1901
1902 static int s3cmci_remove(struct platform_device *pdev)
1903 {
1904         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1905         struct s3cmci_host      *host = mmc_priv(mmc);
1906         struct s3c24xx_mci_pdata *pd = host->pdata;
1907         int i;
1908
1909         s3cmci_shutdown(pdev);
1910
1911         clk_put(host->clk);
1912
1913         tasklet_disable(&host->pio_tasklet);
1914
1915         if (s3cmci_host_usedma(host))
1916                 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1917
1918         free_irq(host->irq, host);
1919
1920         if (!pd->no_wprotect)
1921                 gpio_free(pd->gpio_wprotect);
1922
1923         if (!pd->no_detect)
1924                 gpio_free(pd->gpio_detect);
1925
1926         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1927                 gpio_free(i);
1928
1929
1930         iounmap(host->base);
1931         release_mem_region(host->mem->start, resource_size(host->mem));
1932
1933         mmc_free_host(mmc);
1934         return 0;
1935 }
1936
1937 static struct platform_device_id s3cmci_driver_ids[] = {
1938         {
1939                 .name   = "s3c2410-sdi",
1940                 .driver_data    = 0,
1941         }, {
1942                 .name   = "s3c2412-sdi",
1943                 .driver_data    = 1,
1944         }, {
1945                 .name   = "s3c2440-sdi",
1946                 .driver_data    = 1,
1947         },
1948         { }
1949 };
1950
1951 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1952
1953 static struct platform_driver s3cmci_driver = {
1954         .driver = {
1955                 .name   = "s3c-sdi",
1956                 .owner  = THIS_MODULE,
1957         },
1958         .id_table       = s3cmci_driver_ids,
1959         .probe          = s3cmci_probe,
1960         .remove         = s3cmci_remove,
1961         .shutdown       = s3cmci_shutdown,
1962 };
1963
1964 module_platform_driver(s3cmci_driver);
1965
1966 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1967 MODULE_LICENSE("GPL v2");
1968 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");