drivers/mmc/host/renesas_sdhi_core.c

   1 /*
   2  * Renesas SDHI
   3  *
   4  * Copyright (C) 2015-17 Renesas Electronics Corporation
   5  * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
   6  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   7  * Copyright (C) 2009 Magnus Damm
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * Based on "Compaq ASIC3 support":
  14  *
  15  * Copyright 2001 Compaq Computer Corporation.
  16  * Copyright 2004-2005 Phil Blundell
  17  * Copyright 2007-2008 OpenedHand Ltd.
  18  *
  19  * Authors: Phil Blundell <pb@handhelds.org>,
  20  *          Samuel Ortiz <sameo@openedhand.com>
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/of_device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mfd/tmio.h>
  32 #include <linux/sh_dma.h>
  33 #include <linux/delay.h>
  34 #include <linux/pinctrl/consumer.h>
  35 #include <linux/pinctrl/pinctrl-state.h>
  36 #include <linux/regulator/consumer.h>
  37
  38 #include "renesas_sdhi.h"
  39 #include "tmio_mmc.h"
  40
  41 #define EXT_ACC           0xe4
  42
  43 #define SDHI_VER_GEN2_SDR50     0x490c
  44 #define SDHI_VER_RZ_A1          0x820b
  45 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  46 #define SDHI_VER_GEN2_SDR104    0xcb0d
  47 #define SDHI_VER_GEN3_SD        0xcc10
  48 #define SDHI_VER_GEN3_SDMMC     0xcd10
  49
  50 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  51 {
  52         u32 val;
  53
  54         /*
  55          * see also
  56          *      renesas_sdhi_of_data :: dma_buswidth
  57          */
  58         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  59         case SDHI_VER_GEN2_SDR50:
  60                 val = (width == 32) ? 0x0001 : 0x0000;
  61                 break;
  62         case SDHI_VER_GEN2_SDR104:
  63                 val = (width == 32) ? 0x0000 : 0x0001;
  64                 break;
  65         case SDHI_VER_GEN3_SD:
  66         case SDHI_VER_GEN3_SDMMC:
  67                 if (width == 64)
  68                         val = 0x0000;
  69                 else if (width == 32)
  70                         val = 0x0101;
  71                 else
  72                         val = 0x0001;
  73                 break;
  74         default:
  75                 /* nothing to do */
  76                 return;
  77         }
  78
  79         sd_ctrl_write16(host, EXT_ACC, val);
  80 }
  81
  82 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  83 {
  84         struct mmc_host *mmc = host->mmc;
  85         struct renesas_sdhi *priv = host_to_priv(host);
  86         int ret = clk_prepare_enable(priv->clk);
  87
  88         if (ret < 0)
  89                 return ret;
  90
  91         ret = clk_prepare_enable(priv->clk_cd);
  92         if (ret < 0) {
  93                 clk_disable_unprepare(priv->clk);
  94                 return ret;
  95         }
  96
  97         /*
  98          * The clock driver may not know what maximum frequency
  99          * actually works, so it should be set with the max-frequency
 100          * property which will already have been read to f_max.  If it
 101          * was missing, assume the current frequency is the maximum.
 102          */
 103         if (!mmc->f_max)
 104                 mmc->f_max = clk_get_rate(priv->clk);
 105
 106         /*
 107          * Minimum frequency is the minimum input clock frequency
 108          * divided by our maximum divider.
 109          */
 110         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 111
 112         /* enable 16bit data access on SDBUF as default */
 113         renesas_sdhi_sdbuf_width(host, 16);
 114
 115         return 0;
 116 }
 117
 118 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 119                                             unsigned int new_clock)
 120 {
 121         struct renesas_sdhi *priv = host_to_priv(host);
 122         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 123         int i, ret;
 124
 125         /* tested only on R-Car Gen2+ currently; may work for others */
 126         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 127                 return clk_get_rate(priv->clk);
 128
 129         /*
 130          * We want the bus clock to be as close as possible to, but no
 131          * greater than, new_clock.  As we can divide by 1 << i for
 132          * any i in [0, 9] we want the input clock to be as close as
 133          * possible, but no greater than, new_clock << i.
 134          */
 135         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 136                 freq = clk_round_rate(priv->clk, new_clock << i);
 137                 if (freq > (new_clock << i)) {
 138                         /* Too fast; look for a slightly slower option */
 139                         freq = clk_round_rate(priv->clk,
 140                                               (new_clock << i) / 4 * 3);
 141                         if (freq > (new_clock << i))
 142                                 continue;
 143                 }
 144
 145                 diff = new_clock - (freq >> i);
 146                 if (diff <= diff_min) {
 147                         best_freq = freq;
 148                         diff_min = diff;
 149                 }
 150         }
 151
 152         ret = clk_set_rate(priv->clk, best_freq);
 153
 154         return ret == 0 ? best_freq : clk_get_rate(priv->clk);
 155 }
 156
 157 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 158 {
 159         struct renesas_sdhi *priv = host_to_priv(host);
 160
 161         clk_disable_unprepare(priv->clk);
 162         clk_disable_unprepare(priv->clk_cd);
 163 }
 164
 165 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 166 {
 167         struct tmio_mmc_host *host = mmc_priv(mmc);
 168
 169         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 170                  TMIO_STAT_DAT0);
 171 }
 172
 173 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 174                                                     struct mmc_ios *ios)
 175 {
 176         struct tmio_mmc_host *host = mmc_priv(mmc);
 177         struct renesas_sdhi *priv = host_to_priv(host);
 178         struct pinctrl_state *pin_state;
 179         int ret;
 180
 181         switch (ios->signal_voltage) {
 182         case MMC_SIGNAL_VOLTAGE_330:
 183                 pin_state = priv->pins_default;
 184                 break;
 185         case MMC_SIGNAL_VOLTAGE_180:
 186                 pin_state = priv->pins_uhs;
 187                 break;
 188         default:
 189                 return -EINVAL;
 190         }
 191
 192         /*
 193          * If anything is missing, assume signal voltage is fixed at
 194          * 3.3V and succeed/fail accordingly.
 195          */
 196         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 197                 return ios->signal_voltage ==
 198                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 199
 200         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 201         if (ret)
 202                 return ret;
 203
 204         return pinctrl_select_state(priv->pinctrl, pin_state);
 205 }
 206
 207 /* SCC registers */
 208 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 209 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 210 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 211 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 212 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 213 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 214
 215 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
 216 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 217 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 218 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 219
 220 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
 221 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 222 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
 223 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 224 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
 225 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 226
 227 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 228                                 struct renesas_sdhi *priv, int addr)
 229 {
 230         return readl(priv->scc_ctl + (addr << host->bus_shift));
 231 }
 232
 233 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 234                                   struct renesas_sdhi *priv,
 235                                   int addr, u32 val)
 236 {
 237         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 238 }
 239
 240 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 241 {
 242         struct renesas_sdhi *priv;
 243
 244         priv = host_to_priv(host);
 245
 246         /* set sampling clock selection range */
 247         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 248                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 249
 250         /* Initialize SCC */
 251         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 252
 253         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 254                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 255                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
 256
 257         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 258                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 259
 260         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 261                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 262                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 263
 264         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 265                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 266
 267         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 268                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 269                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 270
 271         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 272
 273         /* Read TAPNUM */
 274         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 275                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 276                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 277 }
 278
 279 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
 280                                         unsigned long tap)
 281 {
 282         struct renesas_sdhi *priv = host_to_priv(host);
 283
 284         /* Set sampling clock position */
 285         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
 286 }
 287
 288 #define SH_MOBILE_SDHI_MAX_TAP 3
 289
 290 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 291 {
 292         struct renesas_sdhi *priv = host_to_priv(host);
 293         unsigned long tap_cnt;  /* counter of tuning success */
 294         unsigned long tap_set;  /* tap position */
 295         unsigned long tap_start;/* start position of tuning success */
 296         unsigned long tap_end;  /* end position of tuning success */
 297         unsigned long ntap;     /* temporary counter of tuning success */
 298         unsigned long i;
 299
 300         /* Clear SCC_RVSREQ */
 301         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 302
 303         /*
 304          * Find the longest consecutive run of successful probes.  If that
 305          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 306          * center index as the tap.
 307          */
 308         tap_cnt = 0;
 309         ntap = 0;
 310         tap_start = 0;
 311         tap_end = 0;
 312         for (i = 0; i < host->tap_num * 2; i++) {
 313                 if (test_bit(i, host->taps)) {
 314                         ntap++;
 315                 } else {
 316                         if (ntap > tap_cnt) {
 317                                 tap_start = i - ntap;
 318                                 tap_end = i - 1;
 319                                 tap_cnt = ntap;
 320                         }
 321                         ntap = 0;
 322                 }
 323         }
 324
 325         if (ntap > tap_cnt) {
 326                 tap_start = i - ntap;
 327                 tap_end = i - 1;
 328                 tap_cnt = ntap;
 329         }
 330
 331         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 332                 tap_set = (tap_start + tap_end) / 2 % host->tap_num;
 333         else
 334                 return -EIO;
 335
 336         /* Set SCC */
 337         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
 338
 339         /* Enable auto re-tuning */
 340         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 341                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 342                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 343
 344         return 0;
 345 }
 346
 347 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 348 {
 349         struct renesas_sdhi *priv = host_to_priv(host);
 350
 351         /* Check SCC error */
 352         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 353             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
 354             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 355             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 356                 /* Clear SCC error */
 357                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 358                 return true;
 359         }
 360
 361         return false;
 362 }
 363
 364 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
 365 {
 366         struct renesas_sdhi *priv;
 367
 368         priv = host_to_priv(host);
 369
 370         /* Reset SCC */
 371         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 372                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 373
 374         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 375                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 376                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 377
 378         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 379                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 380
 381         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 382                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 383                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 384
 385         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 386                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 387                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 388 }
 389
 390 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 391 {
 392         int timeout = 1000;
 393         /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 394         u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 395
 396         while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 397                               & bit) == wait_state)
 398                 udelay(1);
 399
 400         if (!timeout) {
 401                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 402                 return -EBUSY;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 409 {
 410         u32 bit = TMIO_STAT_SCLKDIVEN;
 411
 412         switch (addr) {
 413         case CTL_SD_CMD:
 414         case CTL_STOP_INTERNAL_ACTION:
 415         case CTL_XFER_BLK_COUNT:
 416         case CTL_SD_XFER_LEN:
 417         case CTL_SD_MEM_CARD_OPT:
 418         case CTL_TRANSACTION_CTL:
 419         case CTL_DMA_ENABLE:
 420         case EXT_ACC:
 421                 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 422                         bit = TMIO_STAT_CMD_BUSY;
 423                 /* fallthrough */
 424         case CTL_SD_CARD_CLK_CTL:
 425                 return renesas_sdhi_wait_idle(host, bit);
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 432                                        unsigned int direction, int blk_size)
 433 {
 434         /*
 435          * In Renesas controllers, when performing a
 436          * multiple block read of one or two blocks,
 437          * depending on the timing with which the
 438          * response register is read, the response
 439          * value may not be read properly.
 440          * Use single block read for this HW bug
 441          */
 442         if ((direction == MMC_DATA_READ) &&
 443             blk_size == 2)
 444                 return 1;
 445
 446         return blk_size;
 447 }
 448
 449 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 450 {
 451         /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 452         int width = (host->bus_shift == 2) ? 64 : 32;
 453
 454         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 455         renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 456 }
 457
 458 int renesas_sdhi_probe(struct platform_device *pdev,
 459                        const struct tmio_mmc_dma_ops *dma_ops)
 460 {
 461         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 462         const struct renesas_sdhi_of_data *of_data;
 463         struct tmio_mmc_data *mmc_data;
 464         struct tmio_mmc_dma *dma_priv;
 465         struct tmio_mmc_host *host;
 466         struct renesas_sdhi *priv;
 467         struct resource *res;
 468         int irq, ret, i;
 469
 470         of_data = of_device_get_match_data(&pdev->dev);
 471
 472         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 473         if (!res)
 474                 return -EINVAL;
 475
 476         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 477                             GFP_KERNEL);
 478         if (!priv)
 479                 return -ENOMEM;
 480
 481         mmc_data = &priv->mmc_data;
 482         dma_priv = &priv->dma_priv;
 483
 484         priv->clk = devm_clk_get(&pdev->dev, NULL);
 485         if (IS_ERR(priv->clk)) {
 486                 ret = PTR_ERR(priv->clk);
 487                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 488                 return ret;
 489         }
 490
 491         /*
 492          * Some controllers provide a 2nd clock just to run the internal card
 493          * detection logic. Unfortunately, the existing driver architecture does
 494          * not support a separation of clocks for runtime PM usage. When
 495          * native hotplug is used, the tmio driver assumes that the core
 496          * must continue to run for card detect to stay active, so we cannot
 497          * disable it.
 498          * Additionally, it is prohibited to supply a clock to the core but not
 499          * to the card detect circuit. That leaves us with if separate clocks
 500          * are presented, we must treat them both as virtually 1 clock.
 501          */
 502         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 503         if (IS_ERR(priv->clk_cd))
 504                 priv->clk_cd = NULL;
 505
 506         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 507         if (!IS_ERR(priv->pinctrl)) {
 508                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 509                                                 PINCTRL_STATE_DEFAULT);
 510                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 511                                                 "state_uhs");
 512         }
 513
 514         host = tmio_mmc_host_alloc(pdev, mmc_data);
 515         if (IS_ERR(host))
 516                 return PTR_ERR(host);
 517
 518         if (of_data) {
 519                 mmc_data->flags |= of_data->tmio_flags;
 520                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 521                 mmc_data->capabilities |= of_data->capabilities;
 522                 mmc_data->capabilities2 |= of_data->capabilities2;
 523                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 524                 mmc_data->max_blk_count = of_data->max_blk_count;
 525                 mmc_data->max_segs = of_data->max_segs;
 526                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 527                 host->bus_shift = of_data->bus_shift;
 528         }
 529
 530         host->write16_hook      = renesas_sdhi_write16_hook;
 531         host->clk_enable        = renesas_sdhi_clk_enable;
 532         host->clk_update        = renesas_sdhi_clk_update;
 533         host->clk_disable       = renesas_sdhi_clk_disable;
 534         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 535         host->dma_ops           = dma_ops;
 536
 537         /* SDR speeds are only available on Gen2+ */
 538         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 539                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 540                 host->ops.card_busy = renesas_sdhi_card_busy;
 541                 host->ops.start_signal_voltage_switch =
 542                         renesas_sdhi_start_signal_voltage_switch;
 543         }
 544
 545         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 546         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 547                 host->bus_shift = 1;
 548
 549         if (mmd)
 550                 *mmc_data = *mmd;
 551
 552         dma_priv->filter = shdma_chan_filter;
 553         dma_priv->enable = renesas_sdhi_enable_dma;
 554
 555         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 556         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 557
 558         /*
 559          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 560          * bus width mode.
 561          */
 562         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 563
 564         /*
 565          * All SDHI blocks support SDIO IRQ signalling.
 566          */
 567         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 568
 569         /* All SDHI have CMD12 control bit */
 570         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 571
 572         /* All SDHI have SDIO status bits which must be 1 */
 573         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 574
 575         ret = renesas_sdhi_clk_enable(host);
 576         if (ret)
 577                 goto efree;
 578
 579         ret = tmio_mmc_host_probe(host);
 580         if (ret < 0)
 581                 goto edisclk;
 582
 583         /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
 584         if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50)
 585                 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
 586
 587         /* Enable tuning iff we have an SCC and a supported mode */
 588         if (of_data && of_data->scc_offset &&
 589             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 590              host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) {
 591                 const struct renesas_sdhi_scc *taps = of_data->taps;
 592                 bool hit = false;
 593
 594                 host->mmc->caps |= MMC_CAP_HW_RESET;
 595
 596                 for (i = 0; i < of_data->taps_num; i++) {
 597                         if (taps[i].clk_rate == 0 ||
 598                             taps[i].clk_rate == host->mmc->f_max) {
 599                                 priv->scc_tappos = taps->tap;
 600                                 hit = true;
 601                                 break;
 602                         }
 603                 }
 604
 605                 if (!hit)
 606                         dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
 607
 608                 priv->scc_ctl = host->ctl + of_data->scc_offset;
 609                 host->init_tuning = renesas_sdhi_init_tuning;
 610                 host->prepare_tuning = renesas_sdhi_prepare_tuning;
 611                 host->select_tuning = renesas_sdhi_select_tuning;
 612                 host->check_scc_error = renesas_sdhi_check_scc_error;
 613                 host->hw_reset = renesas_sdhi_hw_reset;
 614         }
 615
 616         i = 0;
 617         while (1) {
 618                 irq = platform_get_irq(pdev, i);
 619                 if (irq < 0)
 620                         break;
 621                 i++;
 622                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 623                                        dev_name(&pdev->dev), host);
 624                 if (ret)
 625                         goto eirq;
 626         }
 627
 628         /* There must be at least one IRQ source */
 629         if (!i) {
 630                 ret = irq;
 631                 goto eirq;
 632         }
 633
 634         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 635                  mmc_hostname(host->mmc), (unsigned long)
 636                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 637                  host->mmc->f_max / 1000000);
 638
 639         return ret;
 640
 641 eirq:
 642         tmio_mmc_host_remove(host);
 643 edisclk:
 644         renesas_sdhi_clk_disable(host);
 645 efree:
 646         tmio_mmc_host_free(host);
 647
 648         return ret;
 649 }
 650 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
 651
 652 int renesas_sdhi_remove(struct platform_device *pdev)
 653 {
 654         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
 655
 656         tmio_mmc_host_remove(host);
 657         renesas_sdhi_clk_disable(host);
 658
 659         return 0;
 660 }
 661 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
 662
 663 MODULE_LICENSE("GPL v2");