Merge branch 'msm-mmc_sdcc' of git://codeaurora.org/quic/kernel/dwalker/linux-msm
[sfrench/cifs-2.6.git] / drivers / mmc / host / msm_sdcc.c
1 /*
2  *  linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
3  *
4  *  Copyright (C) 2007 Google Inc,
5  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6  *  Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * Based on mmci.c
13  *
14  * Author: San Mehat (san@android.com)
15  *
16  */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/highmem.h>
27 #include <linux/log2.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/mmc/sdio.h>
31 #include <linux/clk.h>
32 #include <linux/scatterlist.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/debugfs.h>
36 #include <linux/io.h>
37 #include <linux/memory.h>
38 #include <linux/gfp.h>
39
40 #include <asm/cacheflush.h>
41 #include <asm/div64.h>
42 #include <asm/sizes.h>
43
44 #include <mach/mmc.h>
45 #include <mach/msm_iomap.h>
46 #include <mach/dma.h>
47
48 #include "msm_sdcc.h"
49
50 #define DRIVER_NAME "msm-sdcc"
51
52 #define BUSCLK_PWRSAVE 1
53 #define BUSCLK_TIMEOUT (HZ)
54 static unsigned int msmsdcc_fmin = 144000;
55 static unsigned int msmsdcc_fmax = 50000000;
56 static unsigned int msmsdcc_4bit = 1;
57 static unsigned int msmsdcc_pwrsave = 1;
58 static unsigned int msmsdcc_piopoll = 1;
59 static unsigned int msmsdcc_sdioirq;
60
61 #define PIO_SPINMAX 30
62 #define CMD_SPINMAX 20
63
64
65 static inline void
66 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
67 {
68         WARN_ON(!host->clks_on);
69
70         BUG_ON(host->curr.mrq);
71
72         if (deferr) {
73                 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
74         } else {
75                 del_timer_sync(&host->busclk_timer);
76                 /* Need to check clks_on again in case the busclk
77                  * timer fired
78                  */
79                 if (host->clks_on) {
80                         clk_disable(host->clk);
81                         clk_disable(host->pclk);
82                         host->clks_on = 0;
83                 }
84         }
85 }
86
87 static inline int
88 msmsdcc_enable_clocks(struct msmsdcc_host *host)
89 {
90         int rc;
91
92         del_timer_sync(&host->busclk_timer);
93
94         if (!host->clks_on) {
95                 rc = clk_enable(host->pclk);
96                 if (rc)
97                         return rc;
98                 rc = clk_enable(host->clk);
99                 if (rc) {
100                         clk_disable(host->pclk);
101                         return rc;
102                 }
103                 udelay(1 + ((3 * USEC_PER_SEC) /
104                        (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
105                 host->clks_on = 1;
106         }
107         return 0;
108 }
109
110 static inline unsigned int
111 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
112 {
113         return readl(host->base + reg);
114 }
115
116 static inline void
117 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
118 {
119         writel(data, host->base + reg);
120         /* 3 clk delay required! */
121         udelay(1 + ((3 * USEC_PER_SEC) /
122                (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
123 }
124
125 static void
126 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
127                       u32 c);
128
129 static void
130 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
131 {
132         BUG_ON(host->curr.data);
133
134         host->curr.mrq = NULL;
135         host->curr.cmd = NULL;
136
137         if (mrq->data)
138                 mrq->data->bytes_xfered = host->curr.data_xfered;
139         if (mrq->cmd->error == -ETIMEDOUT)
140                 mdelay(5);
141
142 #if BUSCLK_PWRSAVE
143         msmsdcc_disable_clocks(host, 1);
144 #endif
145         /*
146          * Need to drop the host lock here; mmc_request_done may call
147          * back into the driver...
148          */
149         spin_unlock(&host->lock);
150         mmc_request_done(host->mmc, mrq);
151         spin_lock(&host->lock);
152 }
153
154 static void
155 msmsdcc_stop_data(struct msmsdcc_host *host)
156 {
157         host->curr.data = NULL;
158         host->curr.got_dataend = host->curr.got_datablkend = 0;
159 }
160
161 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
162 {
163         switch (host->pdev_id) {
164         case 1:
165                 return MSM_SDC1_PHYS + MMCIFIFO;
166         case 2:
167                 return MSM_SDC2_PHYS + MMCIFIFO;
168         case 3:
169                 return MSM_SDC3_PHYS + MMCIFIFO;
170         case 4:
171                 return MSM_SDC4_PHYS + MMCIFIFO;
172         }
173         BUG();
174         return 0;
175 }
176
177 static inline void
178 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
179        msmsdcc_writel(host, arg, MMCIARGUMENT);
180        msmsdcc_writel(host, c, MMCICOMMAND);
181 }
182
183 static void
184 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
185 {
186         struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
187
188         msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
189         msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
190                        MMCIDATALENGTH);
191         msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
192         msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
193
194         if (host->cmd_cmd) {
195                 msmsdcc_start_command_exec(host,
196                                            (u32) host->cmd_cmd->arg,
197                                            (u32) host->cmd_c);
198         }
199         host->dma.active = 1;
200 }
201
202 static void
203 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
204                           unsigned int result,
205                           struct msm_dmov_errdata *err)
206 {
207         struct msmsdcc_dma_data *dma_data =
208                 container_of(cmd, struct msmsdcc_dma_data, hdr);
209         struct msmsdcc_host     *host = dma_data->host;
210         unsigned long           flags;
211         struct mmc_request      *mrq;
212
213         spin_lock_irqsave(&host->lock, flags);
214         host->dma.active = 0;
215
216         mrq = host->curr.mrq;
217         BUG_ON(!mrq);
218         WARN_ON(!mrq->data);
219
220         if (!(result & DMOV_RSLT_VALID)) {
221                 pr_err("msmsdcc: Invalid DataMover result\n");
222                 goto out;
223         }
224
225         if (result & DMOV_RSLT_DONE) {
226                 host->curr.data_xfered = host->curr.xfer_size;
227         } else {
228                 /* Error or flush  */
229                 if (result & DMOV_RSLT_ERROR)
230                         pr_err("%s: DMA error (0x%.8x)\n",
231                                mmc_hostname(host->mmc), result);
232                 if (result & DMOV_RSLT_FLUSH)
233                         pr_err("%s: DMA channel flushed (0x%.8x)\n",
234                                mmc_hostname(host->mmc), result);
235                 if (err)
236                         pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
237                                err->flush[0], err->flush[1], err->flush[2],
238                                err->flush[3], err->flush[4], err->flush[5]);
239                 if (!mrq->data->error)
240                         mrq->data->error = -EIO;
241         }
242         dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
243                      host->dma.dir);
244
245         if (host->curr.user_pages) {
246                 struct scatterlist *sg = host->dma.sg;
247                 int i;
248
249                 for (i = 0; i < host->dma.num_ents; i++)
250                         flush_dcache_page(sg_page(sg++));
251         }
252
253         host->dma.sg = NULL;
254         host->dma.busy = 0;
255
256         if ((host->curr.got_dataend && host->curr.got_datablkend)
257              || mrq->data->error) {
258
259                 /*
260                  * If we've already gotten our DATAEND / DATABLKEND
261                  * for this request, then complete it through here.
262                  */
263                 msmsdcc_stop_data(host);
264
265                 if (!mrq->data->error)
266                         host->curr.data_xfered = host->curr.xfer_size;
267                 if (!mrq->data->stop || mrq->cmd->error) {
268                         host->curr.mrq = NULL;
269                         host->curr.cmd = NULL;
270                         mrq->data->bytes_xfered = host->curr.data_xfered;
271
272                         spin_unlock_irqrestore(&host->lock, flags);
273 #if BUSCLK_PWRSAVE
274                         msmsdcc_disable_clocks(host, 1);
275 #endif
276                         mmc_request_done(host->mmc, mrq);
277                         return;
278                 } else
279                         msmsdcc_start_command(host, mrq->data->stop, 0);
280         }
281
282 out:
283         spin_unlock_irqrestore(&host->lock, flags);
284         return;
285 }
286
287 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
288 {
289         if (host->dma.channel == -1)
290                 return -ENOENT;
291
292         if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
293                 return -EINVAL;
294         if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
295                 return -EINVAL;
296         return 0;
297 }
298
299 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
300 {
301         struct msmsdcc_nc_dmadata *nc;
302         dmov_box *box;
303         uint32_t rows;
304         uint32_t crci;
305         unsigned int n;
306         int i, rc;
307         struct scatterlist *sg = data->sg;
308
309         rc = validate_dma(host, data);
310         if (rc)
311                 return rc;
312
313         host->dma.sg = data->sg;
314         host->dma.num_ents = data->sg_len;
315
316        BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
317
318         nc = host->dma.nc;
319
320         switch (host->pdev_id) {
321         case 1:
322                 crci = MSMSDCC_CRCI_SDC1;
323                 break;
324         case 2:
325                 crci = MSMSDCC_CRCI_SDC2;
326                 break;
327         case 3:
328                 crci = MSMSDCC_CRCI_SDC3;
329                 break;
330         case 4:
331                 crci = MSMSDCC_CRCI_SDC4;
332                 break;
333         default:
334                 host->dma.sg = NULL;
335                 host->dma.num_ents = 0;
336                 return -ENOENT;
337         }
338
339         if (data->flags & MMC_DATA_READ)
340                 host->dma.dir = DMA_FROM_DEVICE;
341         else
342                 host->dma.dir = DMA_TO_DEVICE;
343
344         host->curr.user_pages = 0;
345
346         box = &nc->cmd[0];
347         for (i = 0; i < host->dma.num_ents; i++) {
348                 box->cmd = CMD_MODE_BOX;
349
350         /* Initialize sg dma address */
351         sg->dma_address = page_to_dma(mmc_dev(host->mmc), sg_page(sg))
352                                 + sg->offset;
353
354         if (i == (host->dma.num_ents - 1))
355                         box->cmd |= CMD_LC;
356                 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
357                         (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
358                         (sg_dma_len(sg) / MCI_FIFOSIZE) ;
359
360                 if (data->flags & MMC_DATA_READ) {
361                         box->src_row_addr = msmsdcc_fifo_addr(host);
362                         box->dst_row_addr = sg_dma_address(sg);
363
364                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
365                                            (MCI_FIFOSIZE);
366                         box->row_offset = MCI_FIFOSIZE;
367
368                         box->num_rows = rows * ((1 << 16) + 1);
369                         box->cmd |= CMD_SRC_CRCI(crci);
370                 } else {
371                         box->src_row_addr = sg_dma_address(sg);
372                         box->dst_row_addr = msmsdcc_fifo_addr(host);
373
374                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
375                                            (MCI_FIFOSIZE);
376                         box->row_offset = (MCI_FIFOSIZE << 16);
377
378                         box->num_rows = rows * ((1 << 16) + 1);
379                         box->cmd |= CMD_DST_CRCI(crci);
380                 }
381                 box++;
382                 sg++;
383         }
384
385         /* location of command block must be 64 bit aligned */
386         BUG_ON(host->dma.cmd_busaddr & 0x07);
387
388         nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
389         host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
390                                DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
391         host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
392
393         n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
394                         host->dma.num_ents, host->dma.dir);
395 /* dsb inside dma_map_sg will write nc out to mem as well */
396
397         if (n != host->dma.num_ents) {
398                 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
399                         mmc_hostname(host->mmc));
400                 host->dma.sg = NULL;
401                 host->dma.num_ents = 0;
402                 return -ENOMEM;
403         }
404
405         return 0;
406 }
407
408 static int
409 snoop_cccr_abort(struct mmc_command *cmd)
410 {
411         if ((cmd->opcode == 52) &&
412             (cmd->arg & 0x80000000) &&
413             (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
414                 return 1;
415         return 0;
416 }
417
418 static void
419 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
420                                 struct mmc_command *cmd, u32 *c)
421 {
422         *c |= (cmd->opcode | MCI_CPSM_ENABLE);
423
424         if (cmd->flags & MMC_RSP_PRESENT) {
425                 if (cmd->flags & MMC_RSP_136)
426                         *c |= MCI_CPSM_LONGRSP;
427                 *c |= MCI_CPSM_RESPONSE;
428         }
429
430         if (/*interrupt*/0)
431                 *c |= MCI_CPSM_INTERRUPT;
432
433         if ((((cmd->opcode == 17) || (cmd->opcode == 18))  ||
434              ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
435               (cmd->opcode == 53))
436                 *c |= MCI_CSPM_DATCMD;
437
438         if (cmd == cmd->mrq->stop)
439                 *c |= MCI_CSPM_MCIABORT;
440
441         if (snoop_cccr_abort(cmd))
442                 *c |= MCI_CSPM_MCIABORT;
443
444         if (host->curr.cmd != NULL) {
445                 printk(KERN_ERR "%s: Overlapping command requests\n",
446                         mmc_hostname(host->mmc));
447         }
448         host->curr.cmd = cmd;
449 }
450
451 static void
452 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
453                         struct mmc_command *cmd, u32 c)
454 {
455         unsigned int datactrl, timeout;
456         unsigned long long clks;
457         unsigned int pio_irqmask = 0;
458
459         host->curr.data = data;
460         host->curr.xfer_size = data->blksz * data->blocks;
461         host->curr.xfer_remain = host->curr.xfer_size;
462         host->curr.data_xfered = 0;
463         host->curr.got_dataend = 0;
464         host->curr.got_datablkend = 0;
465
466         memset(&host->pio, 0, sizeof(host->pio));
467
468         datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
469
470         if (!msmsdcc_config_dma(host, data))
471                 datactrl |= MCI_DPSM_DMAENABLE;
472         else {
473                 host->pio.sg = data->sg;
474                 host->pio.sg_len = data->sg_len;
475                 host->pio.sg_off = 0;
476
477                 if (data->flags & MMC_DATA_READ) {
478                         pio_irqmask = MCI_RXFIFOHALFFULLMASK;
479                         if (host->curr.xfer_remain < MCI_FIFOSIZE)
480                                 pio_irqmask |= MCI_RXDATAAVLBLMASK;
481                 } else
482                         pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
483         }
484
485         if (data->flags & MMC_DATA_READ)
486                 datactrl |= MCI_DPSM_DIRECTION;
487
488         clks = (unsigned long long)data->timeout_ns * host->clk_rate;
489         do_div(clks, NSEC_PER_SEC);
490         timeout = data->timeout_clks + (unsigned int)clks*2 ;
491
492         if (datactrl & MCI_DPSM_DMAENABLE) {
493                 /* Save parameters for the exec function */
494                 host->cmd_timeout = timeout;
495                 host->cmd_pio_irqmask = pio_irqmask;
496                 host->cmd_datactrl = datactrl;
497                 host->cmd_cmd = cmd;
498
499                 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
500                 host->dma.hdr.data = (void *)host;
501                 host->dma.busy = 1;
502
503                 if (cmd) {
504                         msmsdcc_start_command_deferred(host, cmd, &c);
505                         host->cmd_c = c;
506                 }
507                 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
508         } else {
509                 msmsdcc_writel(host, timeout, MMCIDATATIMER);
510
511                 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
512
513                 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
514                 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
515
516                 if (cmd) {
517                         /* Daisy-chain the command if requested */
518                         msmsdcc_start_command(host, cmd, c);
519                 }
520         }
521 }
522
523 static void
524 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
525 {
526         if (cmd == cmd->mrq->stop)
527                 c |= MCI_CSPM_MCIABORT;
528
529         host->stats.cmds++;
530
531         msmsdcc_start_command_deferred(host, cmd, &c);
532         msmsdcc_start_command_exec(host, cmd->arg, c);
533 }
534
535 static void
536 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
537                  unsigned int status)
538 {
539         if (status & MCI_DATACRCFAIL) {
540                 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
541                 pr_err("%s: opcode 0x%.8x\n", __func__,
542                        data->mrq->cmd->opcode);
543                 pr_err("%s: blksz %d, blocks %d\n", __func__,
544                        data->blksz, data->blocks);
545                 data->error = -EILSEQ;
546         } else if (status & MCI_DATATIMEOUT) {
547                 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
548                 data->error = -ETIMEDOUT;
549         } else if (status & MCI_RXOVERRUN) {
550                 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
551                 data->error = -EIO;
552         } else if (status & MCI_TXUNDERRUN) {
553                 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
554                 data->error = -EIO;
555         } else {
556                 pr_err("%s: Unknown error (0x%.8x)\n",
557                        mmc_hostname(host->mmc), status);
558                 data->error = -EIO;
559         }
560 }
561
562
563 static int
564 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
565 {
566         uint32_t        *ptr = (uint32_t *) buffer;
567         int             count = 0;
568
569         while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
570                 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
571                 ptr++;
572                 count += sizeof(uint32_t);
573
574                 remain -=  sizeof(uint32_t);
575                 if (remain == 0)
576                         break;
577         }
578         return count;
579 }
580
581 static int
582 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
583                   unsigned int remain, u32 status)
584 {
585         void __iomem *base = host->base;
586         char *ptr = buffer;
587
588         do {
589                 unsigned int count, maxcnt;
590
591                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
592                                                     MCI_FIFOHALFSIZE;
593                 count = min(remain, maxcnt);
594
595                 writesl(base + MMCIFIFO, ptr, count >> 2);
596                 ptr += count;
597                 remain -= count;
598
599                 if (remain == 0)
600                         break;
601
602                 status = msmsdcc_readl(host, MMCISTATUS);
603         } while (status & MCI_TXFIFOHALFEMPTY);
604
605         return ptr - buffer;
606 }
607
608 static int
609 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
610 {
611         while (maxspin) {
612                 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
613                         return 0;
614                 udelay(1);
615                 --maxspin;
616         }
617         return -ETIMEDOUT;
618 }
619
620 static irqreturn_t
621 msmsdcc_pio_irq(int irq, void *dev_id)
622 {
623         struct msmsdcc_host     *host = dev_id;
624         uint32_t                status;
625
626         status = msmsdcc_readl(host, MMCISTATUS);
627
628         do {
629                 unsigned long flags;
630                 unsigned int remain, len;
631                 char *buffer;
632
633                 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
634                         if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
635                                 break;
636
637                         if (msmsdcc_spin_on_status(host,
638                                                    (MCI_TXFIFOHALFEMPTY |
639                                                    MCI_RXDATAAVLBL),
640                                                    PIO_SPINMAX)) {
641                                 break;
642                         }
643                 }
644
645                 /* Map the current scatter buffer */
646                 local_irq_save(flags);
647                 buffer = kmap_atomic(sg_page(host->pio.sg),
648                                      KM_BIO_SRC_IRQ) + host->pio.sg->offset;
649                 buffer += host->pio.sg_off;
650                 remain = host->pio.sg->length - host->pio.sg_off;
651                 len = 0;
652                 if (status & MCI_RXACTIVE)
653                         len = msmsdcc_pio_read(host, buffer, remain);
654                 if (status & MCI_TXACTIVE)
655                         len = msmsdcc_pio_write(host, buffer, remain, status);
656
657                 /* Unmap the buffer */
658                 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
659                 local_irq_restore(flags);
660
661                 host->pio.sg_off += len;
662                 host->curr.xfer_remain -= len;
663                 host->curr.data_xfered += len;
664                 remain -= len;
665
666                 if (remain == 0) {
667                         /* This sg page is full - do some housekeeping */
668                         if (status & MCI_RXACTIVE && host->curr.user_pages)
669                                 flush_dcache_page(sg_page(host->pio.sg));
670
671                         if (!--host->pio.sg_len) {
672                                 memset(&host->pio, 0, sizeof(host->pio));
673                                 break;
674                         }
675
676                         /* Advance to next sg */
677                         host->pio.sg++;
678                         host->pio.sg_off = 0;
679                 }
680
681                 status = msmsdcc_readl(host, MMCISTATUS);
682         } while (1);
683
684         if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
685                 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
686
687         if (!host->curr.xfer_remain)
688                 msmsdcc_writel(host, 0, MMCIMASK1);
689
690         return IRQ_HANDLED;
691 }
692
693 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
694 {
695         struct mmc_command *cmd = host->curr.cmd;
696
697         host->curr.cmd = NULL;
698         cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
699         cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
700         cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
701         cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
702
703         if (status & MCI_CMDTIMEOUT) {
704                 cmd->error = -ETIMEDOUT;
705         } else if (status & MCI_CMDCRCFAIL &&
706                    cmd->flags & MMC_RSP_CRC) {
707                 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
708                 cmd->error = -EILSEQ;
709         }
710
711         if (!cmd->data || cmd->error) {
712                 if (host->curr.data && host->dma.sg)
713                         msm_dmov_stop_cmd(host->dma.channel,
714                                           &host->dma.hdr, 0);
715                 else if (host->curr.data) { /* Non DMA */
716                         msmsdcc_stop_data(host);
717                         msmsdcc_request_end(host, cmd->mrq);
718                 } else /* host->data == NULL */
719                         msmsdcc_request_end(host, cmd->mrq);
720         } else if (cmd->data)
721                 if (!(cmd->data->flags & MMC_DATA_READ))
722                         msmsdcc_start_data(host, cmd->data,
723                                                 NULL, 0);
724 }
725
726 static void
727 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
728                         void __iomem *base)
729 {
730         struct mmc_data *data = host->curr.data;
731
732         if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
733                       MCI_CMDTIMEOUT) && host->curr.cmd) {
734                 msmsdcc_do_cmdirq(host, status);
735         }
736
737         if (!data)
738                 return;
739
740         /* Check for data errors */
741         if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
742                       MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
743                 msmsdcc_data_err(host, data, status);
744                 host->curr.data_xfered = 0;
745                 if (host->dma.sg)
746                         msm_dmov_stop_cmd(host->dma.channel,
747                                           &host->dma.hdr, 0);
748                 else {
749                         if (host->curr.data)
750                                 msmsdcc_stop_data(host);
751                         if (!data->stop)
752                                 msmsdcc_request_end(host, data->mrq);
753                         else
754                                 msmsdcc_start_command(host, data->stop, 0);
755                 }
756         }
757
758         /* Check for data done */
759         if (!host->curr.got_dataend && (status & MCI_DATAEND))
760                 host->curr.got_dataend = 1;
761
762         if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
763                 host->curr.got_datablkend = 1;
764
765         /*
766          * If DMA is still in progress, we complete via the completion handler
767          */
768         if (host->curr.got_dataend && host->curr.got_datablkend &&
769             !host->dma.busy) {
770                 /*
771                  * There appears to be an issue in the controller where
772                  * if you request a small block transfer (< fifo size),
773                  * you may get your DATAEND/DATABLKEND irq without the
774                  * PIO data irq.
775                  *
776                  * Check to see if there is still data to be read,
777                  * and simulate a PIO irq.
778                  */
779                 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
780                         msmsdcc_pio_irq(1, host);
781
782                 msmsdcc_stop_data(host);
783                 if (!data->error)
784                         host->curr.data_xfered = host->curr.xfer_size;
785
786                 if (!data->stop)
787                         msmsdcc_request_end(host, data->mrq);
788                 else
789                         msmsdcc_start_command(host, data->stop, 0);
790         }
791 }
792
793 static irqreturn_t
794 msmsdcc_irq(int irq, void *dev_id)
795 {
796         struct msmsdcc_host     *host = dev_id;
797         void __iomem            *base = host->base;
798         u32                     status;
799         int                     ret = 0;
800         int                     cardint = 0;
801
802         spin_lock(&host->lock);
803
804         do {
805                 status = msmsdcc_readl(host, MMCISTATUS);
806                 status &= (msmsdcc_readl(host, MMCIMASK0) |
807                                               MCI_DATABLOCKENDMASK);
808                 msmsdcc_writel(host, status, MMCICLEAR);
809
810                 if (status & MCI_SDIOINTR)
811                         status &= ~MCI_SDIOINTR;
812
813                 if (!status)
814                         break;
815
816                 msmsdcc_handle_irq_data(host, status, base);
817
818                 if (status & MCI_SDIOINTOPER) {
819                         cardint = 1;
820                         status &= ~MCI_SDIOINTOPER;
821                 }
822                 ret = 1;
823         } while (status);
824
825         spin_unlock(&host->lock);
826
827         /*
828          * We have to delay handling the card interrupt as it calls
829          * back into the driver.
830          */
831         if (cardint)
832                 mmc_signal_sdio_irq(host->mmc);
833
834         return IRQ_RETVAL(ret);
835 }
836
837 static void
838 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
839 {
840         struct msmsdcc_host *host = mmc_priv(mmc);
841         unsigned long flags;
842
843         WARN_ON(host->curr.mrq != NULL);
844         WARN_ON(host->pwr == 0);
845
846         spin_lock_irqsave(&host->lock, flags);
847
848         host->stats.reqs++;
849
850         if (host->eject) {
851                 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
852                         mrq->cmd->error = 0;
853                         mrq->data->bytes_xfered = mrq->data->blksz *
854                                                   mrq->data->blocks;
855                 } else
856                         mrq->cmd->error = -ENOMEDIUM;
857
858                 spin_unlock_irqrestore(&host->lock, flags);
859                 mmc_request_done(mmc, mrq);
860                 return;
861         }
862
863         msmsdcc_enable_clocks(host);
864
865         host->curr.mrq = mrq;
866
867         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
868                 /* Queue/read data, daisy-chain command when data starts */
869                 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
870         else
871                 msmsdcc_start_command(host, mrq->cmd, 0);
872
873         if (host->cmdpoll && !msmsdcc_spin_on_status(host,
874                                 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
875                                 CMD_SPINMAX)) {
876                 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
877                 msmsdcc_do_cmdirq(host, status);
878                 msmsdcc_writel(host,
879                                MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
880                                MMCICLEAR);
881                 host->stats.cmdpoll_hits++;
882         } else {
883                 host->stats.cmdpoll_misses++;
884         }
885         spin_unlock_irqrestore(&host->lock, flags);
886 }
887
888 static void
889 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
890 {
891         struct msmsdcc_host *host = mmc_priv(mmc);
892         u32 clk = 0, pwr = 0;
893         int rc;
894         unsigned long flags;
895
896         spin_lock_irqsave(&host->lock, flags);
897
898         msmsdcc_enable_clocks(host);
899
900         if (ios->clock) {
901                 if (ios->clock != host->clk_rate) {
902                         rc = clk_set_rate(host->clk, ios->clock);
903                         if (rc < 0)
904                                 pr_err("%s: Error setting clock rate (%d)\n",
905                                        mmc_hostname(host->mmc), rc);
906                         else
907                                 host->clk_rate = ios->clock;
908                 }
909                 clk |= MCI_CLK_ENABLE;
910         }
911
912         if (ios->bus_width == MMC_BUS_WIDTH_4)
913                 clk |= (2 << 10); /* Set WIDEBUS */
914
915         if (ios->clock > 400000 && msmsdcc_pwrsave)
916                 clk |= (1 << 9); /* PWRSAVE */
917
918         clk |= (1 << 12); /* FLOW_ENA */
919         clk |= (1 << 15); /* feedback clock */
920
921         if (host->plat->translate_vdd)
922                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
923
924         switch (ios->power_mode) {
925         case MMC_POWER_OFF:
926                 break;
927         case MMC_POWER_UP:
928                 pwr |= MCI_PWR_UP;
929                 break;
930         case MMC_POWER_ON:
931                 pwr |= MCI_PWR_ON;
932                 break;
933         }
934
935         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
936                 pwr |= MCI_OD;
937
938         msmsdcc_writel(host, clk, MMCICLOCK);
939
940         if (host->pwr != pwr) {
941                 host->pwr = pwr;
942                 msmsdcc_writel(host, pwr, MMCIPOWER);
943         }
944 #if BUSCLK_PWRSAVE
945         msmsdcc_disable_clocks(host, 1);
946 #endif
947         spin_unlock_irqrestore(&host->lock, flags);
948 }
949
950 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
951 {
952         struct msmsdcc_host *host = mmc_priv(mmc);
953         unsigned long flags;
954         u32 status;
955
956         spin_lock_irqsave(&host->lock, flags);
957         if (msmsdcc_sdioirq == 1) {
958                 status = msmsdcc_readl(host, MMCIMASK0);
959                 if (enable)
960                         status |= MCI_SDIOINTOPERMASK;
961                 else
962                         status &= ~MCI_SDIOINTOPERMASK;
963                 host->saved_irq0mask = status;
964                 msmsdcc_writel(host, status, MMCIMASK0);
965         }
966         spin_unlock_irqrestore(&host->lock, flags);
967 }
968
969 static const struct mmc_host_ops msmsdcc_ops = {
970         .request        = msmsdcc_request,
971         .set_ios        = msmsdcc_set_ios,
972         .enable_sdio_irq = msmsdcc_enable_sdio_irq,
973 };
974
975 static void
976 msmsdcc_check_status(unsigned long data)
977 {
978         struct msmsdcc_host *host = (struct msmsdcc_host *)data;
979         unsigned int status;
980
981         if (!host->plat->status) {
982                 mmc_detect_change(host->mmc, 0);
983                 goto out;
984         }
985
986         status = host->plat->status(mmc_dev(host->mmc));
987         host->eject = !status;
988         if (status ^ host->oldstat) {
989                 pr_info("%s: Slot status change detected (%d -> %d)\n",
990                         mmc_hostname(host->mmc), host->oldstat, status);
991                 if (status)
992                         mmc_detect_change(host->mmc, (5 * HZ) / 2);
993                 else
994                         mmc_detect_change(host->mmc, 0);
995         }
996
997         host->oldstat = status;
998
999 out:
1000         if (host->timer.function)
1001                 mod_timer(&host->timer, jiffies + HZ);
1002 }
1003
1004 static irqreturn_t
1005 msmsdcc_platform_status_irq(int irq, void *dev_id)
1006 {
1007         struct msmsdcc_host *host = dev_id;
1008
1009         printk(KERN_DEBUG "%s: %d\n", __func__, irq);
1010         msmsdcc_check_status((unsigned long) host);
1011         return IRQ_HANDLED;
1012 }
1013
1014 static void
1015 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1016 {
1017         struct msmsdcc_host *host = dev_id;
1018
1019         printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1020                card_present);
1021         msmsdcc_check_status((unsigned long) host);
1022 }
1023
1024 static void
1025 msmsdcc_busclk_expired(unsigned long _data)
1026 {
1027         struct msmsdcc_host     *host = (struct msmsdcc_host *) _data;
1028
1029         if (host->clks_on)
1030                 msmsdcc_disable_clocks(host, 0);
1031 }
1032
1033 static int
1034 msmsdcc_init_dma(struct msmsdcc_host *host)
1035 {
1036         memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1037         host->dma.host = host;
1038         host->dma.channel = -1;
1039
1040         if (!host->dmares)
1041                 return -ENODEV;
1042
1043         host->dma.nc = dma_alloc_coherent(NULL,
1044                                           sizeof(struct msmsdcc_nc_dmadata),
1045                                           &host->dma.nc_busaddr,
1046                                           GFP_KERNEL);
1047         if (host->dma.nc == NULL) {
1048                 pr_err("Unable to allocate DMA buffer\n");
1049                 return -ENOMEM;
1050         }
1051         memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1052         host->dma.cmd_busaddr = host->dma.nc_busaddr;
1053         host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1054                                 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1055         host->dma.channel = host->dmares->start;
1056
1057         return 0;
1058 }
1059
1060 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1061 static void
1062 do_resume_work(struct work_struct *work)
1063 {
1064         struct msmsdcc_host *host =
1065                 container_of(work, struct msmsdcc_host, resume_task);
1066         struct mmc_host *mmc = host->mmc;
1067
1068         if (mmc) {
1069                 mmc_resume_host(mmc);
1070                 if (host->stat_irq)
1071                         enable_irq(host->stat_irq);
1072         }
1073 }
1074 #endif
1075
1076 static int
1077 msmsdcc_probe(struct platform_device *pdev)
1078 {
1079         struct mmc_platform_data *plat = pdev->dev.platform_data;
1080         struct msmsdcc_host *host;
1081         struct mmc_host *mmc;
1082         struct resource *cmd_irqres = NULL;
1083         struct resource *pio_irqres = NULL;
1084         struct resource *stat_irqres = NULL;
1085         struct resource *memres = NULL;
1086         struct resource *dmares = NULL;
1087         int ret;
1088
1089         /* must have platform data */
1090         if (!plat) {
1091                 pr_err("%s: Platform data not available\n", __func__);
1092                 ret = -EINVAL;
1093                 goto out;
1094         }
1095
1096         if (pdev->id < 1 || pdev->id > 4)
1097                 return -EINVAL;
1098
1099         if (pdev->resource == NULL || pdev->num_resources < 2) {
1100                 pr_err("%s: Invalid resource\n", __func__);
1101                 return -ENXIO;
1102         }
1103
1104         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105         dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1106         cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1107                                                   "cmd_irq");
1108         pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1109                                                   "pio_irq");
1110         stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1111                                                    "status_irq");
1112
1113         if (!cmd_irqres || !pio_irqres || !memres) {
1114                 pr_err("%s: Invalid resource\n", __func__);
1115                 return -ENXIO;
1116         }
1117
1118         /*
1119          * Setup our host structure
1120          */
1121
1122         mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1123         if (!mmc) {
1124                 ret = -ENOMEM;
1125                 goto out;
1126         }
1127
1128         host = mmc_priv(mmc);
1129         host->pdev_id = pdev->id;
1130         host->plat = plat;
1131         host->mmc = mmc;
1132         host->curr.cmd = NULL;
1133
1134         host->cmdpoll = 1;
1135
1136         host->base = ioremap(memres->start, PAGE_SIZE);
1137         if (!host->base) {
1138                 ret = -ENOMEM;
1139                 goto out;
1140         }
1141
1142         host->cmd_irqres = cmd_irqres;
1143         host->pio_irqres = pio_irqres;
1144         host->memres = memres;
1145         host->dmares = dmares;
1146         spin_lock_init(&host->lock);
1147
1148 #ifdef CONFIG_MMC_EMBEDDED_SDIO
1149         if (plat->embedded_sdio)
1150                 mmc_set_embedded_sdio_data(mmc,
1151                                            &plat->embedded_sdio->cis,
1152                                            &plat->embedded_sdio->cccr,
1153                                            plat->embedded_sdio->funcs,
1154                                            plat->embedded_sdio->num_funcs);
1155 #endif
1156
1157         /*
1158          * Setup DMA
1159          */
1160         msmsdcc_init_dma(host);
1161
1162         /* Get our clocks */
1163         host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1164         if (IS_ERR(host->pclk)) {
1165                 ret = PTR_ERR(host->pclk);
1166                 goto host_free;
1167         }
1168
1169         host->clk = clk_get(&pdev->dev, "sdc_clk");
1170         if (IS_ERR(host->clk)) {
1171                 ret = PTR_ERR(host->clk);
1172                 goto pclk_put;
1173         }
1174
1175         /* Enable clocks */
1176         ret = msmsdcc_enable_clocks(host);
1177         if (ret)
1178                 goto clk_put;
1179
1180         ret = clk_set_rate(host->clk, msmsdcc_fmin);
1181         if (ret) {
1182                 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1183                 goto clk_disable;
1184         }
1185
1186         host->pclk_rate = clk_get_rate(host->pclk);
1187         host->clk_rate = clk_get_rate(host->clk);
1188
1189         /*
1190          * Setup MMC host structure
1191          */
1192         mmc->ops = &msmsdcc_ops;
1193         mmc->f_min = msmsdcc_fmin;
1194         mmc->f_max = msmsdcc_fmax;
1195         mmc->ocr_avail = plat->ocr_mask;
1196
1197         if (msmsdcc_4bit)
1198                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1199         if (msmsdcc_sdioirq)
1200                 mmc->caps |= MMC_CAP_SDIO_IRQ;
1201         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1202
1203         mmc->max_phys_segs = NR_SG;
1204         mmc->max_hw_segs = NR_SG;
1205         mmc->max_blk_size = 4096;       /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1206         mmc->max_blk_count = 65536;
1207
1208         mmc->max_req_size = 33554432;   /* MCI_DATA_LENGTH is 25 bits */
1209         mmc->max_seg_size = mmc->max_req_size;
1210
1211         msmsdcc_writel(host, 0, MMCIMASK0);
1212         msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1213
1214         msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1215         host->saved_irq0mask = MCI_IRQENABLE;
1216
1217         /*
1218          * Setup card detect change
1219          */
1220
1221         memset(&host->timer, 0, sizeof(host->timer));
1222
1223         if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1224                 unsigned long irqflags = IRQF_SHARED |
1225                         (stat_irqres->flags & IRQF_TRIGGER_MASK);
1226
1227                 host->stat_irq = stat_irqres->start;
1228                 ret = request_irq(host->stat_irq,
1229                                   msmsdcc_platform_status_irq,
1230                                   irqflags,
1231                                   DRIVER_NAME " (slot)",
1232                                   host);
1233                 if (ret) {
1234                         pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1235                                mmc_hostname(mmc), host->stat_irq, ret);
1236                         goto clk_disable;
1237                 }
1238         } else if (plat->register_status_notify) {
1239                 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1240         } else if (!plat->status)
1241                 pr_err("%s: No card detect facilities available\n",
1242                        mmc_hostname(mmc));
1243         else {
1244                 init_timer(&host->timer);
1245                 host->timer.data = (unsigned long)host;
1246                 host->timer.function = msmsdcc_check_status;
1247                 host->timer.expires = jiffies + HZ;
1248                 add_timer(&host->timer);
1249         }
1250
1251         if (plat->status) {
1252                 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1253                 host->eject = !host->oldstat;
1254         }
1255
1256         init_timer(&host->busclk_timer);
1257         host->busclk_timer.data = (unsigned long) host;
1258         host->busclk_timer.function = msmsdcc_busclk_expired;
1259
1260         ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1261                           DRIVER_NAME " (cmd)", host);
1262         if (ret)
1263                 goto stat_irq_free;
1264
1265         ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1266                           DRIVER_NAME " (pio)", host);
1267         if (ret)
1268                 goto cmd_irq_free;
1269
1270         mmc_set_drvdata(pdev, mmc);
1271         mmc_add_host(mmc);
1272
1273         pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1274                 mmc_hostname(mmc), (unsigned long long)memres->start,
1275                 (unsigned int) cmd_irqres->start,
1276                 (unsigned int) host->stat_irq, host->dma.channel);
1277         pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1278                 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1279         pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1280                 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1281         pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1282         pr_info("%s: Power save feature enable = %d\n",
1283                 mmc_hostname(mmc), msmsdcc_pwrsave);
1284
1285         if (host->dma.channel != -1) {
1286                 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1287                         mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1288                 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1289                         mmc_hostname(mmc), host->dma.cmd_busaddr,
1290                         host->dma.cmdptr_busaddr);
1291         } else
1292                 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1293         if (host->timer.function)
1294                 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1295
1296 #if BUSCLK_PWRSAVE
1297         msmsdcc_disable_clocks(host, 1);
1298 #endif
1299         return 0;
1300  cmd_irq_free:
1301         free_irq(cmd_irqres->start, host);
1302  stat_irq_free:
1303         if (host->stat_irq)
1304                 free_irq(host->stat_irq, host);
1305  clk_disable:
1306         msmsdcc_disable_clocks(host, 0);
1307  clk_put:
1308         clk_put(host->clk);
1309  pclk_put:
1310         clk_put(host->pclk);
1311  host_free:
1312         mmc_free_host(mmc);
1313  out:
1314         return ret;
1315 }
1316
1317 static int
1318 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1319 {
1320         struct mmc_host *mmc = mmc_get_drvdata(dev);
1321         int rc = 0;
1322
1323         if (mmc) {
1324                 struct msmsdcc_host *host = mmc_priv(mmc);
1325
1326                 if (host->stat_irq)
1327                         disable_irq(host->stat_irq);
1328
1329                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1330                         rc = mmc_suspend_host(mmc, state);
1331                 if (!rc)
1332                         msmsdcc_writel(host, 0, MMCIMASK0);
1333                 if (host->clks_on)
1334                         msmsdcc_disable_clocks(host, 0);
1335         }
1336         return rc;
1337 }
1338
1339 static int
1340 msmsdcc_resume(struct platform_device *dev)
1341 {
1342         struct mmc_host *mmc = mmc_get_drvdata(dev);
1343
1344         if (mmc) {
1345                 struct msmsdcc_host *host = mmc_priv(mmc);
1346
1347                 msmsdcc_enable_clocks(host);
1348
1349                 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1350
1351                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1352                         mmc_resume_host(mmc);
1353                 if (host->stat_irq)
1354                         enable_irq(host->stat_irq);
1355 #if BUSCLK_PWRSAVE
1356                 msmsdcc_disable_clocks(host, 1);
1357 #endif
1358         }
1359         return 0;
1360 }
1361
1362 static struct platform_driver msmsdcc_driver = {
1363         .probe          = msmsdcc_probe,
1364         .suspend        = msmsdcc_suspend,
1365         .resume         = msmsdcc_resume,
1366         .driver         = {
1367                 .name   = "msm_sdcc",
1368         },
1369 };
1370
1371 static int __init msmsdcc_init(void)
1372 {
1373         return platform_driver_register(&msmsdcc_driver);
1374 }
1375
1376 static void __exit msmsdcc_exit(void)
1377 {
1378         platform_driver_unregister(&msmsdcc_driver);
1379 }
1380
1381 module_init(msmsdcc_init);
1382 module_exit(msmsdcc_exit);
1383
1384 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1385 MODULE_LICENSE("GPL");