drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/ioport.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/delay.h>
  31 #include <linux/irq.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/mmc/sd.h>
  36 #include <linux/mmc/sdio.h>
  37 #include <linux/bitops.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/of.h>
  40 #include <linux/of_gpio.h>
  41 #include <linux/mmc/slot-gpio.h>
  42
  43 #include "dw_mmc.h"
  44
  45 /* Common flag combinations */
  46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  47                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  48                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  49 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  50                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  51 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  52                                  DW_MCI_CMD_ERROR_FLAGS)
  53 #define DW_MCI_SEND_STATUS      1
  54 #define DW_MCI_RECV_STATUS      2
  55 #define DW_MCI_DMA_THRESHOLD    16
  56
  57 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  58 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
  59
  60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  63                                  SDMMC_IDMAC_INT_TI)
  64
  65 #define DESC_RING_BUF_SZ        PAGE_SIZE
  66
  67 struct idmac_desc_64addr {
  68         u32             des0;   /* Control Descriptor */
  69 #define IDMAC_OWN_CLR64(x) \
  70         !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  71
  72         u32             des1;   /* Reserved */
  73
  74         u32             des2;   /*Buffer sizes */
  75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  76         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  77          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  78
  79         u32             des3;   /* Reserved */
  80
  81         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  82         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  83
  84         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  85         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  86 };
  87
  88 struct idmac_desc {
  89         __le32          des0;   /* Control Descriptor */
  90 #define IDMAC_DES0_DIC  BIT(1)
  91 #define IDMAC_DES0_LD   BIT(2)
  92 #define IDMAC_DES0_FD   BIT(3)
  93 #define IDMAC_DES0_CH   BIT(4)
  94 #define IDMAC_DES0_ER   BIT(5)
  95 #define IDMAC_DES0_CES  BIT(30)
  96 #define IDMAC_DES0_OWN  BIT(31)
  97
  98         __le32          des1;   /* Buffer sizes */
  99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 100         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
 101
 102         __le32          des2;   /* buffer 1 physical address */
 103
 104         __le32          des3;   /* buffer 2 physical address */
 105 };
 106
 107 /* Each descriptor can transfer up to 4KB of data in chained mode */
 108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 109
 110 #if defined(CONFIG_DEBUG_FS)
 111 static int dw_mci_req_show(struct seq_file *s, void *v)
 112 {
 113         struct dw_mci_slot *slot = s->private;
 114         struct mmc_request *mrq;
 115         struct mmc_command *cmd;
 116         struct mmc_command *stop;
 117         struct mmc_data *data;
 118
 119         /* Make sure we get a consistent snapshot */
 120         spin_lock_bh(&slot->host->lock);
 121         mrq = slot->mrq;
 122
 123         if (mrq) {
 124                 cmd = mrq->cmd;
 125                 data = mrq->data;
 126                 stop = mrq->stop;
 127
 128                 if (cmd)
 129                         seq_printf(s,
 130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 131                                    cmd->opcode, cmd->arg, cmd->flags,
 132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 133                                    cmd->resp[2], cmd->error);
 134                 if (data)
 135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 136                                    data->bytes_xfered, data->blocks,
 137                                    data->blksz, data->flags, data->error);
 138                 if (stop)
 139                         seq_printf(s,
 140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 141                                    stop->opcode, stop->arg, stop->flags,
 142                                    stop->resp[0], stop->resp[1], stop->resp[2],
 143                                    stop->resp[2], stop->error);
 144         }
 145
 146         spin_unlock_bh(&slot->host->lock);
 147
 148         return 0;
 149 }
 150
 151 static int dw_mci_req_open(struct inode *inode, struct file *file)
 152 {
 153         return single_open(file, dw_mci_req_show, inode->i_private);
 154 }
 155
 156 static const struct file_operations dw_mci_req_fops = {
 157         .owner          = THIS_MODULE,
 158         .open           = dw_mci_req_open,
 159         .read           = seq_read,
 160         .llseek         = seq_lseek,
 161         .release        = single_release,
 162 };
 163
 164 static int dw_mci_regs_show(struct seq_file *s, void *v)
 165 {
 166         struct dw_mci *host = s->private;
 167
 168         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
 169         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
 170         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
 171         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
 172         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
 173         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
 174
 175         return 0;
 176 }
 177
 178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 179 {
 180         return single_open(file, dw_mci_regs_show, inode->i_private);
 181 }
 182
 183 static const struct file_operations dw_mci_regs_fops = {
 184         .owner          = THIS_MODULE,
 185         .open           = dw_mci_regs_open,
 186         .read           = seq_read,
 187         .llseek         = seq_lseek,
 188         .release        = single_release,
 189 };
 190
 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 192 {
 193         struct mmc_host *mmc = slot->mmc;
 194         struct dw_mci *host = slot->host;
 195         struct dentry *root;
 196         struct dentry *node;
 197
 198         root = mmc->debugfs_root;
 199         if (!root)
 200                 return;
 201
 202         node = debugfs_create_file("regs", S_IRUSR, root, host,
 203                                    &dw_mci_regs_fops);
 204         if (!node)
 205                 goto err;
 206
 207         node = debugfs_create_file("req", S_IRUSR, root, slot,
 208                                    &dw_mci_req_fops);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 217                                   (u32 *)&host->pending_events);
 218         if (!node)
 219                 goto err;
 220
 221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 222                                   (u32 *)&host->completed_events);
 223         if (!node)
 224                 goto err;
 225
 226         return;
 227
 228 err:
 229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 230 }
 231 #endif /* defined(CONFIG_DEBUG_FS) */
 232
 233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
 234 {
 235         u32 ctrl;
 236
 237         ctrl = mci_readl(host, CTRL);
 238         ctrl |= reset;
 239         mci_writel(host, CTRL, ctrl);
 240
 241         /* wait till resets clear */
 242         if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
 243                                       !(ctrl & reset),
 244                                       1, 500 * USEC_PER_MSEC)) {
 245                 dev_err(host->dev,
 246                         "Timeout resetting block (ctrl reset %#x)\n",
 247                         ctrl & reset);
 248                 return false;
 249         }
 250
 251         return true;
 252 }
 253
 254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 255 {
 256         u32 status;
 257
 258         /*
 259          * Databook says that before issuing a new data transfer command
 260          * we need to check to see if the card is busy.  Data transfer commands
 261          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 262          *
 263          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 264          * expected.
 265          */
 266         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 267             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 268                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
 269                                               status,
 270                                               !(status & SDMMC_STATUS_BUSY),
 271                                               10, 500 * USEC_PER_MSEC))
 272                         dev_err(host->dev, "Busy; trying anyway\n");
 273         }
 274 }
 275
 276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 277 {
 278         struct dw_mci *host = slot->host;
 279         unsigned int cmd_status = 0;
 280
 281         mci_writel(host, CMDARG, arg);
 282         wmb(); /* drain writebuffer */
 283         dw_mci_wait_while_busy(host, cmd);
 284         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 285
 286         if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
 287                                       !(cmd_status & SDMMC_CMD_START),
 288                                       1, 500 * USEC_PER_MSEC))
 289                 dev_err(&slot->mmc->class_dev,
 290                         "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 291                         cmd, arg, cmd_status);
 292 }
 293
 294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 295 {
 296         struct dw_mci_slot *slot = mmc_priv(mmc);
 297         struct dw_mci *host = slot->host;
 298         u32 cmdr;
 299
 300         cmd->error = -EINPROGRESS;
 301         cmdr = cmd->opcode;
 302
 303         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 304             cmd->opcode == MMC_GO_IDLE_STATE ||
 305             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 306             (cmd->opcode == SD_IO_RW_DIRECT &&
 307              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 308                 cmdr |= SDMMC_CMD_STOP;
 309         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 310                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 311
 312         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 313                 u32 clk_en_a;
 314
 315                 /* Special bit makes CMD11 not die */
 316                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 317
 318                 /* Change state to continue to handle CMD11 weirdness */
 319                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 320                 slot->host->state = STATE_SENDING_CMD11;
 321
 322                 /*
 323                  * We need to disable low power mode (automatic clock stop)
 324                  * while doing voltage switch so we don't confuse the card,
 325                  * since stopping the clock is a specific part of the UHS
 326                  * voltage change dance.
 327                  *
 328                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 329                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 330                  * ever called with a non-zero clock.  That shouldn't happen
 331                  * until the voltage change is all done.
 332                  */
 333                 clk_en_a = mci_readl(host, CLKENA);
 334                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 335                 mci_writel(host, CLKENA, clk_en_a);
 336                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 337                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 338         }
 339
 340         if (cmd->flags & MMC_RSP_PRESENT) {
 341                 /* We expect a response, so set this bit */
 342                 cmdr |= SDMMC_CMD_RESP_EXP;
 343                 if (cmd->flags & MMC_RSP_136)
 344                         cmdr |= SDMMC_CMD_RESP_LONG;
 345         }
 346
 347         if (cmd->flags & MMC_RSP_CRC)
 348                 cmdr |= SDMMC_CMD_RESP_CRC;
 349
 350         if (cmd->data) {
 351                 cmdr |= SDMMC_CMD_DAT_EXP;
 352                 if (cmd->data->flags & MMC_DATA_WRITE)
 353                         cmdr |= SDMMC_CMD_DAT_WR;
 354         }
 355
 356         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 357                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 358
 359         return cmdr;
 360 }
 361
 362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 363 {
 364         struct mmc_command *stop;
 365         u32 cmdr;
 366
 367         if (!cmd->data)
 368                 return 0;
 369
 370         stop = &host->stop_abort;
 371         cmdr = cmd->opcode;
 372         memset(stop, 0, sizeof(struct mmc_command));
 373
 374         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 375             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 376             cmdr == MMC_WRITE_BLOCK ||
 377             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 378             cmdr == MMC_SEND_TUNING_BLOCK ||
 379             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 380                 stop->opcode = MMC_STOP_TRANSMISSION;
 381                 stop->arg = 0;
 382                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 383         } else if (cmdr == SD_IO_RW_EXTENDED) {
 384                 stop->opcode = SD_IO_RW_DIRECT;
 385                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 386                              ((cmd->arg >> 28) & 0x7);
 387                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 388         } else {
 389                 return 0;
 390         }
 391
 392         cmdr = stop->opcode | SDMMC_CMD_STOP |
 393                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 394
 395         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
 396                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 397
 398         return cmdr;
 399 }
 400
 401 static inline void dw_mci_set_cto(struct dw_mci *host)
 402 {
 403         unsigned int cto_clks;
 404         unsigned int cto_ms;
 405
 406         cto_clks = mci_readl(host, TMOUT) & 0xff;
 407         cto_ms = DIV_ROUND_UP(cto_clks, host->bus_hz / 1000);
 408
 409         /* add a bit spare time */
 410         cto_ms += 10;
 411
 412         mod_timer(&host->cto_timer,
 413                   jiffies + msecs_to_jiffies(cto_ms) + 1);
 414 }
 415
 416 static void dw_mci_start_command(struct dw_mci *host,
 417                                  struct mmc_command *cmd, u32 cmd_flags)
 418 {
 419         host->cmd = cmd;
 420         dev_vdbg(host->dev,
 421                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 422                  cmd->arg, cmd_flags);
 423
 424         mci_writel(host, CMDARG, cmd->arg);
 425         wmb(); /* drain writebuffer */
 426         dw_mci_wait_while_busy(host, cmd_flags);
 427
 428         /* response expected command only */
 429         if (cmd_flags & SDMMC_CMD_RESP_EXP)
 430                 dw_mci_set_cto(host);
 431
 432         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 433 }
 434
 435 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 436 {
 437         struct mmc_command *stop = &host->stop_abort;
 438
 439         dw_mci_start_command(host, stop, host->stop_cmdr);
 440 }
 441
 442 /* DMA interface functions */
 443 static void dw_mci_stop_dma(struct dw_mci *host)
 444 {
 445         if (host->using_dma) {
 446                 host->dma_ops->stop(host);
 447                 host->dma_ops->cleanup(host);
 448         }
 449
 450         /* Data transfer was stopped by the interrupt handler */
 451         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 452 }
 453
 454 static void dw_mci_dma_cleanup(struct dw_mci *host)
 455 {
 456         struct mmc_data *data = host->data;
 457
 458         if (data && data->host_cookie == COOKIE_MAPPED) {
 459                 dma_unmap_sg(host->dev,
 460                              data->sg,
 461                              data->sg_len,
 462                              mmc_get_dma_dir(data));
 463                 data->host_cookie = COOKIE_UNMAPPED;
 464         }
 465 }
 466
 467 static void dw_mci_idmac_reset(struct dw_mci *host)
 468 {
 469         u32 bmod = mci_readl(host, BMOD);
 470         /* Software reset of DMA */
 471         bmod |= SDMMC_IDMAC_SWRESET;
 472         mci_writel(host, BMOD, bmod);
 473 }
 474
 475 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 476 {
 477         u32 temp;
 478
 479         /* Disable and reset the IDMAC interface */
 480         temp = mci_readl(host, CTRL);
 481         temp &= ~SDMMC_CTRL_USE_IDMAC;
 482         temp |= SDMMC_CTRL_DMA_RESET;
 483         mci_writel(host, CTRL, temp);
 484
 485         /* Stop the IDMAC running */
 486         temp = mci_readl(host, BMOD);
 487         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 488         temp |= SDMMC_IDMAC_SWRESET;
 489         mci_writel(host, BMOD, temp);
 490 }
 491
 492 static void dw_mci_dmac_complete_dma(void *arg)
 493 {
 494         struct dw_mci *host = arg;
 495         struct mmc_data *data = host->data;
 496
 497         dev_vdbg(host->dev, "DMA complete\n");
 498
 499         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 500             data && (data->flags & MMC_DATA_READ))
 501                 /* Invalidate cache after read */
 502                 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
 503                                     data->sg,
 504                                     data->sg_len,
 505                                     DMA_FROM_DEVICE);
 506
 507         host->dma_ops->cleanup(host);
 508
 509         /*
 510          * If the card was removed, data will be NULL. No point in trying to
 511          * send the stop command or waiting for NBUSY in this case.
 512          */
 513         if (data) {
 514                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 515                 tasklet_schedule(&host->tasklet);
 516         }
 517 }
 518
 519 static int dw_mci_idmac_init(struct dw_mci *host)
 520 {
 521         int i;
 522
 523         if (host->dma_64bit_address == 1) {
 524                 struct idmac_desc_64addr *p;
 525                 /* Number of descriptors in the ring buffer */
 526                 host->ring_size =
 527                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 528
 529                 /* Forward link the descriptor list */
 530                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 531                                                                 i++, p++) {
 532                         p->des6 = (host->sg_dma +
 533                                         (sizeof(struct idmac_desc_64addr) *
 534                                                         (i + 1))) & 0xffffffff;
 535
 536                         p->des7 = (u64)(host->sg_dma +
 537                                         (sizeof(struct idmac_desc_64addr) *
 538                                                         (i + 1))) >> 32;
 539                         /* Initialize reserved and buffer size fields to "0" */
 540                         p->des1 = 0;
 541                         p->des2 = 0;
 542                         p->des3 = 0;
 543                 }
 544
 545                 /* Set the last descriptor as the end-of-ring descriptor */
 546                 p->des6 = host->sg_dma & 0xffffffff;
 547                 p->des7 = (u64)host->sg_dma >> 32;
 548                 p->des0 = IDMAC_DES0_ER;
 549
 550         } else {
 551                 struct idmac_desc *p;
 552                 /* Number of descriptors in the ring buffer */
 553                 host->ring_size =
 554                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 555
 556                 /* Forward link the descriptor list */
 557                 for (i = 0, p = host->sg_cpu;
 558                      i < host->ring_size - 1;
 559                      i++, p++) {
 560                         p->des3 = cpu_to_le32(host->sg_dma +
 561                                         (sizeof(struct idmac_desc) * (i + 1)));
 562                         p->des1 = 0;
 563                 }
 564
 565                 /* Set the last descriptor as the end-of-ring descriptor */
 566                 p->des3 = cpu_to_le32(host->sg_dma);
 567                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 568         }
 569
 570         dw_mci_idmac_reset(host);
 571
 572         if (host->dma_64bit_address == 1) {
 573                 /* Mask out interrupts - get Tx & Rx complete only */
 574                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 575                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 576                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 577
 578                 /* Set the descriptor base address */
 579                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 580                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 581
 582         } else {
 583                 /* Mask out interrupts - get Tx & Rx complete only */
 584                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 585                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 586                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 587
 588                 /* Set the descriptor base address */
 589                 mci_writel(host, DBADDR, host->sg_dma);
 590         }
 591
 592         return 0;
 593 }
 594
 595 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 596                                          struct mmc_data *data,
 597                                          unsigned int sg_len)
 598 {
 599         unsigned int desc_len;
 600         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 601         u32 val;
 602         int i;
 603
 604         desc_first = desc_last = desc = host->sg_cpu;
 605
 606         for (i = 0; i < sg_len; i++) {
 607                 unsigned int length = sg_dma_len(&data->sg[i]);
 608
 609                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 610
 611                 for ( ; length ; desc++) {
 612                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 613                                    length : DW_MCI_DESC_DATA_LENGTH;
 614
 615                         length -= desc_len;
 616
 617                         /*
 618                          * Wait for the former clear OWN bit operation
 619                          * of IDMAC to make sure that this descriptor
 620                          * isn't still owned by IDMAC as IDMAC's write
 621                          * ops and CPU's read ops are asynchronous.
 622                          */
 623                         if (readl_poll_timeout_atomic(&desc->des0, val,
 624                                                 !(val & IDMAC_DES0_OWN),
 625                                                 10, 100 * USEC_PER_MSEC))
 626                                 goto err_own_bit;
 627
 628                         /*
 629                          * Set the OWN bit and disable interrupts
 630                          * for this descriptor
 631                          */
 632                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 633                                                 IDMAC_DES0_CH;
 634
 635                         /* Buffer length */
 636                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 637
 638                         /* Physical address to DMA to/from */
 639                         desc->des4 = mem_addr & 0xffffffff;
 640                         desc->des5 = mem_addr >> 32;
 641
 642                         /* Update physical address for the next desc */
 643                         mem_addr += desc_len;
 644
 645                         /* Save pointer to the last descriptor */
 646                         desc_last = desc;
 647                 }
 648         }
 649
 650         /* Set first descriptor */
 651         desc_first->des0 |= IDMAC_DES0_FD;
 652
 653         /* Set last descriptor */
 654         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 655         desc_last->des0 |= IDMAC_DES0_LD;
 656
 657         return 0;
 658 err_own_bit:
 659         /* restore the descriptor chain as it's polluted */
 660         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 661         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 662         dw_mci_idmac_init(host);
 663         return -EINVAL;
 664 }
 665
 666
 667 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 668                                          struct mmc_data *data,
 669                                          unsigned int sg_len)
 670 {
 671         unsigned int desc_len;
 672         struct idmac_desc *desc_first, *desc_last, *desc;
 673         u32 val;
 674         int i;
 675
 676         desc_first = desc_last = desc = host->sg_cpu;
 677
 678         for (i = 0; i < sg_len; i++) {
 679                 unsigned int length = sg_dma_len(&data->sg[i]);
 680
 681                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 682
 683                 for ( ; length ; desc++) {
 684                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 685                                    length : DW_MCI_DESC_DATA_LENGTH;
 686
 687                         length -= desc_len;
 688
 689                         /*
 690                          * Wait for the former clear OWN bit operation
 691                          * of IDMAC to make sure that this descriptor
 692                          * isn't still owned by IDMAC as IDMAC's write
 693                          * ops and CPU's read ops are asynchronous.
 694                          */
 695                         if (readl_poll_timeout_atomic(&desc->des0, val,
 696                                                       IDMAC_OWN_CLR64(val),
 697                                                       10,
 698                                                       100 * USEC_PER_MSEC))
 699                                 goto err_own_bit;
 700
 701                         /*
 702                          * Set the OWN bit and disable interrupts
 703                          * for this descriptor
 704                          */
 705                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 706                                                  IDMAC_DES0_DIC |
 707                                                  IDMAC_DES0_CH);
 708
 709                         /* Buffer length */
 710                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 711
 712                         /* Physical address to DMA to/from */
 713                         desc->des2 = cpu_to_le32(mem_addr);
 714
 715                         /* Update physical address for the next desc */
 716                         mem_addr += desc_len;
 717
 718                         /* Save pointer to the last descriptor */
 719                         desc_last = desc;
 720                 }
 721         }
 722
 723         /* Set first descriptor */
 724         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 725
 726         /* Set last descriptor */
 727         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 728                                        IDMAC_DES0_DIC));
 729         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 730
 731         return 0;
 732 err_own_bit:
 733         /* restore the descriptor chain as it's polluted */
 734         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 735         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 736         dw_mci_idmac_init(host);
 737         return -EINVAL;
 738 }
 739
 740 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 741 {
 742         u32 temp;
 743         int ret;
 744
 745         if (host->dma_64bit_address == 1)
 746                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 747         else
 748                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 749
 750         if (ret)
 751                 goto out;
 752
 753         /* drain writebuffer */
 754         wmb();
 755
 756         /* Make sure to reset DMA in case we did PIO before this */
 757         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 758         dw_mci_idmac_reset(host);
 759
 760         /* Select IDMAC interface */
 761         temp = mci_readl(host, CTRL);
 762         temp |= SDMMC_CTRL_USE_IDMAC;
 763         mci_writel(host, CTRL, temp);
 764
 765         /* drain writebuffer */
 766         wmb();
 767
 768         /* Enable the IDMAC */
 769         temp = mci_readl(host, BMOD);
 770         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 771         mci_writel(host, BMOD, temp);
 772
 773         /* Start it running */
 774         mci_writel(host, PLDMND, 1);
 775
 776 out:
 777         return ret;
 778 }
 779
 780 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 781         .init = dw_mci_idmac_init,
 782         .start = dw_mci_idmac_start_dma,
 783         .stop = dw_mci_idmac_stop_dma,
 784         .complete = dw_mci_dmac_complete_dma,
 785         .cleanup = dw_mci_dma_cleanup,
 786 };
 787
 788 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 789 {
 790         dmaengine_terminate_async(host->dms->ch);
 791 }
 792
 793 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 794                                             unsigned int sg_len)
 795 {
 796         struct dma_slave_config cfg;
 797         struct dma_async_tx_descriptor *desc = NULL;
 798         struct scatterlist *sgl = host->data->sg;
 799         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 800         u32 sg_elems = host->data->sg_len;
 801         u32 fifoth_val;
 802         u32 fifo_offset = host->fifo_reg - host->regs;
 803         int ret = 0;
 804
 805         /* Set external dma config: burst size, burst width */
 806         cfg.dst_addr = host->phy_regs + fifo_offset;
 807         cfg.src_addr = cfg.dst_addr;
 808         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 809         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 810
 811         /* Match burst msize with external dma config */
 812         fifoth_val = mci_readl(host, FIFOTH);
 813         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 814         cfg.src_maxburst = cfg.dst_maxburst;
 815
 816         if (host->data->flags & MMC_DATA_WRITE)
 817                 cfg.direction = DMA_MEM_TO_DEV;
 818         else
 819                 cfg.direction = DMA_DEV_TO_MEM;
 820
 821         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 822         if (ret) {
 823                 dev_err(host->dev, "Failed to config edmac.\n");
 824                 return -EBUSY;
 825         }
 826
 827         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 828                                        sg_len, cfg.direction,
 829                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 830         if (!desc) {
 831                 dev_err(host->dev, "Can't prepare slave sg.\n");
 832                 return -EBUSY;
 833         }
 834
 835         /* Set dw_mci_dmac_complete_dma as callback */
 836         desc->callback = dw_mci_dmac_complete_dma;
 837         desc->callback_param = (void *)host;
 838         dmaengine_submit(desc);
 839
 840         /* Flush cache before write */
 841         if (host->data->flags & MMC_DATA_WRITE)
 842                 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
 843                                        sg_elems, DMA_TO_DEVICE);
 844
 845         dma_async_issue_pending(host->dms->ch);
 846
 847         return 0;
 848 }
 849
 850 static int dw_mci_edmac_init(struct dw_mci *host)
 851 {
 852         /* Request external dma channel */
 853         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 854         if (!host->dms)
 855                 return -ENOMEM;
 856
 857         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 858         if (!host->dms->ch) {
 859                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 860                 kfree(host->dms);
 861                 host->dms = NULL;
 862                 return -ENXIO;
 863         }
 864
 865         return 0;
 866 }
 867
 868 static void dw_mci_edmac_exit(struct dw_mci *host)
 869 {
 870         if (host->dms) {
 871                 if (host->dms->ch) {
 872                         dma_release_channel(host->dms->ch);
 873                         host->dms->ch = NULL;
 874                 }
 875                 kfree(host->dms);
 876                 host->dms = NULL;
 877         }
 878 }
 879
 880 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 881         .init = dw_mci_edmac_init,
 882         .exit = dw_mci_edmac_exit,
 883         .start = dw_mci_edmac_start_dma,
 884         .stop = dw_mci_edmac_stop_dma,
 885         .complete = dw_mci_dmac_complete_dma,
 886         .cleanup = dw_mci_dma_cleanup,
 887 };
 888
 889 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 890                                    struct mmc_data *data,
 891                                    int cookie)
 892 {
 893         struct scatterlist *sg;
 894         unsigned int i, sg_len;
 895
 896         if (data->host_cookie == COOKIE_PRE_MAPPED)
 897                 return data->sg_len;
 898
 899         /*
 900          * We don't do DMA on "complex" transfers, i.e. with
 901          * non-word-aligned buffers or lengths. Also, we don't bother
 902          * with all the DMA setup overhead for short transfers.
 903          */
 904         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 905                 return -EINVAL;
 906
 907         if (data->blksz & 3)
 908                 return -EINVAL;
 909
 910         for_each_sg(data->sg, sg, data->sg_len, i) {
 911                 if (sg->offset & 3 || sg->length & 3)
 912                         return -EINVAL;
 913         }
 914
 915         sg_len = dma_map_sg(host->dev,
 916                             data->sg,
 917                             data->sg_len,
 918                             mmc_get_dma_dir(data));
 919         if (sg_len == 0)
 920                 return -EINVAL;
 921
 922         data->host_cookie = cookie;
 923
 924         return sg_len;
 925 }
 926
 927 static void dw_mci_pre_req(struct mmc_host *mmc,
 928                            struct mmc_request *mrq)
 929 {
 930         struct dw_mci_slot *slot = mmc_priv(mmc);
 931         struct mmc_data *data = mrq->data;
 932
 933         if (!slot->host->use_dma || !data)
 934                 return;
 935
 936         /* This data might be unmapped at this time */
 937         data->host_cookie = COOKIE_UNMAPPED;
 938
 939         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
 940                                 COOKIE_PRE_MAPPED) < 0)
 941                 data->host_cookie = COOKIE_UNMAPPED;
 942 }
 943
 944 static void dw_mci_post_req(struct mmc_host *mmc,
 945                             struct mmc_request *mrq,
 946                             int err)
 947 {
 948         struct dw_mci_slot *slot = mmc_priv(mmc);
 949         struct mmc_data *data = mrq->data;
 950
 951         if (!slot->host->use_dma || !data)
 952                 return;
 953
 954         if (data->host_cookie != COOKIE_UNMAPPED)
 955                 dma_unmap_sg(slot->host->dev,
 956                              data->sg,
 957                              data->sg_len,
 958                              mmc_get_dma_dir(data));
 959         data->host_cookie = COOKIE_UNMAPPED;
 960 }
 961
 962 static int dw_mci_get_cd(struct mmc_host *mmc)
 963 {
 964         int present;
 965         struct dw_mci_slot *slot = mmc_priv(mmc);
 966         struct dw_mci *host = slot->host;
 967         int gpio_cd = mmc_gpio_get_cd(mmc);
 968
 969         /* Use platform get_cd function, else try onboard card detect */
 970         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
 971                                 || !mmc_card_is_removable(mmc))) {
 972                 present = 1;
 973
 974                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 975                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
 976                                 dev_info(&mmc->class_dev,
 977                                         "card is polling.\n");
 978                         } else {
 979                                 dev_info(&mmc->class_dev,
 980                                         "card is non-removable.\n");
 981                         }
 982                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 983                 }
 984
 985                 return present;
 986         } else if (gpio_cd >= 0)
 987                 present = gpio_cd;
 988         else
 989                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 990                         == 0 ? 1 : 0;
 991
 992         spin_lock_bh(&host->lock);
 993         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 994                 dev_dbg(&mmc->class_dev, "card is present\n");
 995         else if (!present &&
 996                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 997                 dev_dbg(&mmc->class_dev, "card is not present\n");
 998         spin_unlock_bh(&host->lock);
 999
1000         return present;
1001 }
1002
1003 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1004 {
1005         unsigned int blksz = data->blksz;
1006         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1007         u32 fifo_width = 1 << host->data_shift;
1008         u32 blksz_depth = blksz / fifo_width, fifoth_val;
1009         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1010         int idx = ARRAY_SIZE(mszs) - 1;
1011
1012         /* pio should ship this scenario */
1013         if (!host->use_dma)
1014                 return;
1015
1016         tx_wmark = (host->fifo_depth) / 2;
1017         tx_wmark_invers = host->fifo_depth - tx_wmark;
1018
1019         /*
1020          * MSIZE is '1',
1021          * if blksz is not a multiple of the FIFO width
1022          */
1023         if (blksz % fifo_width)
1024                 goto done;
1025
1026         do {
1027                 if (!((blksz_depth % mszs[idx]) ||
1028                      (tx_wmark_invers % mszs[idx]))) {
1029                         msize = idx;
1030                         rx_wmark = mszs[idx] - 1;
1031                         break;
1032                 }
1033         } while (--idx > 0);
1034         /*
1035          * If idx is '0', it won't be tried
1036          * Thus, initial values are uesed
1037          */
1038 done:
1039         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1040         mci_writel(host, FIFOTH, fifoth_val);
1041 }
1042
1043 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1044 {
1045         unsigned int blksz = data->blksz;
1046         u32 blksz_depth, fifo_depth;
1047         u16 thld_size;
1048         u8 enable;
1049
1050         /*
1051          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1052          * in the FIFO region, so we really shouldn't access it).
1053          */
1054         if (host->verid < DW_MMC_240A ||
1055                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1056                 return;
1057
1058         /*
1059          * Card write Threshold is introduced since 2.80a
1060          * It's used when HS400 mode is enabled.
1061          */
1062         if (data->flags & MMC_DATA_WRITE &&
1063                 !(host->timing != MMC_TIMING_MMC_HS400))
1064                 return;
1065
1066         if (data->flags & MMC_DATA_WRITE)
1067                 enable = SDMMC_CARD_WR_THR_EN;
1068         else
1069                 enable = SDMMC_CARD_RD_THR_EN;
1070
1071         if (host->timing != MMC_TIMING_MMC_HS200 &&
1072             host->timing != MMC_TIMING_UHS_SDR104)
1073                 goto disable;
1074
1075         blksz_depth = blksz / (1 << host->data_shift);
1076         fifo_depth = host->fifo_depth;
1077
1078         if (blksz_depth > fifo_depth)
1079                 goto disable;
1080
1081         /*
1082          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1083          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1084          * Currently just choose blksz.
1085          */
1086         thld_size = blksz;
1087         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1088         return;
1089
1090 disable:
1091         mci_writel(host, CDTHRCTL, 0);
1092 }
1093
1094 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1095 {
1096         unsigned long irqflags;
1097         int sg_len;
1098         u32 temp;
1099
1100         host->using_dma = 0;
1101
1102         /* If we don't have a channel, we can't do DMA */
1103         if (!host->use_dma)
1104                 return -ENODEV;
1105
1106         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1107         if (sg_len < 0) {
1108                 host->dma_ops->stop(host);
1109                 return sg_len;
1110         }
1111
1112         host->using_dma = 1;
1113
1114         if (host->use_dma == TRANS_MODE_IDMAC)
1115                 dev_vdbg(host->dev,
1116                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1117                          (unsigned long)host->sg_cpu,
1118                          (unsigned long)host->sg_dma,
1119                          sg_len);
1120
1121         /*
1122          * Decide the MSIZE and RX/TX Watermark.
1123          * If current block size is same with previous size,
1124          * no need to update fifoth.
1125          */
1126         if (host->prev_blksz != data->blksz)
1127                 dw_mci_adjust_fifoth(host, data);
1128
1129         /* Enable the DMA interface */
1130         temp = mci_readl(host, CTRL);
1131         temp |= SDMMC_CTRL_DMA_ENABLE;
1132         mci_writel(host, CTRL, temp);
1133
1134         /* Disable RX/TX IRQs, let DMA handle it */
1135         spin_lock_irqsave(&host->irq_lock, irqflags);
1136         temp = mci_readl(host, INTMASK);
1137         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1138         mci_writel(host, INTMASK, temp);
1139         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1140
1141         if (host->dma_ops->start(host, sg_len)) {
1142                 host->dma_ops->stop(host);
1143                 /* We can't do DMA, try PIO for this one */
1144                 dev_dbg(host->dev,
1145                         "%s: fall back to PIO mode for current transfer\n",
1146                         __func__);
1147                 return -ENODEV;
1148         }
1149
1150         return 0;
1151 }
1152
1153 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1154 {
1155         unsigned long irqflags;
1156         int flags = SG_MITER_ATOMIC;
1157         u32 temp;
1158
1159         data->error = -EINPROGRESS;
1160
1161         WARN_ON(host->data);
1162         host->sg = NULL;
1163         host->data = data;
1164
1165         if (data->flags & MMC_DATA_READ)
1166                 host->dir_status = DW_MCI_RECV_STATUS;
1167         else
1168                 host->dir_status = DW_MCI_SEND_STATUS;
1169
1170         dw_mci_ctrl_thld(host, data);
1171
1172         if (dw_mci_submit_data_dma(host, data)) {
1173                 if (host->data->flags & MMC_DATA_READ)
1174                         flags |= SG_MITER_TO_SG;
1175                 else
1176                         flags |= SG_MITER_FROM_SG;
1177
1178                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1179                 host->sg = data->sg;
1180                 host->part_buf_start = 0;
1181                 host->part_buf_count = 0;
1182
1183                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1184
1185                 spin_lock_irqsave(&host->irq_lock, irqflags);
1186                 temp = mci_readl(host, INTMASK);
1187                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1188                 mci_writel(host, INTMASK, temp);
1189                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1190
1191                 temp = mci_readl(host, CTRL);
1192                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1193                 mci_writel(host, CTRL, temp);
1194
1195                 /*
1196                  * Use the initial fifoth_val for PIO mode. If wm_algined
1197                  * is set, we set watermark same as data size.
1198                  * If next issued data may be transfered by DMA mode,
1199                  * prev_blksz should be invalidated.
1200                  */
1201                 if (host->wm_aligned)
1202                         dw_mci_adjust_fifoth(host, data);
1203                 else
1204                         mci_writel(host, FIFOTH, host->fifoth_val);
1205                 host->prev_blksz = 0;
1206         } else {
1207                 /*
1208                  * Keep the current block size.
1209                  * It will be used to decide whether to update
1210                  * fifoth register next time.
1211                  */
1212                 host->prev_blksz = data->blksz;
1213         }
1214 }
1215
1216 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1217 {
1218         struct dw_mci *host = slot->host;
1219         unsigned int clock = slot->clock;
1220         u32 div;
1221         u32 clk_en_a;
1222         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1223
1224         /* We must continue to set bit 28 in CMD until the change is complete */
1225         if (host->state == STATE_WAITING_CMD11_DONE)
1226                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1227
1228         if (!clock) {
1229                 mci_writel(host, CLKENA, 0);
1230                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1231         } else if (clock != host->current_speed || force_clkinit) {
1232                 div = host->bus_hz / clock;
1233                 if (host->bus_hz % clock && host->bus_hz > clock)
1234                         /*
1235                          * move the + 1 after the divide to prevent
1236                          * over-clocking the card.
1237                          */
1238                         div += 1;
1239
1240                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1241
1242                 if ((clock != slot->__clk_old &&
1243                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1244                         force_clkinit) {
1245                         /* Silent the verbose log if calling from PM context */
1246                         if (!force_clkinit)
1247                                 dev_info(&slot->mmc->class_dev,
1248                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1249                                          slot->id, host->bus_hz, clock,
1250                                          div ? ((host->bus_hz / div) >> 1) :
1251                                          host->bus_hz, div);
1252
1253                         /*
1254                          * If card is polling, display the message only
1255                          * one time at boot time.
1256                          */
1257                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1258                                         slot->mmc->f_min == clock)
1259                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1260                 }
1261
1262                 /* disable clock */
1263                 mci_writel(host, CLKENA, 0);
1264                 mci_writel(host, CLKSRC, 0);
1265
1266                 /* inform CIU */
1267                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1268
1269                 /* set clock to desired speed */
1270                 mci_writel(host, CLKDIV, div);
1271
1272                 /* inform CIU */
1273                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1274
1275                 /* enable clock; only low power if no SDIO */
1276                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1277                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1278                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1279                 mci_writel(host, CLKENA, clk_en_a);
1280
1281                 /* inform CIU */
1282                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1283
1284                 /* keep the last clock value that was requested from core */
1285                 slot->__clk_old = clock;
1286         }
1287
1288         host->current_speed = clock;
1289
1290         /* Set the current slot bus width */
1291         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1292 }
1293
1294 static void __dw_mci_start_request(struct dw_mci *host,
1295                                    struct dw_mci_slot *slot,
1296                                    struct mmc_command *cmd)
1297 {
1298         struct mmc_request *mrq;
1299         struct mmc_data *data;
1300         u32 cmdflags;
1301
1302         mrq = slot->mrq;
1303
1304         host->mrq = mrq;
1305
1306         host->pending_events = 0;
1307         host->completed_events = 0;
1308         host->cmd_status = 0;
1309         host->data_status = 0;
1310         host->dir_status = 0;
1311
1312         data = cmd->data;
1313         if (data) {
1314                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1315                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1316                 mci_writel(host, BLKSIZ, data->blksz);
1317         }
1318
1319         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1320
1321         /* this is the first command, send the initialization clock */
1322         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1323                 cmdflags |= SDMMC_CMD_INIT;
1324
1325         if (data) {
1326                 dw_mci_submit_data(host, data);
1327                 wmb(); /* drain writebuffer */
1328         }
1329
1330         dw_mci_start_command(host, cmd, cmdflags);
1331
1332         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1333                 unsigned long irqflags;
1334
1335                 /*
1336                  * Databook says to fail after 2ms w/ no response, but evidence
1337                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1338                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1339                  * is just about to roll over.
1340                  *
1341                  * We do this whole thing under spinlock and only if the
1342                  * command hasn't already completed (indicating the the irq
1343                  * already ran so we don't want the timeout).
1344                  */
1345                 spin_lock_irqsave(&host->irq_lock, irqflags);
1346                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1347                         mod_timer(&host->cmd11_timer,
1348                                 jiffies + msecs_to_jiffies(500) + 1);
1349                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1350         }
1351
1352         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1353 }
1354
1355 static void dw_mci_start_request(struct dw_mci *host,
1356                                  struct dw_mci_slot *slot)
1357 {
1358         struct mmc_request *mrq = slot->mrq;
1359         struct mmc_command *cmd;
1360
1361         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1362         __dw_mci_start_request(host, slot, cmd);
1363 }
1364
1365 /* must be called with host->lock held */
1366 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1367                                  struct mmc_request *mrq)
1368 {
1369         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1370                  host->state);
1371
1372         slot->mrq = mrq;
1373
1374         if (host->state == STATE_WAITING_CMD11_DONE) {
1375                 dev_warn(&slot->mmc->class_dev,
1376                          "Voltage change didn't complete\n");
1377                 /*
1378                  * this case isn't expected to happen, so we can
1379                  * either crash here or just try to continue on
1380                  * in the closest possible state
1381                  */
1382                 host->state = STATE_IDLE;
1383         }
1384
1385         if (host->state == STATE_IDLE) {
1386                 host->state = STATE_SENDING_CMD;
1387                 dw_mci_start_request(host, slot);
1388         } else {
1389                 list_add_tail(&slot->queue_node, &host->queue);
1390         }
1391 }
1392
1393 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1394 {
1395         struct dw_mci_slot *slot = mmc_priv(mmc);
1396         struct dw_mci *host = slot->host;
1397
1398         WARN_ON(slot->mrq);
1399
1400         /*
1401          * The check for card presence and queueing of the request must be
1402          * atomic, otherwise the card could be removed in between and the
1403          * request wouldn't fail until another card was inserted.
1404          */
1405
1406         if (!dw_mci_get_cd(mmc)) {
1407                 mrq->cmd->error = -ENOMEDIUM;
1408                 mmc_request_done(mmc, mrq);
1409                 return;
1410         }
1411
1412         spin_lock_bh(&host->lock);
1413
1414         dw_mci_queue_request(host, slot, mrq);
1415
1416         spin_unlock_bh(&host->lock);
1417 }
1418
1419 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1420 {
1421         struct dw_mci_slot *slot = mmc_priv(mmc);
1422         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1423         u32 regs;
1424         int ret;
1425
1426         switch (ios->bus_width) {
1427         case MMC_BUS_WIDTH_4:
1428                 slot->ctype = SDMMC_CTYPE_4BIT;
1429                 break;
1430         case MMC_BUS_WIDTH_8:
1431                 slot->ctype = SDMMC_CTYPE_8BIT;
1432                 break;
1433         default:
1434                 /* set default 1 bit mode */
1435                 slot->ctype = SDMMC_CTYPE_1BIT;
1436         }
1437
1438         regs = mci_readl(slot->host, UHS_REG);
1439
1440         /* DDR mode set */
1441         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1442             ios->timing == MMC_TIMING_UHS_DDR50 ||
1443             ios->timing == MMC_TIMING_MMC_HS400)
1444                 regs |= ((0x1 << slot->id) << 16);
1445         else
1446                 regs &= ~((0x1 << slot->id) << 16);
1447
1448         mci_writel(slot->host, UHS_REG, regs);
1449         slot->host->timing = ios->timing;
1450
1451         /*
1452          * Use mirror of ios->clock to prevent race with mmc
1453          * core ios update when finding the minimum.
1454          */
1455         slot->clock = ios->clock;
1456
1457         if (drv_data && drv_data->set_ios)
1458                 drv_data->set_ios(slot->host, ios);
1459
1460         switch (ios->power_mode) {
1461         case MMC_POWER_UP:
1462                 if (!IS_ERR(mmc->supply.vmmc)) {
1463                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1464                                         ios->vdd);
1465                         if (ret) {
1466                                 dev_err(slot->host->dev,
1467                                         "failed to enable vmmc regulator\n");
1468                                 /*return, if failed turn on vmmc*/
1469                                 return;
1470                         }
1471                 }
1472                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1473                 regs = mci_readl(slot->host, PWREN);
1474                 regs |= (1 << slot->id);
1475                 mci_writel(slot->host, PWREN, regs);
1476                 break;
1477         case MMC_POWER_ON:
1478                 if (!slot->host->vqmmc_enabled) {
1479                         if (!IS_ERR(mmc->supply.vqmmc)) {
1480                                 ret = regulator_enable(mmc->supply.vqmmc);
1481                                 if (ret < 0)
1482                                         dev_err(slot->host->dev,
1483                                                 "failed to enable vqmmc\n");
1484                                 else
1485                                         slot->host->vqmmc_enabled = true;
1486
1487                         } else {
1488                                 /* Keep track so we don't reset again */
1489                                 slot->host->vqmmc_enabled = true;
1490                         }
1491
1492                         /* Reset our state machine after powering on */
1493                         dw_mci_ctrl_reset(slot->host,
1494                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1495                 }
1496
1497                 /* Adjust clock / bus width after power is up */
1498                 dw_mci_setup_bus(slot, false);
1499
1500                 break;
1501         case MMC_POWER_OFF:
1502                 /* Turn clock off before power goes down */
1503                 dw_mci_setup_bus(slot, false);
1504
1505                 if (!IS_ERR(mmc->supply.vmmc))
1506                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1507
1508                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1509                         regulator_disable(mmc->supply.vqmmc);
1510                 slot->host->vqmmc_enabled = false;
1511
1512                 regs = mci_readl(slot->host, PWREN);
1513                 regs &= ~(1 << slot->id);
1514                 mci_writel(slot->host, PWREN, regs);
1515                 break;
1516         default:
1517                 break;
1518         }
1519
1520         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1521                 slot->host->state = STATE_IDLE;
1522 }
1523
1524 static int dw_mci_card_busy(struct mmc_host *mmc)
1525 {
1526         struct dw_mci_slot *slot = mmc_priv(mmc);
1527         u32 status;
1528
1529         /*
1530          * Check the busy bit which is low when DAT[3:0]
1531          * (the data lines) are 0000
1532          */
1533         status = mci_readl(slot->host, STATUS);
1534
1535         return !!(status & SDMMC_STATUS_BUSY);
1536 }
1537
1538 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1539 {
1540         struct dw_mci_slot *slot = mmc_priv(mmc);
1541         struct dw_mci *host = slot->host;
1542         const struct dw_mci_drv_data *drv_data = host->drv_data;
1543         u32 uhs;
1544         u32 v18 = SDMMC_UHS_18V << slot->id;
1545         int ret;
1546
1547         if (drv_data && drv_data->switch_voltage)
1548                 return drv_data->switch_voltage(mmc, ios);
1549
1550         /*
1551          * Program the voltage.  Note that some instances of dw_mmc may use
1552          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1553          * does no harm but you need to set the regulator directly.  Try both.
1554          */
1555         uhs = mci_readl(host, UHS_REG);
1556         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1557                 uhs &= ~v18;
1558         else
1559                 uhs |= v18;
1560
1561         if (!IS_ERR(mmc->supply.vqmmc)) {
1562                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1563
1564                 if (ret) {
1565                         dev_dbg(&mmc->class_dev,
1566                                          "Regulator set error %d - %s V\n",
1567                                          ret, uhs & v18 ? "1.8" : "3.3");
1568                         return ret;
1569                 }
1570         }
1571         mci_writel(host, UHS_REG, uhs);
1572
1573         return 0;
1574 }
1575
1576 static int dw_mci_get_ro(struct mmc_host *mmc)
1577 {
1578         int read_only;
1579         struct dw_mci_slot *slot = mmc_priv(mmc);
1580         int gpio_ro = mmc_gpio_get_ro(mmc);
1581
1582         /* Use platform get_ro function, else try on board write protect */
1583         if (gpio_ro >= 0)
1584                 read_only = gpio_ro;
1585         else
1586                 read_only =
1587                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1588
1589         dev_dbg(&mmc->class_dev, "card is %s\n",
1590                 read_only ? "read-only" : "read-write");
1591
1592         return read_only;
1593 }
1594
1595 static void dw_mci_hw_reset(struct mmc_host *mmc)
1596 {
1597         struct dw_mci_slot *slot = mmc_priv(mmc);
1598         struct dw_mci *host = slot->host;
1599         int reset;
1600
1601         if (host->use_dma == TRANS_MODE_IDMAC)
1602                 dw_mci_idmac_reset(host);
1603
1604         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1605                                      SDMMC_CTRL_FIFO_RESET))
1606                 return;
1607
1608         /*
1609          * According to eMMC spec, card reset procedure:
1610          * tRstW >= 1us:   RST_n pulse width
1611          * tRSCA >= 200us: RST_n to Command time
1612          * tRSTH >= 1us:   RST_n high period
1613          */
1614         reset = mci_readl(host, RST_N);
1615         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1616         mci_writel(host, RST_N, reset);
1617         usleep_range(1, 2);
1618         reset |= SDMMC_RST_HWACTIVE << slot->id;
1619         mci_writel(host, RST_N, reset);
1620         usleep_range(200, 300);
1621 }
1622
1623 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1624 {
1625         struct dw_mci_slot *slot = mmc_priv(mmc);
1626         struct dw_mci *host = slot->host;
1627
1628         /*
1629          * Low power mode will stop the card clock when idle.  According to the
1630          * description of the CLKENA register we should disable low power mode
1631          * for SDIO cards if we need SDIO interrupts to work.
1632          */
1633         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1634                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1635                 u32 clk_en_a_old;
1636                 u32 clk_en_a;
1637
1638                 clk_en_a_old = mci_readl(host, CLKENA);
1639
1640                 if (card->type == MMC_TYPE_SDIO ||
1641                     card->type == MMC_TYPE_SD_COMBO) {
1642                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1643                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1644                 } else {
1645                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1646                         clk_en_a = clk_en_a_old | clken_low_pwr;
1647                 }
1648
1649                 if (clk_en_a != clk_en_a_old) {
1650                         mci_writel(host, CLKENA, clk_en_a);
1651                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1652                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1653                 }
1654         }
1655 }
1656
1657 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1658 {
1659         struct dw_mci *host = slot->host;
1660         unsigned long irqflags;
1661         u32 int_mask;
1662
1663         spin_lock_irqsave(&host->irq_lock, irqflags);
1664
1665         /* Enable/disable Slot Specific SDIO interrupt */
1666         int_mask = mci_readl(host, INTMASK);
1667         if (enb)
1668                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1669         else
1670                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1671         mci_writel(host, INTMASK, int_mask);
1672
1673         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1674 }
1675
1676 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1677 {
1678         struct dw_mci_slot *slot = mmc_priv(mmc);
1679         struct dw_mci *host = slot->host;
1680
1681         __dw_mci_enable_sdio_irq(slot, enb);
1682
1683         /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1684         if (enb)
1685                 pm_runtime_get_noresume(host->dev);
1686         else
1687                 pm_runtime_put_noidle(host->dev);
1688 }
1689
1690 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1691 {
1692         struct dw_mci_slot *slot = mmc_priv(mmc);
1693
1694         __dw_mci_enable_sdio_irq(slot, 1);
1695 }
1696
1697 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1698 {
1699         struct dw_mci_slot *slot = mmc_priv(mmc);
1700         struct dw_mci *host = slot->host;
1701         const struct dw_mci_drv_data *drv_data = host->drv_data;
1702         int err = -EINVAL;
1703
1704         if (drv_data && drv_data->execute_tuning)
1705                 err = drv_data->execute_tuning(slot, opcode);
1706         return err;
1707 }
1708
1709 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1710                                        struct mmc_ios *ios)
1711 {
1712         struct dw_mci_slot *slot = mmc_priv(mmc);
1713         struct dw_mci *host = slot->host;
1714         const struct dw_mci_drv_data *drv_data = host->drv_data;
1715
1716         if (drv_data && drv_data->prepare_hs400_tuning)
1717                 return drv_data->prepare_hs400_tuning(host, ios);
1718
1719         return 0;
1720 }
1721
1722 static bool dw_mci_reset(struct dw_mci *host)
1723 {
1724         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1725         bool ret = false;
1726         u32 status = 0;
1727
1728         /*
1729          * Resetting generates a block interrupt, hence setting
1730          * the scatter-gather pointer to NULL.
1731          */
1732         if (host->sg) {
1733                 sg_miter_stop(&host->sg_miter);
1734                 host->sg = NULL;
1735         }
1736
1737         if (host->use_dma)
1738                 flags |= SDMMC_CTRL_DMA_RESET;
1739
1740         if (dw_mci_ctrl_reset(host, flags)) {
1741                 /*
1742                  * In all cases we clear the RAWINTS
1743                  * register to clear any interrupts.
1744                  */
1745                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1746
1747                 if (!host->use_dma) {
1748                         ret = true;
1749                         goto ciu_out;
1750                 }
1751
1752                 /* Wait for dma_req to be cleared */
1753                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1754                                               status,
1755                                               !(status & SDMMC_STATUS_DMA_REQ),
1756                                               1, 500 * USEC_PER_MSEC)) {
1757                         dev_err(host->dev,
1758                                 "%s: Timeout waiting for dma_req to be cleared\n",
1759                                 __func__);
1760                         goto ciu_out;
1761                 }
1762
1763                 /* when using DMA next we reset the fifo again */
1764                 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1765                         goto ciu_out;
1766         } else {
1767                 /* if the controller reset bit did clear, then set clock regs */
1768                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1769                         dev_err(host->dev,
1770                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1771                                 __func__);
1772                         goto ciu_out;
1773                 }
1774         }
1775
1776         if (host->use_dma == TRANS_MODE_IDMAC)
1777                 /* It is also recommended that we reset and reprogram idmac */
1778                 dw_mci_idmac_reset(host);
1779
1780         ret = true;
1781
1782 ciu_out:
1783         /* After a CTRL reset we need to have CIU set clock registers  */
1784         mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1785
1786         return ret;
1787 }
1788
1789 static const struct mmc_host_ops dw_mci_ops = {
1790         .request                = dw_mci_request,
1791         .pre_req                = dw_mci_pre_req,
1792         .post_req               = dw_mci_post_req,
1793         .set_ios                = dw_mci_set_ios,
1794         .get_ro                 = dw_mci_get_ro,
1795         .get_cd                 = dw_mci_get_cd,
1796         .hw_reset               = dw_mci_hw_reset,
1797         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1798         .ack_sdio_irq           = dw_mci_ack_sdio_irq,
1799         .execute_tuning         = dw_mci_execute_tuning,
1800         .card_busy              = dw_mci_card_busy,
1801         .start_signal_voltage_switch = dw_mci_switch_voltage,
1802         .init_card              = dw_mci_init_card,
1803         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1804 };
1805
1806 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1807         __releases(&host->lock)
1808         __acquires(&host->lock)
1809 {
1810         struct dw_mci_slot *slot;
1811         struct mmc_host *prev_mmc = host->slot->mmc;
1812
1813         WARN_ON(host->cmd || host->data);
1814
1815         host->slot->mrq = NULL;
1816         host->mrq = NULL;
1817         if (!list_empty(&host->queue)) {
1818                 slot = list_entry(host->queue.next,
1819                                   struct dw_mci_slot, queue_node);
1820                 list_del(&slot->queue_node);
1821                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1822                          mmc_hostname(slot->mmc));
1823                 host->state = STATE_SENDING_CMD;
1824                 dw_mci_start_request(host, slot);
1825         } else {
1826                 dev_vdbg(host->dev, "list empty\n");
1827
1828                 if (host->state == STATE_SENDING_CMD11)
1829                         host->state = STATE_WAITING_CMD11_DONE;
1830                 else
1831                         host->state = STATE_IDLE;
1832         }
1833
1834         spin_unlock(&host->lock);
1835         mmc_request_done(prev_mmc, mrq);
1836         spin_lock(&host->lock);
1837 }
1838
1839 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1840 {
1841         u32 status = host->cmd_status;
1842
1843         host->cmd_status = 0;
1844
1845         /* Read the response from the card (up to 16 bytes) */
1846         if (cmd->flags & MMC_RSP_PRESENT) {
1847                 if (cmd->flags & MMC_RSP_136) {
1848                         cmd->resp[3] = mci_readl(host, RESP0);
1849                         cmd->resp[2] = mci_readl(host, RESP1);
1850                         cmd->resp[1] = mci_readl(host, RESP2);
1851                         cmd->resp[0] = mci_readl(host, RESP3);
1852                 } else {
1853                         cmd->resp[0] = mci_readl(host, RESP0);
1854                         cmd->resp[1] = 0;
1855                         cmd->resp[2] = 0;
1856                         cmd->resp[3] = 0;
1857                 }
1858         }
1859
1860         if (status & SDMMC_INT_RTO)
1861                 cmd->error = -ETIMEDOUT;
1862         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1863                 cmd->error = -EILSEQ;
1864         else if (status & SDMMC_INT_RESP_ERR)
1865                 cmd->error = -EIO;
1866         else
1867                 cmd->error = 0;
1868
1869         return cmd->error;
1870 }
1871
1872 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1873 {
1874         u32 status = host->data_status;
1875
1876         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1877                 if (status & SDMMC_INT_DRTO) {
1878                         data->error = -ETIMEDOUT;
1879                 } else if (status & SDMMC_INT_DCRC) {
1880                         data->error = -EILSEQ;
1881                 } else if (status & SDMMC_INT_EBE) {
1882                         if (host->dir_status ==
1883                                 DW_MCI_SEND_STATUS) {
1884                                 /*
1885                                  * No data CRC status was returned.
1886                                  * The number of bytes transferred
1887                                  * will be exaggerated in PIO mode.
1888                                  */
1889                                 data->bytes_xfered = 0;
1890                                 data->error = -ETIMEDOUT;
1891                         } else if (host->dir_status ==
1892                                         DW_MCI_RECV_STATUS) {
1893                                 data->error = -EILSEQ;
1894                         }
1895                 } else {
1896                         /* SDMMC_INT_SBE is included */
1897                         data->error = -EILSEQ;
1898                 }
1899
1900                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1901
1902                 /*
1903                  * After an error, there may be data lingering
1904                  * in the FIFO
1905                  */
1906                 dw_mci_reset(host);
1907         } else {
1908                 data->bytes_xfered = data->blocks * data->blksz;
1909                 data->error = 0;
1910         }
1911
1912         return data->error;
1913 }
1914
1915 static void dw_mci_set_drto(struct dw_mci *host)
1916 {
1917         unsigned int drto_clks;
1918         unsigned int drto_ms;
1919
1920         drto_clks = mci_readl(host, TMOUT) >> 8;
1921         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1922
1923         /* add a bit spare time */
1924         drto_ms += 10;
1925
1926         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1927 }
1928
1929 static void dw_mci_tasklet_func(unsigned long priv)
1930 {
1931         struct dw_mci *host = (struct dw_mci *)priv;
1932         struct mmc_data *data;
1933         struct mmc_command *cmd;
1934         struct mmc_request *mrq;
1935         enum dw_mci_state state;
1936         enum dw_mci_state prev_state;
1937         unsigned int err;
1938
1939         spin_lock(&host->lock);
1940
1941         state = host->state;
1942         data = host->data;
1943         mrq = host->mrq;
1944
1945         do {
1946                 prev_state = state;
1947
1948                 switch (state) {
1949                 case STATE_IDLE:
1950                 case STATE_WAITING_CMD11_DONE:
1951                         break;
1952
1953                 case STATE_SENDING_CMD11:
1954                 case STATE_SENDING_CMD:
1955                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1956                                                 &host->pending_events))
1957                                 break;
1958
1959                         cmd = host->cmd;
1960                         host->cmd = NULL;
1961                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1962                         err = dw_mci_command_complete(host, cmd);
1963                         if (cmd == mrq->sbc && !err) {
1964                                 prev_state = state = STATE_SENDING_CMD;
1965                                 __dw_mci_start_request(host, host->slot,
1966                                                        mrq->cmd);
1967                                 goto unlock;
1968                         }
1969
1970                         if (cmd->data && err) {
1971                                 /*
1972                                  * During UHS tuning sequence, sending the stop
1973                                  * command after the response CRC error would
1974                                  * throw the system into a confused state
1975                                  * causing all future tuning phases to report
1976                                  * failure.
1977                                  *
1978                                  * In such case controller will move into a data
1979                                  * transfer state after a response error or
1980                                  * response CRC error. Let's let that finish
1981                                  * before trying to send a stop, so we'll go to
1982                                  * STATE_SENDING_DATA.
1983                                  *
1984                                  * Although letting the data transfer take place
1985                                  * will waste a bit of time (we already know
1986                                  * the command was bad), it can't cause any
1987                                  * errors since it's possible it would have
1988                                  * taken place anyway if this tasklet got
1989                                  * delayed. Allowing the transfer to take place
1990                                  * avoids races and keeps things simple.
1991                                  */
1992                                 if ((err != -ETIMEDOUT) &&
1993                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1994                                         state = STATE_SENDING_DATA;
1995                                         continue;
1996                                 }
1997
1998                                 dw_mci_stop_dma(host);
1999                                 send_stop_abort(host, data);
2000                                 state = STATE_SENDING_STOP;
2001                                 break;
2002                         }
2003
2004                         if (!cmd->data || err) {
2005                                 dw_mci_request_end(host, mrq);
2006                                 goto unlock;
2007                         }
2008
2009                         prev_state = state = STATE_SENDING_DATA;
2010                         /* fall through */
2011
2012                 case STATE_SENDING_DATA:
2013                         /*
2014                          * We could get a data error and never a transfer
2015                          * complete so we'd better check for it here.
2016                          *
2017                          * Note that we don't really care if we also got a
2018                          * transfer complete; stopping the DMA and sending an
2019                          * abort won't hurt.
2020                          */
2021                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2022                                                &host->pending_events)) {
2023                                 dw_mci_stop_dma(host);
2024                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2025                                                            SDMMC_INT_EBE)))
2026                                         send_stop_abort(host, data);
2027                                 state = STATE_DATA_ERROR;
2028                                 break;
2029                         }
2030
2031                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2032                                                 &host->pending_events)) {
2033                                 /*
2034                                  * If all data-related interrupts don't come
2035                                  * within the given time in reading data state.
2036                                  */
2037                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2038                                         dw_mci_set_drto(host);
2039                                 break;
2040                         }
2041
2042                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2043
2044                         /*
2045                          * Handle an EVENT_DATA_ERROR that might have shown up
2046                          * before the transfer completed.  This might not have
2047                          * been caught by the check above because the interrupt
2048                          * could have gone off between the previous check and
2049                          * the check for transfer complete.
2050                          *
2051                          * Technically this ought not be needed assuming we
2052                          * get a DATA_COMPLETE eventually (we'll notice the
2053                          * error and end the request), but it shouldn't hurt.
2054                          *
2055                          * This has the advantage of sending the stop command.
2056                          */
2057                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2058                                                &host->pending_events)) {
2059                                 dw_mci_stop_dma(host);
2060                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2061                                                            SDMMC_INT_EBE)))
2062                                         send_stop_abort(host, data);
2063                                 state = STATE_DATA_ERROR;
2064                                 break;
2065                         }
2066                         prev_state = state = STATE_DATA_BUSY;
2067
2068                         /* fall through */
2069
2070                 case STATE_DATA_BUSY:
2071                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2072                                                 &host->pending_events)) {
2073                                 /*
2074                                  * If data error interrupt comes but data over
2075                                  * interrupt doesn't come within the given time.
2076                                  * in reading data state.
2077                                  */
2078                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2079                                         dw_mci_set_drto(host);
2080                                 break;
2081                         }
2082
2083                         host->data = NULL;
2084                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2085                         err = dw_mci_data_complete(host, data);
2086
2087                         if (!err) {
2088                                 if (!data->stop || mrq->sbc) {
2089                                         if (mrq->sbc && data->stop)
2090                                                 data->stop->error = 0;
2091                                         dw_mci_request_end(host, mrq);
2092                                         goto unlock;
2093                                 }
2094
2095                                 /* stop command for open-ended transfer*/
2096                                 if (data->stop)
2097                                         send_stop_abort(host, data);
2098                         } else {
2099                                 /*
2100                                  * If we don't have a command complete now we'll
2101                                  * never get one since we just reset everything;
2102                                  * better end the request.
2103                                  *
2104                                  * If we do have a command complete we'll fall
2105                                  * through to the SENDING_STOP command and
2106                                  * everything will be peachy keen.
2107                                  */
2108                                 if (!test_bit(EVENT_CMD_COMPLETE,
2109                                               &host->pending_events)) {
2110                                         host->cmd = NULL;
2111                                         dw_mci_request_end(host, mrq);
2112                                         goto unlock;
2113                                 }
2114                         }
2115
2116                         /*
2117                          * If err has non-zero,
2118                          * stop-abort command has been already issued.
2119                          */
2120                         prev_state = state = STATE_SENDING_STOP;
2121
2122                         /* fall through */
2123
2124                 case STATE_SENDING_STOP:
2125                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2126                                                 &host->pending_events))
2127                                 break;
2128
2129                         /* CMD error in data command */
2130                         if (mrq->cmd->error && mrq->data)
2131                                 dw_mci_reset(host);
2132
2133                         host->cmd = NULL;
2134                         host->data = NULL;
2135
2136                         if (!mrq->sbc && mrq->stop)
2137                                 dw_mci_command_complete(host, mrq->stop);
2138                         else
2139                                 host->cmd_status = 0;
2140
2141                         dw_mci_request_end(host, mrq);
2142                         goto unlock;
2143
2144                 case STATE_DATA_ERROR:
2145                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2146                                                 &host->pending_events))
2147                                 break;
2148
2149                         state = STATE_DATA_BUSY;
2150                         break;
2151                 }
2152         } while (state != prev_state);
2153
2154         host->state = state;
2155 unlock:
2156         spin_unlock(&host->lock);
2157
2158 }
2159
2160 /* push final bytes to part_buf, only use during push */
2161 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2162 {
2163         memcpy((void *)&host->part_buf, buf, cnt);
2164         host->part_buf_count = cnt;
2165 }
2166
2167 /* append bytes to part_buf, only use during push */
2168 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2169 {
2170         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2171         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2172         host->part_buf_count += cnt;
2173         return cnt;
2174 }
2175
2176 /* pull first bytes from part_buf, only use during pull */
2177 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2178 {
2179         cnt = min_t(int, cnt, host->part_buf_count);
2180         if (cnt) {
2181                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2182                        cnt);
2183                 host->part_buf_count -= cnt;
2184                 host->part_buf_start += cnt;
2185         }
2186         return cnt;
2187 }
2188
2189 /* pull final bytes from the part_buf, assuming it's just been filled */
2190 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2191 {
2192         memcpy(buf, &host->part_buf, cnt);
2193         host->part_buf_start = cnt;
2194         host->part_buf_count = (1 << host->data_shift) - cnt;
2195 }
2196
2197 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2198 {
2199         struct mmc_data *data = host->data;
2200         int init_cnt = cnt;
2201
2202         /* try and push anything in the part_buf */
2203         if (unlikely(host->part_buf_count)) {
2204                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2205
2206                 buf += len;
2207                 cnt -= len;
2208                 if (host->part_buf_count == 2) {
2209                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2210                         host->part_buf_count = 0;
2211                 }
2212         }
2213 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2214         if (unlikely((unsigned long)buf & 0x1)) {
2215                 while (cnt >= 2) {
2216                         u16 aligned_buf[64];
2217                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2218                         int items = len >> 1;
2219                         int i;
2220                         /* memcpy from input buffer into aligned buffer */
2221                         memcpy(aligned_buf, buf, len);
2222                         buf += len;
2223                         cnt -= len;
2224                         /* push data from aligned buffer into fifo */
2225                         for (i = 0; i < items; ++i)
2226                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2227                 }
2228         } else
2229 #endif
2230         {
2231                 u16 *pdata = buf;
2232
2233                 for (; cnt >= 2; cnt -= 2)
2234                         mci_fifo_writew(host->fifo_reg, *pdata++);
2235                 buf = pdata;
2236         }
2237         /* put anything remaining in the part_buf */
2238         if (cnt) {
2239                 dw_mci_set_part_bytes(host, buf, cnt);
2240                  /* Push data if we have reached the expected data length */
2241                 if ((data->bytes_xfered + init_cnt) ==
2242                     (data->blksz * data->blocks))
2243                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2244         }
2245 }
2246
2247 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2248 {
2249 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2250         if (unlikely((unsigned long)buf & 0x1)) {
2251                 while (cnt >= 2) {
2252                         /* pull data from fifo into aligned buffer */
2253                         u16 aligned_buf[64];
2254                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2255                         int items = len >> 1;
2256                         int i;
2257
2258                         for (i = 0; i < items; ++i)
2259                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2260                         /* memcpy from aligned buffer into output buffer */
2261                         memcpy(buf, aligned_buf, len);
2262                         buf += len;
2263                         cnt -= len;
2264                 }
2265         } else
2266 #endif
2267         {
2268                 u16 *pdata = buf;
2269
2270                 for (; cnt >= 2; cnt -= 2)
2271                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2272                 buf = pdata;
2273         }
2274         if (cnt) {
2275                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2276                 dw_mci_pull_final_bytes(host, buf, cnt);
2277         }
2278 }
2279
2280 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2281 {
2282         struct mmc_data *data = host->data;
2283         int init_cnt = cnt;
2284
2285         /* try and push anything in the part_buf */
2286         if (unlikely(host->part_buf_count)) {
2287                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2288
2289                 buf += len;
2290                 cnt -= len;
2291                 if (host->part_buf_count == 4) {
2292                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2293                         host->part_buf_count = 0;
2294                 }
2295         }
2296 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2297         if (unlikely((unsigned long)buf & 0x3)) {
2298                 while (cnt >= 4) {
2299                         u32 aligned_buf[32];
2300                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2301                         int items = len >> 2;
2302                         int i;
2303                         /* memcpy from input buffer into aligned buffer */
2304                         memcpy(aligned_buf, buf, len);
2305                         buf += len;
2306                         cnt -= len;
2307                         /* push data from aligned buffer into fifo */
2308                         for (i = 0; i < items; ++i)
2309                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2310                 }
2311         } else
2312 #endif
2313         {
2314                 u32 *pdata = buf;
2315
2316                 for (; cnt >= 4; cnt -= 4)
2317                         mci_fifo_writel(host->fifo_reg, *pdata++);
2318                 buf = pdata;
2319         }
2320         /* put anything remaining in the part_buf */
2321         if (cnt) {
2322                 dw_mci_set_part_bytes(host, buf, cnt);
2323                  /* Push data if we have reached the expected data length */
2324                 if ((data->bytes_xfered + init_cnt) ==
2325                     (data->blksz * data->blocks))
2326                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2327         }
2328 }
2329
2330 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2331 {
2332 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2333         if (unlikely((unsigned long)buf & 0x3)) {
2334                 while (cnt >= 4) {
2335                         /* pull data from fifo into aligned buffer */
2336                         u32 aligned_buf[32];
2337                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2338                         int items = len >> 2;
2339                         int i;
2340
2341                         for (i = 0; i < items; ++i)
2342                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2343                         /* memcpy from aligned buffer into output buffer */
2344                         memcpy(buf, aligned_buf, len);
2345                         buf += len;
2346                         cnt -= len;
2347                 }
2348         } else
2349 #endif
2350         {
2351                 u32 *pdata = buf;
2352
2353                 for (; cnt >= 4; cnt -= 4)
2354                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2355                 buf = pdata;
2356         }
2357         if (cnt) {
2358                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2359                 dw_mci_pull_final_bytes(host, buf, cnt);
2360         }
2361 }
2362
2363 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2364 {
2365         struct mmc_data *data = host->data;
2366         int init_cnt = cnt;
2367
2368         /* try and push anything in the part_buf */
2369         if (unlikely(host->part_buf_count)) {
2370                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2371
2372                 buf += len;
2373                 cnt -= len;
2374
2375                 if (host->part_buf_count == 8) {
2376                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2377                         host->part_buf_count = 0;
2378                 }
2379         }
2380 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2381         if (unlikely((unsigned long)buf & 0x7)) {
2382                 while (cnt >= 8) {
2383                         u64 aligned_buf[16];
2384                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2385                         int items = len >> 3;
2386                         int i;
2387                         /* memcpy from input buffer into aligned buffer */
2388                         memcpy(aligned_buf, buf, len);
2389                         buf += len;
2390                         cnt -= len;
2391                         /* push data from aligned buffer into fifo */
2392                         for (i = 0; i < items; ++i)
2393                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2394                 }
2395         } else
2396 #endif
2397         {
2398                 u64 *pdata = buf;
2399
2400                 for (; cnt >= 8; cnt -= 8)
2401                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2402                 buf = pdata;
2403         }
2404         /* put anything remaining in the part_buf */
2405         if (cnt) {
2406                 dw_mci_set_part_bytes(host, buf, cnt);
2407                 /* Push data if we have reached the expected data length */
2408                 if ((data->bytes_xfered + init_cnt) ==
2409                     (data->blksz * data->blocks))
2410                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2411         }
2412 }
2413
2414 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2415 {
2416 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2417         if (unlikely((unsigned long)buf & 0x7)) {
2418                 while (cnt >= 8) {
2419                         /* pull data from fifo into aligned buffer */
2420                         u64 aligned_buf[16];
2421                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2422                         int items = len >> 3;
2423                         int i;
2424
2425                         for (i = 0; i < items; ++i)
2426                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2427
2428                         /* memcpy from aligned buffer into output buffer */
2429                         memcpy(buf, aligned_buf, len);
2430                         buf += len;
2431                         cnt -= len;
2432                 }
2433         } else
2434 #endif
2435         {
2436                 u64 *pdata = buf;
2437
2438                 for (; cnt >= 8; cnt -= 8)
2439                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2440                 buf = pdata;
2441         }
2442         if (cnt) {
2443                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2444                 dw_mci_pull_final_bytes(host, buf, cnt);
2445         }
2446 }
2447
2448 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2449 {
2450         int len;
2451
2452         /* get remaining partial bytes */
2453         len = dw_mci_pull_part_bytes(host, buf, cnt);
2454         if (unlikely(len == cnt))
2455                 return;
2456         buf += len;
2457         cnt -= len;
2458
2459         /* get the rest of the data */
2460         host->pull_data(host, buf, cnt);
2461 }
2462
2463 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2464 {
2465         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2466         void *buf;
2467         unsigned int offset;
2468         struct mmc_data *data = host->data;
2469         int shift = host->data_shift;
2470         u32 status;
2471         unsigned int len;
2472         unsigned int remain, fcnt;
2473
2474         do {
2475                 if (!sg_miter_next(sg_miter))
2476                         goto done;
2477
2478                 host->sg = sg_miter->piter.sg;
2479                 buf = sg_miter->addr;
2480                 remain = sg_miter->length;
2481                 offset = 0;
2482
2483                 do {
2484                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2485                                         << shift) + host->part_buf_count;
2486                         len = min(remain, fcnt);
2487                         if (!len)
2488                                 break;
2489                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2490                         data->bytes_xfered += len;
2491                         offset += len;
2492                         remain -= len;
2493                 } while (remain);
2494
2495                 sg_miter->consumed = offset;
2496                 status = mci_readl(host, MINTSTS);
2497                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2498         /* if the RXDR is ready read again */
2499         } while ((status & SDMMC_INT_RXDR) ||
2500                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2501
2502         if (!remain) {
2503                 if (!sg_miter_next(sg_miter))
2504                         goto done;
2505                 sg_miter->consumed = 0;
2506         }
2507         sg_miter_stop(sg_miter);
2508         return;
2509
2510 done:
2511         sg_miter_stop(sg_miter);
2512         host->sg = NULL;
2513         smp_wmb(); /* drain writebuffer */
2514         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2515 }
2516
2517 static void dw_mci_write_data_pio(struct dw_mci *host)
2518 {
2519         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2520         void *buf;
2521         unsigned int offset;
2522         struct mmc_data *data = host->data;
2523         int shift = host->data_shift;
2524         u32 status;
2525         unsigned int len;
2526         unsigned int fifo_depth = host->fifo_depth;
2527         unsigned int remain, fcnt;
2528
2529         do {
2530                 if (!sg_miter_next(sg_miter))
2531                         goto done;
2532
2533                 host->sg = sg_miter->piter.sg;
2534                 buf = sg_miter->addr;
2535                 remain = sg_miter->length;
2536                 offset = 0;
2537
2538                 do {
2539                         fcnt = ((fifo_depth -
2540                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2541                                         << shift) - host->part_buf_count;
2542                         len = min(remain, fcnt);
2543                         if (!len)
2544                                 break;
2545                         host->push_data(host, (void *)(buf + offset), len);
2546                         data->bytes_xfered += len;
2547                         offset += len;
2548                         remain -= len;
2549                 } while (remain);
2550
2551                 sg_miter->consumed = offset;
2552                 status = mci_readl(host, MINTSTS);
2553                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2554         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2555
2556         if (!remain) {
2557                 if (!sg_miter_next(sg_miter))
2558                         goto done;
2559                 sg_miter->consumed = 0;
2560         }
2561         sg_miter_stop(sg_miter);
2562         return;
2563
2564 done:
2565         sg_miter_stop(sg_miter);
2566         host->sg = NULL;
2567         smp_wmb(); /* drain writebuffer */
2568         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2569 }
2570
2571 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2572 {
2573         if (!host->cmd_status)
2574                 host->cmd_status = status;
2575
2576         smp_wmb(); /* drain writebuffer */
2577
2578         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2579         tasklet_schedule(&host->tasklet);
2580 }
2581
2582 static void dw_mci_handle_cd(struct dw_mci *host)
2583 {
2584         struct dw_mci_slot *slot = host->slot;
2585
2586         if (slot->mmc->ops->card_event)
2587                 slot->mmc->ops->card_event(slot->mmc);
2588         mmc_detect_change(slot->mmc,
2589                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2590 }
2591
2592 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2593 {
2594         struct dw_mci *host = dev_id;
2595         u32 pending;
2596         struct dw_mci_slot *slot = host->slot;
2597
2598         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2599
2600         if (pending) {
2601                 /* Check volt switch first, since it can look like an error */
2602                 if ((host->state == STATE_SENDING_CMD11) &&
2603                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2604                         unsigned long irqflags;
2605
2606                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2607                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2608
2609                         /*
2610                          * Hold the lock; we know cmd11_timer can't be kicked
2611                          * off after the lock is released, so safe to delete.
2612                          */
2613                         spin_lock_irqsave(&host->irq_lock, irqflags);
2614                         dw_mci_cmd_interrupt(host, pending);
2615                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2616
2617                         del_timer(&host->cmd11_timer);
2618                 }
2619
2620                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2621                         del_timer(&host->cto_timer);
2622                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2623                         host->cmd_status = pending;
2624                         smp_wmb(); /* drain writebuffer */
2625                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2626                 }
2627
2628                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2629                         /* if there is an error report DATA_ERROR */
2630                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2631                         host->data_status = pending;
2632                         smp_wmb(); /* drain writebuffer */
2633                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2634                         tasklet_schedule(&host->tasklet);
2635                 }
2636
2637                 if (pending & SDMMC_INT_DATA_OVER) {
2638                         del_timer(&host->dto_timer);
2639
2640                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2641                         if (!host->data_status)
2642                                 host->data_status = pending;
2643                         smp_wmb(); /* drain writebuffer */
2644                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2645                                 if (host->sg != NULL)
2646                                         dw_mci_read_data_pio(host, true);
2647                         }
2648                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2649                         tasklet_schedule(&host->tasklet);
2650                 }
2651
2652                 if (pending & SDMMC_INT_RXDR) {
2653                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2654                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2655                                 dw_mci_read_data_pio(host, false);
2656                 }
2657
2658                 if (pending & SDMMC_INT_TXDR) {
2659                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2660                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2661                                 dw_mci_write_data_pio(host);
2662                 }
2663
2664                 if (pending & SDMMC_INT_CMD_DONE) {
2665                         del_timer(&host->cto_timer);
2666                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2667                         dw_mci_cmd_interrupt(host, pending);
2668                 }
2669
2670                 if (pending & SDMMC_INT_CD) {
2671                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2672                         dw_mci_handle_cd(host);
2673                 }
2674
2675                 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2676                         mci_writel(host, RINTSTS,
2677                                    SDMMC_INT_SDIO(slot->sdio_id));
2678                         __dw_mci_enable_sdio_irq(slot, 0);
2679                         sdio_signal_irq(slot->mmc);
2680                 }
2681
2682         }
2683
2684         if (host->use_dma != TRANS_MODE_IDMAC)
2685                 return IRQ_HANDLED;
2686
2687         /* Handle IDMA interrupts */
2688         if (host->dma_64bit_address == 1) {
2689                 pending = mci_readl(host, IDSTS64);
2690                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2691                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2692                                                         SDMMC_IDMAC_INT_RI);
2693                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2694                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2695                                 host->dma_ops->complete((void *)host);
2696                 }
2697         } else {
2698                 pending = mci_readl(host, IDSTS);
2699                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2700                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2701                                                         SDMMC_IDMAC_INT_RI);
2702                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2703                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2704                                 host->dma_ops->complete((void *)host);
2705                 }
2706         }
2707
2708         return IRQ_HANDLED;
2709 }
2710
2711 static int dw_mci_init_slot(struct dw_mci *host)
2712 {
2713         struct mmc_host *mmc;
2714         struct dw_mci_slot *slot;
2715         const struct dw_mci_drv_data *drv_data = host->drv_data;
2716         int ctrl_id, ret;
2717         u32 freq[2];
2718
2719         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2720         if (!mmc)
2721                 return -ENOMEM;
2722
2723         slot = mmc_priv(mmc);
2724         slot->id = 0;
2725         slot->sdio_id = host->sdio_id0 + slot->id;
2726         slot->mmc = mmc;
2727         slot->host = host;
2728         host->slot = slot;
2729
2730         mmc->ops = &dw_mci_ops;
2731         if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2732                                            freq, 2)) {
2733                 mmc->f_min = DW_MCI_FREQ_MIN;
2734                 mmc->f_max = DW_MCI_FREQ_MAX;
2735         } else {
2736                 dev_info(host->dev,
2737                         "'clock-freq-min-max' property was deprecated.\n");
2738                 mmc->f_min = freq[0];
2739                 mmc->f_max = freq[1];
2740         }
2741
2742         /*if there are external regulators, get them*/
2743         ret = mmc_regulator_get_supply(mmc);
2744         if (ret == -EPROBE_DEFER)
2745                 goto err_host_allocated;
2746
2747         if (!mmc->ocr_avail)
2748                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2749
2750         if (host->pdata->caps)
2751                 mmc->caps = host->pdata->caps;
2752
2753         /*
2754          * Support MMC_CAP_ERASE by default.
2755          * It needs to use trim/discard/erase commands.
2756          */
2757         mmc->caps |= MMC_CAP_ERASE;
2758
2759         if (host->pdata->pm_caps)
2760                 mmc->pm_caps = host->pdata->pm_caps;
2761
2762         if (host->dev->of_node) {
2763                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2764                 if (ctrl_id < 0)
2765                         ctrl_id = 0;
2766         } else {
2767                 ctrl_id = to_platform_device(host->dev)->id;
2768         }
2769         if (drv_data && drv_data->caps)
2770                 mmc->caps |= drv_data->caps[ctrl_id];
2771
2772         if (host->pdata->caps2)
2773                 mmc->caps2 = host->pdata->caps2;
2774
2775         ret = mmc_of_parse(mmc);
2776         if (ret)
2777                 goto err_host_allocated;
2778
2779         /* Process SDIO IRQs through the sdio_irq_work. */
2780         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2781                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2782
2783         /* Useful defaults if platform data is unset. */
2784         if (host->use_dma == TRANS_MODE_IDMAC) {
2785                 mmc->max_segs = host->ring_size;
2786                 mmc->max_blk_size = 65535;
2787                 mmc->max_seg_size = 0x1000;
2788                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2789                 mmc->max_blk_count = mmc->max_req_size / 512;
2790         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2791                 mmc->max_segs = 64;
2792                 mmc->max_blk_size = 65535;
2793                 mmc->max_blk_count = 65535;
2794                 mmc->max_req_size =
2795                                 mmc->max_blk_size * mmc->max_blk_count;
2796                 mmc->max_seg_size = mmc->max_req_size;
2797         } else {
2798                 /* TRANS_MODE_PIO */
2799                 mmc->max_segs = 64;
2800                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2801                 mmc->max_blk_count = 512;
2802                 mmc->max_req_size = mmc->max_blk_size *
2803                                     mmc->max_blk_count;
2804                 mmc->max_seg_size = mmc->max_req_size;
2805         }
2806
2807         dw_mci_get_cd(mmc);
2808
2809         ret = mmc_add_host(mmc);
2810         if (ret)
2811                 goto err_host_allocated;
2812
2813 #if defined(CONFIG_DEBUG_FS)
2814         dw_mci_init_debugfs(slot);
2815 #endif
2816
2817         return 0;
2818
2819 err_host_allocated:
2820         mmc_free_host(mmc);
2821         return ret;
2822 }
2823
2824 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2825 {
2826         /* Debugfs stuff is cleaned up by mmc core */
2827         mmc_remove_host(slot->mmc);
2828         slot->host->slot = NULL;
2829         mmc_free_host(slot->mmc);
2830 }
2831
2832 static void dw_mci_init_dma(struct dw_mci *host)
2833 {
2834         int addr_config;
2835         struct device *dev = host->dev;
2836
2837         /*
2838         * Check tansfer mode from HCON[17:16]
2839         * Clear the ambiguous description of dw_mmc databook:
2840         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2841         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2842         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2843         * 2b'11: Non DW DMA Interface -> pio only
2844         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2845         * simpler request/acknowledge handshake mechanism and both of them
2846         * are regarded as external dma master for dw_mmc.
2847         */
2848         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2849         if (host->use_dma == DMA_INTERFACE_IDMA) {
2850                 host->use_dma = TRANS_MODE_IDMAC;
2851         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2852                    host->use_dma == DMA_INTERFACE_GDMA) {
2853                 host->use_dma = TRANS_MODE_EDMAC;
2854         } else {
2855                 goto no_dma;
2856         }
2857
2858         /* Determine which DMA interface to use */
2859         if (host->use_dma == TRANS_MODE_IDMAC) {
2860                 /*
2861                 * Check ADDR_CONFIG bit in HCON to find
2862                 * IDMAC address bus width
2863                 */
2864                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2865
2866                 if (addr_config == 1) {
2867                         /* host supports IDMAC in 64-bit address mode */
2868                         host->dma_64bit_address = 1;
2869                         dev_info(host->dev,
2870                                  "IDMAC supports 64-bit address mode.\n");
2871                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2872                                 dma_set_coherent_mask(host->dev,
2873                                                       DMA_BIT_MASK(64));
2874                 } else {
2875                         /* host supports IDMAC in 32-bit address mode */
2876                         host->dma_64bit_address = 0;
2877                         dev_info(host->dev,
2878                                  "IDMAC supports 32-bit address mode.\n");
2879                 }
2880
2881                 /* Alloc memory for sg translation */
2882                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2883                                                    DESC_RING_BUF_SZ,
2884                                                    &host->sg_dma, GFP_KERNEL);
2885                 if (!host->sg_cpu) {
2886                         dev_err(host->dev,
2887                                 "%s: could not alloc DMA memory\n",
2888                                 __func__);
2889                         goto no_dma;
2890                 }
2891
2892                 host->dma_ops = &dw_mci_idmac_ops;
2893                 dev_info(host->dev, "Using internal DMA controller.\n");
2894         } else {
2895                 /* TRANS_MODE_EDMAC: check dma bindings again */
2896                 if ((device_property_read_string_array(dev, "dma-names",
2897                                                        NULL, 0) < 0) ||
2898                     !device_property_present(dev, "dmas")) {
2899                         goto no_dma;
2900                 }
2901                 host->dma_ops = &dw_mci_edmac_ops;
2902                 dev_info(host->dev, "Using external DMA controller.\n");
2903         }
2904
2905         if (host->dma_ops->init && host->dma_ops->start &&
2906             host->dma_ops->stop && host->dma_ops->cleanup) {
2907                 if (host->dma_ops->init(host)) {
2908                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2909                                 __func__);
2910                         goto no_dma;
2911                 }
2912         } else {
2913                 dev_err(host->dev, "DMA initialization not found.\n");
2914                 goto no_dma;
2915         }
2916
2917         return;
2918
2919 no_dma:
2920         dev_info(host->dev, "Using PIO mode.\n");
2921         host->use_dma = TRANS_MODE_PIO;
2922 }
2923
2924 static void dw_mci_cmd11_timer(unsigned long arg)
2925 {
2926         struct dw_mci *host = (struct dw_mci *)arg;
2927
2928         if (host->state != STATE_SENDING_CMD11) {
2929                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2930                 return;
2931         }
2932
2933         host->cmd_status = SDMMC_INT_RTO;
2934         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2935         tasklet_schedule(&host->tasklet);
2936 }
2937
2938 static void dw_mci_cto_timer(unsigned long arg)
2939 {
2940         struct dw_mci *host = (struct dw_mci *)arg;
2941
2942         switch (host->state) {
2943         case STATE_SENDING_CMD11:
2944         case STATE_SENDING_CMD:
2945         case STATE_SENDING_STOP:
2946                 /*
2947                  * If CMD_DONE interrupt does NOT come in sending command
2948                  * state, we should notify the driver to terminate current
2949                  * transfer and report a command timeout to the core.
2950                  */
2951                 host->cmd_status = SDMMC_INT_RTO;
2952                 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2953                 tasklet_schedule(&host->tasklet);
2954                 break;
2955         default:
2956                 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
2957                          host->state);
2958                 break;
2959         }
2960 }
2961
2962 static void dw_mci_dto_timer(unsigned long arg)
2963 {
2964         struct dw_mci *host = (struct dw_mci *)arg;
2965
2966         switch (host->state) {
2967         case STATE_SENDING_DATA:
2968         case STATE_DATA_BUSY:
2969                 /*
2970                  * If DTO interrupt does NOT come in sending data state,
2971                  * we should notify the driver to terminate current transfer
2972                  * and report a data timeout to the core.
2973                  */
2974                 host->data_status = SDMMC_INT_DRTO;
2975                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2976                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2977                 tasklet_schedule(&host->tasklet);
2978                 break;
2979         default:
2980                 break;
2981         }
2982 }
2983
2984 #ifdef CONFIG_OF
2985 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2986 {
2987         struct dw_mci_board *pdata;
2988         struct device *dev = host->dev;
2989         const struct dw_mci_drv_data *drv_data = host->drv_data;
2990         int ret;
2991         u32 clock_frequency;
2992
2993         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2994         if (!pdata)
2995                 return ERR_PTR(-ENOMEM);
2996
2997         /* find reset controller when exist */
2998         pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
2999         if (IS_ERR(pdata->rstc)) {
3000                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3001                         return ERR_PTR(-EPROBE_DEFER);
3002         }
3003
3004         /* find out number of slots supported */
3005         if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
3006                 dev_info(dev, "'num-slots' was deprecated.\n");
3007
3008         if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3009                 dev_info(dev,
3010                          "fifo-depth property not found, using value of FIFOTH register as default\n");
3011
3012         device_property_read_u32(dev, "card-detect-delay",
3013                                  &pdata->detect_delay_ms);
3014
3015         device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3016
3017         if (device_property_present(dev, "fifo-watermark-aligned"))
3018                 host->wm_aligned = true;
3019
3020         if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3021                 pdata->bus_hz = clock_frequency;
3022
3023         if (drv_data && drv_data->parse_dt) {
3024                 ret = drv_data->parse_dt(host);
3025                 if (ret)
3026                         return ERR_PTR(ret);
3027         }
3028
3029         return pdata;
3030 }
3031
3032 #else /* CONFIG_OF */
3033 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3034 {
3035         return ERR_PTR(-EINVAL);
3036 }
3037 #endif /* CONFIG_OF */
3038
3039 static void dw_mci_enable_cd(struct dw_mci *host)
3040 {
3041         unsigned long irqflags;
3042         u32 temp;
3043
3044         /*
3045          * No need for CD if all slots have a non-error GPIO
3046          * as well as broken card detection is found.
3047          */
3048         if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3049                 return;
3050
3051         if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3052                 spin_lock_irqsave(&host->irq_lock, irqflags);
3053                 temp = mci_readl(host, INTMASK);
3054                 temp  |= SDMMC_INT_CD;
3055                 mci_writel(host, INTMASK, temp);
3056                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3057         }
3058 }
3059
3060 int dw_mci_probe(struct dw_mci *host)
3061 {
3062         const struct dw_mci_drv_data *drv_data = host->drv_data;
3063         int width, i, ret = 0;
3064         u32 fifo_size;
3065
3066         if (!host->pdata) {
3067                 host->pdata = dw_mci_parse_dt(host);
3068                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3069                         return -EPROBE_DEFER;
3070                 } else if (IS_ERR(host->pdata)) {
3071                         dev_err(host->dev, "platform data not available\n");
3072                         return -EINVAL;
3073                 }
3074         }
3075
3076         host->biu_clk = devm_clk_get(host->dev, "biu");
3077         if (IS_ERR(host->biu_clk)) {
3078                 dev_dbg(host->dev, "biu clock not available\n");
3079         } else {
3080                 ret = clk_prepare_enable(host->biu_clk);
3081                 if (ret) {
3082                         dev_err(host->dev, "failed to enable biu clock\n");
3083                         return ret;
3084                 }
3085         }
3086
3087         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3088         if (IS_ERR(host->ciu_clk)) {
3089                 dev_dbg(host->dev, "ciu clock not available\n");
3090                 host->bus_hz = host->pdata->bus_hz;
3091         } else {
3092                 ret = clk_prepare_enable(host->ciu_clk);
3093                 if (ret) {
3094                         dev_err(host->dev, "failed to enable ciu clock\n");
3095                         goto err_clk_biu;
3096                 }
3097
3098                 if (host->pdata->bus_hz) {
3099                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3100                         if (ret)
3101                                 dev_warn(host->dev,
3102                                          "Unable to set bus rate to %uHz\n",
3103                                          host->pdata->bus_hz);
3104                 }
3105                 host->bus_hz = clk_get_rate(host->ciu_clk);
3106         }
3107
3108         if (!host->bus_hz) {
3109                 dev_err(host->dev,
3110                         "Platform data must supply bus speed\n");
3111                 ret = -ENODEV;
3112                 goto err_clk_ciu;
3113         }
3114
3115         if (!IS_ERR(host->pdata->rstc)) {
3116                 reset_control_assert(host->pdata->rstc);
3117                 usleep_range(10, 50);
3118                 reset_control_deassert(host->pdata->rstc);
3119         }
3120
3121         if (drv_data && drv_data->init) {
3122                 ret = drv_data->init(host);
3123                 if (ret) {
3124                         dev_err(host->dev,
3125                                 "implementation specific init failed\n");
3126                         goto err_clk_ciu;
3127                 }
3128         }
3129
3130         setup_timer(&host->cmd11_timer,
3131                     dw_mci_cmd11_timer, (unsigned long)host);
3132
3133         setup_timer(&host->cto_timer,
3134                     dw_mci_cto_timer, (unsigned long)host);
3135
3136         setup_timer(&host->dto_timer,
3137                     dw_mci_dto_timer, (unsigned long)host);
3138
3139         spin_lock_init(&host->lock);
3140         spin_lock_init(&host->irq_lock);
3141         INIT_LIST_HEAD(&host->queue);
3142
3143         /*
3144          * Get the host data width - this assumes that HCON has been set with
3145          * the correct values.
3146          */
3147         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3148         if (!i) {
3149                 host->push_data = dw_mci_push_data16;
3150                 host->pull_data = dw_mci_pull_data16;
3151                 width = 16;
3152                 host->data_shift = 1;
3153         } else if (i == 2) {
3154                 host->push_data = dw_mci_push_data64;
3155                 host->pull_data = dw_mci_pull_data64;
3156                 width = 64;
3157                 host->data_shift = 3;
3158         } else {
3159                 /* Check for a reserved value, and warn if it is */
3160                 WARN((i != 1),
3161                      "HCON reports a reserved host data width!\n"
3162                      "Defaulting to 32-bit access.\n");
3163                 host->push_data = dw_mci_push_data32;
3164                 host->pull_data = dw_mci_pull_data32;
3165                 width = 32;
3166                 host->data_shift = 2;
3167         }
3168
3169         /* Reset all blocks */
3170         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3171                 ret = -ENODEV;
3172                 goto err_clk_ciu;
3173         }
3174
3175         host->dma_ops = host->pdata->dma_ops;
3176         dw_mci_init_dma(host);
3177
3178         /* Clear the interrupts for the host controller */
3179         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3180         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3181
3182         /* Put in max timeout */
3183         mci_writel(host, TMOUT, 0xFFFFFFFF);
3184
3185         /*
3186          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3187          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3188          */
3189         if (!host->pdata->fifo_depth) {
3190                 /*
3191                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3192                  * have been overwritten by the bootloader, just like we're
3193                  * about to do, so if you know the value for your hardware, you
3194                  * should put it in the platform data.
3195                  */
3196                 fifo_size = mci_readl(host, FIFOTH);
3197                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3198         } else {
3199                 fifo_size = host->pdata->fifo_depth;
3200         }
3201         host->fifo_depth = fifo_size;
3202         host->fifoth_val =
3203                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3204         mci_writel(host, FIFOTH, host->fifoth_val);
3205
3206         /* disable clock to CIU */
3207         mci_writel(host, CLKENA, 0);
3208         mci_writel(host, CLKSRC, 0);
3209
3210         /*
3211          * In 2.40a spec, Data offset is changed.
3212          * Need to check the version-id and set data-offset for DATA register.
3213          */
3214         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3215         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3216
3217         if (host->data_addr_override)
3218                 host->fifo_reg = host->regs + host->data_addr_override;
3219         else if (host->verid < DW_MMC_240A)
3220                 host->fifo_reg = host->regs + DATA_OFFSET;
3221         else
3222                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3223
3224         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3225         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3226                                host->irq_flags, "dw-mci", host);
3227         if (ret)
3228                 goto err_dmaunmap;
3229
3230         /*
3231          * Enable interrupts for command done, data over, data empty,
3232          * receive ready and error such as transmit, receive timeout, crc error
3233          */
3234         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3235                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3236                    DW_MCI_ERROR_FLAGS);
3237         /* Enable mci interrupt */
3238         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3239
3240         dev_info(host->dev,
3241                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3242                  host->irq, width, fifo_size);
3243
3244         /* We need at least one slot to succeed */
3245         ret = dw_mci_init_slot(host);
3246         if (ret) {
3247                 dev_dbg(host->dev, "slot %d init failed\n", i);
3248                 goto err_dmaunmap;
3249         }
3250
3251         /* Now that slots are all setup, we can enable card detect */
3252         dw_mci_enable_cd(host);
3253
3254         return 0;
3255
3256 err_dmaunmap:
3257         if (host->use_dma && host->dma_ops->exit)
3258                 host->dma_ops->exit(host);
3259
3260         if (!IS_ERR(host->pdata->rstc))
3261                 reset_control_assert(host->pdata->rstc);
3262
3263 err_clk_ciu:
3264         clk_disable_unprepare(host->ciu_clk);
3265
3266 err_clk_biu:
3267         clk_disable_unprepare(host->biu_clk);
3268
3269         return ret;
3270 }
3271 EXPORT_SYMBOL(dw_mci_probe);
3272
3273 void dw_mci_remove(struct dw_mci *host)
3274 {
3275         dev_dbg(host->dev, "remove slot\n");
3276         if (host->slot)
3277                 dw_mci_cleanup_slot(host->slot);
3278
3279         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3280         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3281
3282         /* disable clock to CIU */
3283         mci_writel(host, CLKENA, 0);
3284         mci_writel(host, CLKSRC, 0);
3285
3286         if (host->use_dma && host->dma_ops->exit)
3287                 host->dma_ops->exit(host);
3288
3289         if (!IS_ERR(host->pdata->rstc))
3290                 reset_control_assert(host->pdata->rstc);
3291
3292         clk_disable_unprepare(host->ciu_clk);
3293         clk_disable_unprepare(host->biu_clk);
3294 }
3295 EXPORT_SYMBOL(dw_mci_remove);
3296
3297
3298
3299 #ifdef CONFIG_PM
3300 int dw_mci_runtime_suspend(struct device *dev)
3301 {
3302         struct dw_mci *host = dev_get_drvdata(dev);
3303
3304         if (host->use_dma && host->dma_ops->exit)
3305                 host->dma_ops->exit(host);
3306
3307         clk_disable_unprepare(host->ciu_clk);
3308
3309         if (host->slot &&
3310             (mmc_can_gpio_cd(host->slot->mmc) ||
3311              !mmc_card_is_removable(host->slot->mmc)))
3312                 clk_disable_unprepare(host->biu_clk);
3313
3314         return 0;
3315 }
3316 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3317
3318 int dw_mci_runtime_resume(struct device *dev)
3319 {
3320         int ret = 0;
3321         struct dw_mci *host = dev_get_drvdata(dev);
3322
3323         if (host->slot &&
3324             (mmc_can_gpio_cd(host->slot->mmc) ||
3325              !mmc_card_is_removable(host->slot->mmc))) {
3326                 ret = clk_prepare_enable(host->biu_clk);
3327                 if (ret)
3328                         return ret;
3329         }
3330
3331         ret = clk_prepare_enable(host->ciu_clk);
3332         if (ret)
3333                 goto err;
3334
3335         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3336                 clk_disable_unprepare(host->ciu_clk);
3337                 ret = -ENODEV;
3338                 goto err;
3339         }
3340
3341         if (host->use_dma && host->dma_ops->init)
3342                 host->dma_ops->init(host);
3343
3344         /*
3345          * Restore the initial value at FIFOTH register
3346          * And Invalidate the prev_blksz with zero
3347          */
3348          mci_writel(host, FIFOTH, host->fifoth_val);
3349          host->prev_blksz = 0;
3350
3351         /* Put in max timeout */
3352         mci_writel(host, TMOUT, 0xFFFFFFFF);
3353
3354         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3355         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3356                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3357                    DW_MCI_ERROR_FLAGS);
3358         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3359
3360
3361         if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3362                 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3363
3364         /* Force setup bus to guarantee available clock output */
3365         dw_mci_setup_bus(host->slot, true);
3366
3367         /* Now that slots are all setup, we can enable card detect */
3368         dw_mci_enable_cd(host);
3369
3370         return 0;
3371
3372 err:
3373         if (host->slot &&
3374             (mmc_can_gpio_cd(host->slot->mmc) ||
3375              !mmc_card_is_removable(host->slot->mmc)))
3376                 clk_disable_unprepare(host->biu_clk);
3377
3378         return ret;
3379 }
3380 EXPORT_SYMBOL(dw_mci_runtime_resume);
3381 #endif /* CONFIG_PM */
3382
3383 static int __init dw_mci_init(void)
3384 {
3385         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3386         return 0;
3387 }
3388
3389 static void __exit dw_mci_exit(void)
3390 {
3391 }
3392
3393 module_init(dw_mci_init);
3394 module_exit(dw_mci_exit);
3395
3396 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3397 MODULE_AUTHOR("NXP Semiconductor VietNam");
3398 MODULE_AUTHOR("Imagination Technologies Ltd");
3399 MODULE_LICENSE("GPL v2");