50148991f30e768877dd14325e2025a17c86861f
[sfrench/cifs-2.6.git] / drivers / mmc / host / dw_mmc.c
1 /*
2  * Synopsys DesignWare Multimedia Card Interface driver
3  *  (Based on NXP driver for lpc 31xx)
4  *
5  * Copyright (C) 2009 NXP Semiconductors
6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/of.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
42
43 #include "dw_mmc.h"
44
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
48                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
52                                  DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS      1
54 #define DW_MCI_RECV_STATUS      2
55 #define DW_MCI_DMA_THRESHOLD    16
56
57 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
59
60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63                                  SDMMC_IDMAC_INT_TI)
64
65 #define DESC_RING_BUF_SZ        PAGE_SIZE
66
67 struct idmac_desc_64addr {
68         u32             des0;   /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70         !((x) & cpu_to_le32(IDMAC_DES0_OWN))
71
72         u32             des1;   /* Reserved */
73
74         u32             des2;   /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
78
79         u32             des3;   /* Reserved */
80
81         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
82         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
83
84         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
85         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
86 };
87
88 struct idmac_desc {
89         __le32          des0;   /* Control Descriptor */
90 #define IDMAC_DES0_DIC  BIT(1)
91 #define IDMAC_DES0_LD   BIT(2)
92 #define IDMAC_DES0_FD   BIT(3)
93 #define IDMAC_DES0_CH   BIT(4)
94 #define IDMAC_DES0_ER   BIT(5)
95 #define IDMAC_DES0_CES  BIT(30)
96 #define IDMAC_DES0_OWN  BIT(31)
97
98         __le32          des1;   /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
101
102         __le32          des2;   /* buffer 1 physical address */
103
104         __le32          des3;   /* buffer 2 physical address */
105 };
106
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
109
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
112 {
113         struct dw_mci_slot *slot = s->private;
114         struct mmc_request *mrq;
115         struct mmc_command *cmd;
116         struct mmc_command *stop;
117         struct mmc_data *data;
118
119         /* Make sure we get a consistent snapshot */
120         spin_lock_bh(&slot->host->lock);
121         mrq = slot->mrq;
122
123         if (mrq) {
124                 cmd = mrq->cmd;
125                 data = mrq->data;
126                 stop = mrq->stop;
127
128                 if (cmd)
129                         seq_printf(s,
130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131                                    cmd->opcode, cmd->arg, cmd->flags,
132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
133                                    cmd->resp[2], cmd->error);
134                 if (data)
135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136                                    data->bytes_xfered, data->blocks,
137                                    data->blksz, data->flags, data->error);
138                 if (stop)
139                         seq_printf(s,
140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141                                    stop->opcode, stop->arg, stop->flags,
142                                    stop->resp[0], stop->resp[1], stop->resp[2],
143                                    stop->resp[2], stop->error);
144         }
145
146         spin_unlock_bh(&slot->host->lock);
147
148         return 0;
149 }
150
151 static int dw_mci_req_open(struct inode *inode, struct file *file)
152 {
153         return single_open(file, dw_mci_req_show, inode->i_private);
154 }
155
156 static const struct file_operations dw_mci_req_fops = {
157         .owner          = THIS_MODULE,
158         .open           = dw_mci_req_open,
159         .read           = seq_read,
160         .llseek         = seq_lseek,
161         .release        = single_release,
162 };
163
164 static int dw_mci_regs_show(struct seq_file *s, void *v)
165 {
166         struct dw_mci *host = s->private;
167
168         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
169         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
170         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
171         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
172         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
173         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
174
175         return 0;
176 }
177
178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
179 {
180         return single_open(file, dw_mci_regs_show, inode->i_private);
181 }
182
183 static const struct file_operations dw_mci_regs_fops = {
184         .owner          = THIS_MODULE,
185         .open           = dw_mci_regs_open,
186         .read           = seq_read,
187         .llseek         = seq_lseek,
188         .release        = single_release,
189 };
190
191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
192 {
193         struct mmc_host *mmc = slot->mmc;
194         struct dw_mci *host = slot->host;
195         struct dentry *root;
196         struct dentry *node;
197
198         root = mmc->debugfs_root;
199         if (!root)
200                 return;
201
202         node = debugfs_create_file("regs", S_IRUSR, root, host,
203                                    &dw_mci_regs_fops);
204         if (!node)
205                 goto err;
206
207         node = debugfs_create_file("req", S_IRUSR, root, slot,
208                                    &dw_mci_req_fops);
209         if (!node)
210                 goto err;
211
212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
213         if (!node)
214                 goto err;
215
216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
217                                   (u32 *)&host->pending_events);
218         if (!node)
219                 goto err;
220
221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
222                                   (u32 *)&host->completed_events);
223         if (!node)
224                 goto err;
225
226         return;
227
228 err:
229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
230 }
231 #endif /* defined(CONFIG_DEBUG_FS) */
232
233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
234 {
235         u32 ctrl;
236
237         ctrl = mci_readl(host, CTRL);
238         ctrl |= reset;
239         mci_writel(host, CTRL, ctrl);
240
241         /* wait till resets clear */
242         if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
243                                       !(ctrl & reset),
244                                       1, 500 * USEC_PER_MSEC)) {
245                 dev_err(host->dev,
246                         "Timeout resetting block (ctrl reset %#x)\n",
247                         ctrl & reset);
248                 return false;
249         }
250
251         return true;
252 }
253
254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
255 {
256         u32 status;
257
258         /*
259          * Databook says that before issuing a new data transfer command
260          * we need to check to see if the card is busy.  Data transfer commands
261          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
262          *
263          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
264          * expected.
265          */
266         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
267             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
268                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
269                                               status,
270                                               !(status & SDMMC_STATUS_BUSY),
271                                               10, 500 * USEC_PER_MSEC))
272                         dev_err(host->dev, "Busy; trying anyway\n");
273         }
274 }
275
276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
277 {
278         struct dw_mci *host = slot->host;
279         unsigned int cmd_status = 0;
280
281         mci_writel(host, CMDARG, arg);
282         wmb(); /* drain writebuffer */
283         dw_mci_wait_while_busy(host, cmd);
284         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
285
286         if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
287                                       !(cmd_status & SDMMC_CMD_START),
288                                       1, 500 * USEC_PER_MSEC))
289                 dev_err(&slot->mmc->class_dev,
290                         "Timeout sending command (cmd %#x arg %#x status %#x)\n",
291                         cmd, arg, cmd_status);
292 }
293
294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
295 {
296         struct dw_mci_slot *slot = mmc_priv(mmc);
297         struct dw_mci *host = slot->host;
298         u32 cmdr;
299
300         cmd->error = -EINPROGRESS;
301         cmdr = cmd->opcode;
302
303         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
304             cmd->opcode == MMC_GO_IDLE_STATE ||
305             cmd->opcode == MMC_GO_INACTIVE_STATE ||
306             (cmd->opcode == SD_IO_RW_DIRECT &&
307              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
308                 cmdr |= SDMMC_CMD_STOP;
309         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
310                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
311
312         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
313                 u32 clk_en_a;
314
315                 /* Special bit makes CMD11 not die */
316                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
317
318                 /* Change state to continue to handle CMD11 weirdness */
319                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
320                 slot->host->state = STATE_SENDING_CMD11;
321
322                 /*
323                  * We need to disable low power mode (automatic clock stop)
324                  * while doing voltage switch so we don't confuse the card,
325                  * since stopping the clock is a specific part of the UHS
326                  * voltage change dance.
327                  *
328                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
329                  * unconditionally turned back on in dw_mci_setup_bus() if it's
330                  * ever called with a non-zero clock.  That shouldn't happen
331                  * until the voltage change is all done.
332                  */
333                 clk_en_a = mci_readl(host, CLKENA);
334                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
335                 mci_writel(host, CLKENA, clk_en_a);
336                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
337                              SDMMC_CMD_PRV_DAT_WAIT, 0);
338         }
339
340         if (cmd->flags & MMC_RSP_PRESENT) {
341                 /* We expect a response, so set this bit */
342                 cmdr |= SDMMC_CMD_RESP_EXP;
343                 if (cmd->flags & MMC_RSP_136)
344                         cmdr |= SDMMC_CMD_RESP_LONG;
345         }
346
347         if (cmd->flags & MMC_RSP_CRC)
348                 cmdr |= SDMMC_CMD_RESP_CRC;
349
350         if (cmd->data) {
351                 cmdr |= SDMMC_CMD_DAT_EXP;
352                 if (cmd->data->flags & MMC_DATA_WRITE)
353                         cmdr |= SDMMC_CMD_DAT_WR;
354         }
355
356         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
357                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
358
359         return cmdr;
360 }
361
362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
363 {
364         struct mmc_command *stop;
365         u32 cmdr;
366
367         if (!cmd->data)
368                 return 0;
369
370         stop = &host->stop_abort;
371         cmdr = cmd->opcode;
372         memset(stop, 0, sizeof(struct mmc_command));
373
374         if (cmdr == MMC_READ_SINGLE_BLOCK ||
375             cmdr == MMC_READ_MULTIPLE_BLOCK ||
376             cmdr == MMC_WRITE_BLOCK ||
377             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
378             cmdr == MMC_SEND_TUNING_BLOCK ||
379             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
380                 stop->opcode = MMC_STOP_TRANSMISSION;
381                 stop->arg = 0;
382                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
383         } else if (cmdr == SD_IO_RW_EXTENDED) {
384                 stop->opcode = SD_IO_RW_DIRECT;
385                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
386                              ((cmd->arg >> 28) & 0x7);
387                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
388         } else {
389                 return 0;
390         }
391
392         cmdr = stop->opcode | SDMMC_CMD_STOP |
393                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
394
395         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
396                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
397
398         return cmdr;
399 }
400
401 static inline void dw_mci_set_cto(struct dw_mci *host)
402 {
403         unsigned int cto_clks;
404         unsigned int cto_div;
405         unsigned int cto_ms;
406         unsigned long irqflags;
407
408         cto_clks = mci_readl(host, TMOUT) & 0xff;
409         cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
410         if (cto_div == 0)
411                 cto_div = 1;
412         cto_ms = DIV_ROUND_UP(MSEC_PER_SEC * cto_clks * cto_div, host->bus_hz);
413
414         /* add a bit spare time */
415         cto_ms += 10;
416
417         /*
418          * The durations we're working with are fairly short so we have to be
419          * extra careful about synchronization here.  Specifically in hardware a
420          * command timeout is _at most_ 5.1 ms, so that means we expect an
421          * interrupt (either command done or timeout) to come rather quickly
422          * after the mci_writel.  ...but just in case we have a long interrupt
423          * latency let's add a bit of paranoia.
424          *
425          * In general we'll assume that at least an interrupt will be asserted
426          * in hardware by the time the cto_timer runs.  ...and if it hasn't
427          * been asserted in hardware by that time then we'll assume it'll never
428          * come.
429          */
430         spin_lock_irqsave(&host->irq_lock, irqflags);
431         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
432                 mod_timer(&host->cto_timer,
433                         jiffies + msecs_to_jiffies(cto_ms) + 1);
434         spin_unlock_irqrestore(&host->irq_lock, irqflags);
435 }
436
437 static void dw_mci_start_command(struct dw_mci *host,
438                                  struct mmc_command *cmd, u32 cmd_flags)
439 {
440         host->cmd = cmd;
441         dev_vdbg(host->dev,
442                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
443                  cmd->arg, cmd_flags);
444
445         mci_writel(host, CMDARG, cmd->arg);
446         wmb(); /* drain writebuffer */
447         dw_mci_wait_while_busy(host, cmd_flags);
448
449         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
450
451         /* response expected command only */
452         if (cmd_flags & SDMMC_CMD_RESP_EXP)
453                 dw_mci_set_cto(host);
454 }
455
456 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
457 {
458         struct mmc_command *stop = &host->stop_abort;
459
460         dw_mci_start_command(host, stop, host->stop_cmdr);
461 }
462
463 /* DMA interface functions */
464 static void dw_mci_stop_dma(struct dw_mci *host)
465 {
466         if (host->using_dma) {
467                 host->dma_ops->stop(host);
468                 host->dma_ops->cleanup(host);
469         }
470
471         /* Data transfer was stopped by the interrupt handler */
472         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
473 }
474
475 static void dw_mci_dma_cleanup(struct dw_mci *host)
476 {
477         struct mmc_data *data = host->data;
478
479         if (data && data->host_cookie == COOKIE_MAPPED) {
480                 dma_unmap_sg(host->dev,
481                              data->sg,
482                              data->sg_len,
483                              mmc_get_dma_dir(data));
484                 data->host_cookie = COOKIE_UNMAPPED;
485         }
486 }
487
488 static void dw_mci_idmac_reset(struct dw_mci *host)
489 {
490         u32 bmod = mci_readl(host, BMOD);
491         /* Software reset of DMA */
492         bmod |= SDMMC_IDMAC_SWRESET;
493         mci_writel(host, BMOD, bmod);
494 }
495
496 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
497 {
498         u32 temp;
499
500         /* Disable and reset the IDMAC interface */
501         temp = mci_readl(host, CTRL);
502         temp &= ~SDMMC_CTRL_USE_IDMAC;
503         temp |= SDMMC_CTRL_DMA_RESET;
504         mci_writel(host, CTRL, temp);
505
506         /* Stop the IDMAC running */
507         temp = mci_readl(host, BMOD);
508         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
509         temp |= SDMMC_IDMAC_SWRESET;
510         mci_writel(host, BMOD, temp);
511 }
512
513 static void dw_mci_dmac_complete_dma(void *arg)
514 {
515         struct dw_mci *host = arg;
516         struct mmc_data *data = host->data;
517
518         dev_vdbg(host->dev, "DMA complete\n");
519
520         if ((host->use_dma == TRANS_MODE_EDMAC) &&
521             data && (data->flags & MMC_DATA_READ))
522                 /* Invalidate cache after read */
523                 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
524                                     data->sg,
525                                     data->sg_len,
526                                     DMA_FROM_DEVICE);
527
528         host->dma_ops->cleanup(host);
529
530         /*
531          * If the card was removed, data will be NULL. No point in trying to
532          * send the stop command or waiting for NBUSY in this case.
533          */
534         if (data) {
535                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
536                 tasklet_schedule(&host->tasklet);
537         }
538 }
539
540 static int dw_mci_idmac_init(struct dw_mci *host)
541 {
542         int i;
543
544         if (host->dma_64bit_address == 1) {
545                 struct idmac_desc_64addr *p;
546                 /* Number of descriptors in the ring buffer */
547                 host->ring_size =
548                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
549
550                 /* Forward link the descriptor list */
551                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
552                                                                 i++, p++) {
553                         p->des6 = (host->sg_dma +
554                                         (sizeof(struct idmac_desc_64addr) *
555                                                         (i + 1))) & 0xffffffff;
556
557                         p->des7 = (u64)(host->sg_dma +
558                                         (sizeof(struct idmac_desc_64addr) *
559                                                         (i + 1))) >> 32;
560                         /* Initialize reserved and buffer size fields to "0" */
561                         p->des1 = 0;
562                         p->des2 = 0;
563                         p->des3 = 0;
564                 }
565
566                 /* Set the last descriptor as the end-of-ring descriptor */
567                 p->des6 = host->sg_dma & 0xffffffff;
568                 p->des7 = (u64)host->sg_dma >> 32;
569                 p->des0 = IDMAC_DES0_ER;
570
571         } else {
572                 struct idmac_desc *p;
573                 /* Number of descriptors in the ring buffer */
574                 host->ring_size =
575                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
576
577                 /* Forward link the descriptor list */
578                 for (i = 0, p = host->sg_cpu;
579                      i < host->ring_size - 1;
580                      i++, p++) {
581                         p->des3 = cpu_to_le32(host->sg_dma +
582                                         (sizeof(struct idmac_desc) * (i + 1)));
583                         p->des1 = 0;
584                 }
585
586                 /* Set the last descriptor as the end-of-ring descriptor */
587                 p->des3 = cpu_to_le32(host->sg_dma);
588                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
589         }
590
591         dw_mci_idmac_reset(host);
592
593         if (host->dma_64bit_address == 1) {
594                 /* Mask out interrupts - get Tx & Rx complete only */
595                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
596                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
597                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
598
599                 /* Set the descriptor base address */
600                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
601                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
602
603         } else {
604                 /* Mask out interrupts - get Tx & Rx complete only */
605                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
606                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
607                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
608
609                 /* Set the descriptor base address */
610                 mci_writel(host, DBADDR, host->sg_dma);
611         }
612
613         return 0;
614 }
615
616 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
617                                          struct mmc_data *data,
618                                          unsigned int sg_len)
619 {
620         unsigned int desc_len;
621         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
622         u32 val;
623         int i;
624
625         desc_first = desc_last = desc = host->sg_cpu;
626
627         for (i = 0; i < sg_len; i++) {
628                 unsigned int length = sg_dma_len(&data->sg[i]);
629
630                 u64 mem_addr = sg_dma_address(&data->sg[i]);
631
632                 for ( ; length ; desc++) {
633                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
634                                    length : DW_MCI_DESC_DATA_LENGTH;
635
636                         length -= desc_len;
637
638                         /*
639                          * Wait for the former clear OWN bit operation
640                          * of IDMAC to make sure that this descriptor
641                          * isn't still owned by IDMAC as IDMAC's write
642                          * ops and CPU's read ops are asynchronous.
643                          */
644                         if (readl_poll_timeout_atomic(&desc->des0, val,
645                                                 !(val & IDMAC_DES0_OWN),
646                                                 10, 100 * USEC_PER_MSEC))
647                                 goto err_own_bit;
648
649                         /*
650                          * Set the OWN bit and disable interrupts
651                          * for this descriptor
652                          */
653                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
654                                                 IDMAC_DES0_CH;
655
656                         /* Buffer length */
657                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
658
659                         /* Physical address to DMA to/from */
660                         desc->des4 = mem_addr & 0xffffffff;
661                         desc->des5 = mem_addr >> 32;
662
663                         /* Update physical address for the next desc */
664                         mem_addr += desc_len;
665
666                         /* Save pointer to the last descriptor */
667                         desc_last = desc;
668                 }
669         }
670
671         /* Set first descriptor */
672         desc_first->des0 |= IDMAC_DES0_FD;
673
674         /* Set last descriptor */
675         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
676         desc_last->des0 |= IDMAC_DES0_LD;
677
678         return 0;
679 err_own_bit:
680         /* restore the descriptor chain as it's polluted */
681         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
682         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
683         dw_mci_idmac_init(host);
684         return -EINVAL;
685 }
686
687
688 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
689                                          struct mmc_data *data,
690                                          unsigned int sg_len)
691 {
692         unsigned int desc_len;
693         struct idmac_desc *desc_first, *desc_last, *desc;
694         u32 val;
695         int i;
696
697         desc_first = desc_last = desc = host->sg_cpu;
698
699         for (i = 0; i < sg_len; i++) {
700                 unsigned int length = sg_dma_len(&data->sg[i]);
701
702                 u32 mem_addr = sg_dma_address(&data->sg[i]);
703
704                 for ( ; length ; desc++) {
705                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
706                                    length : DW_MCI_DESC_DATA_LENGTH;
707
708                         length -= desc_len;
709
710                         /*
711                          * Wait for the former clear OWN bit operation
712                          * of IDMAC to make sure that this descriptor
713                          * isn't still owned by IDMAC as IDMAC's write
714                          * ops and CPU's read ops are asynchronous.
715                          */
716                         if (readl_poll_timeout_atomic(&desc->des0, val,
717                                                       IDMAC_OWN_CLR64(val),
718                                                       10,
719                                                       100 * USEC_PER_MSEC))
720                                 goto err_own_bit;
721
722                         /*
723                          * Set the OWN bit and disable interrupts
724                          * for this descriptor
725                          */
726                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
727                                                  IDMAC_DES0_DIC |
728                                                  IDMAC_DES0_CH);
729
730                         /* Buffer length */
731                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
732
733                         /* Physical address to DMA to/from */
734                         desc->des2 = cpu_to_le32(mem_addr);
735
736                         /* Update physical address for the next desc */
737                         mem_addr += desc_len;
738
739                         /* Save pointer to the last descriptor */
740                         desc_last = desc;
741                 }
742         }
743
744         /* Set first descriptor */
745         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
746
747         /* Set last descriptor */
748         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
749                                        IDMAC_DES0_DIC));
750         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
751
752         return 0;
753 err_own_bit:
754         /* restore the descriptor chain as it's polluted */
755         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
756         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
757         dw_mci_idmac_init(host);
758         return -EINVAL;
759 }
760
761 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
762 {
763         u32 temp;
764         int ret;
765
766         if (host->dma_64bit_address == 1)
767                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
768         else
769                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
770
771         if (ret)
772                 goto out;
773
774         /* drain writebuffer */
775         wmb();
776
777         /* Make sure to reset DMA in case we did PIO before this */
778         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
779         dw_mci_idmac_reset(host);
780
781         /* Select IDMAC interface */
782         temp = mci_readl(host, CTRL);
783         temp |= SDMMC_CTRL_USE_IDMAC;
784         mci_writel(host, CTRL, temp);
785
786         /* drain writebuffer */
787         wmb();
788
789         /* Enable the IDMAC */
790         temp = mci_readl(host, BMOD);
791         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
792         mci_writel(host, BMOD, temp);
793
794         /* Start it running */
795         mci_writel(host, PLDMND, 1);
796
797 out:
798         return ret;
799 }
800
801 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
802         .init = dw_mci_idmac_init,
803         .start = dw_mci_idmac_start_dma,
804         .stop = dw_mci_idmac_stop_dma,
805         .complete = dw_mci_dmac_complete_dma,
806         .cleanup = dw_mci_dma_cleanup,
807 };
808
809 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
810 {
811         dmaengine_terminate_async(host->dms->ch);
812 }
813
814 static int dw_mci_edmac_start_dma(struct dw_mci *host,
815                                             unsigned int sg_len)
816 {
817         struct dma_slave_config cfg;
818         struct dma_async_tx_descriptor *desc = NULL;
819         struct scatterlist *sgl = host->data->sg;
820         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
821         u32 sg_elems = host->data->sg_len;
822         u32 fifoth_val;
823         u32 fifo_offset = host->fifo_reg - host->regs;
824         int ret = 0;
825
826         /* Set external dma config: burst size, burst width */
827         cfg.dst_addr = host->phy_regs + fifo_offset;
828         cfg.src_addr = cfg.dst_addr;
829         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
830         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
831
832         /* Match burst msize with external dma config */
833         fifoth_val = mci_readl(host, FIFOTH);
834         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
835         cfg.src_maxburst = cfg.dst_maxburst;
836
837         if (host->data->flags & MMC_DATA_WRITE)
838                 cfg.direction = DMA_MEM_TO_DEV;
839         else
840                 cfg.direction = DMA_DEV_TO_MEM;
841
842         ret = dmaengine_slave_config(host->dms->ch, &cfg);
843         if (ret) {
844                 dev_err(host->dev, "Failed to config edmac.\n");
845                 return -EBUSY;
846         }
847
848         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
849                                        sg_len, cfg.direction,
850                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
851         if (!desc) {
852                 dev_err(host->dev, "Can't prepare slave sg.\n");
853                 return -EBUSY;
854         }
855
856         /* Set dw_mci_dmac_complete_dma as callback */
857         desc->callback = dw_mci_dmac_complete_dma;
858         desc->callback_param = (void *)host;
859         dmaengine_submit(desc);
860
861         /* Flush cache before write */
862         if (host->data->flags & MMC_DATA_WRITE)
863                 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
864                                        sg_elems, DMA_TO_DEVICE);
865
866         dma_async_issue_pending(host->dms->ch);
867
868         return 0;
869 }
870
871 static int dw_mci_edmac_init(struct dw_mci *host)
872 {
873         /* Request external dma channel */
874         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
875         if (!host->dms)
876                 return -ENOMEM;
877
878         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
879         if (!host->dms->ch) {
880                 dev_err(host->dev, "Failed to get external DMA channel.\n");
881                 kfree(host->dms);
882                 host->dms = NULL;
883                 return -ENXIO;
884         }
885
886         return 0;
887 }
888
889 static void dw_mci_edmac_exit(struct dw_mci *host)
890 {
891         if (host->dms) {
892                 if (host->dms->ch) {
893                         dma_release_channel(host->dms->ch);
894                         host->dms->ch = NULL;
895                 }
896                 kfree(host->dms);
897                 host->dms = NULL;
898         }
899 }
900
901 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
902         .init = dw_mci_edmac_init,
903         .exit = dw_mci_edmac_exit,
904         .start = dw_mci_edmac_start_dma,
905         .stop = dw_mci_edmac_stop_dma,
906         .complete = dw_mci_dmac_complete_dma,
907         .cleanup = dw_mci_dma_cleanup,
908 };
909
910 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
911                                    struct mmc_data *data,
912                                    int cookie)
913 {
914         struct scatterlist *sg;
915         unsigned int i, sg_len;
916
917         if (data->host_cookie == COOKIE_PRE_MAPPED)
918                 return data->sg_len;
919
920         /*
921          * We don't do DMA on "complex" transfers, i.e. with
922          * non-word-aligned buffers or lengths. Also, we don't bother
923          * with all the DMA setup overhead for short transfers.
924          */
925         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
926                 return -EINVAL;
927
928         if (data->blksz & 3)
929                 return -EINVAL;
930
931         for_each_sg(data->sg, sg, data->sg_len, i) {
932                 if (sg->offset & 3 || sg->length & 3)
933                         return -EINVAL;
934         }
935
936         sg_len = dma_map_sg(host->dev,
937                             data->sg,
938                             data->sg_len,
939                             mmc_get_dma_dir(data));
940         if (sg_len == 0)
941                 return -EINVAL;
942
943         data->host_cookie = cookie;
944
945         return sg_len;
946 }
947
948 static void dw_mci_pre_req(struct mmc_host *mmc,
949                            struct mmc_request *mrq)
950 {
951         struct dw_mci_slot *slot = mmc_priv(mmc);
952         struct mmc_data *data = mrq->data;
953
954         if (!slot->host->use_dma || !data)
955                 return;
956
957         /* This data might be unmapped at this time */
958         data->host_cookie = COOKIE_UNMAPPED;
959
960         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
961                                 COOKIE_PRE_MAPPED) < 0)
962                 data->host_cookie = COOKIE_UNMAPPED;
963 }
964
965 static void dw_mci_post_req(struct mmc_host *mmc,
966                             struct mmc_request *mrq,
967                             int err)
968 {
969         struct dw_mci_slot *slot = mmc_priv(mmc);
970         struct mmc_data *data = mrq->data;
971
972         if (!slot->host->use_dma || !data)
973                 return;
974
975         if (data->host_cookie != COOKIE_UNMAPPED)
976                 dma_unmap_sg(slot->host->dev,
977                              data->sg,
978                              data->sg_len,
979                              mmc_get_dma_dir(data));
980         data->host_cookie = COOKIE_UNMAPPED;
981 }
982
983 static int dw_mci_get_cd(struct mmc_host *mmc)
984 {
985         int present;
986         struct dw_mci_slot *slot = mmc_priv(mmc);
987         struct dw_mci *host = slot->host;
988         int gpio_cd = mmc_gpio_get_cd(mmc);
989
990         /* Use platform get_cd function, else try onboard card detect */
991         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
992                                 || !mmc_card_is_removable(mmc))) {
993                 present = 1;
994
995                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
996                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
997                                 dev_info(&mmc->class_dev,
998                                         "card is polling.\n");
999                         } else {
1000                                 dev_info(&mmc->class_dev,
1001                                         "card is non-removable.\n");
1002                         }
1003                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1004                 }
1005
1006                 return present;
1007         } else if (gpio_cd >= 0)
1008                 present = gpio_cd;
1009         else
1010                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1011                         == 0 ? 1 : 0;
1012
1013         spin_lock_bh(&host->lock);
1014         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1015                 dev_dbg(&mmc->class_dev, "card is present\n");
1016         else if (!present &&
1017                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1018                 dev_dbg(&mmc->class_dev, "card is not present\n");
1019         spin_unlock_bh(&host->lock);
1020
1021         return present;
1022 }
1023
1024 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1025 {
1026         unsigned int blksz = data->blksz;
1027         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1028         u32 fifo_width = 1 << host->data_shift;
1029         u32 blksz_depth = blksz / fifo_width, fifoth_val;
1030         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1031         int idx = ARRAY_SIZE(mszs) - 1;
1032
1033         /* pio should ship this scenario */
1034         if (!host->use_dma)
1035                 return;
1036
1037         tx_wmark = (host->fifo_depth) / 2;
1038         tx_wmark_invers = host->fifo_depth - tx_wmark;
1039
1040         /*
1041          * MSIZE is '1',
1042          * if blksz is not a multiple of the FIFO width
1043          */
1044         if (blksz % fifo_width)
1045                 goto done;
1046
1047         do {
1048                 if (!((blksz_depth % mszs[idx]) ||
1049                      (tx_wmark_invers % mszs[idx]))) {
1050                         msize = idx;
1051                         rx_wmark = mszs[idx] - 1;
1052                         break;
1053                 }
1054         } while (--idx > 0);
1055         /*
1056          * If idx is '0', it won't be tried
1057          * Thus, initial values are uesed
1058          */
1059 done:
1060         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1061         mci_writel(host, FIFOTH, fifoth_val);
1062 }
1063
1064 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1065 {
1066         unsigned int blksz = data->blksz;
1067         u32 blksz_depth, fifo_depth;
1068         u16 thld_size;
1069         u8 enable;
1070
1071         /*
1072          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1073          * in the FIFO region, so we really shouldn't access it).
1074          */
1075         if (host->verid < DW_MMC_240A ||
1076                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1077                 return;
1078
1079         /*
1080          * Card write Threshold is introduced since 2.80a
1081          * It's used when HS400 mode is enabled.
1082          */
1083         if (data->flags & MMC_DATA_WRITE &&
1084                 !(host->timing != MMC_TIMING_MMC_HS400))
1085                 return;
1086
1087         if (data->flags & MMC_DATA_WRITE)
1088                 enable = SDMMC_CARD_WR_THR_EN;
1089         else
1090                 enable = SDMMC_CARD_RD_THR_EN;
1091
1092         if (host->timing != MMC_TIMING_MMC_HS200 &&
1093             host->timing != MMC_TIMING_UHS_SDR104)
1094                 goto disable;
1095
1096         blksz_depth = blksz / (1 << host->data_shift);
1097         fifo_depth = host->fifo_depth;
1098
1099         if (blksz_depth > fifo_depth)
1100                 goto disable;
1101
1102         /*
1103          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1104          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1105          * Currently just choose blksz.
1106          */
1107         thld_size = blksz;
1108         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1109         return;
1110
1111 disable:
1112         mci_writel(host, CDTHRCTL, 0);
1113 }
1114
1115 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1116 {
1117         unsigned long irqflags;
1118         int sg_len;
1119         u32 temp;
1120
1121         host->using_dma = 0;
1122
1123         /* If we don't have a channel, we can't do DMA */
1124         if (!host->use_dma)
1125                 return -ENODEV;
1126
1127         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1128         if (sg_len < 0) {
1129                 host->dma_ops->stop(host);
1130                 return sg_len;
1131         }
1132
1133         host->using_dma = 1;
1134
1135         if (host->use_dma == TRANS_MODE_IDMAC)
1136                 dev_vdbg(host->dev,
1137                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1138                          (unsigned long)host->sg_cpu,
1139                          (unsigned long)host->sg_dma,
1140                          sg_len);
1141
1142         /*
1143          * Decide the MSIZE and RX/TX Watermark.
1144          * If current block size is same with previous size,
1145          * no need to update fifoth.
1146          */
1147         if (host->prev_blksz != data->blksz)
1148                 dw_mci_adjust_fifoth(host, data);
1149
1150         /* Enable the DMA interface */
1151         temp = mci_readl(host, CTRL);
1152         temp |= SDMMC_CTRL_DMA_ENABLE;
1153         mci_writel(host, CTRL, temp);
1154
1155         /* Disable RX/TX IRQs, let DMA handle it */
1156         spin_lock_irqsave(&host->irq_lock, irqflags);
1157         temp = mci_readl(host, INTMASK);
1158         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1159         mci_writel(host, INTMASK, temp);
1160         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1161
1162         if (host->dma_ops->start(host, sg_len)) {
1163                 host->dma_ops->stop(host);
1164                 /* We can't do DMA, try PIO for this one */
1165                 dev_dbg(host->dev,
1166                         "%s: fall back to PIO mode for current transfer\n",
1167                         __func__);
1168                 return -ENODEV;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1175 {
1176         unsigned long irqflags;
1177         int flags = SG_MITER_ATOMIC;
1178         u32 temp;
1179
1180         data->error = -EINPROGRESS;
1181
1182         WARN_ON(host->data);
1183         host->sg = NULL;
1184         host->data = data;
1185
1186         if (data->flags & MMC_DATA_READ)
1187                 host->dir_status = DW_MCI_RECV_STATUS;
1188         else
1189                 host->dir_status = DW_MCI_SEND_STATUS;
1190
1191         dw_mci_ctrl_thld(host, data);
1192
1193         if (dw_mci_submit_data_dma(host, data)) {
1194                 if (host->data->flags & MMC_DATA_READ)
1195                         flags |= SG_MITER_TO_SG;
1196                 else
1197                         flags |= SG_MITER_FROM_SG;
1198
1199                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200                 host->sg = data->sg;
1201                 host->part_buf_start = 0;
1202                 host->part_buf_count = 0;
1203
1204                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1205
1206                 spin_lock_irqsave(&host->irq_lock, irqflags);
1207                 temp = mci_readl(host, INTMASK);
1208                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1209                 mci_writel(host, INTMASK, temp);
1210                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1211
1212                 temp = mci_readl(host, CTRL);
1213                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1214                 mci_writel(host, CTRL, temp);
1215
1216                 /*
1217                  * Use the initial fifoth_val for PIO mode. If wm_algined
1218                  * is set, we set watermark same as data size.
1219                  * If next issued data may be transfered by DMA mode,
1220                  * prev_blksz should be invalidated.
1221                  */
1222                 if (host->wm_aligned)
1223                         dw_mci_adjust_fifoth(host, data);
1224                 else
1225                         mci_writel(host, FIFOTH, host->fifoth_val);
1226                 host->prev_blksz = 0;
1227         } else {
1228                 /*
1229                  * Keep the current block size.
1230                  * It will be used to decide whether to update
1231                  * fifoth register next time.
1232                  */
1233                 host->prev_blksz = data->blksz;
1234         }
1235 }
1236
1237 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1238 {
1239         struct dw_mci *host = slot->host;
1240         unsigned int clock = slot->clock;
1241         u32 div;
1242         u32 clk_en_a;
1243         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1244
1245         /* We must continue to set bit 28 in CMD until the change is complete */
1246         if (host->state == STATE_WAITING_CMD11_DONE)
1247                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1248
1249         if (!clock) {
1250                 mci_writel(host, CLKENA, 0);
1251                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1252         } else if (clock != host->current_speed || force_clkinit) {
1253                 div = host->bus_hz / clock;
1254                 if (host->bus_hz % clock && host->bus_hz > clock)
1255                         /*
1256                          * move the + 1 after the divide to prevent
1257                          * over-clocking the card.
1258                          */
1259                         div += 1;
1260
1261                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1262
1263                 if ((clock != slot->__clk_old &&
1264                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1265                         force_clkinit) {
1266                         /* Silent the verbose log if calling from PM context */
1267                         if (!force_clkinit)
1268                                 dev_info(&slot->mmc->class_dev,
1269                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1270                                          slot->id, host->bus_hz, clock,
1271                                          div ? ((host->bus_hz / div) >> 1) :
1272                                          host->bus_hz, div);
1273
1274                         /*
1275                          * If card is polling, display the message only
1276                          * one time at boot time.
1277                          */
1278                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1279                                         slot->mmc->f_min == clock)
1280                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1281                 }
1282
1283                 /* disable clock */
1284                 mci_writel(host, CLKENA, 0);
1285                 mci_writel(host, CLKSRC, 0);
1286
1287                 /* inform CIU */
1288                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1289
1290                 /* set clock to desired speed */
1291                 mci_writel(host, CLKDIV, div);
1292
1293                 /* inform CIU */
1294                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1295
1296                 /* enable clock; only low power if no SDIO */
1297                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1298                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1299                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1300                 mci_writel(host, CLKENA, clk_en_a);
1301
1302                 /* inform CIU */
1303                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1304
1305                 /* keep the last clock value that was requested from core */
1306                 slot->__clk_old = clock;
1307         }
1308
1309         host->current_speed = clock;
1310
1311         /* Set the current slot bus width */
1312         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1313 }
1314
1315 static void __dw_mci_start_request(struct dw_mci *host,
1316                                    struct dw_mci_slot *slot,
1317                                    struct mmc_command *cmd)
1318 {
1319         struct mmc_request *mrq;
1320         struct mmc_data *data;
1321         u32 cmdflags;
1322
1323         mrq = slot->mrq;
1324
1325         host->mrq = mrq;
1326
1327         host->pending_events = 0;
1328         host->completed_events = 0;
1329         host->cmd_status = 0;
1330         host->data_status = 0;
1331         host->dir_status = 0;
1332
1333         data = cmd->data;
1334         if (data) {
1335                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1336                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1337                 mci_writel(host, BLKSIZ, data->blksz);
1338         }
1339
1340         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1341
1342         /* this is the first command, send the initialization clock */
1343         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1344                 cmdflags |= SDMMC_CMD_INIT;
1345
1346         if (data) {
1347                 dw_mci_submit_data(host, data);
1348                 wmb(); /* drain writebuffer */
1349         }
1350
1351         dw_mci_start_command(host, cmd, cmdflags);
1352
1353         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1354                 unsigned long irqflags;
1355
1356                 /*
1357                  * Databook says to fail after 2ms w/ no response, but evidence
1358                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1359                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1360                  * is just about to roll over.
1361                  *
1362                  * We do this whole thing under spinlock and only if the
1363                  * command hasn't already completed (indicating the the irq
1364                  * already ran so we don't want the timeout).
1365                  */
1366                 spin_lock_irqsave(&host->irq_lock, irqflags);
1367                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1368                         mod_timer(&host->cmd11_timer,
1369                                 jiffies + msecs_to_jiffies(500) + 1);
1370                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1371         }
1372
1373         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1374 }
1375
1376 static void dw_mci_start_request(struct dw_mci *host,
1377                                  struct dw_mci_slot *slot)
1378 {
1379         struct mmc_request *mrq = slot->mrq;
1380         struct mmc_command *cmd;
1381
1382         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1383         __dw_mci_start_request(host, slot, cmd);
1384 }
1385
1386 /* must be called with host->lock held */
1387 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1388                                  struct mmc_request *mrq)
1389 {
1390         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1391                  host->state);
1392
1393         slot->mrq = mrq;
1394
1395         if (host->state == STATE_WAITING_CMD11_DONE) {
1396                 dev_warn(&slot->mmc->class_dev,
1397                          "Voltage change didn't complete\n");
1398                 /*
1399                  * this case isn't expected to happen, so we can
1400                  * either crash here or just try to continue on
1401                  * in the closest possible state
1402                  */
1403                 host->state = STATE_IDLE;
1404         }
1405
1406         if (host->state == STATE_IDLE) {
1407                 host->state = STATE_SENDING_CMD;
1408                 dw_mci_start_request(host, slot);
1409         } else {
1410                 list_add_tail(&slot->queue_node, &host->queue);
1411         }
1412 }
1413
1414 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1415 {
1416         struct dw_mci_slot *slot = mmc_priv(mmc);
1417         struct dw_mci *host = slot->host;
1418
1419         WARN_ON(slot->mrq);
1420
1421         /*
1422          * The check for card presence and queueing of the request must be
1423          * atomic, otherwise the card could be removed in between and the
1424          * request wouldn't fail until another card was inserted.
1425          */
1426
1427         if (!dw_mci_get_cd(mmc)) {
1428                 mrq->cmd->error = -ENOMEDIUM;
1429                 mmc_request_done(mmc, mrq);
1430                 return;
1431         }
1432
1433         spin_lock_bh(&host->lock);
1434
1435         dw_mci_queue_request(host, slot, mrq);
1436
1437         spin_unlock_bh(&host->lock);
1438 }
1439
1440 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1441 {
1442         struct dw_mci_slot *slot = mmc_priv(mmc);
1443         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1444         u32 regs;
1445         int ret;
1446
1447         switch (ios->bus_width) {
1448         case MMC_BUS_WIDTH_4:
1449                 slot->ctype = SDMMC_CTYPE_4BIT;
1450                 break;
1451         case MMC_BUS_WIDTH_8:
1452                 slot->ctype = SDMMC_CTYPE_8BIT;
1453                 break;
1454         default:
1455                 /* set default 1 bit mode */
1456                 slot->ctype = SDMMC_CTYPE_1BIT;
1457         }
1458
1459         regs = mci_readl(slot->host, UHS_REG);
1460
1461         /* DDR mode set */
1462         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1463             ios->timing == MMC_TIMING_UHS_DDR50 ||
1464             ios->timing == MMC_TIMING_MMC_HS400)
1465                 regs |= ((0x1 << slot->id) << 16);
1466         else
1467                 regs &= ~((0x1 << slot->id) << 16);
1468
1469         mci_writel(slot->host, UHS_REG, regs);
1470         slot->host->timing = ios->timing;
1471
1472         /*
1473          * Use mirror of ios->clock to prevent race with mmc
1474          * core ios update when finding the minimum.
1475          */
1476         slot->clock = ios->clock;
1477
1478         if (drv_data && drv_data->set_ios)
1479                 drv_data->set_ios(slot->host, ios);
1480
1481         switch (ios->power_mode) {
1482         case MMC_POWER_UP:
1483                 if (!IS_ERR(mmc->supply.vmmc)) {
1484                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1485                                         ios->vdd);
1486                         if (ret) {
1487                                 dev_err(slot->host->dev,
1488                                         "failed to enable vmmc regulator\n");
1489                                 /*return, if failed turn on vmmc*/
1490                                 return;
1491                         }
1492                 }
1493                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1494                 regs = mci_readl(slot->host, PWREN);
1495                 regs |= (1 << slot->id);
1496                 mci_writel(slot->host, PWREN, regs);
1497                 break;
1498         case MMC_POWER_ON:
1499                 if (!slot->host->vqmmc_enabled) {
1500                         if (!IS_ERR(mmc->supply.vqmmc)) {
1501                                 ret = regulator_enable(mmc->supply.vqmmc);
1502                                 if (ret < 0)
1503                                         dev_err(slot->host->dev,
1504                                                 "failed to enable vqmmc\n");
1505                                 else
1506                                         slot->host->vqmmc_enabled = true;
1507
1508                         } else {
1509                                 /* Keep track so we don't reset again */
1510                                 slot->host->vqmmc_enabled = true;
1511                         }
1512
1513                         /* Reset our state machine after powering on */
1514                         dw_mci_ctrl_reset(slot->host,
1515                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1516                 }
1517
1518                 /* Adjust clock / bus width after power is up */
1519                 dw_mci_setup_bus(slot, false);
1520
1521                 break;
1522         case MMC_POWER_OFF:
1523                 /* Turn clock off before power goes down */
1524                 dw_mci_setup_bus(slot, false);
1525
1526                 if (!IS_ERR(mmc->supply.vmmc))
1527                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1528
1529                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1530                         regulator_disable(mmc->supply.vqmmc);
1531                 slot->host->vqmmc_enabled = false;
1532
1533                 regs = mci_readl(slot->host, PWREN);
1534                 regs &= ~(1 << slot->id);
1535                 mci_writel(slot->host, PWREN, regs);
1536                 break;
1537         default:
1538                 break;
1539         }
1540
1541         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1542                 slot->host->state = STATE_IDLE;
1543 }
1544
1545 static int dw_mci_card_busy(struct mmc_host *mmc)
1546 {
1547         struct dw_mci_slot *slot = mmc_priv(mmc);
1548         u32 status;
1549
1550         /*
1551          * Check the busy bit which is low when DAT[3:0]
1552          * (the data lines) are 0000
1553          */
1554         status = mci_readl(slot->host, STATUS);
1555
1556         return !!(status & SDMMC_STATUS_BUSY);
1557 }
1558
1559 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1560 {
1561         struct dw_mci_slot *slot = mmc_priv(mmc);
1562         struct dw_mci *host = slot->host;
1563         const struct dw_mci_drv_data *drv_data = host->drv_data;
1564         u32 uhs;
1565         u32 v18 = SDMMC_UHS_18V << slot->id;
1566         int ret;
1567
1568         if (drv_data && drv_data->switch_voltage)
1569                 return drv_data->switch_voltage(mmc, ios);
1570
1571         /*
1572          * Program the voltage.  Note that some instances of dw_mmc may use
1573          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1574          * does no harm but you need to set the regulator directly.  Try both.
1575          */
1576         uhs = mci_readl(host, UHS_REG);
1577         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1578                 uhs &= ~v18;
1579         else
1580                 uhs |= v18;
1581
1582         if (!IS_ERR(mmc->supply.vqmmc)) {
1583                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1584
1585                 if (ret) {
1586                         dev_dbg(&mmc->class_dev,
1587                                          "Regulator set error %d - %s V\n",
1588                                          ret, uhs & v18 ? "1.8" : "3.3");
1589                         return ret;
1590                 }
1591         }
1592         mci_writel(host, UHS_REG, uhs);
1593
1594         return 0;
1595 }
1596
1597 static int dw_mci_get_ro(struct mmc_host *mmc)
1598 {
1599         int read_only;
1600         struct dw_mci_slot *slot = mmc_priv(mmc);
1601         int gpio_ro = mmc_gpio_get_ro(mmc);
1602
1603         /* Use platform get_ro function, else try on board write protect */
1604         if (gpio_ro >= 0)
1605                 read_only = gpio_ro;
1606         else
1607                 read_only =
1608                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1609
1610         dev_dbg(&mmc->class_dev, "card is %s\n",
1611                 read_only ? "read-only" : "read-write");
1612
1613         return read_only;
1614 }
1615
1616 static void dw_mci_hw_reset(struct mmc_host *mmc)
1617 {
1618         struct dw_mci_slot *slot = mmc_priv(mmc);
1619         struct dw_mci *host = slot->host;
1620         int reset;
1621
1622         if (host->use_dma == TRANS_MODE_IDMAC)
1623                 dw_mci_idmac_reset(host);
1624
1625         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1626                                      SDMMC_CTRL_FIFO_RESET))
1627                 return;
1628
1629         /*
1630          * According to eMMC spec, card reset procedure:
1631          * tRstW >= 1us:   RST_n pulse width
1632          * tRSCA >= 200us: RST_n to Command time
1633          * tRSTH >= 1us:   RST_n high period
1634          */
1635         reset = mci_readl(host, RST_N);
1636         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1637         mci_writel(host, RST_N, reset);
1638         usleep_range(1, 2);
1639         reset |= SDMMC_RST_HWACTIVE << slot->id;
1640         mci_writel(host, RST_N, reset);
1641         usleep_range(200, 300);
1642 }
1643
1644 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1645 {
1646         struct dw_mci_slot *slot = mmc_priv(mmc);
1647         struct dw_mci *host = slot->host;
1648
1649         /*
1650          * Low power mode will stop the card clock when idle.  According to the
1651          * description of the CLKENA register we should disable low power mode
1652          * for SDIO cards if we need SDIO interrupts to work.
1653          */
1654         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1655                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1656                 u32 clk_en_a_old;
1657                 u32 clk_en_a;
1658
1659                 clk_en_a_old = mci_readl(host, CLKENA);
1660
1661                 if (card->type == MMC_TYPE_SDIO ||
1662                     card->type == MMC_TYPE_SD_COMBO) {
1663                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1664                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1665                 } else {
1666                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1667                         clk_en_a = clk_en_a_old | clken_low_pwr;
1668                 }
1669
1670                 if (clk_en_a != clk_en_a_old) {
1671                         mci_writel(host, CLKENA, clk_en_a);
1672                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1673                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1674                 }
1675         }
1676 }
1677
1678 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1679 {
1680         struct dw_mci *host = slot->host;
1681         unsigned long irqflags;
1682         u32 int_mask;
1683
1684         spin_lock_irqsave(&host->irq_lock, irqflags);
1685
1686         /* Enable/disable Slot Specific SDIO interrupt */
1687         int_mask = mci_readl(host, INTMASK);
1688         if (enb)
1689                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1690         else
1691                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1692         mci_writel(host, INTMASK, int_mask);
1693
1694         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1695 }
1696
1697 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1698 {
1699         struct dw_mci_slot *slot = mmc_priv(mmc);
1700         struct dw_mci *host = slot->host;
1701
1702         __dw_mci_enable_sdio_irq(slot, enb);
1703
1704         /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1705         if (enb)
1706                 pm_runtime_get_noresume(host->dev);
1707         else
1708                 pm_runtime_put_noidle(host->dev);
1709 }
1710
1711 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1712 {
1713         struct dw_mci_slot *slot = mmc_priv(mmc);
1714
1715         __dw_mci_enable_sdio_irq(slot, 1);
1716 }
1717
1718 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1719 {
1720         struct dw_mci_slot *slot = mmc_priv(mmc);
1721         struct dw_mci *host = slot->host;
1722         const struct dw_mci_drv_data *drv_data = host->drv_data;
1723         int err = -EINVAL;
1724
1725         if (drv_data && drv_data->execute_tuning)
1726                 err = drv_data->execute_tuning(slot, opcode);
1727         return err;
1728 }
1729
1730 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1731                                        struct mmc_ios *ios)
1732 {
1733         struct dw_mci_slot *slot = mmc_priv(mmc);
1734         struct dw_mci *host = slot->host;
1735         const struct dw_mci_drv_data *drv_data = host->drv_data;
1736
1737         if (drv_data && drv_data->prepare_hs400_tuning)
1738                 return drv_data->prepare_hs400_tuning(host, ios);
1739
1740         return 0;
1741 }
1742
1743 static bool dw_mci_reset(struct dw_mci *host)
1744 {
1745         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1746         bool ret = false;
1747         u32 status = 0;
1748
1749         /*
1750          * Resetting generates a block interrupt, hence setting
1751          * the scatter-gather pointer to NULL.
1752          */
1753         if (host->sg) {
1754                 sg_miter_stop(&host->sg_miter);
1755                 host->sg = NULL;
1756         }
1757
1758         if (host->use_dma)
1759                 flags |= SDMMC_CTRL_DMA_RESET;
1760
1761         if (dw_mci_ctrl_reset(host, flags)) {
1762                 /*
1763                  * In all cases we clear the RAWINTS
1764                  * register to clear any interrupts.
1765                  */
1766                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1767
1768                 if (!host->use_dma) {
1769                         ret = true;
1770                         goto ciu_out;
1771                 }
1772
1773                 /* Wait for dma_req to be cleared */
1774                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1775                                               status,
1776                                               !(status & SDMMC_STATUS_DMA_REQ),
1777                                               1, 500 * USEC_PER_MSEC)) {
1778                         dev_err(host->dev,
1779                                 "%s: Timeout waiting for dma_req to be cleared\n",
1780                                 __func__);
1781                         goto ciu_out;
1782                 }
1783
1784                 /* when using DMA next we reset the fifo again */
1785                 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1786                         goto ciu_out;
1787         } else {
1788                 /* if the controller reset bit did clear, then set clock regs */
1789                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1790                         dev_err(host->dev,
1791                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1792                                 __func__);
1793                         goto ciu_out;
1794                 }
1795         }
1796
1797         if (host->use_dma == TRANS_MODE_IDMAC)
1798                 /* It is also recommended that we reset and reprogram idmac */
1799                 dw_mci_idmac_reset(host);
1800
1801         ret = true;
1802
1803 ciu_out:
1804         /* After a CTRL reset we need to have CIU set clock registers  */
1805         mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1806
1807         return ret;
1808 }
1809
1810 static const struct mmc_host_ops dw_mci_ops = {
1811         .request                = dw_mci_request,
1812         .pre_req                = dw_mci_pre_req,
1813         .post_req               = dw_mci_post_req,
1814         .set_ios                = dw_mci_set_ios,
1815         .get_ro                 = dw_mci_get_ro,
1816         .get_cd                 = dw_mci_get_cd,
1817         .hw_reset               = dw_mci_hw_reset,
1818         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1819         .ack_sdio_irq           = dw_mci_ack_sdio_irq,
1820         .execute_tuning         = dw_mci_execute_tuning,
1821         .card_busy              = dw_mci_card_busy,
1822         .start_signal_voltage_switch = dw_mci_switch_voltage,
1823         .init_card              = dw_mci_init_card,
1824         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1825 };
1826
1827 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1828         __releases(&host->lock)
1829         __acquires(&host->lock)
1830 {
1831         struct dw_mci_slot *slot;
1832         struct mmc_host *prev_mmc = host->slot->mmc;
1833
1834         WARN_ON(host->cmd || host->data);
1835
1836         host->slot->mrq = NULL;
1837         host->mrq = NULL;
1838         if (!list_empty(&host->queue)) {
1839                 slot = list_entry(host->queue.next,
1840                                   struct dw_mci_slot, queue_node);
1841                 list_del(&slot->queue_node);
1842                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1843                          mmc_hostname(slot->mmc));
1844                 host->state = STATE_SENDING_CMD;
1845                 dw_mci_start_request(host, slot);
1846         } else {
1847                 dev_vdbg(host->dev, "list empty\n");
1848
1849                 if (host->state == STATE_SENDING_CMD11)
1850                         host->state = STATE_WAITING_CMD11_DONE;
1851                 else
1852                         host->state = STATE_IDLE;
1853         }
1854
1855         spin_unlock(&host->lock);
1856         mmc_request_done(prev_mmc, mrq);
1857         spin_lock(&host->lock);
1858 }
1859
1860 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1861 {
1862         u32 status = host->cmd_status;
1863
1864         host->cmd_status = 0;
1865
1866         /* Read the response from the card (up to 16 bytes) */
1867         if (cmd->flags & MMC_RSP_PRESENT) {
1868                 if (cmd->flags & MMC_RSP_136) {
1869                         cmd->resp[3] = mci_readl(host, RESP0);
1870                         cmd->resp[2] = mci_readl(host, RESP1);
1871                         cmd->resp[1] = mci_readl(host, RESP2);
1872                         cmd->resp[0] = mci_readl(host, RESP3);
1873                 } else {
1874                         cmd->resp[0] = mci_readl(host, RESP0);
1875                         cmd->resp[1] = 0;
1876                         cmd->resp[2] = 0;
1877                         cmd->resp[3] = 0;
1878                 }
1879         }
1880
1881         if (status & SDMMC_INT_RTO)
1882                 cmd->error = -ETIMEDOUT;
1883         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1884                 cmd->error = -EILSEQ;
1885         else if (status & SDMMC_INT_RESP_ERR)
1886                 cmd->error = -EIO;
1887         else
1888                 cmd->error = 0;
1889
1890         return cmd->error;
1891 }
1892
1893 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1894 {
1895         u32 status = host->data_status;
1896
1897         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1898                 if (status & SDMMC_INT_DRTO) {
1899                         data->error = -ETIMEDOUT;
1900                 } else if (status & SDMMC_INT_DCRC) {
1901                         data->error = -EILSEQ;
1902                 } else if (status & SDMMC_INT_EBE) {
1903                         if (host->dir_status ==
1904                                 DW_MCI_SEND_STATUS) {
1905                                 /*
1906                                  * No data CRC status was returned.
1907                                  * The number of bytes transferred
1908                                  * will be exaggerated in PIO mode.
1909                                  */
1910                                 data->bytes_xfered = 0;
1911                                 data->error = -ETIMEDOUT;
1912                         } else if (host->dir_status ==
1913                                         DW_MCI_RECV_STATUS) {
1914                                 data->error = -EILSEQ;
1915                         }
1916                 } else {
1917                         /* SDMMC_INT_SBE is included */
1918                         data->error = -EILSEQ;
1919                 }
1920
1921                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1922
1923                 /*
1924                  * After an error, there may be data lingering
1925                  * in the FIFO
1926                  */
1927                 dw_mci_reset(host);
1928         } else {
1929                 data->bytes_xfered = data->blocks * data->blksz;
1930                 data->error = 0;
1931         }
1932
1933         return data->error;
1934 }
1935
1936 static void dw_mci_set_drto(struct dw_mci *host)
1937 {
1938         unsigned int drto_clks;
1939         unsigned int drto_ms;
1940
1941         drto_clks = mci_readl(host, TMOUT) >> 8;
1942         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1943
1944         /* add a bit spare time */
1945         drto_ms += 10;
1946
1947         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1948 }
1949
1950 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1951 {
1952         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1953                 return false;
1954
1955         /*
1956          * Really be certain that the timer has stopped.  This is a bit of
1957          * paranoia and could only really happen if we had really bad
1958          * interrupt latency and the interrupt routine and timeout were
1959          * running concurrently so that the del_timer() in the interrupt
1960          * handler couldn't run.
1961          */
1962         WARN_ON(del_timer_sync(&host->cto_timer));
1963         clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1964
1965         return true;
1966 }
1967
1968 static void dw_mci_tasklet_func(unsigned long priv)
1969 {
1970         struct dw_mci *host = (struct dw_mci *)priv;
1971         struct mmc_data *data;
1972         struct mmc_command *cmd;
1973         struct mmc_request *mrq;
1974         enum dw_mci_state state;
1975         enum dw_mci_state prev_state;
1976         unsigned int err;
1977
1978         spin_lock(&host->lock);
1979
1980         state = host->state;
1981         data = host->data;
1982         mrq = host->mrq;
1983
1984         do {
1985                 prev_state = state;
1986
1987                 switch (state) {
1988                 case STATE_IDLE:
1989                 case STATE_WAITING_CMD11_DONE:
1990                         break;
1991
1992                 case STATE_SENDING_CMD11:
1993                 case STATE_SENDING_CMD:
1994                         if (!dw_mci_clear_pending_cmd_complete(host))
1995                                 break;
1996
1997                         cmd = host->cmd;
1998                         host->cmd = NULL;
1999                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2000                         err = dw_mci_command_complete(host, cmd);
2001                         if (cmd == mrq->sbc && !err) {
2002                                 prev_state = state = STATE_SENDING_CMD;
2003                                 __dw_mci_start_request(host, host->slot,
2004                                                        mrq->cmd);
2005                                 goto unlock;
2006                         }
2007
2008                         if (cmd->data && err) {
2009                                 /*
2010                                  * During UHS tuning sequence, sending the stop
2011                                  * command after the response CRC error would
2012                                  * throw the system into a confused state
2013                                  * causing all future tuning phases to report
2014                                  * failure.
2015                                  *
2016                                  * In such case controller will move into a data
2017                                  * transfer state after a response error or
2018                                  * response CRC error. Let's let that finish
2019                                  * before trying to send a stop, so we'll go to
2020                                  * STATE_SENDING_DATA.
2021                                  *
2022                                  * Although letting the data transfer take place
2023                                  * will waste a bit of time (we already know
2024                                  * the command was bad), it can't cause any
2025                                  * errors since it's possible it would have
2026                                  * taken place anyway if this tasklet got
2027                                  * delayed. Allowing the transfer to take place
2028                                  * avoids races and keeps things simple.
2029                                  */
2030                                 if ((err != -ETIMEDOUT) &&
2031                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
2032                                         state = STATE_SENDING_DATA;
2033                                         continue;
2034                                 }
2035
2036                                 dw_mci_stop_dma(host);
2037                                 send_stop_abort(host, data);
2038                                 state = STATE_SENDING_STOP;
2039                                 break;
2040                         }
2041
2042                         if (!cmd->data || err) {
2043                                 dw_mci_request_end(host, mrq);
2044                                 goto unlock;
2045                         }
2046
2047                         prev_state = state = STATE_SENDING_DATA;
2048                         /* fall through */
2049
2050                 case STATE_SENDING_DATA:
2051                         /*
2052                          * We could get a data error and never a transfer
2053                          * complete so we'd better check for it here.
2054                          *
2055                          * Note that we don't really care if we also got a
2056                          * transfer complete; stopping the DMA and sending an
2057                          * abort won't hurt.
2058                          */
2059                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2060                                                &host->pending_events)) {
2061                                 dw_mci_stop_dma(host);
2062                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2063                                                            SDMMC_INT_EBE)))
2064                                         send_stop_abort(host, data);
2065                                 state = STATE_DATA_ERROR;
2066                                 break;
2067                         }
2068
2069                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2070                                                 &host->pending_events)) {
2071                                 /*
2072                                  * If all data-related interrupts don't come
2073                                  * within the given time in reading data state.
2074                                  */
2075                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2076                                         dw_mci_set_drto(host);
2077                                 break;
2078                         }
2079
2080                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2081
2082                         /*
2083                          * Handle an EVENT_DATA_ERROR that might have shown up
2084                          * before the transfer completed.  This might not have
2085                          * been caught by the check above because the interrupt
2086                          * could have gone off between the previous check and
2087                          * the check for transfer complete.
2088                          *
2089                          * Technically this ought not be needed assuming we
2090                          * get a DATA_COMPLETE eventually (we'll notice the
2091                          * error and end the request), but it shouldn't hurt.
2092                          *
2093                          * This has the advantage of sending the stop command.
2094                          */
2095                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2096                                                &host->pending_events)) {
2097                                 dw_mci_stop_dma(host);
2098                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2099                                                            SDMMC_INT_EBE)))
2100                                         send_stop_abort(host, data);
2101                                 state = STATE_DATA_ERROR;
2102                                 break;
2103                         }
2104                         prev_state = state = STATE_DATA_BUSY;
2105
2106                         /* fall through */
2107
2108                 case STATE_DATA_BUSY:
2109                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2110                                                 &host->pending_events)) {
2111                                 /*
2112                                  * If data error interrupt comes but data over
2113                                  * interrupt doesn't come within the given time.
2114                                  * in reading data state.
2115                                  */
2116                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2117                                         dw_mci_set_drto(host);
2118                                 break;
2119                         }
2120
2121                         host->data = NULL;
2122                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2123                         err = dw_mci_data_complete(host, data);
2124
2125                         if (!err) {
2126                                 if (!data->stop || mrq->sbc) {
2127                                         if (mrq->sbc && data->stop)
2128                                                 data->stop->error = 0;
2129                                         dw_mci_request_end(host, mrq);
2130                                         goto unlock;
2131                                 }
2132
2133                                 /* stop command for open-ended transfer*/
2134                                 if (data->stop)
2135                                         send_stop_abort(host, data);
2136                         } else {
2137                                 /*
2138                                  * If we don't have a command complete now we'll
2139                                  * never get one since we just reset everything;
2140                                  * better end the request.
2141                                  *
2142                                  * If we do have a command complete we'll fall
2143                                  * through to the SENDING_STOP command and
2144                                  * everything will be peachy keen.
2145                                  */
2146                                 if (!test_bit(EVENT_CMD_COMPLETE,
2147                                               &host->pending_events)) {
2148                                         host->cmd = NULL;
2149                                         dw_mci_request_end(host, mrq);
2150                                         goto unlock;
2151                                 }
2152                         }
2153
2154                         /*
2155                          * If err has non-zero,
2156                          * stop-abort command has been already issued.
2157                          */
2158                         prev_state = state = STATE_SENDING_STOP;
2159
2160                         /* fall through */
2161
2162                 case STATE_SENDING_STOP:
2163                         if (!dw_mci_clear_pending_cmd_complete(host))
2164                                 break;
2165
2166                         /* CMD error in data command */
2167                         if (mrq->cmd->error && mrq->data)
2168                                 dw_mci_reset(host);
2169
2170                         host->cmd = NULL;
2171                         host->data = NULL;
2172
2173                         if (!mrq->sbc && mrq->stop)
2174                                 dw_mci_command_complete(host, mrq->stop);
2175                         else
2176                                 host->cmd_status = 0;
2177
2178                         dw_mci_request_end(host, mrq);
2179                         goto unlock;
2180
2181                 case STATE_DATA_ERROR:
2182                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2183                                                 &host->pending_events))
2184                                 break;
2185
2186                         state = STATE_DATA_BUSY;
2187                         break;
2188                 }
2189         } while (state != prev_state);
2190
2191         host->state = state;
2192 unlock:
2193         spin_unlock(&host->lock);
2194
2195 }
2196
2197 /* push final bytes to part_buf, only use during push */
2198 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2199 {
2200         memcpy((void *)&host->part_buf, buf, cnt);
2201         host->part_buf_count = cnt;
2202 }
2203
2204 /* append bytes to part_buf, only use during push */
2205 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2206 {
2207         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2208         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2209         host->part_buf_count += cnt;
2210         return cnt;
2211 }
2212
2213 /* pull first bytes from part_buf, only use during pull */
2214 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2215 {
2216         cnt = min_t(int, cnt, host->part_buf_count);
2217         if (cnt) {
2218                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2219                        cnt);
2220                 host->part_buf_count -= cnt;
2221                 host->part_buf_start += cnt;
2222         }
2223         return cnt;
2224 }
2225
2226 /* pull final bytes from the part_buf, assuming it's just been filled */
2227 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2228 {
2229         memcpy(buf, &host->part_buf, cnt);
2230         host->part_buf_start = cnt;
2231         host->part_buf_count = (1 << host->data_shift) - cnt;
2232 }
2233
2234 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2235 {
2236         struct mmc_data *data = host->data;
2237         int init_cnt = cnt;
2238
2239         /* try and push anything in the part_buf */
2240         if (unlikely(host->part_buf_count)) {
2241                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2242
2243                 buf += len;
2244                 cnt -= len;
2245                 if (host->part_buf_count == 2) {
2246                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2247                         host->part_buf_count = 0;
2248                 }
2249         }
2250 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2251         if (unlikely((unsigned long)buf & 0x1)) {
2252                 while (cnt >= 2) {
2253                         u16 aligned_buf[64];
2254                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2255                         int items = len >> 1;
2256                         int i;
2257                         /* memcpy from input buffer into aligned buffer */
2258                         memcpy(aligned_buf, buf, len);
2259                         buf += len;
2260                         cnt -= len;
2261                         /* push data from aligned buffer into fifo */
2262                         for (i = 0; i < items; ++i)
2263                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2264                 }
2265         } else
2266 #endif
2267         {
2268                 u16 *pdata = buf;
2269
2270                 for (; cnt >= 2; cnt -= 2)
2271                         mci_fifo_writew(host->fifo_reg, *pdata++);
2272                 buf = pdata;
2273         }
2274         /* put anything remaining in the part_buf */
2275         if (cnt) {
2276                 dw_mci_set_part_bytes(host, buf, cnt);
2277                  /* Push data if we have reached the expected data length */
2278                 if ((data->bytes_xfered + init_cnt) ==
2279                     (data->blksz * data->blocks))
2280                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2281         }
2282 }
2283
2284 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2285 {
2286 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2287         if (unlikely((unsigned long)buf & 0x1)) {
2288                 while (cnt >= 2) {
2289                         /* pull data from fifo into aligned buffer */
2290                         u16 aligned_buf[64];
2291                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2292                         int items = len >> 1;
2293                         int i;
2294
2295                         for (i = 0; i < items; ++i)
2296                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2297                         /* memcpy from aligned buffer into output buffer */
2298                         memcpy(buf, aligned_buf, len);
2299                         buf += len;
2300                         cnt -= len;
2301                 }
2302         } else
2303 #endif
2304         {
2305                 u16 *pdata = buf;
2306
2307                 for (; cnt >= 2; cnt -= 2)
2308                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2309                 buf = pdata;
2310         }
2311         if (cnt) {
2312                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2313                 dw_mci_pull_final_bytes(host, buf, cnt);
2314         }
2315 }
2316
2317 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2318 {
2319         struct mmc_data *data = host->data;
2320         int init_cnt = cnt;
2321
2322         /* try and push anything in the part_buf */
2323         if (unlikely(host->part_buf_count)) {
2324                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2325
2326                 buf += len;
2327                 cnt -= len;
2328                 if (host->part_buf_count == 4) {
2329                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2330                         host->part_buf_count = 0;
2331                 }
2332         }
2333 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2334         if (unlikely((unsigned long)buf & 0x3)) {
2335                 while (cnt >= 4) {
2336                         u32 aligned_buf[32];
2337                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2338                         int items = len >> 2;
2339                         int i;
2340                         /* memcpy from input buffer into aligned buffer */
2341                         memcpy(aligned_buf, buf, len);
2342                         buf += len;
2343                         cnt -= len;
2344                         /* push data from aligned buffer into fifo */
2345                         for (i = 0; i < items; ++i)
2346                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2347                 }
2348         } else
2349 #endif
2350         {
2351                 u32 *pdata = buf;
2352
2353                 for (; cnt >= 4; cnt -= 4)
2354                         mci_fifo_writel(host->fifo_reg, *pdata++);
2355                 buf = pdata;
2356         }
2357         /* put anything remaining in the part_buf */
2358         if (cnt) {
2359                 dw_mci_set_part_bytes(host, buf, cnt);
2360                  /* Push data if we have reached the expected data length */
2361                 if ((data->bytes_xfered + init_cnt) ==
2362                     (data->blksz * data->blocks))
2363                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2364         }
2365 }
2366
2367 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2368 {
2369 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2370         if (unlikely((unsigned long)buf & 0x3)) {
2371                 while (cnt >= 4) {
2372                         /* pull data from fifo into aligned buffer */
2373                         u32 aligned_buf[32];
2374                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2375                         int items = len >> 2;
2376                         int i;
2377
2378                         for (i = 0; i < items; ++i)
2379                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2380                         /* memcpy from aligned buffer into output buffer */
2381                         memcpy(buf, aligned_buf, len);
2382                         buf += len;
2383                         cnt -= len;
2384                 }
2385         } else
2386 #endif
2387         {
2388                 u32 *pdata = buf;
2389
2390                 for (; cnt >= 4; cnt -= 4)
2391                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2392                 buf = pdata;
2393         }
2394         if (cnt) {
2395                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2396                 dw_mci_pull_final_bytes(host, buf, cnt);
2397         }
2398 }
2399
2400 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2401 {
2402         struct mmc_data *data = host->data;
2403         int init_cnt = cnt;
2404
2405         /* try and push anything in the part_buf */
2406         if (unlikely(host->part_buf_count)) {
2407                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2408
2409                 buf += len;
2410                 cnt -= len;
2411
2412                 if (host->part_buf_count == 8) {
2413                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2414                         host->part_buf_count = 0;
2415                 }
2416         }
2417 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2418         if (unlikely((unsigned long)buf & 0x7)) {
2419                 while (cnt >= 8) {
2420                         u64 aligned_buf[16];
2421                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2422                         int items = len >> 3;
2423                         int i;
2424                         /* memcpy from input buffer into aligned buffer */
2425                         memcpy(aligned_buf, buf, len);
2426                         buf += len;
2427                         cnt -= len;
2428                         /* push data from aligned buffer into fifo */
2429                         for (i = 0; i < items; ++i)
2430                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2431                 }
2432         } else
2433 #endif
2434         {
2435                 u64 *pdata = buf;
2436
2437                 for (; cnt >= 8; cnt -= 8)
2438                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2439                 buf = pdata;
2440         }
2441         /* put anything remaining in the part_buf */
2442         if (cnt) {
2443                 dw_mci_set_part_bytes(host, buf, cnt);
2444                 /* Push data if we have reached the expected data length */
2445                 if ((data->bytes_xfered + init_cnt) ==
2446                     (data->blksz * data->blocks))
2447                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2448         }
2449 }
2450
2451 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2452 {
2453 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2454         if (unlikely((unsigned long)buf & 0x7)) {
2455                 while (cnt >= 8) {
2456                         /* pull data from fifo into aligned buffer */
2457                         u64 aligned_buf[16];
2458                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2459                         int items = len >> 3;
2460                         int i;
2461
2462                         for (i = 0; i < items; ++i)
2463                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2464
2465                         /* memcpy from aligned buffer into output buffer */
2466                         memcpy(buf, aligned_buf, len);
2467                         buf += len;
2468                         cnt -= len;
2469                 }
2470         } else
2471 #endif
2472         {
2473                 u64 *pdata = buf;
2474
2475                 for (; cnt >= 8; cnt -= 8)
2476                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2477                 buf = pdata;
2478         }
2479         if (cnt) {
2480                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2481                 dw_mci_pull_final_bytes(host, buf, cnt);
2482         }
2483 }
2484
2485 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2486 {
2487         int len;
2488
2489         /* get remaining partial bytes */
2490         len = dw_mci_pull_part_bytes(host, buf, cnt);
2491         if (unlikely(len == cnt))
2492                 return;
2493         buf += len;
2494         cnt -= len;
2495
2496         /* get the rest of the data */
2497         host->pull_data(host, buf, cnt);
2498 }
2499
2500 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2501 {
2502         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2503         void *buf;
2504         unsigned int offset;
2505         struct mmc_data *data = host->data;
2506         int shift = host->data_shift;
2507         u32 status;
2508         unsigned int len;
2509         unsigned int remain, fcnt;
2510
2511         do {
2512                 if (!sg_miter_next(sg_miter))
2513                         goto done;
2514
2515                 host->sg = sg_miter->piter.sg;
2516                 buf = sg_miter->addr;
2517                 remain = sg_miter->length;
2518                 offset = 0;
2519
2520                 do {
2521                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2522                                         << shift) + host->part_buf_count;
2523                         len = min(remain, fcnt);
2524                         if (!len)
2525                                 break;
2526                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2527                         data->bytes_xfered += len;
2528                         offset += len;
2529                         remain -= len;
2530                 } while (remain);
2531
2532                 sg_miter->consumed = offset;
2533                 status = mci_readl(host, MINTSTS);
2534                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2535         /* if the RXDR is ready read again */
2536         } while ((status & SDMMC_INT_RXDR) ||
2537                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2538
2539         if (!remain) {
2540                 if (!sg_miter_next(sg_miter))
2541                         goto done;
2542                 sg_miter->consumed = 0;
2543         }
2544         sg_miter_stop(sg_miter);
2545         return;
2546
2547 done:
2548         sg_miter_stop(sg_miter);
2549         host->sg = NULL;
2550         smp_wmb(); /* drain writebuffer */
2551         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2552 }
2553
2554 static void dw_mci_write_data_pio(struct dw_mci *host)
2555 {
2556         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2557         void *buf;
2558         unsigned int offset;
2559         struct mmc_data *data = host->data;
2560         int shift = host->data_shift;
2561         u32 status;
2562         unsigned int len;
2563         unsigned int fifo_depth = host->fifo_depth;
2564         unsigned int remain, fcnt;
2565
2566         do {
2567                 if (!sg_miter_next(sg_miter))
2568                         goto done;
2569
2570                 host->sg = sg_miter->piter.sg;
2571                 buf = sg_miter->addr;
2572                 remain = sg_miter->length;
2573                 offset = 0;
2574
2575                 do {
2576                         fcnt = ((fifo_depth -
2577                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2578                                         << shift) - host->part_buf_count;
2579                         len = min(remain, fcnt);
2580                         if (!len)
2581                                 break;
2582                         host->push_data(host, (void *)(buf + offset), len);
2583                         data->bytes_xfered += len;
2584                         offset += len;
2585                         remain -= len;
2586                 } while (remain);
2587
2588                 sg_miter->consumed = offset;
2589                 status = mci_readl(host, MINTSTS);
2590                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2591         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2592
2593         if (!remain) {
2594                 if (!sg_miter_next(sg_miter))
2595                         goto done;
2596                 sg_miter->consumed = 0;
2597         }
2598         sg_miter_stop(sg_miter);
2599         return;
2600
2601 done:
2602         sg_miter_stop(sg_miter);
2603         host->sg = NULL;
2604         smp_wmb(); /* drain writebuffer */
2605         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2606 }
2607
2608 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2609 {
2610         del_timer(&host->cto_timer);
2611
2612         if (!host->cmd_status)
2613                 host->cmd_status = status;
2614
2615         smp_wmb(); /* drain writebuffer */
2616
2617         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2618         tasklet_schedule(&host->tasklet);
2619 }
2620
2621 static void dw_mci_handle_cd(struct dw_mci *host)
2622 {
2623         struct dw_mci_slot *slot = host->slot;
2624
2625         if (slot->mmc->ops->card_event)
2626                 slot->mmc->ops->card_event(slot->mmc);
2627         mmc_detect_change(slot->mmc,
2628                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2629 }
2630
2631 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2632 {
2633         struct dw_mci *host = dev_id;
2634         u32 pending;
2635         struct dw_mci_slot *slot = host->slot;
2636         unsigned long irqflags;
2637
2638         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2639
2640         if (pending) {
2641                 /* Check volt switch first, since it can look like an error */
2642                 if ((host->state == STATE_SENDING_CMD11) &&
2643                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2644                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2645                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2646
2647                         /*
2648                          * Hold the lock; we know cmd11_timer can't be kicked
2649                          * off after the lock is released, so safe to delete.
2650                          */
2651                         spin_lock_irqsave(&host->irq_lock, irqflags);
2652                         dw_mci_cmd_interrupt(host, pending);
2653                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2654
2655                         del_timer(&host->cmd11_timer);
2656                 }
2657
2658                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2659                         spin_lock_irqsave(&host->irq_lock, irqflags);
2660
2661                         del_timer(&host->cto_timer);
2662                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2663                         host->cmd_status = pending;
2664                         smp_wmb(); /* drain writebuffer */
2665                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2666
2667                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2668                 }
2669
2670                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2671                         /* if there is an error report DATA_ERROR */
2672                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2673                         host->data_status = pending;
2674                         smp_wmb(); /* drain writebuffer */
2675                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2676                         tasklet_schedule(&host->tasklet);
2677                 }
2678
2679                 if (pending & SDMMC_INT_DATA_OVER) {
2680                         del_timer(&host->dto_timer);
2681
2682                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2683                         if (!host->data_status)
2684                                 host->data_status = pending;
2685                         smp_wmb(); /* drain writebuffer */
2686                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2687                                 if (host->sg != NULL)
2688                                         dw_mci_read_data_pio(host, true);
2689                         }
2690                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2691                         tasklet_schedule(&host->tasklet);
2692                 }
2693
2694                 if (pending & SDMMC_INT_RXDR) {
2695                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2696                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2697                                 dw_mci_read_data_pio(host, false);
2698                 }
2699
2700                 if (pending & SDMMC_INT_TXDR) {
2701                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2702                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2703                                 dw_mci_write_data_pio(host);
2704                 }
2705
2706                 if (pending & SDMMC_INT_CMD_DONE) {
2707                         spin_lock_irqsave(&host->irq_lock, irqflags);
2708
2709                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2710                         dw_mci_cmd_interrupt(host, pending);
2711
2712                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2713                 }
2714
2715                 if (pending & SDMMC_INT_CD) {
2716                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2717                         dw_mci_handle_cd(host);
2718                 }
2719
2720                 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2721                         mci_writel(host, RINTSTS,
2722                                    SDMMC_INT_SDIO(slot->sdio_id));
2723                         __dw_mci_enable_sdio_irq(slot, 0);
2724                         sdio_signal_irq(slot->mmc);
2725                 }
2726
2727         }
2728
2729         if (host->use_dma != TRANS_MODE_IDMAC)
2730                 return IRQ_HANDLED;
2731
2732         /* Handle IDMA interrupts */
2733         if (host->dma_64bit_address == 1) {
2734                 pending = mci_readl(host, IDSTS64);
2735                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2736                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2737                                                         SDMMC_IDMAC_INT_RI);
2738                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2739                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2740                                 host->dma_ops->complete((void *)host);
2741                 }
2742         } else {
2743                 pending = mci_readl(host, IDSTS);
2744                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2745                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2746                                                         SDMMC_IDMAC_INT_RI);
2747                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2748                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2749                                 host->dma_ops->complete((void *)host);
2750                 }
2751         }
2752
2753         return IRQ_HANDLED;
2754 }
2755
2756 static int dw_mci_init_slot(struct dw_mci *host)
2757 {
2758         struct mmc_host *mmc;
2759         struct dw_mci_slot *slot;
2760         const struct dw_mci_drv_data *drv_data = host->drv_data;
2761         int ctrl_id, ret;
2762         u32 freq[2];
2763
2764         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2765         if (!mmc)
2766                 return -ENOMEM;
2767
2768         slot = mmc_priv(mmc);
2769         slot->id = 0;
2770         slot->sdio_id = host->sdio_id0 + slot->id;
2771         slot->mmc = mmc;
2772         slot->host = host;
2773         host->slot = slot;
2774
2775         mmc->ops = &dw_mci_ops;
2776         if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2777                                            freq, 2)) {
2778                 mmc->f_min = DW_MCI_FREQ_MIN;
2779                 mmc->f_max = DW_MCI_FREQ_MAX;
2780         } else {
2781                 dev_info(host->dev,
2782                         "'clock-freq-min-max' property was deprecated.\n");
2783                 mmc->f_min = freq[0];
2784                 mmc->f_max = freq[1];
2785         }
2786
2787         /*if there are external regulators, get them*/
2788         ret = mmc_regulator_get_supply(mmc);
2789         if (ret == -EPROBE_DEFER)
2790                 goto err_host_allocated;
2791
2792         if (!mmc->ocr_avail)
2793                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2794
2795         if (host->pdata->caps)
2796                 mmc->caps = host->pdata->caps;
2797
2798         /*
2799          * Support MMC_CAP_ERASE by default.
2800          * It needs to use trim/discard/erase commands.
2801          */
2802         mmc->caps |= MMC_CAP_ERASE;
2803
2804         if (host->pdata->pm_caps)
2805                 mmc->pm_caps = host->pdata->pm_caps;
2806
2807         if (host->dev->of_node) {
2808                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2809                 if (ctrl_id < 0)
2810                         ctrl_id = 0;
2811         } else {
2812                 ctrl_id = to_platform_device(host->dev)->id;
2813         }
2814         if (drv_data && drv_data->caps)
2815                 mmc->caps |= drv_data->caps[ctrl_id];
2816
2817         if (host->pdata->caps2)
2818                 mmc->caps2 = host->pdata->caps2;
2819
2820         ret = mmc_of_parse(mmc);
2821         if (ret)
2822                 goto err_host_allocated;
2823
2824         /* Process SDIO IRQs through the sdio_irq_work. */
2825         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2826                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2827
2828         /* Useful defaults if platform data is unset. */
2829         if (host->use_dma == TRANS_MODE_IDMAC) {
2830                 mmc->max_segs = host->ring_size;
2831                 mmc->max_blk_size = 65535;
2832                 mmc->max_seg_size = 0x1000;
2833                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2834                 mmc->max_blk_count = mmc->max_req_size / 512;
2835         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2836                 mmc->max_segs = 64;
2837                 mmc->max_blk_size = 65535;
2838                 mmc->max_blk_count = 65535;
2839                 mmc->max_req_size =
2840                                 mmc->max_blk_size * mmc->max_blk_count;
2841                 mmc->max_seg_size = mmc->max_req_size;
2842         } else {
2843                 /* TRANS_MODE_PIO */
2844                 mmc->max_segs = 64;
2845                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2846                 mmc->max_blk_count = 512;
2847                 mmc->max_req_size = mmc->max_blk_size *
2848                                     mmc->max_blk_count;
2849                 mmc->max_seg_size = mmc->max_req_size;
2850         }
2851
2852         dw_mci_get_cd(mmc);
2853
2854         ret = mmc_add_host(mmc);
2855         if (ret)
2856                 goto err_host_allocated;
2857
2858 #if defined(CONFIG_DEBUG_FS)
2859         dw_mci_init_debugfs(slot);
2860 #endif
2861
2862         return 0;
2863
2864 err_host_allocated:
2865         mmc_free_host(mmc);
2866         return ret;
2867 }
2868
2869 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2870 {
2871         /* Debugfs stuff is cleaned up by mmc core */
2872         mmc_remove_host(slot->mmc);
2873         slot->host->slot = NULL;
2874         mmc_free_host(slot->mmc);
2875 }
2876
2877 static void dw_mci_init_dma(struct dw_mci *host)
2878 {
2879         int addr_config;
2880         struct device *dev = host->dev;
2881
2882         /*
2883         * Check tansfer mode from HCON[17:16]
2884         * Clear the ambiguous description of dw_mmc databook:
2885         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2886         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2887         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2888         * 2b'11: Non DW DMA Interface -> pio only
2889         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2890         * simpler request/acknowledge handshake mechanism and both of them
2891         * are regarded as external dma master for dw_mmc.
2892         */
2893         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2894         if (host->use_dma == DMA_INTERFACE_IDMA) {
2895                 host->use_dma = TRANS_MODE_IDMAC;
2896         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2897                    host->use_dma == DMA_INTERFACE_GDMA) {
2898                 host->use_dma = TRANS_MODE_EDMAC;
2899         } else {
2900                 goto no_dma;
2901         }
2902
2903         /* Determine which DMA interface to use */
2904         if (host->use_dma == TRANS_MODE_IDMAC) {
2905                 /*
2906                 * Check ADDR_CONFIG bit in HCON to find
2907                 * IDMAC address bus width
2908                 */
2909                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2910
2911                 if (addr_config == 1) {
2912                         /* host supports IDMAC in 64-bit address mode */
2913                         host->dma_64bit_address = 1;
2914                         dev_info(host->dev,
2915                                  "IDMAC supports 64-bit address mode.\n");
2916                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2917                                 dma_set_coherent_mask(host->dev,
2918                                                       DMA_BIT_MASK(64));
2919                 } else {
2920                         /* host supports IDMAC in 32-bit address mode */
2921                         host->dma_64bit_address = 0;
2922                         dev_info(host->dev,
2923                                  "IDMAC supports 32-bit address mode.\n");
2924                 }
2925
2926                 /* Alloc memory for sg translation */
2927                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2928                                                    DESC_RING_BUF_SZ,
2929                                                    &host->sg_dma, GFP_KERNEL);
2930                 if (!host->sg_cpu) {
2931                         dev_err(host->dev,
2932                                 "%s: could not alloc DMA memory\n",
2933                                 __func__);
2934                         goto no_dma;
2935                 }
2936
2937                 host->dma_ops = &dw_mci_idmac_ops;
2938                 dev_info(host->dev, "Using internal DMA controller.\n");
2939         } else {
2940                 /* TRANS_MODE_EDMAC: check dma bindings again */
2941                 if ((device_property_read_string_array(dev, "dma-names",
2942                                                        NULL, 0) < 0) ||
2943                     !device_property_present(dev, "dmas")) {
2944                         goto no_dma;
2945                 }
2946                 host->dma_ops = &dw_mci_edmac_ops;
2947                 dev_info(host->dev, "Using external DMA controller.\n");
2948         }
2949
2950         if (host->dma_ops->init && host->dma_ops->start &&
2951             host->dma_ops->stop && host->dma_ops->cleanup) {
2952                 if (host->dma_ops->init(host)) {
2953                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2954                                 __func__);
2955                         goto no_dma;
2956                 }
2957         } else {
2958                 dev_err(host->dev, "DMA initialization not found.\n");
2959                 goto no_dma;
2960         }
2961
2962         return;
2963
2964 no_dma:
2965         dev_info(host->dev, "Using PIO mode.\n");
2966         host->use_dma = TRANS_MODE_PIO;
2967 }
2968
2969 static void dw_mci_cmd11_timer(unsigned long arg)
2970 {
2971         struct dw_mci *host = (struct dw_mci *)arg;
2972
2973         if (host->state != STATE_SENDING_CMD11) {
2974                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2975                 return;
2976         }
2977
2978         host->cmd_status = SDMMC_INT_RTO;
2979         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2980         tasklet_schedule(&host->tasklet);
2981 }
2982
2983 static void dw_mci_cto_timer(unsigned long arg)
2984 {
2985         struct dw_mci *host = (struct dw_mci *)arg;
2986         unsigned long irqflags;
2987         u32 pending;
2988
2989         spin_lock_irqsave(&host->irq_lock, irqflags);
2990
2991         /*
2992          * If somehow we have very bad interrupt latency it's remotely possible
2993          * that the timer could fire while the interrupt is still pending or
2994          * while the interrupt is midway through running.  Let's be paranoid
2995          * and detect those two cases.  Note that this is paranoia is somewhat
2996          * justified because in this function we don't actually cancel the
2997          * pending command in the controller--we just assume it will never come.
2998          */
2999         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3000         if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3001                 /* The interrupt should fire; no need to act but we can warn */
3002                 dev_warn(host->dev, "Unexpected interrupt latency\n");
3003                 goto exit;
3004         }
3005         if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3006                 /* Presumably interrupt handler couldn't delete the timer */
3007                 dev_warn(host->dev, "CTO timeout when already completed\n");
3008                 goto exit;
3009         }
3010
3011         /*
3012          * Continued paranoia to make sure we're in the state we expect.
3013          * This paranoia isn't really justified but it seems good to be safe.
3014          */
3015         switch (host->state) {
3016         case STATE_SENDING_CMD11:
3017         case STATE_SENDING_CMD:
3018         case STATE_SENDING_STOP:
3019                 /*
3020                  * If CMD_DONE interrupt does NOT come in sending command
3021                  * state, we should notify the driver to terminate current
3022                  * transfer and report a command timeout to the core.
3023                  */
3024                 host->cmd_status = SDMMC_INT_RTO;
3025                 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3026                 tasklet_schedule(&host->tasklet);
3027                 break;
3028         default:
3029                 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3030                          host->state);
3031                 break;
3032         }
3033
3034 exit:
3035         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3036 }
3037
3038 static void dw_mci_dto_timer(unsigned long arg)
3039 {
3040         struct dw_mci *host = (struct dw_mci *)arg;
3041
3042         switch (host->state) {
3043         case STATE_SENDING_DATA:
3044         case STATE_DATA_BUSY:
3045                 /*
3046                  * If DTO interrupt does NOT come in sending data state,
3047                  * we should notify the driver to terminate current transfer
3048                  * and report a data timeout to the core.
3049                  */
3050                 host->data_status = SDMMC_INT_DRTO;
3051                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3052                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3053                 tasklet_schedule(&host->tasklet);
3054                 break;
3055         default:
3056                 break;
3057         }
3058 }
3059
3060 #ifdef CONFIG_OF
3061 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3062 {
3063         struct dw_mci_board *pdata;
3064         struct device *dev = host->dev;
3065         const struct dw_mci_drv_data *drv_data = host->drv_data;
3066         int ret;
3067         u32 clock_frequency;
3068
3069         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3070         if (!pdata)
3071                 return ERR_PTR(-ENOMEM);
3072
3073         /* find reset controller when exist */
3074         pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3075         if (IS_ERR(pdata->rstc)) {
3076                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3077                         return ERR_PTR(-EPROBE_DEFER);
3078         }
3079
3080         /* find out number of slots supported */
3081         if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
3082                 dev_info(dev, "'num-slots' was deprecated.\n");
3083
3084         if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3085                 dev_info(dev,
3086                          "fifo-depth property not found, using value of FIFOTH register as default\n");
3087
3088         device_property_read_u32(dev, "card-detect-delay",
3089                                  &pdata->detect_delay_ms);
3090
3091         device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3092
3093         if (device_property_present(dev, "fifo-watermark-aligned"))
3094                 host->wm_aligned = true;
3095
3096         if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3097                 pdata->bus_hz = clock_frequency;
3098
3099         if (drv_data && drv_data->parse_dt) {
3100                 ret = drv_data->parse_dt(host);
3101                 if (ret)
3102                         return ERR_PTR(ret);
3103         }
3104
3105         return pdata;
3106 }
3107
3108 #else /* CONFIG_OF */
3109 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3110 {
3111         return ERR_PTR(-EINVAL);
3112 }
3113 #endif /* CONFIG_OF */
3114
3115 static void dw_mci_enable_cd(struct dw_mci *host)
3116 {
3117         unsigned long irqflags;
3118         u32 temp;
3119
3120         /*
3121          * No need for CD if all slots have a non-error GPIO
3122          * as well as broken card detection is found.
3123          */
3124         if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3125                 return;
3126
3127         if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3128                 spin_lock_irqsave(&host->irq_lock, irqflags);
3129                 temp = mci_readl(host, INTMASK);
3130                 temp  |= SDMMC_INT_CD;
3131                 mci_writel(host, INTMASK, temp);
3132                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3133         }
3134 }
3135
3136 int dw_mci_probe(struct dw_mci *host)
3137 {
3138         const struct dw_mci_drv_data *drv_data = host->drv_data;
3139         int width, i, ret = 0;
3140         u32 fifo_size;
3141
3142         if (!host->pdata) {
3143                 host->pdata = dw_mci_parse_dt(host);
3144                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3145                         return -EPROBE_DEFER;
3146                 } else if (IS_ERR(host->pdata)) {
3147                         dev_err(host->dev, "platform data not available\n");
3148                         return -EINVAL;
3149                 }
3150         }
3151
3152         host->biu_clk = devm_clk_get(host->dev, "biu");
3153         if (IS_ERR(host->biu_clk)) {
3154                 dev_dbg(host->dev, "biu clock not available\n");
3155         } else {
3156                 ret = clk_prepare_enable(host->biu_clk);
3157                 if (ret) {
3158                         dev_err(host->dev, "failed to enable biu clock\n");
3159                         return ret;
3160                 }
3161         }
3162
3163         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3164         if (IS_ERR(host->ciu_clk)) {
3165                 dev_dbg(host->dev, "ciu clock not available\n");
3166                 host->bus_hz = host->pdata->bus_hz;
3167         } else {
3168                 ret = clk_prepare_enable(host->ciu_clk);
3169                 if (ret) {
3170                         dev_err(host->dev, "failed to enable ciu clock\n");
3171                         goto err_clk_biu;
3172                 }
3173
3174                 if (host->pdata->bus_hz) {
3175                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3176                         if (ret)
3177                                 dev_warn(host->dev,
3178                                          "Unable to set bus rate to %uHz\n",
3179                                          host->pdata->bus_hz);
3180                 }
3181                 host->bus_hz = clk_get_rate(host->ciu_clk);
3182         }
3183
3184         if (!host->bus_hz) {
3185                 dev_err(host->dev,
3186                         "Platform data must supply bus speed\n");
3187                 ret = -ENODEV;
3188                 goto err_clk_ciu;
3189         }
3190
3191         if (!IS_ERR(host->pdata->rstc)) {
3192                 reset_control_assert(host->pdata->rstc);
3193                 usleep_range(10, 50);
3194                 reset_control_deassert(host->pdata->rstc);
3195         }
3196
3197         if (drv_data && drv_data->init) {
3198                 ret = drv_data->init(host);
3199                 if (ret) {
3200                         dev_err(host->dev,
3201                                 "implementation specific init failed\n");
3202                         goto err_clk_ciu;
3203                 }
3204         }
3205
3206         setup_timer(&host->cmd11_timer,
3207                     dw_mci_cmd11_timer, (unsigned long)host);
3208
3209         setup_timer(&host->cto_timer,
3210                     dw_mci_cto_timer, (unsigned long)host);
3211
3212         setup_timer(&host->dto_timer,
3213                     dw_mci_dto_timer, (unsigned long)host);
3214
3215         spin_lock_init(&host->lock);
3216         spin_lock_init(&host->irq_lock);
3217         INIT_LIST_HEAD(&host->queue);
3218
3219         /*
3220          * Get the host data width - this assumes that HCON has been set with
3221          * the correct values.
3222          */
3223         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3224         if (!i) {
3225                 host->push_data = dw_mci_push_data16;
3226                 host->pull_data = dw_mci_pull_data16;
3227                 width = 16;
3228                 host->data_shift = 1;
3229         } else if (i == 2) {
3230                 host->push_data = dw_mci_push_data64;
3231                 host->pull_data = dw_mci_pull_data64;
3232                 width = 64;
3233                 host->data_shift = 3;
3234         } else {
3235                 /* Check for a reserved value, and warn if it is */
3236                 WARN((i != 1),
3237                      "HCON reports a reserved host data width!\n"
3238                      "Defaulting to 32-bit access.\n");
3239                 host->push_data = dw_mci_push_data32;
3240                 host->pull_data = dw_mci_pull_data32;
3241                 width = 32;
3242                 host->data_shift = 2;
3243         }
3244
3245         /* Reset all blocks */
3246         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3247                 ret = -ENODEV;
3248                 goto err_clk_ciu;
3249         }
3250
3251         host->dma_ops = host->pdata->dma_ops;
3252         dw_mci_init_dma(host);
3253
3254         /* Clear the interrupts for the host controller */
3255         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3256         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3257
3258         /* Put in max timeout */
3259         mci_writel(host, TMOUT, 0xFFFFFFFF);
3260
3261         /*
3262          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3263          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3264          */
3265         if (!host->pdata->fifo_depth) {
3266                 /*
3267                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3268                  * have been overwritten by the bootloader, just like we're
3269                  * about to do, so if you know the value for your hardware, you
3270                  * should put it in the platform data.
3271                  */
3272                 fifo_size = mci_readl(host, FIFOTH);
3273                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3274         } else {
3275                 fifo_size = host->pdata->fifo_depth;
3276         }
3277         host->fifo_depth = fifo_size;
3278         host->fifoth_val =
3279                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3280         mci_writel(host, FIFOTH, host->fifoth_val);
3281
3282         /* disable clock to CIU */
3283         mci_writel(host, CLKENA, 0);
3284         mci_writel(host, CLKSRC, 0);
3285
3286         /*
3287          * In 2.40a spec, Data offset is changed.
3288          * Need to check the version-id and set data-offset for DATA register.
3289          */
3290         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3291         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3292
3293         if (host->data_addr_override)
3294                 host->fifo_reg = host->regs + host->data_addr_override;
3295         else if (host->verid < DW_MMC_240A)
3296                 host->fifo_reg = host->regs + DATA_OFFSET;
3297         else
3298                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3299
3300         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3301         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3302                                host->irq_flags, "dw-mci", host);
3303         if (ret)
3304                 goto err_dmaunmap;
3305
3306         /*
3307          * Enable interrupts for command done, data over, data empty,
3308          * receive ready and error such as transmit, receive timeout, crc error
3309          */
3310         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3311                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3312                    DW_MCI_ERROR_FLAGS);
3313         /* Enable mci interrupt */
3314         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3315
3316         dev_info(host->dev,
3317                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3318                  host->irq, width, fifo_size);
3319
3320         /* We need at least one slot to succeed */
3321         ret = dw_mci_init_slot(host);
3322         if (ret) {
3323                 dev_dbg(host->dev, "slot %d init failed\n", i);
3324                 goto err_dmaunmap;
3325         }
3326
3327         /* Now that slots are all setup, we can enable card detect */
3328         dw_mci_enable_cd(host);
3329
3330         return 0;
3331
3332 err_dmaunmap:
3333         if (host->use_dma && host->dma_ops->exit)
3334                 host->dma_ops->exit(host);
3335
3336         if (!IS_ERR(host->pdata->rstc))
3337                 reset_control_assert(host->pdata->rstc);
3338
3339 err_clk_ciu:
3340         clk_disable_unprepare(host->ciu_clk);
3341
3342 err_clk_biu:
3343         clk_disable_unprepare(host->biu_clk);
3344
3345         return ret;
3346 }
3347 EXPORT_SYMBOL(dw_mci_probe);
3348
3349 void dw_mci_remove(struct dw_mci *host)
3350 {
3351         dev_dbg(host->dev, "remove slot\n");
3352         if (host->slot)
3353                 dw_mci_cleanup_slot(host->slot);
3354
3355         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3356         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3357
3358         /* disable clock to CIU */
3359         mci_writel(host, CLKENA, 0);
3360         mci_writel(host, CLKSRC, 0);
3361
3362         if (host->use_dma && host->dma_ops->exit)
3363                 host->dma_ops->exit(host);
3364
3365         if (!IS_ERR(host->pdata->rstc))
3366                 reset_control_assert(host->pdata->rstc);
3367
3368         clk_disable_unprepare(host->ciu_clk);
3369         clk_disable_unprepare(host->biu_clk);
3370 }
3371 EXPORT_SYMBOL(dw_mci_remove);
3372
3373
3374
3375 #ifdef CONFIG_PM
3376 int dw_mci_runtime_suspend(struct device *dev)
3377 {
3378         struct dw_mci *host = dev_get_drvdata(dev);
3379
3380         if (host->use_dma && host->dma_ops->exit)
3381                 host->dma_ops->exit(host);
3382
3383         clk_disable_unprepare(host->ciu_clk);
3384
3385         if (host->slot &&
3386             (mmc_can_gpio_cd(host->slot->mmc) ||
3387              !mmc_card_is_removable(host->slot->mmc)))
3388                 clk_disable_unprepare(host->biu_clk);
3389
3390         return 0;
3391 }
3392 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3393
3394 int dw_mci_runtime_resume(struct device *dev)
3395 {
3396         int ret = 0;
3397         struct dw_mci *host = dev_get_drvdata(dev);
3398
3399         if (host->slot &&
3400             (mmc_can_gpio_cd(host->slot->mmc) ||
3401              !mmc_card_is_removable(host->slot->mmc))) {
3402                 ret = clk_prepare_enable(host->biu_clk);
3403                 if (ret)
3404                         return ret;
3405         }
3406
3407         ret = clk_prepare_enable(host->ciu_clk);
3408         if (ret)
3409                 goto err;
3410
3411         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3412                 clk_disable_unprepare(host->ciu_clk);
3413                 ret = -ENODEV;
3414                 goto err;
3415         }
3416
3417         if (host->use_dma && host->dma_ops->init)
3418                 host->dma_ops->init(host);
3419
3420         /*
3421          * Restore the initial value at FIFOTH register
3422          * And Invalidate the prev_blksz with zero
3423          */
3424          mci_writel(host, FIFOTH, host->fifoth_val);
3425          host->prev_blksz = 0;
3426
3427         /* Put in max timeout */
3428         mci_writel(host, TMOUT, 0xFFFFFFFF);
3429
3430         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3431         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3432                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3433                    DW_MCI_ERROR_FLAGS);
3434         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3435
3436
3437         if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3438                 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3439
3440         /* Force setup bus to guarantee available clock output */
3441         dw_mci_setup_bus(host->slot, true);
3442
3443         /* Now that slots are all setup, we can enable card detect */
3444         dw_mci_enable_cd(host);
3445
3446         return 0;
3447
3448 err:
3449         if (host->slot &&
3450             (mmc_can_gpio_cd(host->slot->mmc) ||
3451              !mmc_card_is_removable(host->slot->mmc)))
3452                 clk_disable_unprepare(host->biu_clk);
3453
3454         return ret;
3455 }
3456 EXPORT_SYMBOL(dw_mci_runtime_resume);
3457 #endif /* CONFIG_PM */
3458
3459 static int __init dw_mci_init(void)
3460 {
3461         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3462         return 0;
3463 }
3464
3465 static void __exit dw_mci_exit(void)
3466 {
3467 }
3468
3469 module_init(dw_mci_init);
3470 module_exit(dw_mci_exit);
3471
3472 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3473 MODULE_AUTHOR("NXP Semiconductor VietNam");
3474 MODULE_AUTHOR("Imagination Technologies Ltd");
3475 MODULE_LICENSE("GPL v2");