mmc: dw_mmc: Fix the DTO timeout calculation
[sfrench/cifs-2.6.git] / drivers / mmc / host / dw_mmc.c
1 /*
2  * Synopsys DesignWare Multimedia Card Interface driver
3  *  (Based on NXP driver for lpc 31xx)
4  *
5  * Copyright (C) 2009 NXP Semiconductors
6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/of.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
42
43 #include "dw_mmc.h"
44
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
48                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
52                                  DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS      1
54 #define DW_MCI_RECV_STATUS      2
55 #define DW_MCI_DMA_THRESHOLD    16
56
57 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
59
60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63                                  SDMMC_IDMAC_INT_TI)
64
65 #define DESC_RING_BUF_SZ        PAGE_SIZE
66
67 struct idmac_desc_64addr {
68         u32             des0;   /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70         !((x) & cpu_to_le32(IDMAC_DES0_OWN))
71
72         u32             des1;   /* Reserved */
73
74         u32             des2;   /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
78
79         u32             des3;   /* Reserved */
80
81         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
82         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
83
84         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
85         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
86 };
87
88 struct idmac_desc {
89         __le32          des0;   /* Control Descriptor */
90 #define IDMAC_DES0_DIC  BIT(1)
91 #define IDMAC_DES0_LD   BIT(2)
92 #define IDMAC_DES0_FD   BIT(3)
93 #define IDMAC_DES0_CH   BIT(4)
94 #define IDMAC_DES0_ER   BIT(5)
95 #define IDMAC_DES0_CES  BIT(30)
96 #define IDMAC_DES0_OWN  BIT(31)
97
98         __le32          des1;   /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
101
102         __le32          des2;   /* buffer 1 physical address */
103
104         __le32          des3;   /* buffer 2 physical address */
105 };
106
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
109
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
112 {
113         struct dw_mci_slot *slot = s->private;
114         struct mmc_request *mrq;
115         struct mmc_command *cmd;
116         struct mmc_command *stop;
117         struct mmc_data *data;
118
119         /* Make sure we get a consistent snapshot */
120         spin_lock_bh(&slot->host->lock);
121         mrq = slot->mrq;
122
123         if (mrq) {
124                 cmd = mrq->cmd;
125                 data = mrq->data;
126                 stop = mrq->stop;
127
128                 if (cmd)
129                         seq_printf(s,
130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131                                    cmd->opcode, cmd->arg, cmd->flags,
132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
133                                    cmd->resp[2], cmd->error);
134                 if (data)
135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136                                    data->bytes_xfered, data->blocks,
137                                    data->blksz, data->flags, data->error);
138                 if (stop)
139                         seq_printf(s,
140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141                                    stop->opcode, stop->arg, stop->flags,
142                                    stop->resp[0], stop->resp[1], stop->resp[2],
143                                    stop->resp[2], stop->error);
144         }
145
146         spin_unlock_bh(&slot->host->lock);
147
148         return 0;
149 }
150
151 static int dw_mci_req_open(struct inode *inode, struct file *file)
152 {
153         return single_open(file, dw_mci_req_show, inode->i_private);
154 }
155
156 static const struct file_operations dw_mci_req_fops = {
157         .owner          = THIS_MODULE,
158         .open           = dw_mci_req_open,
159         .read           = seq_read,
160         .llseek         = seq_lseek,
161         .release        = single_release,
162 };
163
164 static int dw_mci_regs_show(struct seq_file *s, void *v)
165 {
166         struct dw_mci *host = s->private;
167
168         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
169         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
170         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
171         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
172         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
173         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
174
175         return 0;
176 }
177
178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
179 {
180         return single_open(file, dw_mci_regs_show, inode->i_private);
181 }
182
183 static const struct file_operations dw_mci_regs_fops = {
184         .owner          = THIS_MODULE,
185         .open           = dw_mci_regs_open,
186         .read           = seq_read,
187         .llseek         = seq_lseek,
188         .release        = single_release,
189 };
190
191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
192 {
193         struct mmc_host *mmc = slot->mmc;
194         struct dw_mci *host = slot->host;
195         struct dentry *root;
196         struct dentry *node;
197
198         root = mmc->debugfs_root;
199         if (!root)
200                 return;
201
202         node = debugfs_create_file("regs", S_IRUSR, root, host,
203                                    &dw_mci_regs_fops);
204         if (!node)
205                 goto err;
206
207         node = debugfs_create_file("req", S_IRUSR, root, slot,
208                                    &dw_mci_req_fops);
209         if (!node)
210                 goto err;
211
212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
213         if (!node)
214                 goto err;
215
216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
217                                   (u32 *)&host->pending_events);
218         if (!node)
219                 goto err;
220
221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
222                                   (u32 *)&host->completed_events);
223         if (!node)
224                 goto err;
225
226         return;
227
228 err:
229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
230 }
231 #endif /* defined(CONFIG_DEBUG_FS) */
232
233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
234 {
235         u32 ctrl;
236
237         ctrl = mci_readl(host, CTRL);
238         ctrl |= reset;
239         mci_writel(host, CTRL, ctrl);
240
241         /* wait till resets clear */
242         if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
243                                       !(ctrl & reset),
244                                       1, 500 * USEC_PER_MSEC)) {
245                 dev_err(host->dev,
246                         "Timeout resetting block (ctrl reset %#x)\n",
247                         ctrl & reset);
248                 return false;
249         }
250
251         return true;
252 }
253
254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
255 {
256         u32 status;
257
258         /*
259          * Databook says that before issuing a new data transfer command
260          * we need to check to see if the card is busy.  Data transfer commands
261          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
262          *
263          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
264          * expected.
265          */
266         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
267             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
268                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
269                                               status,
270                                               !(status & SDMMC_STATUS_BUSY),
271                                               10, 500 * USEC_PER_MSEC))
272                         dev_err(host->dev, "Busy; trying anyway\n");
273         }
274 }
275
276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
277 {
278         struct dw_mci *host = slot->host;
279         unsigned int cmd_status = 0;
280
281         mci_writel(host, CMDARG, arg);
282         wmb(); /* drain writebuffer */
283         dw_mci_wait_while_busy(host, cmd);
284         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
285
286         if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
287                                       !(cmd_status & SDMMC_CMD_START),
288                                       1, 500 * USEC_PER_MSEC))
289                 dev_err(&slot->mmc->class_dev,
290                         "Timeout sending command (cmd %#x arg %#x status %#x)\n",
291                         cmd, arg, cmd_status);
292 }
293
294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
295 {
296         struct dw_mci_slot *slot = mmc_priv(mmc);
297         struct dw_mci *host = slot->host;
298         u32 cmdr;
299
300         cmd->error = -EINPROGRESS;
301         cmdr = cmd->opcode;
302
303         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
304             cmd->opcode == MMC_GO_IDLE_STATE ||
305             cmd->opcode == MMC_GO_INACTIVE_STATE ||
306             (cmd->opcode == SD_IO_RW_DIRECT &&
307              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
308                 cmdr |= SDMMC_CMD_STOP;
309         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
310                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
311
312         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
313                 u32 clk_en_a;
314
315                 /* Special bit makes CMD11 not die */
316                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
317
318                 /* Change state to continue to handle CMD11 weirdness */
319                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
320                 slot->host->state = STATE_SENDING_CMD11;
321
322                 /*
323                  * We need to disable low power mode (automatic clock stop)
324                  * while doing voltage switch so we don't confuse the card,
325                  * since stopping the clock is a specific part of the UHS
326                  * voltage change dance.
327                  *
328                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
329                  * unconditionally turned back on in dw_mci_setup_bus() if it's
330                  * ever called with a non-zero clock.  That shouldn't happen
331                  * until the voltage change is all done.
332                  */
333                 clk_en_a = mci_readl(host, CLKENA);
334                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
335                 mci_writel(host, CLKENA, clk_en_a);
336                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
337                              SDMMC_CMD_PRV_DAT_WAIT, 0);
338         }
339
340         if (cmd->flags & MMC_RSP_PRESENT) {
341                 /* We expect a response, so set this bit */
342                 cmdr |= SDMMC_CMD_RESP_EXP;
343                 if (cmd->flags & MMC_RSP_136)
344                         cmdr |= SDMMC_CMD_RESP_LONG;
345         }
346
347         if (cmd->flags & MMC_RSP_CRC)
348                 cmdr |= SDMMC_CMD_RESP_CRC;
349
350         if (cmd->data) {
351                 cmdr |= SDMMC_CMD_DAT_EXP;
352                 if (cmd->data->flags & MMC_DATA_WRITE)
353                         cmdr |= SDMMC_CMD_DAT_WR;
354         }
355
356         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
357                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
358
359         return cmdr;
360 }
361
362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
363 {
364         struct mmc_command *stop;
365         u32 cmdr;
366
367         if (!cmd->data)
368                 return 0;
369
370         stop = &host->stop_abort;
371         cmdr = cmd->opcode;
372         memset(stop, 0, sizeof(struct mmc_command));
373
374         if (cmdr == MMC_READ_SINGLE_BLOCK ||
375             cmdr == MMC_READ_MULTIPLE_BLOCK ||
376             cmdr == MMC_WRITE_BLOCK ||
377             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
378             cmdr == MMC_SEND_TUNING_BLOCK ||
379             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
380                 stop->opcode = MMC_STOP_TRANSMISSION;
381                 stop->arg = 0;
382                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
383         } else if (cmdr == SD_IO_RW_EXTENDED) {
384                 stop->opcode = SD_IO_RW_DIRECT;
385                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
386                              ((cmd->arg >> 28) & 0x7);
387                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
388         } else {
389                 return 0;
390         }
391
392         cmdr = stop->opcode | SDMMC_CMD_STOP |
393                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
394
395         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
396                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
397
398         return cmdr;
399 }
400
401 static inline void dw_mci_set_cto(struct dw_mci *host)
402 {
403         unsigned int cto_clks;
404         unsigned int cto_div;
405         unsigned int cto_ms;
406         unsigned long irqflags;
407
408         cto_clks = mci_readl(host, TMOUT) & 0xff;
409         cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
410         if (cto_div == 0)
411                 cto_div = 1;
412         cto_ms = DIV_ROUND_UP(MSEC_PER_SEC * cto_clks * cto_div, host->bus_hz);
413
414         /* add a bit spare time */
415         cto_ms += 10;
416
417         /*
418          * The durations we're working with are fairly short so we have to be
419          * extra careful about synchronization here.  Specifically in hardware a
420          * command timeout is _at most_ 5.1 ms, so that means we expect an
421          * interrupt (either command done or timeout) to come rather quickly
422          * after the mci_writel.  ...but just in case we have a long interrupt
423          * latency let's add a bit of paranoia.
424          *
425          * In general we'll assume that at least an interrupt will be asserted
426          * in hardware by the time the cto_timer runs.  ...and if it hasn't
427          * been asserted in hardware by that time then we'll assume it'll never
428          * come.
429          */
430         spin_lock_irqsave(&host->irq_lock, irqflags);
431         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
432                 mod_timer(&host->cto_timer,
433                         jiffies + msecs_to_jiffies(cto_ms) + 1);
434         spin_unlock_irqrestore(&host->irq_lock, irqflags);
435 }
436
437 static void dw_mci_start_command(struct dw_mci *host,
438                                  struct mmc_command *cmd, u32 cmd_flags)
439 {
440         host->cmd = cmd;
441         dev_vdbg(host->dev,
442                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
443                  cmd->arg, cmd_flags);
444
445         mci_writel(host, CMDARG, cmd->arg);
446         wmb(); /* drain writebuffer */
447         dw_mci_wait_while_busy(host, cmd_flags);
448
449         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
450
451         /* response expected command only */
452         if (cmd_flags & SDMMC_CMD_RESP_EXP)
453                 dw_mci_set_cto(host);
454 }
455
456 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
457 {
458         struct mmc_command *stop = &host->stop_abort;
459
460         dw_mci_start_command(host, stop, host->stop_cmdr);
461 }
462
463 /* DMA interface functions */
464 static void dw_mci_stop_dma(struct dw_mci *host)
465 {
466         if (host->using_dma) {
467                 host->dma_ops->stop(host);
468                 host->dma_ops->cleanup(host);
469         }
470
471         /* Data transfer was stopped by the interrupt handler */
472         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
473 }
474
475 static void dw_mci_dma_cleanup(struct dw_mci *host)
476 {
477         struct mmc_data *data = host->data;
478
479         if (data && data->host_cookie == COOKIE_MAPPED) {
480                 dma_unmap_sg(host->dev,
481                              data->sg,
482                              data->sg_len,
483                              mmc_get_dma_dir(data));
484                 data->host_cookie = COOKIE_UNMAPPED;
485         }
486 }
487
488 static void dw_mci_idmac_reset(struct dw_mci *host)
489 {
490         u32 bmod = mci_readl(host, BMOD);
491         /* Software reset of DMA */
492         bmod |= SDMMC_IDMAC_SWRESET;
493         mci_writel(host, BMOD, bmod);
494 }
495
496 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
497 {
498         u32 temp;
499
500         /* Disable and reset the IDMAC interface */
501         temp = mci_readl(host, CTRL);
502         temp &= ~SDMMC_CTRL_USE_IDMAC;
503         temp |= SDMMC_CTRL_DMA_RESET;
504         mci_writel(host, CTRL, temp);
505
506         /* Stop the IDMAC running */
507         temp = mci_readl(host, BMOD);
508         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
509         temp |= SDMMC_IDMAC_SWRESET;
510         mci_writel(host, BMOD, temp);
511 }
512
513 static void dw_mci_dmac_complete_dma(void *arg)
514 {
515         struct dw_mci *host = arg;
516         struct mmc_data *data = host->data;
517
518         dev_vdbg(host->dev, "DMA complete\n");
519
520         if ((host->use_dma == TRANS_MODE_EDMAC) &&
521             data && (data->flags & MMC_DATA_READ))
522                 /* Invalidate cache after read */
523                 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
524                                     data->sg,
525                                     data->sg_len,
526                                     DMA_FROM_DEVICE);
527
528         host->dma_ops->cleanup(host);
529
530         /*
531          * If the card was removed, data will be NULL. No point in trying to
532          * send the stop command or waiting for NBUSY in this case.
533          */
534         if (data) {
535                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
536                 tasklet_schedule(&host->tasklet);
537         }
538 }
539
540 static int dw_mci_idmac_init(struct dw_mci *host)
541 {
542         int i;
543
544         if (host->dma_64bit_address == 1) {
545                 struct idmac_desc_64addr *p;
546                 /* Number of descriptors in the ring buffer */
547                 host->ring_size =
548                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
549
550                 /* Forward link the descriptor list */
551                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
552                                                                 i++, p++) {
553                         p->des6 = (host->sg_dma +
554                                         (sizeof(struct idmac_desc_64addr) *
555                                                         (i + 1))) & 0xffffffff;
556
557                         p->des7 = (u64)(host->sg_dma +
558                                         (sizeof(struct idmac_desc_64addr) *
559                                                         (i + 1))) >> 32;
560                         /* Initialize reserved and buffer size fields to "0" */
561                         p->des1 = 0;
562                         p->des2 = 0;
563                         p->des3 = 0;
564                 }
565
566                 /* Set the last descriptor as the end-of-ring descriptor */
567                 p->des6 = host->sg_dma & 0xffffffff;
568                 p->des7 = (u64)host->sg_dma >> 32;
569                 p->des0 = IDMAC_DES0_ER;
570
571         } else {
572                 struct idmac_desc *p;
573                 /* Number of descriptors in the ring buffer */
574                 host->ring_size =
575                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
576
577                 /* Forward link the descriptor list */
578                 for (i = 0, p = host->sg_cpu;
579                      i < host->ring_size - 1;
580                      i++, p++) {
581                         p->des3 = cpu_to_le32(host->sg_dma +
582                                         (sizeof(struct idmac_desc) * (i + 1)));
583                         p->des1 = 0;
584                 }
585
586                 /* Set the last descriptor as the end-of-ring descriptor */
587                 p->des3 = cpu_to_le32(host->sg_dma);
588                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
589         }
590
591         dw_mci_idmac_reset(host);
592
593         if (host->dma_64bit_address == 1) {
594                 /* Mask out interrupts - get Tx & Rx complete only */
595                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
596                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
597                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
598
599                 /* Set the descriptor base address */
600                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
601                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
602
603         } else {
604                 /* Mask out interrupts - get Tx & Rx complete only */
605                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
606                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
607                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
608
609                 /* Set the descriptor base address */
610                 mci_writel(host, DBADDR, host->sg_dma);
611         }
612
613         return 0;
614 }
615
616 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
617                                          struct mmc_data *data,
618                                          unsigned int sg_len)
619 {
620         unsigned int desc_len;
621         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
622         u32 val;
623         int i;
624
625         desc_first = desc_last = desc = host->sg_cpu;
626
627         for (i = 0; i < sg_len; i++) {
628                 unsigned int length = sg_dma_len(&data->sg[i]);
629
630                 u64 mem_addr = sg_dma_address(&data->sg[i]);
631
632                 for ( ; length ; desc++) {
633                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
634                                    length : DW_MCI_DESC_DATA_LENGTH;
635
636                         length -= desc_len;
637
638                         /*
639                          * Wait for the former clear OWN bit operation
640                          * of IDMAC to make sure that this descriptor
641                          * isn't still owned by IDMAC as IDMAC's write
642                          * ops and CPU's read ops are asynchronous.
643                          */
644                         if (readl_poll_timeout_atomic(&desc->des0, val,
645                                                 !(val & IDMAC_DES0_OWN),
646                                                 10, 100 * USEC_PER_MSEC))
647                                 goto err_own_bit;
648
649                         /*
650                          * Set the OWN bit and disable interrupts
651                          * for this descriptor
652                          */
653                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
654                                                 IDMAC_DES0_CH;
655
656                         /* Buffer length */
657                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
658
659                         /* Physical address to DMA to/from */
660                         desc->des4 = mem_addr & 0xffffffff;
661                         desc->des5 = mem_addr >> 32;
662
663                         /* Update physical address for the next desc */
664                         mem_addr += desc_len;
665
666                         /* Save pointer to the last descriptor */
667                         desc_last = desc;
668                 }
669         }
670
671         /* Set first descriptor */
672         desc_first->des0 |= IDMAC_DES0_FD;
673
674         /* Set last descriptor */
675         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
676         desc_last->des0 |= IDMAC_DES0_LD;
677
678         return 0;
679 err_own_bit:
680         /* restore the descriptor chain as it's polluted */
681         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
682         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
683         dw_mci_idmac_init(host);
684         return -EINVAL;
685 }
686
687
688 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
689                                          struct mmc_data *data,
690                                          unsigned int sg_len)
691 {
692         unsigned int desc_len;
693         struct idmac_desc *desc_first, *desc_last, *desc;
694         u32 val;
695         int i;
696
697         desc_first = desc_last = desc = host->sg_cpu;
698
699         for (i = 0; i < sg_len; i++) {
700                 unsigned int length = sg_dma_len(&data->sg[i]);
701
702                 u32 mem_addr = sg_dma_address(&data->sg[i]);
703
704                 for ( ; length ; desc++) {
705                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
706                                    length : DW_MCI_DESC_DATA_LENGTH;
707
708                         length -= desc_len;
709
710                         /*
711                          * Wait for the former clear OWN bit operation
712                          * of IDMAC to make sure that this descriptor
713                          * isn't still owned by IDMAC as IDMAC's write
714                          * ops and CPU's read ops are asynchronous.
715                          */
716                         if (readl_poll_timeout_atomic(&desc->des0, val,
717                                                       IDMAC_OWN_CLR64(val),
718                                                       10,
719                                                       100 * USEC_PER_MSEC))
720                                 goto err_own_bit;
721
722                         /*
723                          * Set the OWN bit and disable interrupts
724                          * for this descriptor
725                          */
726                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
727                                                  IDMAC_DES0_DIC |
728                                                  IDMAC_DES0_CH);
729
730                         /* Buffer length */
731                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
732
733                         /* Physical address to DMA to/from */
734                         desc->des2 = cpu_to_le32(mem_addr);
735
736                         /* Update physical address for the next desc */
737                         mem_addr += desc_len;
738
739                         /* Save pointer to the last descriptor */
740                         desc_last = desc;
741                 }
742         }
743
744         /* Set first descriptor */
745         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
746
747         /* Set last descriptor */
748         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
749                                        IDMAC_DES0_DIC));
750         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
751
752         return 0;
753 err_own_bit:
754         /* restore the descriptor chain as it's polluted */
755         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
756         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
757         dw_mci_idmac_init(host);
758         return -EINVAL;
759 }
760
761 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
762 {
763         u32 temp;
764         int ret;
765
766         if (host->dma_64bit_address == 1)
767                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
768         else
769                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
770
771         if (ret)
772                 goto out;
773
774         /* drain writebuffer */
775         wmb();
776
777         /* Make sure to reset DMA in case we did PIO before this */
778         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
779         dw_mci_idmac_reset(host);
780
781         /* Select IDMAC interface */
782         temp = mci_readl(host, CTRL);
783         temp |= SDMMC_CTRL_USE_IDMAC;
784         mci_writel(host, CTRL, temp);
785
786         /* drain writebuffer */
787         wmb();
788
789         /* Enable the IDMAC */
790         temp = mci_readl(host, BMOD);
791         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
792         mci_writel(host, BMOD, temp);
793
794         /* Start it running */
795         mci_writel(host, PLDMND, 1);
796
797 out:
798         return ret;
799 }
800
801 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
802         .init = dw_mci_idmac_init,
803         .start = dw_mci_idmac_start_dma,
804         .stop = dw_mci_idmac_stop_dma,
805         .complete = dw_mci_dmac_complete_dma,
806         .cleanup = dw_mci_dma_cleanup,
807 };
808
809 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
810 {
811         dmaengine_terminate_async(host->dms->ch);
812 }
813
814 static int dw_mci_edmac_start_dma(struct dw_mci *host,
815                                             unsigned int sg_len)
816 {
817         struct dma_slave_config cfg;
818         struct dma_async_tx_descriptor *desc = NULL;
819         struct scatterlist *sgl = host->data->sg;
820         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
821         u32 sg_elems = host->data->sg_len;
822         u32 fifoth_val;
823         u32 fifo_offset = host->fifo_reg - host->regs;
824         int ret = 0;
825
826         /* Set external dma config: burst size, burst width */
827         cfg.dst_addr = host->phy_regs + fifo_offset;
828         cfg.src_addr = cfg.dst_addr;
829         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
830         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
831
832         /* Match burst msize with external dma config */
833         fifoth_val = mci_readl(host, FIFOTH);
834         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
835         cfg.src_maxburst = cfg.dst_maxburst;
836
837         if (host->data->flags & MMC_DATA_WRITE)
838                 cfg.direction = DMA_MEM_TO_DEV;
839         else
840                 cfg.direction = DMA_DEV_TO_MEM;
841
842         ret = dmaengine_slave_config(host->dms->ch, &cfg);
843         if (ret) {
844                 dev_err(host->dev, "Failed to config edmac.\n");
845                 return -EBUSY;
846         }
847
848         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
849                                        sg_len, cfg.direction,
850                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
851         if (!desc) {
852                 dev_err(host->dev, "Can't prepare slave sg.\n");
853                 return -EBUSY;
854         }
855
856         /* Set dw_mci_dmac_complete_dma as callback */
857         desc->callback = dw_mci_dmac_complete_dma;
858         desc->callback_param = (void *)host;
859         dmaengine_submit(desc);
860
861         /* Flush cache before write */
862         if (host->data->flags & MMC_DATA_WRITE)
863                 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
864                                        sg_elems, DMA_TO_DEVICE);
865
866         dma_async_issue_pending(host->dms->ch);
867
868         return 0;
869 }
870
871 static int dw_mci_edmac_init(struct dw_mci *host)
872 {
873         /* Request external dma channel */
874         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
875         if (!host->dms)
876                 return -ENOMEM;
877
878         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
879         if (!host->dms->ch) {
880                 dev_err(host->dev, "Failed to get external DMA channel.\n");
881                 kfree(host->dms);
882                 host->dms = NULL;
883                 return -ENXIO;
884         }
885
886         return 0;
887 }
888
889 static void dw_mci_edmac_exit(struct dw_mci *host)
890 {
891         if (host->dms) {
892                 if (host->dms->ch) {
893                         dma_release_channel(host->dms->ch);
894                         host->dms->ch = NULL;
895                 }
896                 kfree(host->dms);
897                 host->dms = NULL;
898         }
899 }
900
901 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
902         .init = dw_mci_edmac_init,
903         .exit = dw_mci_edmac_exit,
904         .start = dw_mci_edmac_start_dma,
905         .stop = dw_mci_edmac_stop_dma,
906         .complete = dw_mci_dmac_complete_dma,
907         .cleanup = dw_mci_dma_cleanup,
908 };
909
910 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
911                                    struct mmc_data *data,
912                                    int cookie)
913 {
914         struct scatterlist *sg;
915         unsigned int i, sg_len;
916
917         if (data->host_cookie == COOKIE_PRE_MAPPED)
918                 return data->sg_len;
919
920         /*
921          * We don't do DMA on "complex" transfers, i.e. with
922          * non-word-aligned buffers or lengths. Also, we don't bother
923          * with all the DMA setup overhead for short transfers.
924          */
925         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
926                 return -EINVAL;
927
928         if (data->blksz & 3)
929                 return -EINVAL;
930
931         for_each_sg(data->sg, sg, data->sg_len, i) {
932                 if (sg->offset & 3 || sg->length & 3)
933                         return -EINVAL;
934         }
935
936         sg_len = dma_map_sg(host->dev,
937                             data->sg,
938                             data->sg_len,
939                             mmc_get_dma_dir(data));
940         if (sg_len == 0)
941                 return -EINVAL;
942
943         data->host_cookie = cookie;
944
945         return sg_len;
946 }
947
948 static void dw_mci_pre_req(struct mmc_host *mmc,
949                            struct mmc_request *mrq)
950 {
951         struct dw_mci_slot *slot = mmc_priv(mmc);
952         struct mmc_data *data = mrq->data;
953
954         if (!slot->host->use_dma || !data)
955                 return;
956
957         /* This data might be unmapped at this time */
958         data->host_cookie = COOKIE_UNMAPPED;
959
960         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
961                                 COOKIE_PRE_MAPPED) < 0)
962                 data->host_cookie = COOKIE_UNMAPPED;
963 }
964
965 static void dw_mci_post_req(struct mmc_host *mmc,
966                             struct mmc_request *mrq,
967                             int err)
968 {
969         struct dw_mci_slot *slot = mmc_priv(mmc);
970         struct mmc_data *data = mrq->data;
971
972         if (!slot->host->use_dma || !data)
973                 return;
974
975         if (data->host_cookie != COOKIE_UNMAPPED)
976                 dma_unmap_sg(slot->host->dev,
977                              data->sg,
978                              data->sg_len,
979                              mmc_get_dma_dir(data));
980         data->host_cookie = COOKIE_UNMAPPED;
981 }
982
983 static int dw_mci_get_cd(struct mmc_host *mmc)
984 {
985         int present;
986         struct dw_mci_slot *slot = mmc_priv(mmc);
987         struct dw_mci *host = slot->host;
988         int gpio_cd = mmc_gpio_get_cd(mmc);
989
990         /* Use platform get_cd function, else try onboard card detect */
991         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
992                                 || !mmc_card_is_removable(mmc))) {
993                 present = 1;
994
995                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
996                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
997                                 dev_info(&mmc->class_dev,
998                                         "card is polling.\n");
999                         } else {
1000                                 dev_info(&mmc->class_dev,
1001                                         "card is non-removable.\n");
1002                         }
1003                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1004                 }
1005
1006                 return present;
1007         } else if (gpio_cd >= 0)
1008                 present = gpio_cd;
1009         else
1010                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1011                         == 0 ? 1 : 0;
1012
1013         spin_lock_bh(&host->lock);
1014         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1015                 dev_dbg(&mmc->class_dev, "card is present\n");
1016         else if (!present &&
1017                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1018                 dev_dbg(&mmc->class_dev, "card is not present\n");
1019         spin_unlock_bh(&host->lock);
1020
1021         return present;
1022 }
1023
1024 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1025 {
1026         unsigned int blksz = data->blksz;
1027         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1028         u32 fifo_width = 1 << host->data_shift;
1029         u32 blksz_depth = blksz / fifo_width, fifoth_val;
1030         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1031         int idx = ARRAY_SIZE(mszs) - 1;
1032
1033         /* pio should ship this scenario */
1034         if (!host->use_dma)
1035                 return;
1036
1037         tx_wmark = (host->fifo_depth) / 2;
1038         tx_wmark_invers = host->fifo_depth - tx_wmark;
1039
1040         /*
1041          * MSIZE is '1',
1042          * if blksz is not a multiple of the FIFO width
1043          */
1044         if (blksz % fifo_width)
1045                 goto done;
1046
1047         do {
1048                 if (!((blksz_depth % mszs[idx]) ||
1049                      (tx_wmark_invers % mszs[idx]))) {
1050                         msize = idx;
1051                         rx_wmark = mszs[idx] - 1;
1052                         break;
1053                 }
1054         } while (--idx > 0);
1055         /*
1056          * If idx is '0', it won't be tried
1057          * Thus, initial values are uesed
1058          */
1059 done:
1060         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1061         mci_writel(host, FIFOTH, fifoth_val);
1062 }
1063
1064 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1065 {
1066         unsigned int blksz = data->blksz;
1067         u32 blksz_depth, fifo_depth;
1068         u16 thld_size;
1069         u8 enable;
1070
1071         /*
1072          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1073          * in the FIFO region, so we really shouldn't access it).
1074          */
1075         if (host->verid < DW_MMC_240A ||
1076                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1077                 return;
1078
1079         /*
1080          * Card write Threshold is introduced since 2.80a
1081          * It's used when HS400 mode is enabled.
1082          */
1083         if (data->flags & MMC_DATA_WRITE &&
1084                 !(host->timing != MMC_TIMING_MMC_HS400))
1085                 return;
1086
1087         if (data->flags & MMC_DATA_WRITE)
1088                 enable = SDMMC_CARD_WR_THR_EN;
1089         else
1090                 enable = SDMMC_CARD_RD_THR_EN;
1091
1092         if (host->timing != MMC_TIMING_MMC_HS200 &&
1093             host->timing != MMC_TIMING_UHS_SDR104)
1094                 goto disable;
1095
1096         blksz_depth = blksz / (1 << host->data_shift);
1097         fifo_depth = host->fifo_depth;
1098
1099         if (blksz_depth > fifo_depth)
1100                 goto disable;
1101
1102         /*
1103          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1104          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1105          * Currently just choose blksz.
1106          */
1107         thld_size = blksz;
1108         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1109         return;
1110
1111 disable:
1112         mci_writel(host, CDTHRCTL, 0);
1113 }
1114
1115 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1116 {
1117         unsigned long irqflags;
1118         int sg_len;
1119         u32 temp;
1120
1121         host->using_dma = 0;
1122
1123         /* If we don't have a channel, we can't do DMA */
1124         if (!host->use_dma)
1125                 return -ENODEV;
1126
1127         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1128         if (sg_len < 0) {
1129                 host->dma_ops->stop(host);
1130                 return sg_len;
1131         }
1132
1133         host->using_dma = 1;
1134
1135         if (host->use_dma == TRANS_MODE_IDMAC)
1136                 dev_vdbg(host->dev,
1137                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1138                          (unsigned long)host->sg_cpu,
1139                          (unsigned long)host->sg_dma,
1140                          sg_len);
1141
1142         /*
1143          * Decide the MSIZE and RX/TX Watermark.
1144          * If current block size is same with previous size,
1145          * no need to update fifoth.
1146          */
1147         if (host->prev_blksz != data->blksz)
1148                 dw_mci_adjust_fifoth(host, data);
1149
1150         /* Enable the DMA interface */
1151         temp = mci_readl(host, CTRL);
1152         temp |= SDMMC_CTRL_DMA_ENABLE;
1153         mci_writel(host, CTRL, temp);
1154
1155         /* Disable RX/TX IRQs, let DMA handle it */
1156         spin_lock_irqsave(&host->irq_lock, irqflags);
1157         temp = mci_readl(host, INTMASK);
1158         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1159         mci_writel(host, INTMASK, temp);
1160         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1161
1162         if (host->dma_ops->start(host, sg_len)) {
1163                 host->dma_ops->stop(host);
1164                 /* We can't do DMA, try PIO for this one */
1165                 dev_dbg(host->dev,
1166                         "%s: fall back to PIO mode for current transfer\n",
1167                         __func__);
1168                 return -ENODEV;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1175 {
1176         unsigned long irqflags;
1177         int flags = SG_MITER_ATOMIC;
1178         u32 temp;
1179
1180         data->error = -EINPROGRESS;
1181
1182         WARN_ON(host->data);
1183         host->sg = NULL;
1184         host->data = data;
1185
1186         if (data->flags & MMC_DATA_READ)
1187                 host->dir_status = DW_MCI_RECV_STATUS;
1188         else
1189                 host->dir_status = DW_MCI_SEND_STATUS;
1190
1191         dw_mci_ctrl_thld(host, data);
1192
1193         if (dw_mci_submit_data_dma(host, data)) {
1194                 if (host->data->flags & MMC_DATA_READ)
1195                         flags |= SG_MITER_TO_SG;
1196                 else
1197                         flags |= SG_MITER_FROM_SG;
1198
1199                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200                 host->sg = data->sg;
1201                 host->part_buf_start = 0;
1202                 host->part_buf_count = 0;
1203
1204                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1205
1206                 spin_lock_irqsave(&host->irq_lock, irqflags);
1207                 temp = mci_readl(host, INTMASK);
1208                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1209                 mci_writel(host, INTMASK, temp);
1210                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1211
1212                 temp = mci_readl(host, CTRL);
1213                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1214                 mci_writel(host, CTRL, temp);
1215
1216                 /*
1217                  * Use the initial fifoth_val for PIO mode. If wm_algined
1218                  * is set, we set watermark same as data size.
1219                  * If next issued data may be transfered by DMA mode,
1220                  * prev_blksz should be invalidated.
1221                  */
1222                 if (host->wm_aligned)
1223                         dw_mci_adjust_fifoth(host, data);
1224                 else
1225                         mci_writel(host, FIFOTH, host->fifoth_val);
1226                 host->prev_blksz = 0;
1227         } else {
1228                 /*
1229                  * Keep the current block size.
1230                  * It will be used to decide whether to update
1231                  * fifoth register next time.
1232                  */
1233                 host->prev_blksz = data->blksz;
1234         }
1235 }
1236
1237 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1238 {
1239         struct dw_mci *host = slot->host;
1240         unsigned int clock = slot->clock;
1241         u32 div;
1242         u32 clk_en_a;
1243         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1244
1245         /* We must continue to set bit 28 in CMD until the change is complete */
1246         if (host->state == STATE_WAITING_CMD11_DONE)
1247                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1248
1249         if (!clock) {
1250                 mci_writel(host, CLKENA, 0);
1251                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1252         } else if (clock != host->current_speed || force_clkinit) {
1253                 div = host->bus_hz / clock;
1254                 if (host->bus_hz % clock && host->bus_hz > clock)
1255                         /*
1256                          * move the + 1 after the divide to prevent
1257                          * over-clocking the card.
1258                          */
1259                         div += 1;
1260
1261                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1262
1263                 if ((clock != slot->__clk_old &&
1264                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1265                         force_clkinit) {
1266                         /* Silent the verbose log if calling from PM context */
1267                         if (!force_clkinit)
1268                                 dev_info(&slot->mmc->class_dev,
1269                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1270                                          slot->id, host->bus_hz, clock,
1271                                          div ? ((host->bus_hz / div) >> 1) :
1272                                          host->bus_hz, div);
1273
1274                         /*
1275                          * If card is polling, display the message only
1276                          * one time at boot time.
1277                          */
1278                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1279                                         slot->mmc->f_min == clock)
1280                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1281                 }
1282
1283                 /* disable clock */
1284                 mci_writel(host, CLKENA, 0);
1285                 mci_writel(host, CLKSRC, 0);
1286
1287                 /* inform CIU */
1288                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1289
1290                 /* set clock to desired speed */
1291                 mci_writel(host, CLKDIV, div);
1292
1293                 /* inform CIU */
1294                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1295
1296                 /* enable clock; only low power if no SDIO */
1297                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1298                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1299                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1300                 mci_writel(host, CLKENA, clk_en_a);
1301
1302                 /* inform CIU */
1303                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1304
1305                 /* keep the last clock value that was requested from core */
1306                 slot->__clk_old = clock;
1307         }
1308
1309         host->current_speed = clock;
1310
1311         /* Set the current slot bus width */
1312         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1313 }
1314
1315 static void __dw_mci_start_request(struct dw_mci *host,
1316                                    struct dw_mci_slot *slot,
1317                                    struct mmc_command *cmd)
1318 {
1319         struct mmc_request *mrq;
1320         struct mmc_data *data;
1321         u32 cmdflags;
1322
1323         mrq = slot->mrq;
1324
1325         host->mrq = mrq;
1326
1327         host->pending_events = 0;
1328         host->completed_events = 0;
1329         host->cmd_status = 0;
1330         host->data_status = 0;
1331         host->dir_status = 0;
1332
1333         data = cmd->data;
1334         if (data) {
1335                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1336                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1337                 mci_writel(host, BLKSIZ, data->blksz);
1338         }
1339
1340         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1341
1342         /* this is the first command, send the initialization clock */
1343         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1344                 cmdflags |= SDMMC_CMD_INIT;
1345
1346         if (data) {
1347                 dw_mci_submit_data(host, data);
1348                 wmb(); /* drain writebuffer */
1349         }
1350
1351         dw_mci_start_command(host, cmd, cmdflags);
1352
1353         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1354                 unsigned long irqflags;
1355
1356                 /*
1357                  * Databook says to fail after 2ms w/ no response, but evidence
1358                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1359                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1360                  * is just about to roll over.
1361                  *
1362                  * We do this whole thing under spinlock and only if the
1363                  * command hasn't already completed (indicating the the irq
1364                  * already ran so we don't want the timeout).
1365                  */
1366                 spin_lock_irqsave(&host->irq_lock, irqflags);
1367                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1368                         mod_timer(&host->cmd11_timer,
1369                                 jiffies + msecs_to_jiffies(500) + 1);
1370                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1371         }
1372
1373         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1374 }
1375
1376 static void dw_mci_start_request(struct dw_mci *host,
1377                                  struct dw_mci_slot *slot)
1378 {
1379         struct mmc_request *mrq = slot->mrq;
1380         struct mmc_command *cmd;
1381
1382         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1383         __dw_mci_start_request(host, slot, cmd);
1384 }
1385
1386 /* must be called with host->lock held */
1387 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1388                                  struct mmc_request *mrq)
1389 {
1390         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1391                  host->state);
1392
1393         slot->mrq = mrq;
1394
1395         if (host->state == STATE_WAITING_CMD11_DONE) {
1396                 dev_warn(&slot->mmc->class_dev,
1397                          "Voltage change didn't complete\n");
1398                 /*
1399                  * this case isn't expected to happen, so we can
1400                  * either crash here or just try to continue on
1401                  * in the closest possible state
1402                  */
1403                 host->state = STATE_IDLE;
1404         }
1405
1406         if (host->state == STATE_IDLE) {
1407                 host->state = STATE_SENDING_CMD;
1408                 dw_mci_start_request(host, slot);
1409         } else {
1410                 list_add_tail(&slot->queue_node, &host->queue);
1411         }
1412 }
1413
1414 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1415 {
1416         struct dw_mci_slot *slot = mmc_priv(mmc);
1417         struct dw_mci *host = slot->host;
1418
1419         WARN_ON(slot->mrq);
1420
1421         /*
1422          * The check for card presence and queueing of the request must be
1423          * atomic, otherwise the card could be removed in between and the
1424          * request wouldn't fail until another card was inserted.
1425          */
1426
1427         if (!dw_mci_get_cd(mmc)) {
1428                 mrq->cmd->error = -ENOMEDIUM;
1429                 mmc_request_done(mmc, mrq);
1430                 return;
1431         }
1432
1433         spin_lock_bh(&host->lock);
1434
1435         dw_mci_queue_request(host, slot, mrq);
1436
1437         spin_unlock_bh(&host->lock);
1438 }
1439
1440 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1441 {
1442         struct dw_mci_slot *slot = mmc_priv(mmc);
1443         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1444         u32 regs;
1445         int ret;
1446
1447         switch (ios->bus_width) {
1448         case MMC_BUS_WIDTH_4:
1449                 slot->ctype = SDMMC_CTYPE_4BIT;
1450                 break;
1451         case MMC_BUS_WIDTH_8:
1452                 slot->ctype = SDMMC_CTYPE_8BIT;
1453                 break;
1454         default:
1455                 /* set default 1 bit mode */
1456                 slot->ctype = SDMMC_CTYPE_1BIT;
1457         }
1458
1459         regs = mci_readl(slot->host, UHS_REG);
1460
1461         /* DDR mode set */
1462         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1463             ios->timing == MMC_TIMING_UHS_DDR50 ||
1464             ios->timing == MMC_TIMING_MMC_HS400)
1465                 regs |= ((0x1 << slot->id) << 16);
1466         else
1467                 regs &= ~((0x1 << slot->id) << 16);
1468
1469         mci_writel(slot->host, UHS_REG, regs);
1470         slot->host->timing = ios->timing;
1471
1472         /*
1473          * Use mirror of ios->clock to prevent race with mmc
1474          * core ios update when finding the minimum.
1475          */
1476         slot->clock = ios->clock;
1477
1478         if (drv_data && drv_data->set_ios)
1479                 drv_data->set_ios(slot->host, ios);
1480
1481         switch (ios->power_mode) {
1482         case MMC_POWER_UP:
1483                 if (!IS_ERR(mmc->supply.vmmc)) {
1484                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1485                                         ios->vdd);
1486                         if (ret) {
1487                                 dev_err(slot->host->dev,
1488                                         "failed to enable vmmc regulator\n");
1489                                 /*return, if failed turn on vmmc*/
1490                                 return;
1491                         }
1492                 }
1493                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1494                 regs = mci_readl(slot->host, PWREN);
1495                 regs |= (1 << slot->id);
1496                 mci_writel(slot->host, PWREN, regs);
1497                 break;
1498         case MMC_POWER_ON:
1499                 if (!slot->host->vqmmc_enabled) {
1500                         if (!IS_ERR(mmc->supply.vqmmc)) {
1501                                 ret = regulator_enable(mmc->supply.vqmmc);
1502                                 if (ret < 0)
1503                                         dev_err(slot->host->dev,
1504                                                 "failed to enable vqmmc\n");
1505                                 else
1506                                         slot->host->vqmmc_enabled = true;
1507
1508                         } else {
1509                                 /* Keep track so we don't reset again */
1510                                 slot->host->vqmmc_enabled = true;
1511                         }
1512
1513                         /* Reset our state machine after powering on */
1514                         dw_mci_ctrl_reset(slot->host,
1515                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1516                 }
1517
1518                 /* Adjust clock / bus width after power is up */
1519                 dw_mci_setup_bus(slot, false);
1520
1521                 break;
1522         case MMC_POWER_OFF:
1523                 /* Turn clock off before power goes down */
1524                 dw_mci_setup_bus(slot, false);
1525
1526                 if (!IS_ERR(mmc->supply.vmmc))
1527                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1528
1529                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1530                         regulator_disable(mmc->supply.vqmmc);
1531                 slot->host->vqmmc_enabled = false;
1532
1533                 regs = mci_readl(slot->host, PWREN);
1534                 regs &= ~(1 << slot->id);
1535                 mci_writel(slot->host, PWREN, regs);
1536                 break;
1537         default:
1538                 break;
1539         }
1540
1541         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1542                 slot->host->state = STATE_IDLE;
1543 }
1544
1545 static int dw_mci_card_busy(struct mmc_host *mmc)
1546 {
1547         struct dw_mci_slot *slot = mmc_priv(mmc);
1548         u32 status;
1549
1550         /*
1551          * Check the busy bit which is low when DAT[3:0]
1552          * (the data lines) are 0000
1553          */
1554         status = mci_readl(slot->host, STATUS);
1555
1556         return !!(status & SDMMC_STATUS_BUSY);
1557 }
1558
1559 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1560 {
1561         struct dw_mci_slot *slot = mmc_priv(mmc);
1562         struct dw_mci *host = slot->host;
1563         const struct dw_mci_drv_data *drv_data = host->drv_data;
1564         u32 uhs;
1565         u32 v18 = SDMMC_UHS_18V << slot->id;
1566         int ret;
1567
1568         if (drv_data && drv_data->switch_voltage)
1569                 return drv_data->switch_voltage(mmc, ios);
1570
1571         /*
1572          * Program the voltage.  Note that some instances of dw_mmc may use
1573          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1574          * does no harm but you need to set the regulator directly.  Try both.
1575          */
1576         uhs = mci_readl(host, UHS_REG);
1577         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1578                 uhs &= ~v18;
1579         else
1580                 uhs |= v18;
1581
1582         if (!IS_ERR(mmc->supply.vqmmc)) {
1583                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1584
1585                 if (ret) {
1586                         dev_dbg(&mmc->class_dev,
1587                                          "Regulator set error %d - %s V\n",
1588                                          ret, uhs & v18 ? "1.8" : "3.3");
1589                         return ret;
1590                 }
1591         }
1592         mci_writel(host, UHS_REG, uhs);
1593
1594         return 0;
1595 }
1596
1597 static int dw_mci_get_ro(struct mmc_host *mmc)
1598 {
1599         int read_only;
1600         struct dw_mci_slot *slot = mmc_priv(mmc);
1601         int gpio_ro = mmc_gpio_get_ro(mmc);
1602
1603         /* Use platform get_ro function, else try on board write protect */
1604         if (gpio_ro >= 0)
1605                 read_only = gpio_ro;
1606         else
1607                 read_only =
1608                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1609
1610         dev_dbg(&mmc->class_dev, "card is %s\n",
1611                 read_only ? "read-only" : "read-write");
1612
1613         return read_only;
1614 }
1615
1616 static void dw_mci_hw_reset(struct mmc_host *mmc)
1617 {
1618         struct dw_mci_slot *slot = mmc_priv(mmc);
1619         struct dw_mci *host = slot->host;
1620         int reset;
1621
1622         if (host->use_dma == TRANS_MODE_IDMAC)
1623                 dw_mci_idmac_reset(host);
1624
1625         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1626                                      SDMMC_CTRL_FIFO_RESET))
1627                 return;
1628
1629         /*
1630          * According to eMMC spec, card reset procedure:
1631          * tRstW >= 1us:   RST_n pulse width
1632          * tRSCA >= 200us: RST_n to Command time
1633          * tRSTH >= 1us:   RST_n high period
1634          */
1635         reset = mci_readl(host, RST_N);
1636         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1637         mci_writel(host, RST_N, reset);
1638         usleep_range(1, 2);
1639         reset |= SDMMC_RST_HWACTIVE << slot->id;
1640         mci_writel(host, RST_N, reset);
1641         usleep_range(200, 300);
1642 }
1643
1644 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1645 {
1646         struct dw_mci_slot *slot = mmc_priv(mmc);
1647         struct dw_mci *host = slot->host;
1648
1649         /*
1650          * Low power mode will stop the card clock when idle.  According to the
1651          * description of the CLKENA register we should disable low power mode
1652          * for SDIO cards if we need SDIO interrupts to work.
1653          */
1654         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1655                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1656                 u32 clk_en_a_old;
1657                 u32 clk_en_a;
1658
1659                 clk_en_a_old = mci_readl(host, CLKENA);
1660
1661                 if (card->type == MMC_TYPE_SDIO ||
1662                     card->type == MMC_TYPE_SD_COMBO) {
1663                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1664                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1665                 } else {
1666                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1667                         clk_en_a = clk_en_a_old | clken_low_pwr;
1668                 }
1669
1670                 if (clk_en_a != clk_en_a_old) {
1671                         mci_writel(host, CLKENA, clk_en_a);
1672                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1673                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1674                 }
1675         }
1676 }
1677
1678 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1679 {
1680         struct dw_mci *host = slot->host;
1681         unsigned long irqflags;
1682         u32 int_mask;
1683
1684         spin_lock_irqsave(&host->irq_lock, irqflags);
1685
1686         /* Enable/disable Slot Specific SDIO interrupt */
1687         int_mask = mci_readl(host, INTMASK);
1688         if (enb)
1689                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1690         else
1691                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1692         mci_writel(host, INTMASK, int_mask);
1693
1694         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1695 }
1696
1697 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1698 {
1699         struct dw_mci_slot *slot = mmc_priv(mmc);
1700         struct dw_mci *host = slot->host;
1701
1702         __dw_mci_enable_sdio_irq(slot, enb);
1703
1704         /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1705         if (enb)
1706                 pm_runtime_get_noresume(host->dev);
1707         else
1708                 pm_runtime_put_noidle(host->dev);
1709 }
1710
1711 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1712 {
1713         struct dw_mci_slot *slot = mmc_priv(mmc);
1714
1715         __dw_mci_enable_sdio_irq(slot, 1);
1716 }
1717
1718 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1719 {
1720         struct dw_mci_slot *slot = mmc_priv(mmc);
1721         struct dw_mci *host = slot->host;
1722         const struct dw_mci_drv_data *drv_data = host->drv_data;
1723         int err = -EINVAL;
1724
1725         if (drv_data && drv_data->execute_tuning)
1726                 err = drv_data->execute_tuning(slot, opcode);
1727         return err;
1728 }
1729
1730 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1731                                        struct mmc_ios *ios)
1732 {
1733         struct dw_mci_slot *slot = mmc_priv(mmc);
1734         struct dw_mci *host = slot->host;
1735         const struct dw_mci_drv_data *drv_data = host->drv_data;
1736
1737         if (drv_data && drv_data->prepare_hs400_tuning)
1738                 return drv_data->prepare_hs400_tuning(host, ios);
1739
1740         return 0;
1741 }
1742
1743 static bool dw_mci_reset(struct dw_mci *host)
1744 {
1745         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1746         bool ret = false;
1747         u32 status = 0;
1748
1749         /*
1750          * Resetting generates a block interrupt, hence setting
1751          * the scatter-gather pointer to NULL.
1752          */
1753         if (host->sg) {
1754                 sg_miter_stop(&host->sg_miter);
1755                 host->sg = NULL;
1756         }
1757
1758         if (host->use_dma)
1759                 flags |= SDMMC_CTRL_DMA_RESET;
1760
1761         if (dw_mci_ctrl_reset(host, flags)) {
1762                 /*
1763                  * In all cases we clear the RAWINTS
1764                  * register to clear any interrupts.
1765                  */
1766                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1767
1768                 if (!host->use_dma) {
1769                         ret = true;
1770                         goto ciu_out;
1771                 }
1772
1773                 /* Wait for dma_req to be cleared */
1774                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1775                                               status,
1776                                               !(status & SDMMC_STATUS_DMA_REQ),
1777                                               1, 500 * USEC_PER_MSEC)) {
1778                         dev_err(host->dev,
1779                                 "%s: Timeout waiting for dma_req to be cleared\n",
1780                                 __func__);
1781                         goto ciu_out;
1782                 }
1783
1784                 /* when using DMA next we reset the fifo again */
1785                 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1786                         goto ciu_out;
1787         } else {
1788                 /* if the controller reset bit did clear, then set clock regs */
1789                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1790                         dev_err(host->dev,
1791                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1792                                 __func__);
1793                         goto ciu_out;
1794                 }
1795         }
1796
1797         if (host->use_dma == TRANS_MODE_IDMAC)
1798                 /* It is also recommended that we reset and reprogram idmac */
1799                 dw_mci_idmac_reset(host);
1800
1801         ret = true;
1802
1803 ciu_out:
1804         /* After a CTRL reset we need to have CIU set clock registers  */
1805         mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1806
1807         return ret;
1808 }
1809
1810 static const struct mmc_host_ops dw_mci_ops = {
1811         .request                = dw_mci_request,
1812         .pre_req                = dw_mci_pre_req,
1813         .post_req               = dw_mci_post_req,
1814         .set_ios                = dw_mci_set_ios,
1815         .get_ro                 = dw_mci_get_ro,
1816         .get_cd                 = dw_mci_get_cd,
1817         .hw_reset               = dw_mci_hw_reset,
1818         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1819         .ack_sdio_irq           = dw_mci_ack_sdio_irq,
1820         .execute_tuning         = dw_mci_execute_tuning,
1821         .card_busy              = dw_mci_card_busy,
1822         .start_signal_voltage_switch = dw_mci_switch_voltage,
1823         .init_card              = dw_mci_init_card,
1824         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1825 };
1826
1827 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1828         __releases(&host->lock)
1829         __acquires(&host->lock)
1830 {
1831         struct dw_mci_slot *slot;
1832         struct mmc_host *prev_mmc = host->slot->mmc;
1833
1834         WARN_ON(host->cmd || host->data);
1835
1836         host->slot->mrq = NULL;
1837         host->mrq = NULL;
1838         if (!list_empty(&host->queue)) {
1839                 slot = list_entry(host->queue.next,
1840                                   struct dw_mci_slot, queue_node);
1841                 list_del(&slot->queue_node);
1842                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1843                          mmc_hostname(slot->mmc));
1844                 host->state = STATE_SENDING_CMD;
1845                 dw_mci_start_request(host, slot);
1846         } else {
1847                 dev_vdbg(host->dev, "list empty\n");
1848
1849                 if (host->state == STATE_SENDING_CMD11)
1850                         host->state = STATE_WAITING_CMD11_DONE;
1851                 else
1852                         host->state = STATE_IDLE;
1853         }
1854
1855         spin_unlock(&host->lock);
1856         mmc_request_done(prev_mmc, mrq);
1857         spin_lock(&host->lock);
1858 }
1859
1860 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1861 {
1862         u32 status = host->cmd_status;
1863
1864         host->cmd_status = 0;
1865
1866         /* Read the response from the card (up to 16 bytes) */
1867         if (cmd->flags & MMC_RSP_PRESENT) {
1868                 if (cmd->flags & MMC_RSP_136) {
1869                         cmd->resp[3] = mci_readl(host, RESP0);
1870                         cmd->resp[2] = mci_readl(host, RESP1);
1871                         cmd->resp[1] = mci_readl(host, RESP2);
1872                         cmd->resp[0] = mci_readl(host, RESP3);
1873                 } else {
1874                         cmd->resp[0] = mci_readl(host, RESP0);
1875                         cmd->resp[1] = 0;
1876                         cmd->resp[2] = 0;
1877                         cmd->resp[3] = 0;
1878                 }
1879         }
1880
1881         if (status & SDMMC_INT_RTO)
1882                 cmd->error = -ETIMEDOUT;
1883         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1884                 cmd->error = -EILSEQ;
1885         else if (status & SDMMC_INT_RESP_ERR)
1886                 cmd->error = -EIO;
1887         else
1888                 cmd->error = 0;
1889
1890         return cmd->error;
1891 }
1892
1893 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1894 {
1895         u32 status = host->data_status;
1896
1897         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1898                 if (status & SDMMC_INT_DRTO) {
1899                         data->error = -ETIMEDOUT;
1900                 } else if (status & SDMMC_INT_DCRC) {
1901                         data->error = -EILSEQ;
1902                 } else if (status & SDMMC_INT_EBE) {
1903                         if (host->dir_status ==
1904                                 DW_MCI_SEND_STATUS) {
1905                                 /*
1906                                  * No data CRC status was returned.
1907                                  * The number of bytes transferred
1908                                  * will be exaggerated in PIO mode.
1909                                  */
1910                                 data->bytes_xfered = 0;
1911                                 data->error = -ETIMEDOUT;
1912                         } else if (host->dir_status ==
1913                                         DW_MCI_RECV_STATUS) {
1914                                 data->error = -EILSEQ;
1915                         }
1916                 } else {
1917                         /* SDMMC_INT_SBE is included */
1918                         data->error = -EILSEQ;
1919                 }
1920
1921                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1922
1923                 /*
1924                  * After an error, there may be data lingering
1925                  * in the FIFO
1926                  */
1927                 dw_mci_reset(host);
1928         } else {
1929                 data->bytes_xfered = data->blocks * data->blksz;
1930                 data->error = 0;
1931         }
1932
1933         return data->error;
1934 }
1935
1936 static void dw_mci_set_drto(struct dw_mci *host)
1937 {
1938         unsigned int drto_clks;
1939         unsigned int drto_div;
1940         unsigned int drto_ms;
1941
1942         drto_clks = mci_readl(host, TMOUT) >> 8;
1943         drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1944         if (drto_div == 0)
1945                 drto_div = 1;
1946         drto_ms = DIV_ROUND_UP(MSEC_PER_SEC * drto_clks * drto_div,
1947                                host->bus_hz);
1948
1949         /* add a bit spare time */
1950         drto_ms += 10;
1951
1952         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1953 }
1954
1955 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1956 {
1957         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1958                 return false;
1959
1960         /*
1961          * Really be certain that the timer has stopped.  This is a bit of
1962          * paranoia and could only really happen if we had really bad
1963          * interrupt latency and the interrupt routine and timeout were
1964          * running concurrently so that the del_timer() in the interrupt
1965          * handler couldn't run.
1966          */
1967         WARN_ON(del_timer_sync(&host->cto_timer));
1968         clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1969
1970         return true;
1971 }
1972
1973 static void dw_mci_tasklet_func(unsigned long priv)
1974 {
1975         struct dw_mci *host = (struct dw_mci *)priv;
1976         struct mmc_data *data;
1977         struct mmc_command *cmd;
1978         struct mmc_request *mrq;
1979         enum dw_mci_state state;
1980         enum dw_mci_state prev_state;
1981         unsigned int err;
1982
1983         spin_lock(&host->lock);
1984
1985         state = host->state;
1986         data = host->data;
1987         mrq = host->mrq;
1988
1989         do {
1990                 prev_state = state;
1991
1992                 switch (state) {
1993                 case STATE_IDLE:
1994                 case STATE_WAITING_CMD11_DONE:
1995                         break;
1996
1997                 case STATE_SENDING_CMD11:
1998                 case STATE_SENDING_CMD:
1999                         if (!dw_mci_clear_pending_cmd_complete(host))
2000                                 break;
2001
2002                         cmd = host->cmd;
2003                         host->cmd = NULL;
2004                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2005                         err = dw_mci_command_complete(host, cmd);
2006                         if (cmd == mrq->sbc && !err) {
2007                                 prev_state = state = STATE_SENDING_CMD;
2008                                 __dw_mci_start_request(host, host->slot,
2009                                                        mrq->cmd);
2010                                 goto unlock;
2011                         }
2012
2013                         if (cmd->data && err) {
2014                                 /*
2015                                  * During UHS tuning sequence, sending the stop
2016                                  * command after the response CRC error would
2017                                  * throw the system into a confused state
2018                                  * causing all future tuning phases to report
2019                                  * failure.
2020                                  *
2021                                  * In such case controller will move into a data
2022                                  * transfer state after a response error or
2023                                  * response CRC error. Let's let that finish
2024                                  * before trying to send a stop, so we'll go to
2025                                  * STATE_SENDING_DATA.
2026                                  *
2027                                  * Although letting the data transfer take place
2028                                  * will waste a bit of time (we already know
2029                                  * the command was bad), it can't cause any
2030                                  * errors since it's possible it would have
2031                                  * taken place anyway if this tasklet got
2032                                  * delayed. Allowing the transfer to take place
2033                                  * avoids races and keeps things simple.
2034                                  */
2035                                 if ((err != -ETIMEDOUT) &&
2036                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
2037                                         state = STATE_SENDING_DATA;
2038                                         continue;
2039                                 }
2040
2041                                 dw_mci_stop_dma(host);
2042                                 send_stop_abort(host, data);
2043                                 state = STATE_SENDING_STOP;
2044                                 break;
2045                         }
2046
2047                         if (!cmd->data || err) {
2048                                 dw_mci_request_end(host, mrq);
2049                                 goto unlock;
2050                         }
2051
2052                         prev_state = state = STATE_SENDING_DATA;
2053                         /* fall through */
2054
2055                 case STATE_SENDING_DATA:
2056                         /*
2057                          * We could get a data error and never a transfer
2058                          * complete so we'd better check for it here.
2059                          *
2060                          * Note that we don't really care if we also got a
2061                          * transfer complete; stopping the DMA and sending an
2062                          * abort won't hurt.
2063                          */
2064                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2065                                                &host->pending_events)) {
2066                                 dw_mci_stop_dma(host);
2067                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2068                                                            SDMMC_INT_EBE)))
2069                                         send_stop_abort(host, data);
2070                                 state = STATE_DATA_ERROR;
2071                                 break;
2072                         }
2073
2074                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2075                                                 &host->pending_events)) {
2076                                 /*
2077                                  * If all data-related interrupts don't come
2078                                  * within the given time in reading data state.
2079                                  */
2080                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2081                                         dw_mci_set_drto(host);
2082                                 break;
2083                         }
2084
2085                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2086
2087                         /*
2088                          * Handle an EVENT_DATA_ERROR that might have shown up
2089                          * before the transfer completed.  This might not have
2090                          * been caught by the check above because the interrupt
2091                          * could have gone off between the previous check and
2092                          * the check for transfer complete.
2093                          *
2094                          * Technically this ought not be needed assuming we
2095                          * get a DATA_COMPLETE eventually (we'll notice the
2096                          * error and end the request), but it shouldn't hurt.
2097                          *
2098                          * This has the advantage of sending the stop command.
2099                          */
2100                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2101                                                &host->pending_events)) {
2102                                 dw_mci_stop_dma(host);
2103                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2104                                                            SDMMC_INT_EBE)))
2105                                         send_stop_abort(host, data);
2106                                 state = STATE_DATA_ERROR;
2107                                 break;
2108                         }
2109                         prev_state = state = STATE_DATA_BUSY;
2110
2111                         /* fall through */
2112
2113                 case STATE_DATA_BUSY:
2114                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2115                                                 &host->pending_events)) {
2116                                 /*
2117                                  * If data error interrupt comes but data over
2118                                  * interrupt doesn't come within the given time.
2119                                  * in reading data state.
2120                                  */
2121                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2122                                         dw_mci_set_drto(host);
2123                                 break;
2124                         }
2125
2126                         host->data = NULL;
2127                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2128                         err = dw_mci_data_complete(host, data);
2129
2130                         if (!err) {
2131                                 if (!data->stop || mrq->sbc) {
2132                                         if (mrq->sbc && data->stop)
2133                                                 data->stop->error = 0;
2134                                         dw_mci_request_end(host, mrq);
2135                                         goto unlock;
2136                                 }
2137
2138                                 /* stop command for open-ended transfer*/
2139                                 if (data->stop)
2140                                         send_stop_abort(host, data);
2141                         } else {
2142                                 /*
2143                                  * If we don't have a command complete now we'll
2144                                  * never get one since we just reset everything;
2145                                  * better end the request.
2146                                  *
2147                                  * If we do have a command complete we'll fall
2148                                  * through to the SENDING_STOP command and
2149                                  * everything will be peachy keen.
2150                                  */
2151                                 if (!test_bit(EVENT_CMD_COMPLETE,
2152                                               &host->pending_events)) {
2153                                         host->cmd = NULL;
2154                                         dw_mci_request_end(host, mrq);
2155                                         goto unlock;
2156                                 }
2157                         }
2158
2159                         /*
2160                          * If err has non-zero,
2161                          * stop-abort command has been already issued.
2162                          */
2163                         prev_state = state = STATE_SENDING_STOP;
2164
2165                         /* fall through */
2166
2167                 case STATE_SENDING_STOP:
2168                         if (!dw_mci_clear_pending_cmd_complete(host))
2169                                 break;
2170
2171                         /* CMD error in data command */
2172                         if (mrq->cmd->error && mrq->data)
2173                                 dw_mci_reset(host);
2174
2175                         host->cmd = NULL;
2176                         host->data = NULL;
2177
2178                         if (!mrq->sbc && mrq->stop)
2179                                 dw_mci_command_complete(host, mrq->stop);
2180                         else
2181                                 host->cmd_status = 0;
2182
2183                         dw_mci_request_end(host, mrq);
2184                         goto unlock;
2185
2186                 case STATE_DATA_ERROR:
2187                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2188                                                 &host->pending_events))
2189                                 break;
2190
2191                         state = STATE_DATA_BUSY;
2192                         break;
2193                 }
2194         } while (state != prev_state);
2195
2196         host->state = state;
2197 unlock:
2198         spin_unlock(&host->lock);
2199
2200 }
2201
2202 /* push final bytes to part_buf, only use during push */
2203 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2204 {
2205         memcpy((void *)&host->part_buf, buf, cnt);
2206         host->part_buf_count = cnt;
2207 }
2208
2209 /* append bytes to part_buf, only use during push */
2210 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2211 {
2212         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2213         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2214         host->part_buf_count += cnt;
2215         return cnt;
2216 }
2217
2218 /* pull first bytes from part_buf, only use during pull */
2219 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2220 {
2221         cnt = min_t(int, cnt, host->part_buf_count);
2222         if (cnt) {
2223                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2224                        cnt);
2225                 host->part_buf_count -= cnt;
2226                 host->part_buf_start += cnt;
2227         }
2228         return cnt;
2229 }
2230
2231 /* pull final bytes from the part_buf, assuming it's just been filled */
2232 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2233 {
2234         memcpy(buf, &host->part_buf, cnt);
2235         host->part_buf_start = cnt;
2236         host->part_buf_count = (1 << host->data_shift) - cnt;
2237 }
2238
2239 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2240 {
2241         struct mmc_data *data = host->data;
2242         int init_cnt = cnt;
2243
2244         /* try and push anything in the part_buf */
2245         if (unlikely(host->part_buf_count)) {
2246                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2247
2248                 buf += len;
2249                 cnt -= len;
2250                 if (host->part_buf_count == 2) {
2251                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2252                         host->part_buf_count = 0;
2253                 }
2254         }
2255 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2256         if (unlikely((unsigned long)buf & 0x1)) {
2257                 while (cnt >= 2) {
2258                         u16 aligned_buf[64];
2259                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2260                         int items = len >> 1;
2261                         int i;
2262                         /* memcpy from input buffer into aligned buffer */
2263                         memcpy(aligned_buf, buf, len);
2264                         buf += len;
2265                         cnt -= len;
2266                         /* push data from aligned buffer into fifo */
2267                         for (i = 0; i < items; ++i)
2268                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2269                 }
2270         } else
2271 #endif
2272         {
2273                 u16 *pdata = buf;
2274
2275                 for (; cnt >= 2; cnt -= 2)
2276                         mci_fifo_writew(host->fifo_reg, *pdata++);
2277                 buf = pdata;
2278         }
2279         /* put anything remaining in the part_buf */
2280         if (cnt) {
2281                 dw_mci_set_part_bytes(host, buf, cnt);
2282                  /* Push data if we have reached the expected data length */
2283                 if ((data->bytes_xfered + init_cnt) ==
2284                     (data->blksz * data->blocks))
2285                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2286         }
2287 }
2288
2289 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2290 {
2291 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2292         if (unlikely((unsigned long)buf & 0x1)) {
2293                 while (cnt >= 2) {
2294                         /* pull data from fifo into aligned buffer */
2295                         u16 aligned_buf[64];
2296                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2297                         int items = len >> 1;
2298                         int i;
2299
2300                         for (i = 0; i < items; ++i)
2301                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2302                         /* memcpy from aligned buffer into output buffer */
2303                         memcpy(buf, aligned_buf, len);
2304                         buf += len;
2305                         cnt -= len;
2306                 }
2307         } else
2308 #endif
2309         {
2310                 u16 *pdata = buf;
2311
2312                 for (; cnt >= 2; cnt -= 2)
2313                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2314                 buf = pdata;
2315         }
2316         if (cnt) {
2317                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2318                 dw_mci_pull_final_bytes(host, buf, cnt);
2319         }
2320 }
2321
2322 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2323 {
2324         struct mmc_data *data = host->data;
2325         int init_cnt = cnt;
2326
2327         /* try and push anything in the part_buf */
2328         if (unlikely(host->part_buf_count)) {
2329                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2330
2331                 buf += len;
2332                 cnt -= len;
2333                 if (host->part_buf_count == 4) {
2334                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2335                         host->part_buf_count = 0;
2336                 }
2337         }
2338 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2339         if (unlikely((unsigned long)buf & 0x3)) {
2340                 while (cnt >= 4) {
2341                         u32 aligned_buf[32];
2342                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2343                         int items = len >> 2;
2344                         int i;
2345                         /* memcpy from input buffer into aligned buffer */
2346                         memcpy(aligned_buf, buf, len);
2347                         buf += len;
2348                         cnt -= len;
2349                         /* push data from aligned buffer into fifo */
2350                         for (i = 0; i < items; ++i)
2351                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2352                 }
2353         } else
2354 #endif
2355         {
2356                 u32 *pdata = buf;
2357
2358                 for (; cnt >= 4; cnt -= 4)
2359                         mci_fifo_writel(host->fifo_reg, *pdata++);
2360                 buf = pdata;
2361         }
2362         /* put anything remaining in the part_buf */
2363         if (cnt) {
2364                 dw_mci_set_part_bytes(host, buf, cnt);
2365                  /* Push data if we have reached the expected data length */
2366                 if ((data->bytes_xfered + init_cnt) ==
2367                     (data->blksz * data->blocks))
2368                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2369         }
2370 }
2371
2372 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2373 {
2374 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2375         if (unlikely((unsigned long)buf & 0x3)) {
2376                 while (cnt >= 4) {
2377                         /* pull data from fifo into aligned buffer */
2378                         u32 aligned_buf[32];
2379                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2380                         int items = len >> 2;
2381                         int i;
2382
2383                         for (i = 0; i < items; ++i)
2384                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2385                         /* memcpy from aligned buffer into output buffer */
2386                         memcpy(buf, aligned_buf, len);
2387                         buf += len;
2388                         cnt -= len;
2389                 }
2390         } else
2391 #endif
2392         {
2393                 u32 *pdata = buf;
2394
2395                 for (; cnt >= 4; cnt -= 4)
2396                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2397                 buf = pdata;
2398         }
2399         if (cnt) {
2400                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2401                 dw_mci_pull_final_bytes(host, buf, cnt);
2402         }
2403 }
2404
2405 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2406 {
2407         struct mmc_data *data = host->data;
2408         int init_cnt = cnt;
2409
2410         /* try and push anything in the part_buf */
2411         if (unlikely(host->part_buf_count)) {
2412                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2413
2414                 buf += len;
2415                 cnt -= len;
2416
2417                 if (host->part_buf_count == 8) {
2418                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2419                         host->part_buf_count = 0;
2420                 }
2421         }
2422 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2423         if (unlikely((unsigned long)buf & 0x7)) {
2424                 while (cnt >= 8) {
2425                         u64 aligned_buf[16];
2426                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2427                         int items = len >> 3;
2428                         int i;
2429                         /* memcpy from input buffer into aligned buffer */
2430                         memcpy(aligned_buf, buf, len);
2431                         buf += len;
2432                         cnt -= len;
2433                         /* push data from aligned buffer into fifo */
2434                         for (i = 0; i < items; ++i)
2435                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2436                 }
2437         } else
2438 #endif
2439         {
2440                 u64 *pdata = buf;
2441
2442                 for (; cnt >= 8; cnt -= 8)
2443                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2444                 buf = pdata;
2445         }
2446         /* put anything remaining in the part_buf */
2447         if (cnt) {
2448                 dw_mci_set_part_bytes(host, buf, cnt);
2449                 /* Push data if we have reached the expected data length */
2450                 if ((data->bytes_xfered + init_cnt) ==
2451                     (data->blksz * data->blocks))
2452                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2453         }
2454 }
2455
2456 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2457 {
2458 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2459         if (unlikely((unsigned long)buf & 0x7)) {
2460                 while (cnt >= 8) {
2461                         /* pull data from fifo into aligned buffer */
2462                         u64 aligned_buf[16];
2463                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2464                         int items = len >> 3;
2465                         int i;
2466
2467                         for (i = 0; i < items; ++i)
2468                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2469
2470                         /* memcpy from aligned buffer into output buffer */
2471                         memcpy(buf, aligned_buf, len);
2472                         buf += len;
2473                         cnt -= len;
2474                 }
2475         } else
2476 #endif
2477         {
2478                 u64 *pdata = buf;
2479
2480                 for (; cnt >= 8; cnt -= 8)
2481                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2482                 buf = pdata;
2483         }
2484         if (cnt) {
2485                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2486                 dw_mci_pull_final_bytes(host, buf, cnt);
2487         }
2488 }
2489
2490 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2491 {
2492         int len;
2493
2494         /* get remaining partial bytes */
2495         len = dw_mci_pull_part_bytes(host, buf, cnt);
2496         if (unlikely(len == cnt))
2497                 return;
2498         buf += len;
2499         cnt -= len;
2500
2501         /* get the rest of the data */
2502         host->pull_data(host, buf, cnt);
2503 }
2504
2505 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2506 {
2507         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2508         void *buf;
2509         unsigned int offset;
2510         struct mmc_data *data = host->data;
2511         int shift = host->data_shift;
2512         u32 status;
2513         unsigned int len;
2514         unsigned int remain, fcnt;
2515
2516         do {
2517                 if (!sg_miter_next(sg_miter))
2518                         goto done;
2519
2520                 host->sg = sg_miter->piter.sg;
2521                 buf = sg_miter->addr;
2522                 remain = sg_miter->length;
2523                 offset = 0;
2524
2525                 do {
2526                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2527                                         << shift) + host->part_buf_count;
2528                         len = min(remain, fcnt);
2529                         if (!len)
2530                                 break;
2531                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2532                         data->bytes_xfered += len;
2533                         offset += len;
2534                         remain -= len;
2535                 } while (remain);
2536
2537                 sg_miter->consumed = offset;
2538                 status = mci_readl(host, MINTSTS);
2539                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2540         /* if the RXDR is ready read again */
2541         } while ((status & SDMMC_INT_RXDR) ||
2542                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2543
2544         if (!remain) {
2545                 if (!sg_miter_next(sg_miter))
2546                         goto done;
2547                 sg_miter->consumed = 0;
2548         }
2549         sg_miter_stop(sg_miter);
2550         return;
2551
2552 done:
2553         sg_miter_stop(sg_miter);
2554         host->sg = NULL;
2555         smp_wmb(); /* drain writebuffer */
2556         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2557 }
2558
2559 static void dw_mci_write_data_pio(struct dw_mci *host)
2560 {
2561         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2562         void *buf;
2563         unsigned int offset;
2564         struct mmc_data *data = host->data;
2565         int shift = host->data_shift;
2566         u32 status;
2567         unsigned int len;
2568         unsigned int fifo_depth = host->fifo_depth;
2569         unsigned int remain, fcnt;
2570
2571         do {
2572                 if (!sg_miter_next(sg_miter))
2573                         goto done;
2574
2575                 host->sg = sg_miter->piter.sg;
2576                 buf = sg_miter->addr;
2577                 remain = sg_miter->length;
2578                 offset = 0;
2579
2580                 do {
2581                         fcnt = ((fifo_depth -
2582                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2583                                         << shift) - host->part_buf_count;
2584                         len = min(remain, fcnt);
2585                         if (!len)
2586                                 break;
2587                         host->push_data(host, (void *)(buf + offset), len);
2588                         data->bytes_xfered += len;
2589                         offset += len;
2590                         remain -= len;
2591                 } while (remain);
2592
2593                 sg_miter->consumed = offset;
2594                 status = mci_readl(host, MINTSTS);
2595                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2596         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2597
2598         if (!remain) {
2599                 if (!sg_miter_next(sg_miter))
2600                         goto done;
2601                 sg_miter->consumed = 0;
2602         }
2603         sg_miter_stop(sg_miter);
2604         return;
2605
2606 done:
2607         sg_miter_stop(sg_miter);
2608         host->sg = NULL;
2609         smp_wmb(); /* drain writebuffer */
2610         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2611 }
2612
2613 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2614 {
2615         del_timer(&host->cto_timer);
2616
2617         if (!host->cmd_status)
2618                 host->cmd_status = status;
2619
2620         smp_wmb(); /* drain writebuffer */
2621
2622         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2623         tasklet_schedule(&host->tasklet);
2624 }
2625
2626 static void dw_mci_handle_cd(struct dw_mci *host)
2627 {
2628         struct dw_mci_slot *slot = host->slot;
2629
2630         if (slot->mmc->ops->card_event)
2631                 slot->mmc->ops->card_event(slot->mmc);
2632         mmc_detect_change(slot->mmc,
2633                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2634 }
2635
2636 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2637 {
2638         struct dw_mci *host = dev_id;
2639         u32 pending;
2640         struct dw_mci_slot *slot = host->slot;
2641         unsigned long irqflags;
2642
2643         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2644
2645         if (pending) {
2646                 /* Check volt switch first, since it can look like an error */
2647                 if ((host->state == STATE_SENDING_CMD11) &&
2648                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2649                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2650                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2651
2652                         /*
2653                          * Hold the lock; we know cmd11_timer can't be kicked
2654                          * off after the lock is released, so safe to delete.
2655                          */
2656                         spin_lock_irqsave(&host->irq_lock, irqflags);
2657                         dw_mci_cmd_interrupt(host, pending);
2658                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2659
2660                         del_timer(&host->cmd11_timer);
2661                 }
2662
2663                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2664                         spin_lock_irqsave(&host->irq_lock, irqflags);
2665
2666                         del_timer(&host->cto_timer);
2667                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2668                         host->cmd_status = pending;
2669                         smp_wmb(); /* drain writebuffer */
2670                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2671
2672                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2673                 }
2674
2675                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2676                         /* if there is an error report DATA_ERROR */
2677                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2678                         host->data_status = pending;
2679                         smp_wmb(); /* drain writebuffer */
2680                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2681                         tasklet_schedule(&host->tasklet);
2682                 }
2683
2684                 if (pending & SDMMC_INT_DATA_OVER) {
2685                         del_timer(&host->dto_timer);
2686
2687                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2688                         if (!host->data_status)
2689                                 host->data_status = pending;
2690                         smp_wmb(); /* drain writebuffer */
2691                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2692                                 if (host->sg != NULL)
2693                                         dw_mci_read_data_pio(host, true);
2694                         }
2695                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2696                         tasklet_schedule(&host->tasklet);
2697                 }
2698
2699                 if (pending & SDMMC_INT_RXDR) {
2700                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2701                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2702                                 dw_mci_read_data_pio(host, false);
2703                 }
2704
2705                 if (pending & SDMMC_INT_TXDR) {
2706                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2707                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2708                                 dw_mci_write_data_pio(host);
2709                 }
2710
2711                 if (pending & SDMMC_INT_CMD_DONE) {
2712                         spin_lock_irqsave(&host->irq_lock, irqflags);
2713
2714                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2715                         dw_mci_cmd_interrupt(host, pending);
2716
2717                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2718                 }
2719
2720                 if (pending & SDMMC_INT_CD) {
2721                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2722                         dw_mci_handle_cd(host);
2723                 }
2724
2725                 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2726                         mci_writel(host, RINTSTS,
2727                                    SDMMC_INT_SDIO(slot->sdio_id));
2728                         __dw_mci_enable_sdio_irq(slot, 0);
2729                         sdio_signal_irq(slot->mmc);
2730                 }
2731
2732         }
2733
2734         if (host->use_dma != TRANS_MODE_IDMAC)
2735                 return IRQ_HANDLED;
2736
2737         /* Handle IDMA interrupts */
2738         if (host->dma_64bit_address == 1) {
2739                 pending = mci_readl(host, IDSTS64);
2740                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2741                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2742                                                         SDMMC_IDMAC_INT_RI);
2743                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2744                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2745                                 host->dma_ops->complete((void *)host);
2746                 }
2747         } else {
2748                 pending = mci_readl(host, IDSTS);
2749                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2750                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2751                                                         SDMMC_IDMAC_INT_RI);
2752                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2753                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2754                                 host->dma_ops->complete((void *)host);
2755                 }
2756         }
2757
2758         return IRQ_HANDLED;
2759 }
2760
2761 static int dw_mci_init_slot(struct dw_mci *host)
2762 {
2763         struct mmc_host *mmc;
2764         struct dw_mci_slot *slot;
2765         const struct dw_mci_drv_data *drv_data = host->drv_data;
2766         int ctrl_id, ret;
2767         u32 freq[2];
2768
2769         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2770         if (!mmc)
2771                 return -ENOMEM;
2772
2773         slot = mmc_priv(mmc);
2774         slot->id = 0;
2775         slot->sdio_id = host->sdio_id0 + slot->id;
2776         slot->mmc = mmc;
2777         slot->host = host;
2778         host->slot = slot;
2779
2780         mmc->ops = &dw_mci_ops;
2781         if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2782                                            freq, 2)) {
2783                 mmc->f_min = DW_MCI_FREQ_MIN;
2784                 mmc->f_max = DW_MCI_FREQ_MAX;
2785         } else {
2786                 dev_info(host->dev,
2787                         "'clock-freq-min-max' property was deprecated.\n");
2788                 mmc->f_min = freq[0];
2789                 mmc->f_max = freq[1];
2790         }
2791
2792         /*if there are external regulators, get them*/
2793         ret = mmc_regulator_get_supply(mmc);
2794         if (ret == -EPROBE_DEFER)
2795                 goto err_host_allocated;
2796
2797         if (!mmc->ocr_avail)
2798                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2799
2800         if (host->pdata->caps)
2801                 mmc->caps = host->pdata->caps;
2802
2803         /*
2804          * Support MMC_CAP_ERASE by default.
2805          * It needs to use trim/discard/erase commands.
2806          */
2807         mmc->caps |= MMC_CAP_ERASE;
2808
2809         if (host->pdata->pm_caps)
2810                 mmc->pm_caps = host->pdata->pm_caps;
2811
2812         if (host->dev->of_node) {
2813                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2814                 if (ctrl_id < 0)
2815                         ctrl_id = 0;
2816         } else {
2817                 ctrl_id = to_platform_device(host->dev)->id;
2818         }
2819         if (drv_data && drv_data->caps)
2820                 mmc->caps |= drv_data->caps[ctrl_id];
2821
2822         if (host->pdata->caps2)
2823                 mmc->caps2 = host->pdata->caps2;
2824
2825         ret = mmc_of_parse(mmc);
2826         if (ret)
2827                 goto err_host_allocated;
2828
2829         /* Process SDIO IRQs through the sdio_irq_work. */
2830         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2831                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2832
2833         /* Useful defaults if platform data is unset. */
2834         if (host->use_dma == TRANS_MODE_IDMAC) {
2835                 mmc->max_segs = host->ring_size;
2836                 mmc->max_blk_size = 65535;
2837                 mmc->max_seg_size = 0x1000;
2838                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2839                 mmc->max_blk_count = mmc->max_req_size / 512;
2840         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2841                 mmc->max_segs = 64;
2842                 mmc->max_blk_size = 65535;
2843                 mmc->max_blk_count = 65535;
2844                 mmc->max_req_size =
2845                                 mmc->max_blk_size * mmc->max_blk_count;
2846                 mmc->max_seg_size = mmc->max_req_size;
2847         } else {
2848                 /* TRANS_MODE_PIO */
2849                 mmc->max_segs = 64;
2850                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2851                 mmc->max_blk_count = 512;
2852                 mmc->max_req_size = mmc->max_blk_size *
2853                                     mmc->max_blk_count;
2854                 mmc->max_seg_size = mmc->max_req_size;
2855         }
2856
2857         dw_mci_get_cd(mmc);
2858
2859         ret = mmc_add_host(mmc);
2860         if (ret)
2861                 goto err_host_allocated;
2862
2863 #if defined(CONFIG_DEBUG_FS)
2864         dw_mci_init_debugfs(slot);
2865 #endif
2866
2867         return 0;
2868
2869 err_host_allocated:
2870         mmc_free_host(mmc);
2871         return ret;
2872 }
2873
2874 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2875 {
2876         /* Debugfs stuff is cleaned up by mmc core */
2877         mmc_remove_host(slot->mmc);
2878         slot->host->slot = NULL;
2879         mmc_free_host(slot->mmc);
2880 }
2881
2882 static void dw_mci_init_dma(struct dw_mci *host)
2883 {
2884         int addr_config;
2885         struct device *dev = host->dev;
2886
2887         /*
2888         * Check tansfer mode from HCON[17:16]
2889         * Clear the ambiguous description of dw_mmc databook:
2890         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2891         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2892         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2893         * 2b'11: Non DW DMA Interface -> pio only
2894         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2895         * simpler request/acknowledge handshake mechanism and both of them
2896         * are regarded as external dma master for dw_mmc.
2897         */
2898         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2899         if (host->use_dma == DMA_INTERFACE_IDMA) {
2900                 host->use_dma = TRANS_MODE_IDMAC;
2901         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2902                    host->use_dma == DMA_INTERFACE_GDMA) {
2903                 host->use_dma = TRANS_MODE_EDMAC;
2904         } else {
2905                 goto no_dma;
2906         }
2907
2908         /* Determine which DMA interface to use */
2909         if (host->use_dma == TRANS_MODE_IDMAC) {
2910                 /*
2911                 * Check ADDR_CONFIG bit in HCON to find
2912                 * IDMAC address bus width
2913                 */
2914                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2915
2916                 if (addr_config == 1) {
2917                         /* host supports IDMAC in 64-bit address mode */
2918                         host->dma_64bit_address = 1;
2919                         dev_info(host->dev,
2920                                  "IDMAC supports 64-bit address mode.\n");
2921                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2922                                 dma_set_coherent_mask(host->dev,
2923                                                       DMA_BIT_MASK(64));
2924                 } else {
2925                         /* host supports IDMAC in 32-bit address mode */
2926                         host->dma_64bit_address = 0;
2927                         dev_info(host->dev,
2928                                  "IDMAC supports 32-bit address mode.\n");
2929                 }
2930
2931                 /* Alloc memory for sg translation */
2932                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2933                                                    DESC_RING_BUF_SZ,
2934                                                    &host->sg_dma, GFP_KERNEL);
2935                 if (!host->sg_cpu) {
2936                         dev_err(host->dev,
2937                                 "%s: could not alloc DMA memory\n",
2938                                 __func__);
2939                         goto no_dma;
2940                 }
2941
2942                 host->dma_ops = &dw_mci_idmac_ops;
2943                 dev_info(host->dev, "Using internal DMA controller.\n");
2944         } else {
2945                 /* TRANS_MODE_EDMAC: check dma bindings again */
2946                 if ((device_property_read_string_array(dev, "dma-names",
2947                                                        NULL, 0) < 0) ||
2948                     !device_property_present(dev, "dmas")) {
2949                         goto no_dma;
2950                 }
2951                 host->dma_ops = &dw_mci_edmac_ops;
2952                 dev_info(host->dev, "Using external DMA controller.\n");
2953         }
2954
2955         if (host->dma_ops->init && host->dma_ops->start &&
2956             host->dma_ops->stop && host->dma_ops->cleanup) {
2957                 if (host->dma_ops->init(host)) {
2958                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2959                                 __func__);
2960                         goto no_dma;
2961                 }
2962         } else {
2963                 dev_err(host->dev, "DMA initialization not found.\n");
2964                 goto no_dma;
2965         }
2966
2967         return;
2968
2969 no_dma:
2970         dev_info(host->dev, "Using PIO mode.\n");
2971         host->use_dma = TRANS_MODE_PIO;
2972 }
2973
2974 static void dw_mci_cmd11_timer(unsigned long arg)
2975 {
2976         struct dw_mci *host = (struct dw_mci *)arg;
2977
2978         if (host->state != STATE_SENDING_CMD11) {
2979                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2980                 return;
2981         }
2982
2983         host->cmd_status = SDMMC_INT_RTO;
2984         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2985         tasklet_schedule(&host->tasklet);
2986 }
2987
2988 static void dw_mci_cto_timer(unsigned long arg)
2989 {
2990         struct dw_mci *host = (struct dw_mci *)arg;
2991         unsigned long irqflags;
2992         u32 pending;
2993
2994         spin_lock_irqsave(&host->irq_lock, irqflags);
2995
2996         /*
2997          * If somehow we have very bad interrupt latency it's remotely possible
2998          * that the timer could fire while the interrupt is still pending or
2999          * while the interrupt is midway through running.  Let's be paranoid
3000          * and detect those two cases.  Note that this is paranoia is somewhat
3001          * justified because in this function we don't actually cancel the
3002          * pending command in the controller--we just assume it will never come.
3003          */
3004         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3005         if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3006                 /* The interrupt should fire; no need to act but we can warn */
3007                 dev_warn(host->dev, "Unexpected interrupt latency\n");
3008                 goto exit;
3009         }
3010         if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3011                 /* Presumably interrupt handler couldn't delete the timer */
3012                 dev_warn(host->dev, "CTO timeout when already completed\n");
3013                 goto exit;
3014         }
3015
3016         /*
3017          * Continued paranoia to make sure we're in the state we expect.
3018          * This paranoia isn't really justified but it seems good to be safe.
3019          */
3020         switch (host->state) {
3021         case STATE_SENDING_CMD11:
3022         case STATE_SENDING_CMD:
3023         case STATE_SENDING_STOP:
3024                 /*
3025                  * If CMD_DONE interrupt does NOT come in sending command
3026                  * state, we should notify the driver to terminate current
3027                  * transfer and report a command timeout to the core.
3028                  */
3029                 host->cmd_status = SDMMC_INT_RTO;
3030                 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3031                 tasklet_schedule(&host->tasklet);
3032                 break;
3033         default:
3034                 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3035                          host->state);
3036                 break;
3037         }
3038
3039 exit:
3040         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3041 }
3042
3043 static void dw_mci_dto_timer(unsigned long arg)
3044 {
3045         struct dw_mci *host = (struct dw_mci *)arg;
3046
3047         switch (host->state) {
3048         case STATE_SENDING_DATA:
3049         case STATE_DATA_BUSY:
3050                 /*
3051                  * If DTO interrupt does NOT come in sending data state,
3052                  * we should notify the driver to terminate current transfer
3053                  * and report a data timeout to the core.
3054                  */
3055                 host->data_status = SDMMC_INT_DRTO;
3056                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3057                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3058                 tasklet_schedule(&host->tasklet);
3059                 break;
3060         default:
3061                 break;
3062         }
3063 }
3064
3065 #ifdef CONFIG_OF
3066 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3067 {
3068         struct dw_mci_board *pdata;
3069         struct device *dev = host->dev;