drivers/mmc/host/dw_mmc-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/clk.h>
  13 #include <linux/mmc/host.h>
  14 #include <linux/of_address.h>
  15 #include <linux/mmc/slot-gpio.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/slab.h>
  18
  19 #include "dw_mmc.h"
  20 #include "dw_mmc-pltfm.h"
  21
  22 #define RK3288_CLKGEN_DIV       2
  23
  24 struct dw_mci_rockchip_priv_data {
  25         struct clk              *drv_clk;
  26         struct clk              *sample_clk;
  27         int                     default_sample_phase;
  28         int                     num_phases;
  29 };
  30
  31 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  32 {
  33         struct dw_mci_rockchip_priv_data *priv = host->priv;
  34         int ret;
  35         unsigned int cclkin;
  36         u32 bus_hz;
  37
  38         if (ios->clock == 0)
  39                 return;
  40
  41         /*
  42          * cclkin: source clock of mmc controller
  43          * bus_hz: card interface clock generated by CLKGEN
  44          * bus_hz = cclkin / RK3288_CLKGEN_DIV
  45          * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
  46          *
  47          * Note: div can only be 0 or 1
  48          *       if DDR50 8bit mode(only emmc work in 8bit mode),
  49          *       div must be set 1
  50          */
  51         if (ios->bus_width == MMC_BUS_WIDTH_8 &&
  52             ios->timing == MMC_TIMING_MMC_DDR52)
  53                 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
  54         else
  55                 cclkin = ios->clock * RK3288_CLKGEN_DIV;
  56
  57         ret = clk_set_rate(host->ciu_clk, cclkin);
  58         if (ret)
  59                 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
  60
  61         bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
  62         if (bus_hz != host->bus_hz) {
  63                 host->bus_hz = bus_hz;
  64                 /* force dw_mci_setup_bus() */
  65                 host->current_speed = 0;
  66         }
  67
  68         /* Make sure we use phases which we can enumerate with */
  69         if (!IS_ERR(priv->sample_clk))
  70                 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
  71
  72         /*
  73          * Set the drive phase offset based on speed mode to achieve hold times.
  74          *
  75          * NOTE: this is _not_ a value that is dynamically tuned and is also
  76          * _not_ a value that will vary from board to board.  It is a value
  77          * that could vary between different SoC models if they had massively
  78          * different output clock delays inside their dw_mmc IP block (delay_o),
  79          * but since it's OK to overshoot a little we don't need to do complex
  80          * calculations and can pick values that will just work for everyone.
  81          *
  82          * When picking values we'll stick with picking 0/90/180/270 since
  83          * those can be made very accurately on all known Rockchip SoCs.
  84          *
  85          * Note that these values match values from the DesignWare Databook
  86          * tables for the most part except for SDR12 and "ID mode".  For those
  87          * two modes the databook calculations assume a clock in of 50MHz.  As
  88          * seen above, we always use a clock in rate that is exactly the
  89          * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
  90          * back out before the controller sees it).
  91          *
  92          * From measurement of a single device, it appears that delay_o is
  93          * about .5 ns.  Since we try to leave a bit of margin, it's expected
  94          * that numbers here will be fine even with much larger delay_o
  95          * (the 1.4 ns assumed by the DesignWare Databook would result in the
  96          * same results, for instance).
  97          */
  98         if (!IS_ERR(priv->drv_clk)) {
  99                 int phase;
 100
 101                 /*
 102                  * In almost all cases a 90 degree phase offset will provide
 103                  * sufficient hold times across all valid input clock rates
 104                  * assuming delay_o is not absurd for a given SoC.  We'll use
 105                  * that as a default.
 106                  */
 107                 phase = 90;
 108
 109                 switch (ios->timing) {
 110                 case MMC_TIMING_MMC_DDR52:
 111                         /*
 112                          * Since clock in rate with MMC_DDR52 is doubled when
 113                          * bus width is 8 we need to double the phase offset
 114                          * to get the same timings.
 115                          */
 116                         if (ios->bus_width == MMC_BUS_WIDTH_8)
 117                                 phase = 180;
 118                         break;
 119                 case MMC_TIMING_UHS_SDR104:
 120                 case MMC_TIMING_MMC_HS200:
 121                         /*
 122                          * In the case of 150 MHz clock (typical max for
 123                          * Rockchip SoCs), 90 degree offset will add a delay
 124                          * of 1.67 ns.  That will meet min hold time of .8 ns
 125                          * as long as clock output delay is < .87 ns.  On
 126                          * SoCs measured this seems to be OK, but it doesn't
 127                          * hurt to give margin here, so we use 180.
 128                          */
 129                         phase = 180;
 130                         break;
 131                 }
 132
 133                 clk_set_phase(priv->drv_clk, phase);
 134         }
 135 }
 136
 137 #define TUNING_ITERATION_TO_PHASE(i, num_phases) \
 138                 (DIV_ROUND_UP((i) * 360, num_phases))
 139
 140 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
 141 {
 142         struct dw_mci *host = slot->host;
 143         struct dw_mci_rockchip_priv_data *priv = host->priv;
 144         struct mmc_host *mmc = slot->mmc;
 145         int ret = 0;
 146         int i;
 147         bool v, prev_v = 0, first_v;
 148         struct range_t {
 149                 int start;
 150                 int end; /* inclusive */
 151         };
 152         struct range_t *ranges;
 153         unsigned int range_count = 0;
 154         int longest_range_len = -1;
 155         int longest_range = -1;
 156         int middle_phase;
 157
 158         if (IS_ERR(priv->sample_clk)) {
 159                 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
 160                 return -EIO;
 161         }
 162
 163         ranges = kmalloc_array(priv->num_phases / 2 + 1,
 164                                sizeof(*ranges), GFP_KERNEL);
 165         if (!ranges)
 166                 return -ENOMEM;
 167
 168         /* Try each phase and extract good ranges */
 169         for (i = 0; i < priv->num_phases; ) {
 170                 clk_set_phase(priv->sample_clk,
 171                               TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
 172
 173                 v = !mmc_send_tuning(mmc, opcode, NULL);
 174
 175                 if (i == 0)
 176                         first_v = v;
 177
 178                 if ((!prev_v) && v) {
 179                         range_count++;
 180                         ranges[range_count-1].start = i;
 181                 }
 182                 if (v) {
 183                         ranges[range_count-1].end = i;
 184                         i++;
 185                 } else if (i == priv->num_phases - 1) {
 186                         /* No extra skipping rules if we're at the end */
 187                         i++;
 188                 } else {
 189                         /*
 190                          * No need to check too close to an invalid
 191                          * one since testing bad phases is slow.  Skip
 192                          * 20 degrees.
 193                          */
 194                         i += DIV_ROUND_UP(20 * priv->num_phases, 360);
 195
 196                         /* Always test the last one */
 197                         if (i >= priv->num_phases)
 198                                 i = priv->num_phases - 1;
 199                 }
 200
 201                 prev_v = v;
 202         }
 203
 204         if (range_count == 0) {
 205                 dev_warn(host->dev, "All phases bad!");
 206                 ret = -EIO;
 207                 goto free;
 208         }
 209
 210         /* wrap around case, merge the end points */
 211         if ((range_count > 1) && first_v && v) {
 212                 ranges[0].start = ranges[range_count-1].start;
 213                 range_count--;
 214         }
 215
 216         if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
 217                 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
 218                 dev_info(host->dev, "All phases work, using default phase %d.",
 219                          priv->default_sample_phase);
 220                 goto free;
 221         }
 222
 223         /* Find the longest range */
 224         for (i = 0; i < range_count; i++) {
 225                 int len = (ranges[i].end - ranges[i].start + 1);
 226
 227                 if (len < 0)
 228                         len += priv->num_phases;
 229
 230                 if (longest_range_len < len) {
 231                         longest_range_len = len;
 232                         longest_range = i;
 233                 }
 234
 235                 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
 236                         TUNING_ITERATION_TO_PHASE(ranges[i].start,
 237                                                   priv->num_phases),
 238                         TUNING_ITERATION_TO_PHASE(ranges[i].end,
 239                                                   priv->num_phases),
 240                         len
 241                 );
 242         }
 243
 244         dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
 245                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
 246                                           priv->num_phases),
 247                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
 248                                           priv->num_phases),
 249                 longest_range_len
 250         );
 251
 252         middle_phase = ranges[longest_range].start + longest_range_len / 2;
 253         middle_phase %= priv->num_phases;
 254         dev_info(host->dev, "Successfully tuned phase to %d\n",
 255                  TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases));
 256
 257         clk_set_phase(priv->sample_clk,
 258                       TUNING_ITERATION_TO_PHASE(middle_phase,
 259                                                 priv->num_phases));
 260
 261 free:
 262         kfree(ranges);
 263         return ret;
 264 }
 265
 266 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
 267 {
 268         struct device_node *np = host->dev->of_node;
 269         struct dw_mci_rockchip_priv_data *priv;
 270
 271         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
 272         if (!priv)
 273                 return -ENOMEM;
 274
 275         if (of_property_read_u32(np, "rockchip,desired-num-phases",
 276                                         &priv->num_phases))
 277                 priv->num_phases = 360;
 278
 279         if (of_property_read_u32(np, "rockchip,default-sample-phase",
 280                                         &priv->default_sample_phase))
 281                 priv->default_sample_phase = 0;
 282
 283         priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
 284         if (IS_ERR(priv->drv_clk))
 285                 dev_dbg(host->dev, "ciu_drv not available\n");
 286
 287         priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
 288         if (IS_ERR(priv->sample_clk))
 289                 dev_dbg(host->dev, "ciu_sample not available\n");
 290
 291         host->priv = priv;
 292
 293         return 0;
 294 }
 295
 296 static int dw_mci_rockchip_init(struct dw_mci *host)
 297 {
 298         /* It is slot 8 on Rockchip SoCs */
 299         host->sdio_id0 = 8;
 300
 301         if (of_device_is_compatible(host->dev->of_node,
 302                                     "rockchip,rk3288-dw-mshc"))
 303                 host->bus_hz /= RK3288_CLKGEN_DIV;
 304
 305         return 0;
 306 }
 307
 308 /* Common capabilities of RK3288 SoC */
 309 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
 310         MMC_CAP_CMD23,
 311         MMC_CAP_CMD23,
 312         MMC_CAP_CMD23,
 313         MMC_CAP_CMD23,
 314 };
 315
 316 static const struct dw_mci_drv_data rk2928_drv_data = {
 317         .init                   = dw_mci_rockchip_init,
 318 };
 319
 320 static const struct dw_mci_drv_data rk3288_drv_data = {
 321         .caps                   = dw_mci_rk3288_dwmmc_caps,
 322         .num_caps               = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
 323         .set_ios                = dw_mci_rk3288_set_ios,
 324         .execute_tuning         = dw_mci_rk3288_execute_tuning,
 325         .parse_dt               = dw_mci_rk3288_parse_dt,
 326         .init                   = dw_mci_rockchip_init,
 327 };
 328
 329 static const struct of_device_id dw_mci_rockchip_match[] = {
 330         { .compatible = "rockchip,rk2928-dw-mshc",
 331                 .data = &rk2928_drv_data },
 332         { .compatible = "rockchip,rk3288-dw-mshc",
 333                 .data = &rk3288_drv_data },
 334         {},
 335 };
 336 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 337
 338 static int dw_mci_rockchip_probe(struct platform_device *pdev)
 339 {
 340         const struct dw_mci_drv_data *drv_data;
 341         const struct of_device_id *match;
 342         int ret;
 343
 344         if (!pdev->dev.of_node)
 345                 return -ENODEV;
 346
 347         match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 348         drv_data = match->data;
 349
 350         pm_runtime_get_noresume(&pdev->dev);
 351         pm_runtime_set_active(&pdev->dev);
 352         pm_runtime_enable(&pdev->dev);
 353         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 354         pm_runtime_use_autosuspend(&pdev->dev);
 355
 356         ret = dw_mci_pltfm_register(pdev, drv_data);
 357         if (ret) {
 358                 pm_runtime_disable(&pdev->dev);
 359                 pm_runtime_set_suspended(&pdev->dev);
 360                 pm_runtime_put_noidle(&pdev->dev);
 361                 return ret;
 362         }
 363
 364         pm_runtime_put_autosuspend(&pdev->dev);
 365
 366         return 0;
 367 }
 368
 369 static int dw_mci_rockchip_remove(struct platform_device *pdev)
 370 {
 371         pm_runtime_get_sync(&pdev->dev);
 372         pm_runtime_disable(&pdev->dev);
 373         pm_runtime_put_noidle(&pdev->dev);
 374
 375         return dw_mci_pltfm_remove(pdev);
 376 }
 377
 378 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
 379         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 380                                 pm_runtime_force_resume)
 381         SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
 382                            dw_mci_runtime_resume,
 383                            NULL)
 384 };
 385
 386 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 387         .probe          = dw_mci_rockchip_probe,
 388         .remove         = dw_mci_rockchip_remove,
 389         .driver         = {
 390                 .name           = "dwmmc_rockchip",
 391                 .of_match_table = dw_mci_rockchip_match,
 392                 .pm             = &dw_mci_rockchip_dev_pm_ops,
 393         },
 394 };
 395
 396 module_platform_driver(dw_mci_rockchip_pltfm_driver);
 397
 398 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 399 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
 400 MODULE_ALIAS("platform:dwmmc_rockchip");
 401 MODULE_LICENSE("GPL v2");