2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
4 * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #ifndef _DW_MMC_EXYNOS_H_
13 #define _DW_MMC_EXYNOS_H_
15 /* Extended Register's Offset */
16 #define SDMMC_CLKSEL 0x09C
17 #define SDMMC_CLKSEL64 0x0A8
19 /* CLKSEL register defines */
20 #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
21 #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
22 #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
23 #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
24 #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
25 SDMMC_CLKSEL_CCLK_DRIVE(y) | \
26 SDMMC_CLKSEL_CCLK_DIVIDER(z))
27 #define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
29 /* Protector Register */
30 #define SDMMC_EMMCP_BASE 0x1000
31 #define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
32 #define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
33 #define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
34 #define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
36 /* SMU control defines */
37 #define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7)
38 #define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6)
39 #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
40 #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
41 #define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3)
42 #define SDMMC_MPSCTRL_ECB_MODE BIT(2)
43 #define SDMMC_MPSCTRL_ENCRYPTION BIT(1)
44 #define SDMMC_MPSCTRL_VALID BIT(0)
46 /* Maximum number of Ending sector */
47 #define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF
49 /* Fixed clock divider */
50 #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
51 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
53 /* Minimal required clock frequency for cclkin, unit: HZ */
54 #define EXYNOS_CCLKIN_MIN 50000000
56 #endif /* _DW_MMC_EXYNOS_H_ */