drivers/misc/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2019 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "include/hw_ip/mmu/mmu_general.h"
  10 #include "include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "include/goya/asic_reg/goya_masks.h"
  12
  13 #include <linux/pci.h>
  14 #include <linux/genalloc.h>
  15 #include <linux/firmware.h>
  16 #include <linux/hwmon.h>
  17 #include <linux/io-64-nonatomic-lo-hi.h>
  18 #include <linux/io-64-nonatomic-hi-lo.h>
  19
  20 /*
  21  * GOYA security scheme:
  22  *
  23  * 1. Host is protected by:
  24  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  25  *        - MMU
  26  *
  27  * 2. DRAM is protected by:
  28  *        - Range registers (protect the first 512MB)
  29  *        - MMU (isolation between users)
  30  *
  31  * 3. Configuration is protected by:
  32  *        - Range registers
  33  *        - Protection bits
  34  *
  35  * When MMU is disabled:
  36  *
  37  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  38  * PQ, CB and the data are on the host.
  39  *
  40  * QMAN TPC/MME:
  41  * PQ, CQ and CP are not secured.
  42  * PQ, CB and the data are on the SRAM/DRAM.
  43  *
  44  * Since QMAN DMA is secured, KMD is parsing the DMA CB:
  45  *     - KMD checks DMA pointer
  46  *     - WREG, MSG_PROT are not allowed.
  47  *     - MSG_LONG/SHORT are allowed.
  48  *
  49  * A read/write transaction by the QMAN to a protected area will succeed if
  50  * and only if the QMAN's CP is secured and MSG_PROT is used
  51  *
  52  *
  53  * When MMU is enabled:
  54  *
  55  * QMAN DMA: PQ, CQ and CP are secured.
  56  * MMU is set to bypass on the Secure props register of the QMAN.
  57  * The reasons we don't enable MMU for PQ, CQ and CP are:
  58  *     - PQ entry is in kernel address space and KMD doesn't map it.
  59  *     - CP writes to MSIX register and to kernel address space (completion
  60  *       queue).
  61  *
  62  * DMA is not secured but because CP is secured, KMD still needs to parse the
  63  * CB, but doesn't need to check the DMA addresses.
  64  *
  65  * For QMAN DMA 0, DMA is also secured because only KMD uses this DMA and KMD
  66  * doesn't map memory in MMU.
  67  *
  68  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  69  *
  70  * DMA RR does NOT protect host because DMA is not secured
  71  *
  72  */
  73
  74 #define GOYA_MMU_REGS_NUM               61
  75
  76 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  77
  78 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  79 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  80 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  81 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  82 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  83 #define GOYA_CPU_TIMEOUT_USEC           10000000        /* 10s */
  84 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  85 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  86 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  87
  88 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  89
  90 #define GOYA_MAX_INITIATORS             20
  91
  92 #define GOYA_MAX_STRING_LEN             20
  93
  94 #define GOYA_CB_POOL_CB_CNT             512
  95 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  96
  97 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
  98                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
  99                 "goya cq 4", "goya cpu eq"
 100 };
 101
 102 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 103         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
 104         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 105         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 106         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 107         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 108         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 109         [PACKET_FENCE]          = sizeof(struct packet_fence),
 110         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 111         [PACKET_NOP]            = sizeof(struct packet_nop),
 112         [PACKET_STOP]           = sizeof(struct packet_stop)
 113 };
 114
 115 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 116         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 117         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 118         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 119         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 120         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 121         mmTPC0_QM_GLBL_SECURE_PROPS,
 122         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 123         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 124         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 125         mmTPC0_CFG_ARUSER,
 126         mmTPC0_CFG_AWUSER,
 127         mmTPC1_QM_GLBL_SECURE_PROPS,
 128         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 129         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 130         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 131         mmTPC1_CFG_ARUSER,
 132         mmTPC1_CFG_AWUSER,
 133         mmTPC2_QM_GLBL_SECURE_PROPS,
 134         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 135         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 136         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 137         mmTPC2_CFG_ARUSER,
 138         mmTPC2_CFG_AWUSER,
 139         mmTPC3_QM_GLBL_SECURE_PROPS,
 140         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 141         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 142         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 143         mmTPC3_CFG_ARUSER,
 144         mmTPC3_CFG_AWUSER,
 145         mmTPC4_QM_GLBL_SECURE_PROPS,
 146         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 147         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 148         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 149         mmTPC4_CFG_ARUSER,
 150         mmTPC4_CFG_AWUSER,
 151         mmTPC5_QM_GLBL_SECURE_PROPS,
 152         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 153         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 154         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 155         mmTPC5_CFG_ARUSER,
 156         mmTPC5_CFG_AWUSER,
 157         mmTPC6_QM_GLBL_SECURE_PROPS,
 158         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 159         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 160         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 161         mmTPC6_CFG_ARUSER,
 162         mmTPC6_CFG_AWUSER,
 163         mmTPC7_QM_GLBL_SECURE_PROPS,
 164         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 165         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 166         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 167         mmTPC7_CFG_ARUSER,
 168         mmTPC7_CFG_AWUSER,
 169         mmMME_QM_GLBL_SECURE_PROPS,
 170         mmMME_QM_GLBL_NON_SECURE_PROPS,
 171         mmMME_CMDQ_GLBL_SECURE_PROPS,
 172         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 173         mmMME_SBA_CONTROL_DATA,
 174         mmMME_SBB_CONTROL_DATA,
 175         mmMME_SBC_CONTROL_DATA,
 176         mmMME_WBC_CONTROL_DATA
 177 };
 178
 179 #define GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE 121
 180
 181 static u32 goya_non_fatal_events[GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE] = {
 182         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 183         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 184         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 185         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 186         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 187         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 188         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 189         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 190         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 191         GOYA_ASYNC_EVENT_ID_MME_ECC,
 192         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 193         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 194         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 195         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 196         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 197         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 198         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 199         GOYA_ASYNC_EVENT_ID_SRAM0,
 200         GOYA_ASYNC_EVENT_ID_SRAM1,
 201         GOYA_ASYNC_EVENT_ID_SRAM2,
 202         GOYA_ASYNC_EVENT_ID_SRAM3,
 203         GOYA_ASYNC_EVENT_ID_SRAM4,
 204         GOYA_ASYNC_EVENT_ID_SRAM5,
 205         GOYA_ASYNC_EVENT_ID_SRAM6,
 206         GOYA_ASYNC_EVENT_ID_SRAM7,
 207         GOYA_ASYNC_EVENT_ID_SRAM8,
 208         GOYA_ASYNC_EVENT_ID_SRAM9,
 209         GOYA_ASYNC_EVENT_ID_SRAM10,
 210         GOYA_ASYNC_EVENT_ID_SRAM11,
 211         GOYA_ASYNC_EVENT_ID_SRAM12,
 212         GOYA_ASYNC_EVENT_ID_SRAM13,
 213         GOYA_ASYNC_EVENT_ID_SRAM14,
 214         GOYA_ASYNC_EVENT_ID_SRAM15,
 215         GOYA_ASYNC_EVENT_ID_SRAM16,
 216         GOYA_ASYNC_EVENT_ID_SRAM17,
 217         GOYA_ASYNC_EVENT_ID_SRAM18,
 218         GOYA_ASYNC_EVENT_ID_SRAM19,
 219         GOYA_ASYNC_EVENT_ID_SRAM20,
 220         GOYA_ASYNC_EVENT_ID_SRAM21,
 221         GOYA_ASYNC_EVENT_ID_SRAM22,
 222         GOYA_ASYNC_EVENT_ID_SRAM23,
 223         GOYA_ASYNC_EVENT_ID_SRAM24,
 224         GOYA_ASYNC_EVENT_ID_SRAM25,
 225         GOYA_ASYNC_EVENT_ID_SRAM26,
 226         GOYA_ASYNC_EVENT_ID_SRAM27,
 227         GOYA_ASYNC_EVENT_ID_SRAM28,
 228         GOYA_ASYNC_EVENT_ID_SRAM29,
 229         GOYA_ASYNC_EVENT_ID_GIC500,
 230         GOYA_ASYNC_EVENT_ID_PLL0,
 231         GOYA_ASYNC_EVENT_ID_PLL1,
 232         GOYA_ASYNC_EVENT_ID_PLL3,
 233         GOYA_ASYNC_EVENT_ID_PLL4,
 234         GOYA_ASYNC_EVENT_ID_PLL5,
 235         GOYA_ASYNC_EVENT_ID_PLL6,
 236         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 237         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 238         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 239         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 240         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 241         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 242         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 243         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 244         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 245         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 246         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 247         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 248         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 249         GOYA_ASYNC_EVENT_ID_MME_WACS,
 250         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 251         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 252         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 253         GOYA_ASYNC_EVENT_ID_PSOC,
 254         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 255         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 256         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 257         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 258         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 259         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 260         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 261         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 262         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 263         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 264         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 265         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 266         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 267         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 268         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 269         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 270         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 271         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 272         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 273         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 274         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 275         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 276         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 277         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 278         GOYA_ASYNC_EVENT_ID_MME_QM,
 279         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 280         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 281         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 282         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 283         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 284         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 285         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 286         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 287         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 288         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 289         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 290         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 291         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 292         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 293         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 294         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 295         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 296         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 297         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 298         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 299         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 300         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 301         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 302         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4
 303 };
 304
 305 static int goya_armcp_info_get(struct hl_device *hdev);
 306 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 307 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 308 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 309 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
 310                                         u64 phys_addr);
 311
 312 static void goya_get_fixed_properties(struct hl_device *hdev)
 313 {
 314         struct asic_fixed_properties *prop = &hdev->asic_prop;
 315         int i;
 316
 317         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 318                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 319                 prop->hw_queues_props[i].kmd_only = 0;
 320         }
 321
 322         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 323                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 324                 prop->hw_queues_props[i].kmd_only = 1;
 325         }
 326
 327         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 328                         NUMBER_OF_INT_HW_QUEUES; i++) {
 329                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 330                 prop->hw_queues_props[i].kmd_only = 0;
 331         }
 332
 333         for (; i < HL_MAX_QUEUES; i++)
 334                 prop->hw_queues_props[i].type = QUEUE_TYPE_NA;
 335
 336         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 337
 338         prop->dram_base_address = DRAM_PHYS_BASE;
 339         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 340         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 341         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 342
 343         prop->sram_base_address = SRAM_BASE_ADDR;
 344         prop->sram_size = SRAM_SIZE;
 345         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 346         prop->sram_user_base_address = prop->sram_base_address +
 347                                                 SRAM_USER_BASE_OFFSET;
 348
 349         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 350         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 351         if (hdev->pldm)
 352                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 353         else
 354                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 355         prop->mmu_pte_size = HL_PTE_SIZE;
 356         prop->mmu_hop_table_size = HOP_TABLE_SIZE;
 357         prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 358         prop->dram_page_size = PAGE_SIZE_2MB;
 359
 360         prop->host_phys_base_address = HOST_PHYS_BASE;
 361         prop->va_space_host_start_address = VA_HOST_SPACE_START;
 362         prop->va_space_host_end_address = VA_HOST_SPACE_END;
 363         prop->va_space_dram_start_address = VA_DDR_SPACE_START;
 364         prop->va_space_dram_end_address = VA_DDR_SPACE_END;
 365         prop->dram_size_for_default_page_mapping =
 366                         prop->va_space_dram_end_address;
 367         prop->cfg_size = CFG_SIZE;
 368         prop->max_asid = MAX_ASID;
 369         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 370         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 371         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 372         prop->max_power_default = MAX_POWER_DEFAULT;
 373         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 374
 375         prop->high_pll = PLL_HIGH_DEFAULT;
 376 }
 377
 378 int goya_send_pci_access_msg(struct hl_device *hdev, u32 opcode)
 379 {
 380         struct armcp_packet pkt;
 381
 382         memset(&pkt, 0, sizeof(pkt));
 383
 384         pkt.ctl = cpu_to_le32(opcode << ARMCP_PKT_CTL_OPCODE_SHIFT);
 385
 386         return hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt,
 387                         sizeof(pkt), HL_DEVICE_TIMEOUT_USEC, NULL);
 388 }
 389
 390 /*
 391  * goya_pci_bars_map - Map PCI BARS of Goya device
 392  *
 393  * @hdev: pointer to hl_device structure
 394  *
 395  * Request PCI regions and map them to kernel virtual addresses.
 396  * Returns 0 on success
 397  *
 398  */
 399 static int goya_pci_bars_map(struct hl_device *hdev)
 400 {
 401         struct pci_dev *pdev = hdev->pdev;
 402         int rc;
 403
 404         rc = pci_request_regions(pdev, HL_NAME);
 405         if (rc) {
 406                 dev_err(hdev->dev, "Cannot obtain PCI resources\n");
 407                 return rc;
 408         }
 409
 410         hdev->pcie_bar[SRAM_CFG_BAR_ID] =
 411                         pci_ioremap_bar(pdev, SRAM_CFG_BAR_ID);
 412         if (!hdev->pcie_bar[SRAM_CFG_BAR_ID]) {
 413                 dev_err(hdev->dev, "pci_ioremap_bar failed for CFG\n");
 414                 rc = -ENODEV;
 415                 goto err_release_regions;
 416         }
 417
 418         hdev->pcie_bar[MSIX_BAR_ID] = pci_ioremap_bar(pdev, MSIX_BAR_ID);
 419         if (!hdev->pcie_bar[MSIX_BAR_ID]) {
 420                 dev_err(hdev->dev, "pci_ioremap_bar failed for MSIX\n");
 421                 rc = -ENODEV;
 422                 goto err_unmap_sram_cfg;
 423         }
 424
 425         hdev->pcie_bar[DDR_BAR_ID] = pci_ioremap_wc_bar(pdev, DDR_BAR_ID);
 426         if (!hdev->pcie_bar[DDR_BAR_ID]) {
 427                 dev_err(hdev->dev, "pci_ioremap_bar failed for DDR\n");
 428                 rc = -ENODEV;
 429                 goto err_unmap_msix;
 430         }
 431
 432         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 433                                 (CFG_BASE - SRAM_BASE_ADDR);
 434
 435         return 0;
 436
 437 err_unmap_msix:
 438         iounmap(hdev->pcie_bar[MSIX_BAR_ID]);
 439 err_unmap_sram_cfg:
 440         iounmap(hdev->pcie_bar[SRAM_CFG_BAR_ID]);
 441 err_release_regions:
 442         pci_release_regions(pdev);
 443
 444         return rc;
 445 }
 446
 447 /*
 448  * goya_pci_bars_unmap - Unmap PCI BARS of Goya device
 449  *
 450  * @hdev: pointer to hl_device structure
 451  *
 452  * Release all PCI BARS and unmap their virtual addresses
 453  *
 454  */
 455 static void goya_pci_bars_unmap(struct hl_device *hdev)
 456 {
 457         struct pci_dev *pdev = hdev->pdev;
 458
 459         iounmap(hdev->pcie_bar[DDR_BAR_ID]);
 460         iounmap(hdev->pcie_bar[MSIX_BAR_ID]);
 461         iounmap(hdev->pcie_bar[SRAM_CFG_BAR_ID]);
 462         pci_release_regions(pdev);
 463 }
 464
 465 /*
 466  * goya_elbi_write - Write through the ELBI interface
 467  *
 468  * @hdev: pointer to hl_device structure
 469  *
 470  * return 0 on success, -1 on failure
 471  *
 472  */
 473 static int goya_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
 474 {
 475         struct pci_dev *pdev = hdev->pdev;
 476         ktime_t timeout;
 477         u32 val;
 478
 479         /* Clear previous status */
 480         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
 481
 482         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
 483         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
 484         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
 485                                 PCI_CONFIG_ELBI_CTRL_WRITE);
 486
 487         timeout = ktime_add_ms(ktime_get(), 10);
 488         for (;;) {
 489                 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
 490                 if (val & PCI_CONFIG_ELBI_STS_MASK)
 491                         break;
 492                 if (ktime_compare(ktime_get(), timeout) > 0) {
 493                         pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
 494                                                 &val);
 495                         break;
 496                 }
 497                 usleep_range(300, 500);
 498         }
 499
 500         if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
 501                 return 0;
 502
 503         if (val & PCI_CONFIG_ELBI_STS_ERR) {
 504                 dev_err(hdev->dev, "Error writing to ELBI\n");
 505                 return -EIO;
 506         }
 507
 508         if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
 509                 dev_err(hdev->dev, "ELBI write didn't finish in time\n");
 510                 return -EIO;
 511         }
 512
 513         dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
 514         return -EIO;
 515 }
 516
 517 /*
 518  * goya_iatu_write - iatu write routine
 519  *
 520  * @hdev: pointer to hl_device structure
 521  *
 522  */
 523 static int goya_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
 524 {
 525         u32 dbi_offset;
 526         int rc;
 527
 528         dbi_offset = addr & 0xFFF;
 529
 530         rc = goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0x00300000);
 531         rc |= goya_elbi_write(hdev, mmPCIE_DBI_BASE + dbi_offset, data);
 532
 533         if (rc)
 534                 return -EIO;
 535
 536         return 0;
 537 }
 538
 539 static void goya_reset_link_through_bridge(struct hl_device *hdev)
 540 {
 541         struct pci_dev *pdev = hdev->pdev;
 542         struct pci_dev *parent_port;
 543         u16 val;
 544
 545         parent_port = pdev->bus->self;
 546         pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val);
 547         val |= PCI_BRIDGE_CTL_BUS_RESET;
 548         pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
 549         ssleep(1);
 550
 551         val &= ~(PCI_BRIDGE_CTL_BUS_RESET);
 552         pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
 553         ssleep(3);
 554 }
 555
 556 /*
 557  * goya_set_ddr_bar_base - set DDR bar to map specific device address
 558  *
 559  * @hdev: pointer to hl_device structure
 560  * @addr: address in DDR. Must be aligned to DDR bar size
 561  *
 562  * This function configures the iATU so that the DDR bar will start at the
 563  * specified addr.
 564  *
 565  */
 566 static int goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 567 {
 568         struct goya_device *goya = hdev->asic_specific;
 569         int rc;
 570
 571         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 572                 return 0;
 573
 574         /* Inbound Region 1 - Bar 4 - Point to DDR */
 575         rc = goya_iatu_write(hdev, 0x314, lower_32_bits(addr));
 576         rc |= goya_iatu_write(hdev, 0x318, upper_32_bits(addr));
 577         rc |= goya_iatu_write(hdev, 0x300, 0);
 578         /* Enable + Bar match + match enable + Bar 4 */
 579         rc |= goya_iatu_write(hdev, 0x304, 0xC0080400);
 580
 581         /* Return the DBI window to the default location */
 582         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0);
 583         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI_32, 0);
 584
 585         if (rc) {
 586                 dev_err(hdev->dev, "failed to map DDR bar to 0x%08llx\n", addr);
 587                 return -EIO;
 588         }
 589
 590         if (goya)
 591                 goya->ddr_bar_cur_addr = addr;
 592
 593         return 0;
 594 }
 595
 596 /*
 597  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 598  *
 599  * @hdev: pointer to hl_device structure
 600  *
 601  * This is needed in case the firmware doesn't initialize the iATU
 602  *
 603  */
 604 static int goya_init_iatu(struct hl_device *hdev)
 605 {
 606         int rc;
 607
 608         /* Inbound Region 0 - Bar 0 - Point to SRAM_BASE_ADDR */
 609         rc  = goya_iatu_write(hdev, 0x114, lower_32_bits(SRAM_BASE_ADDR));
 610         rc |= goya_iatu_write(hdev, 0x118, upper_32_bits(SRAM_BASE_ADDR));
 611         rc |= goya_iatu_write(hdev, 0x100, 0);
 612         /* Enable + Bar match + match enable */
 613         rc |= goya_iatu_write(hdev, 0x104, 0xC0080000);
 614
 615         /* Inbound Region 1 - Bar 4 - Point to DDR */
 616         rc |= goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
 617
 618         /* Outbound Region 0 - Point to Host */
 619         rc |= goya_iatu_write(hdev, 0x008, lower_32_bits(HOST_PHYS_BASE));
 620         rc |= goya_iatu_write(hdev, 0x00C, upper_32_bits(HOST_PHYS_BASE));
 621         rc |= goya_iatu_write(hdev, 0x010,
 622                 lower_32_bits(HOST_PHYS_BASE + HOST_PHYS_SIZE - 1));
 623         rc |= goya_iatu_write(hdev, 0x014, 0);
 624         rc |= goya_iatu_write(hdev, 0x018, 0);
 625         rc |= goya_iatu_write(hdev, 0x020,
 626                 upper_32_bits(HOST_PHYS_BASE + HOST_PHYS_SIZE - 1));
 627         /* Increase region size */
 628         rc |= goya_iatu_write(hdev, 0x000, 0x00002000);
 629         /* Enable */
 630         rc |= goya_iatu_write(hdev, 0x004, 0x80000000);
 631
 632         /* Return the DBI window to the default location */
 633         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0);
 634         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI_32, 0);
 635
 636         if (rc)
 637                 return -EIO;
 638
 639         return 0;
 640 }
 641
 642 /*
 643  * goya_early_init - GOYA early initialization code
 644  *
 645  * @hdev: pointer to hl_device structure
 646  *
 647  * Verify PCI bars
 648  * Set DMA masks
 649  * PCI controller initialization
 650  * Map PCI bars
 651  *
 652  */
 653 static int goya_early_init(struct hl_device *hdev)
 654 {
 655         struct asic_fixed_properties *prop = &hdev->asic_prop;
 656         struct pci_dev *pdev = hdev->pdev;
 657         u32 val;
 658         int rc;
 659
 660         goya_get_fixed_properties(hdev);
 661
 662         /* Check BAR sizes */
 663         if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
 664                 dev_err(hdev->dev,
 665                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 666                         SRAM_CFG_BAR_ID,
 667                         (unsigned long long) pci_resource_len(pdev,
 668                                                         SRAM_CFG_BAR_ID),
 669                         CFG_BAR_SIZE);
 670                 return -ENODEV;
 671         }
 672
 673         if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
 674                 dev_err(hdev->dev,
 675                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 676                         MSIX_BAR_ID,
 677                         (unsigned long long) pci_resource_len(pdev,
 678                                                                 MSIX_BAR_ID),
 679                         MSIX_BAR_SIZE);
 680                 return -ENODEV;
 681         }
 682
 683         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 684
 685         /* set DMA mask for GOYA */
 686         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
 687         if (rc) {
 688                 dev_warn(hdev->dev, "Unable to set pci dma mask to 39 bits\n");
 689                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 690                 if (rc) {
 691                         dev_err(hdev->dev,
 692                                 "Unable to set pci dma mask to 32 bits\n");
 693                         return rc;
 694                 }
 695         }
 696
 697         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
 698         if (rc) {
 699                 dev_warn(hdev->dev,
 700                         "Unable to set pci consistent dma mask to 39 bits\n");
 701                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 702                 if (rc) {
 703                         dev_err(hdev->dev,
 704                                 "Unable to set pci consistent dma mask to 32 bits\n");
 705                         return rc;
 706                 }
 707         }
 708
 709         if (hdev->reset_pcilink)
 710                 goya_reset_link_through_bridge(hdev);
 711
 712         rc = pci_enable_device_mem(pdev);
 713         if (rc) {
 714                 dev_err(hdev->dev, "can't enable PCI device\n");
 715                 return rc;
 716         }
 717
 718         pci_set_master(pdev);
 719
 720         rc = goya_init_iatu(hdev);
 721         if (rc) {
 722                 dev_err(hdev->dev, "Failed to initialize iATU\n");
 723                 goto disable_device;
 724         }
 725
 726         rc = goya_pci_bars_map(hdev);
 727         if (rc) {
 728                 dev_err(hdev->dev, "Failed to initialize PCI BARS\n");
 729                 goto disable_device;
 730         }
 731
 732         if (!hdev->pldm) {
 733                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 734                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 735                         dev_warn(hdev->dev,
 736                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 737         }
 738
 739         return 0;
 740
 741 disable_device:
 742         pci_clear_master(pdev);
 743         pci_disable_device(pdev);
 744
 745         return rc;
 746 }
 747
 748 /*
 749  * goya_early_fini - GOYA early finalization code
 750  *
 751  * @hdev: pointer to hl_device structure
 752  *
 753  * Unmap PCI bars
 754  *
 755  */
 756 static int goya_early_fini(struct hl_device *hdev)
 757 {
 758         goya_pci_bars_unmap(hdev);
 759
 760         pci_clear_master(hdev->pdev);
 761         pci_disable_device(hdev->pdev);
 762
 763         return 0;
 764 }
 765
 766 /*
 767  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 768  *
 769  * @hdev: pointer to hl_device structure
 770  *
 771  */
 772 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 773 {
 774         struct asic_fixed_properties *prop = &hdev->asic_prop;
 775
 776         prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR);
 777         prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF);
 778         prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD);
 779         prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 780 }
 781
 782 /*
 783  * goya_late_init - GOYA late initialization code
 784  *
 785  * @hdev: pointer to hl_device structure
 786  *
 787  * Get ArmCP info and send message to CPU to enable PCI access
 788  */
 789 static int goya_late_init(struct hl_device *hdev)
 790 {
 791         struct asic_fixed_properties *prop = &hdev->asic_prop;
 792         struct goya_device *goya = hdev->asic_specific;
 793         int rc;
 794
 795         rc = goya->armcp_info_get(hdev);
 796         if (rc) {
 797                 dev_err(hdev->dev, "Failed to get armcp info\n");
 798                 return rc;
 799         }
 800
 801         /* Now that we have the DRAM size in ASIC prop, we need to check
 802          * its size and configure the DMA_IF DDR wrap protection (which is in
 803          * the MMU block) accordingly. The value is the log2 of the DRAM size
 804          */
 805         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 806
 807         rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS);
 808         if (rc) {
 809                 dev_err(hdev->dev, "Failed to enable PCI access from CPU\n");
 810                 return rc;
 811         }
 812
 813         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
 814                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
 815
 816         goya_fetch_psoc_frequency(hdev);
 817
 818         rc = goya_mmu_clear_pgt_range(hdev);
 819         if (rc) {
 820                 dev_err(hdev->dev, "Failed to clear MMU page tables range\n");
 821                 goto disable_pci_access;
 822         }
 823
 824         rc = goya_mmu_set_dram_default_page(hdev);
 825         if (rc) {
 826                 dev_err(hdev->dev, "Failed to set DRAM default page\n");
 827                 goto disable_pci_access;
 828         }
 829
 830         return 0;
 831
 832 disable_pci_access:
 833         goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
 834
 835         return rc;
 836 }
 837
 838 /*
 839  * goya_late_fini - GOYA late tear-down code
 840  *
 841  * @hdev: pointer to hl_device structure
 842  *
 843  * Free sensors allocated structures
 844  */
 845 void goya_late_fini(struct hl_device *hdev)
 846 {
 847         const struct hwmon_channel_info **channel_info_arr;
 848         int i = 0;
 849
 850         if (!hdev->hl_chip_info->info)
 851                 return;
 852
 853         channel_info_arr = hdev->hl_chip_info->info;
 854
 855         while (channel_info_arr[i]) {
 856                 kfree(channel_info_arr[i]->config);
 857                 kfree(channel_info_arr[i]);
 858                 i++;
 859         }
 860
 861         kfree(channel_info_arr);
 862
 863         hdev->hl_chip_info->info = NULL;
 864 }
 865
 866 /*
 867  * goya_sw_init - Goya software initialization code
 868  *
 869  * @hdev: pointer to hl_device structure
 870  *
 871  */
 872 static int goya_sw_init(struct hl_device *hdev)
 873 {
 874         struct goya_device *goya;
 875         int rc;
 876
 877         /* Allocate device structure */
 878         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 879         if (!goya)
 880                 return -ENOMEM;
 881
 882         goya->test_cpu_queue = goya_test_cpu_queue;
 883         goya->armcp_info_get = goya_armcp_info_get;
 884
 885         /* according to goya_init_iatu */
 886         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 887
 888         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 889         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 890         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 891
 892         hdev->asic_specific = goya;
 893
 894         /* Create DMA pool for small allocations */
 895         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 896                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 897         if (!hdev->dma_pool) {
 898                 dev_err(hdev->dev, "failed to create DMA pool\n");
 899                 rc = -ENOMEM;
 900                 goto free_goya_device;
 901         }
 902
 903         hdev->cpu_accessible_dma_mem =
 904                         hdev->asic_funcs->dma_alloc_coherent(hdev,
 905                                         CPU_ACCESSIBLE_MEM_SIZE,
 906                                         &hdev->cpu_accessible_dma_address,
 907                                         GFP_KERNEL | __GFP_ZERO);
 908
 909         if (!hdev->cpu_accessible_dma_mem) {
 910                 dev_err(hdev->dev,
 911                         "failed to allocate %d of dma memory for CPU accessible memory space\n",
 912                         CPU_ACCESSIBLE_MEM_SIZE);
 913                 rc = -ENOMEM;
 914                 goto free_dma_pool;
 915         }
 916
 917         hdev->cpu_accessible_dma_pool = gen_pool_create(CPU_PKT_SHIFT, -1);
 918         if (!hdev->cpu_accessible_dma_pool) {
 919                 dev_err(hdev->dev,
 920                         "Failed to create CPU accessible DMA pool\n");
 921                 rc = -ENOMEM;
 922                 goto free_cpu_pq_dma_mem;
 923         }
 924
 925         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
 926                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
 927                                 CPU_ACCESSIBLE_MEM_SIZE, -1);
 928         if (rc) {
 929                 dev_err(hdev->dev,
 930                         "Failed to add memory to CPU accessible DMA pool\n");
 931                 rc = -EFAULT;
 932                 goto free_cpu_pq_pool;
 933         }
 934
 935         spin_lock_init(&goya->hw_queues_lock);
 936
 937         return 0;
 938
 939 free_cpu_pq_pool:
 940         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 941 free_cpu_pq_dma_mem:
 942         hdev->asic_funcs->dma_free_coherent(hdev, CPU_ACCESSIBLE_MEM_SIZE,
 943                         hdev->cpu_accessible_dma_mem,
 944                         hdev->cpu_accessible_dma_address);
 945 free_dma_pool:
 946         dma_pool_destroy(hdev->dma_pool);
 947 free_goya_device:
 948         kfree(goya);
 949
 950         return rc;
 951 }
 952
 953 /*
 954  * goya_sw_fini - Goya software tear-down code
 955  *
 956  * @hdev: pointer to hl_device structure
 957  *
 958  */
 959 static int goya_sw_fini(struct hl_device *hdev)
 960 {
 961         struct goya_device *goya = hdev->asic_specific;
 962
 963         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 964
 965         hdev->asic_funcs->dma_free_coherent(hdev, CPU_ACCESSIBLE_MEM_SIZE,
 966                         hdev->cpu_accessible_dma_mem,
 967                         hdev->cpu_accessible_dma_address);
 968
 969         dma_pool_destroy(hdev->dma_pool);
 970
 971         kfree(goya);
 972
 973         return 0;
 974 }
 975
 976 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
 977                 dma_addr_t bus_address)
 978 {
 979         struct goya_device *goya = hdev->asic_specific;
 980         u32 mtr_base_lo, mtr_base_hi;
 981         u32 so_base_lo, so_base_hi;
 982         u32 gic_base_lo, gic_base_hi;
 983         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
 984
 985         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 986         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 987         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 988         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 989
 990         gic_base_lo =
 991                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 992         gic_base_hi =
 993                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 994
 995         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
 996         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
 997
 998         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
 999         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1000         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1001
1002         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1003         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1004         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1005         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1006         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1007         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1008         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1009                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1010
1011         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1012         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1013         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1014
1015         if (goya->hw_cap_initialized & HW_CAP_MMU)
1016                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1017         else
1018                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1019
1020         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN);
1021         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1022 }
1023
1024 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1025 {
1026         u32 gic_base_lo, gic_base_hi;
1027         u64 sob_addr;
1028         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1029
1030         gic_base_lo =
1031                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1032         gic_base_hi =
1033                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1034
1035         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1036         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1037         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1038                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1039
1040         if (dma_id)
1041                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1042                                 (dma_id - 1) * 4;
1043         else
1044                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1045
1046         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + reg_off, lower_32_bits(sob_addr));
1047         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1048         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1049 }
1050
1051 /*
1052  * goya_init_dma_qmans - Initialize QMAN DMA registers
1053  *
1054  * @hdev: pointer to hl_device structure
1055  *
1056  * Initialize the H/W registers of the QMAN DMA channels
1057  *
1058  */
1059 static void goya_init_dma_qmans(struct hl_device *hdev)
1060 {
1061         struct goya_device *goya = hdev->asic_specific;
1062         struct hl_hw_queue *q;
1063         dma_addr_t bus_address;
1064         int i;
1065
1066         if (goya->hw_cap_initialized & HW_CAP_DMA)
1067                 return;
1068
1069         q = &hdev->kernel_queues[0];
1070
1071         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1072                 bus_address = q->bus_address +
1073                                 hdev->asic_prop.host_phys_base_address;
1074
1075                 goya_init_dma_qman(hdev, i, bus_address);
1076                 goya_init_dma_ch(hdev, i);
1077         }
1078
1079         goya->hw_cap_initialized |= HW_CAP_DMA;
1080 }
1081
1082 /*
1083  * goya_disable_external_queues - Disable external queues
1084  *
1085  * @hdev: pointer to hl_device structure
1086  *
1087  */
1088 static void goya_disable_external_queues(struct hl_device *hdev)
1089 {
1090         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1091         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1092         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1093         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1094         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1095 }
1096
1097 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1098                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
1099 {
1100         int rc;
1101         u32 status;
1102
1103         /* use the values of TPC0 as they are all the same*/
1104
1105         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1106
1107         status = RREG32(cp_sts_reg);
1108         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1109                 rc = hl_poll_timeout(
1110                         hdev,
1111                         cp_sts_reg,
1112                         status,
1113                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1114                         1000,
1115                         QMAN_FENCE_TIMEOUT_USEC);
1116
1117                 /* if QMAN is stuck in fence no need to check for stop */
1118                 if (rc)
1119                         return 0;
1120         }
1121
1122         rc = hl_poll_timeout(
1123                 hdev,
1124                 glbl_sts0_reg,
1125                 status,
1126                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1127                 1000,
1128                 QMAN_STOP_TIMEOUT_USEC);
1129
1130         if (rc) {
1131                 dev_err(hdev->dev,
1132                         "Timeout while waiting for QMAN to stop\n");
1133                 return -EINVAL;
1134         }
1135
1136         return 0;
1137 }
1138
1139 /*
1140  * goya_stop_external_queues - Stop external queues
1141  *
1142  * @hdev: pointer to hl_device structure
1143  *
1144  * Returns 0 on success
1145  *
1146  */
1147 static int goya_stop_external_queues(struct hl_device *hdev)
1148 {
1149         int rc, retval = 0;
1150
1151         rc = goya_stop_queue(hdev,
1152                         mmDMA_QM_0_GLBL_CFG1,
1153                         mmDMA_QM_0_CP_STS,
1154                         mmDMA_QM_0_GLBL_STS0);
1155
1156         if (rc) {
1157                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1158                 retval = -EIO;
1159         }
1160
1161         rc = goya_stop_queue(hdev,
1162                         mmDMA_QM_1_GLBL_CFG1,
1163                         mmDMA_QM_1_CP_STS,
1164                         mmDMA_QM_1_GLBL_STS0);
1165
1166         if (rc) {
1167                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1168                 retval = -EIO;
1169         }
1170
1171         rc = goya_stop_queue(hdev,
1172                         mmDMA_QM_2_GLBL_CFG1,
1173                         mmDMA_QM_2_CP_STS,
1174                         mmDMA_QM_2_GLBL_STS0);
1175
1176         if (rc) {
1177                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1178                 retval = -EIO;
1179         }
1180
1181         rc = goya_stop_queue(hdev,
1182                         mmDMA_QM_3_GLBL_CFG1,
1183                         mmDMA_QM_3_CP_STS,
1184                         mmDMA_QM_3_GLBL_STS0);
1185
1186         if (rc) {
1187                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1188                 retval = -EIO;
1189         }
1190
1191         rc = goya_stop_queue(hdev,
1192                         mmDMA_QM_4_GLBL_CFG1,
1193                         mmDMA_QM_4_CP_STS,
1194                         mmDMA_QM_4_GLBL_STS0);
1195
1196         if (rc) {
1197                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1198                 retval = -EIO;
1199         }
1200
1201         return retval;
1202 }
1203
1204 /*
1205  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1206  *
1207  * @hdev: pointer to hl_device structure
1208  *
1209  * Returns 0 on success
1210  *
1211  */
1212 static int goya_init_cpu_queues(struct hl_device *hdev)
1213 {
1214         struct goya_device *goya = hdev->asic_specific;
1215         struct hl_eq *eq;
1216         dma_addr_t bus_address;
1217         u32 status;
1218         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1219         int err;
1220
1221         if (!hdev->cpu_queues_enable)
1222                 return 0;
1223
1224         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1225                 return 0;
1226
1227         eq = &hdev->event_queue;
1228
1229         bus_address = cpu_pq->bus_address +
1230                         hdev->asic_prop.host_phys_base_address;
1231         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_0, lower_32_bits(bus_address));
1232         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_1, upper_32_bits(bus_address));
1233
1234         bus_address = eq->bus_address + hdev->asic_prop.host_phys_base_address;
1235         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_2, lower_32_bits(bus_address));
1236         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_3, upper_32_bits(bus_address));
1237
1238         bus_address = hdev->cpu_accessible_dma_address +
1239                         hdev->asic_prop.host_phys_base_address;
1240         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_8, lower_32_bits(bus_address));
1241         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_9, upper_32_bits(bus_address));
1242
1243         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_5, HL_QUEUE_SIZE_IN_BYTES);
1244         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_4, HL_EQ_SIZE_IN_BYTES);
1245         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_10, CPU_ACCESSIBLE_MEM_SIZE);
1246
1247         /* Used for EQ CI */
1248         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, 0);
1249
1250         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1251
1252         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_7, PQ_INIT_STATUS_READY_FOR_CP);
1253
1254         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1255                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1256
1257         err = hl_poll_timeout(
1258                 hdev,
1259                 mmPSOC_GLOBAL_CONF_SCRATCHPAD_7,
1260                 status,
1261                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1262                 1000,
1263                 GOYA_CPU_TIMEOUT_USEC);
1264
1265         if (err) {
1266                 dev_err(hdev->dev,
1267                         "Failed to communicate with ARM CPU (ArmCP timeout)\n");
1268                 return -EIO;
1269         }
1270
1271         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1272         return 0;
1273 }
1274
1275 static void goya_set_pll_refclk(struct hl_device *hdev)
1276 {
1277         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1278         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1279         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1280         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1281
1282         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1283         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1284         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1285         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1286
1287         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1288         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1289         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1290         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1291
1292         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1293         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1294         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1295         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1296
1297         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1298         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1299         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1300         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1301
1302         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1303         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1304         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1305         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1306
1307         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1308         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1309         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1310         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1311 }
1312
1313 static void goya_disable_clk_rlx(struct hl_device *hdev)
1314 {
1315         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1316         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1317 }
1318
1319 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1320 {
1321         u64 tpc_eml_address;
1322         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1323         int err, slm_index;
1324
1325         tpc_offset = tpc_id * 0x40000;
1326         tpc_eml_offset = tpc_id * 0x200000;
1327         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1328         tpc_slm_offset = tpc_eml_address + 0x100000;
1329
1330         /*
1331          * Workaround for Bug H2 #2443 :
1332          * "TPC SB is not initialized on chip reset"
1333          */
1334
1335         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1336         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1337                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1338                         tpc_id);
1339
1340         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1341
1342         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1343         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1344         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1345         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1346         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1347         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1348         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1349         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1350         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1351         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1352
1353         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1354                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1355
1356         err = hl_poll_timeout(
1357                 hdev,
1358                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1359                 val,
1360                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1361                 1000,
1362                 HL_DEVICE_TIMEOUT_USEC);
1363
1364         if (err)
1365                 dev_err(hdev->dev,
1366                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1367
1368         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1369                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1370
1371         msleep(GOYA_RESET_WAIT_MSEC);
1372
1373         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1374                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1375
1376         msleep(GOYA_RESET_WAIT_MSEC);
1377
1378         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1379                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1380
1381         val = RREG32(tpc_slm_offset);
1382 }
1383
1384 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1385 {
1386         struct goya_device *goya = hdev->asic_specific;
1387         int i;
1388
1389         if (hdev->pldm)
1390                 return;
1391
1392         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1393                 return;
1394
1395         /* Workaround for H2 #2443 */
1396
1397         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1398                 _goya_tpc_mbist_workaround(hdev, i);
1399
1400         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1401 }
1402
1403 /*
1404  * goya_init_golden_registers - Initialize golden registers
1405  *
1406  * @hdev: pointer to hl_device structure
1407  *
1408  * Initialize the H/W registers of the device
1409  *
1410  */
1411 static void goya_init_golden_registers(struct hl_device *hdev)
1412 {
1413         struct goya_device *goya = hdev->asic_specific;
1414         u32 polynom[10], tpc_intr_mask, offset;
1415         int i;
1416
1417         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1418                 return;
1419
1420         polynom[0] = 0x00020080;
1421         polynom[1] = 0x00401000;
1422         polynom[2] = 0x00200800;
1423         polynom[3] = 0x00002000;
1424         polynom[4] = 0x00080200;
1425         polynom[5] = 0x00040100;
1426         polynom[6] = 0x00100400;
1427         polynom[7] = 0x00004000;
1428         polynom[8] = 0x00010000;
1429         polynom[9] = 0x00008000;
1430
1431         /* Mask all arithmetic interrupts from TPC */
1432         tpc_intr_mask = 0x7FFF;
1433
1434         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1435                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1436                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1437                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1438                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1439                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1440
1441                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1442                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1443                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1444                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1445                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1446
1447
1448                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1449                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1450                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1451                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1452                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1453
1454                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1455                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1456                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1457                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1458                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1459
1460                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1461                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1462                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1463                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1464                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1465
1466                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1467                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1468                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1469                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1470                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1471         }
1472
1473         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1474         WREG32(mmMME_AGU, 0x0f0f0f10);
1475         WREG32(mmMME_SEI_MASK, ~0x0);
1476
1477         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1478         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1479         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1480         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1481         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1482         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1483         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1484         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1485         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1486         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1487         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1488         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1489         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1490         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1491         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1492         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1493         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1494         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1495         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1496         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1497         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1498         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1499         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1500         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1501         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1502         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1503         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1504         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1505         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1506         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1507         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1508         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1509         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1510         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1511         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1512         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1513         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1514         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1515         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1516         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1517         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1518         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1519         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1520         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1521         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1522         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1523         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1524         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1525         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1526         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1527         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1528         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1529         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1530         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1531         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1532         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1533         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1534         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1535         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1536         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1537         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1538         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1539         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1540         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1541         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1542         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1543         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1544         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1545         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1546         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1547         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1548         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1549         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1550         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1551         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1552         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1553         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1554         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1555         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1556         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1557         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1558         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1559         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1560         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1561
1562         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1563         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1564         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1565         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1566         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1567         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1568         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1569         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1570         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1571         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1572         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1573         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1574
1575         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1576         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1577         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1578         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1579         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1580         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1581         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1582         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1583         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1584         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1585         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1586         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1587
1588         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1589         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1590         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1591         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1592         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1593         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1594         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1595         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1596         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1597         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1598         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1599         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1600
1601         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1602         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1603         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1604         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1605         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1606         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1607         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1608         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1609         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1610         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1611         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1612         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1613
1614         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1615         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1616         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1617         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1618         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1619         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1620         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1621         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1622         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1623         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1624         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1625         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1626
1627         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1628         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1629         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1630         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1631         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1632         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1633         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1634         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1635         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1636         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1637         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1638         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1639
1640         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1641                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1642                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1643                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1644                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1645                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1646                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1647
1648                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1649                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1650                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1651                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1652                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1653                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1654                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1655                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1656
1657                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1658                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1659         }
1660
1661         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1662                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1663                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1664                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1665                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1666         }
1667
1668         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1669                 /*
1670                  * Workaround for Bug H2 #2441 :
1671                  * "ST.NOP set trace event illegal opcode"
1672                  */
1673                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1674
1675                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1676                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1677                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1678                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1679         }
1680
1681         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1682         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1683                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1684
1685         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1686         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1687                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1688
1689         /*
1690          * Workaround for H2 #HW-23 bug
1691          * Set DMA max outstanding read requests to 240 on DMA CH 1. Set it
1692          * to 16 on KMD DMA
1693          * We need to limit only these DMAs because the user can only read
1694          * from Host using DMA CH 1
1695          */
1696         WREG32(mmDMA_CH_0_CFG0, 0x0fff0010);
1697         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1698
1699         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1700 }
1701
1702 static void goya_init_mme_qman(struct hl_device *hdev)
1703 {
1704         u32 mtr_base_lo, mtr_base_hi;
1705         u32 so_base_lo, so_base_hi;
1706         u32 gic_base_lo, gic_base_hi;
1707         u64 qman_base_addr;
1708
1709         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1710         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1711         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1712         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1713
1714         gic_base_lo =
1715                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1716         gic_base_hi =
1717                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1718
1719         qman_base_addr = hdev->asic_prop.sram_base_address +
1720                                 MME_QMAN_BASE_OFFSET;
1721
1722         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1723         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1724         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1725         WREG32(mmMME_QM_PQ_PI, 0);
1726         WREG32(mmMME_QM_PQ_CI, 0);
1727         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1728         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1729         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1730         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1731
1732         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1733         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1734         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1735         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1736
1737         /* QMAN CQ has 8 cache lines */
1738         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1739
1740         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1741         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1742
1743         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1744
1745         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1746
1747         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1748
1749         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1750 }
1751
1752 static void goya_init_mme_cmdq(struct hl_device *hdev)
1753 {
1754         u32 mtr_base_lo, mtr_base_hi;
1755         u32 so_base_lo, so_base_hi;
1756         u32 gic_base_lo, gic_base_hi;
1757         u64 qman_base_addr;
1758
1759         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1760         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1761         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1762         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1763
1764         gic_base_lo =
1765                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1766         gic_base_hi =
1767                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1768
1769         qman_base_addr = hdev->asic_prop.sram_base_address +
1770                                 MME_QMAN_BASE_OFFSET;
1771
1772         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1773         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1774         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1775         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1776
1777         /* CMDQ CQ has 20 cache lines */
1778         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1779
1780         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1781         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1782
1783         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1784
1785         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1786
1787         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1788
1789         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1790 }
1791
1792 static void goya_init_mme_qmans(struct hl_device *hdev)
1793 {
1794         struct goya_device *goya = hdev->asic_specific;
1795         u32 so_base_lo, so_base_hi;
1796
1797         if (goya->hw_cap_initialized & HW_CAP_MME)
1798                 return;
1799
1800         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1801         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1802
1803         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1804         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1805
1806         goya_init_mme_qman(hdev);
1807         goya_init_mme_cmdq(hdev);
1808
1809         goya->hw_cap_initialized |= HW_CAP_MME;
1810 }
1811
1812 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1813 {
1814         u32 mtr_base_lo, mtr_base_hi;
1815         u32 so_base_lo, so_base_hi;
1816         u32 gic_base_lo, gic_base_hi;
1817         u64 qman_base_addr;
1818         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1819
1820         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1821         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1822         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1823         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1824
1825         gic_base_lo =
1826                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1827         gic_base_hi =
1828                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1829
1830         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1831
1832         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1833         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1834         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1835         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1836         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1837         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1838         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1839         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1840         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1841
1842         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1843         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1844         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1845         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1846
1847         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1848
1849         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1850         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1851
1852         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1853                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1854
1855         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1856
1857         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1858
1859         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1860 }
1861
1862 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1863 {
1864         u32 mtr_base_lo, mtr_base_hi;
1865         u32 so_base_lo, so_base_hi;
1866         u32 gic_base_lo, gic_base_hi;
1867         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1868
1869         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1870         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1871         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1872         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1873
1874         gic_base_lo =
1875                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1876         gic_base_hi =
1877                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1878
1879         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1880         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1881         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1882         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1883
1884         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1885
1886         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1887         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1888
1889         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1890                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1891
1892         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1893
1894         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1895
1896         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1897 }
1898
1899 static void goya_init_tpc_qmans(struct hl_device *hdev)
1900 {
1901         struct goya_device *goya = hdev->asic_specific;
1902         u32 so_base_lo, so_base_hi;
1903         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1904                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1905         int i;
1906
1907         if (goya->hw_cap_initialized & HW_CAP_TPC)
1908                 return;
1909
1910         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1911         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1912
1913         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1914                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1915                                 so_base_lo);
1916                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1917                                 so_base_hi);
1918         }
1919
1920         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1921         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1922         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1923         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1924         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1925         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1926         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1927         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1928
1929         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1930                 goya_init_tpc_cmdq(hdev, i);
1931
1932         goya->hw_cap_initialized |= HW_CAP_TPC;
1933 }
1934
1935 /*
1936  * goya_disable_internal_queues - Disable internal queues
1937  *
1938  * @hdev: pointer to hl_device structure
1939  *
1940  */
1941 static void goya_disable_internal_queues(struct hl_device *hdev)
1942 {
1943         WREG32(mmMME_QM_GLBL_CFG0, 0);
1944         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1945
1946         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
1947         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
1948
1949         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
1950         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
1951
1952         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
1953         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
1954
1955         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
1956         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
1957
1958         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
1959         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
1960
1961         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
1962         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
1963
1964         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
1965         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
1966
1967         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
1968         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
1969 }
1970
1971 /*
1972  * goya_stop_internal_queues - Stop internal queues
1973  *
1974  * @hdev: pointer to hl_device structure
1975  *
1976  * Returns 0 on success
1977  *
1978  */
1979 static int goya_stop_internal_queues(struct hl_device *hdev)
1980 {
1981         int rc, retval = 0;
1982
1983         /*
1984          * Each queue (QMAN) is a separate H/W logic. That means that each
1985          * QMAN can be stopped independently and failure to stop one does NOT
1986          * mandate we should not try to stop other QMANs
1987          */
1988
1989         rc = goya_stop_queue(hdev,
1990                         mmMME_QM_GLBL_CFG1,
1991                         mmMME_QM_CP_STS,
1992                         mmMME_QM_GLBL_STS0);
1993
1994         if (rc) {
1995                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
1996                 retval = -EIO;
1997         }
1998
1999         rc = goya_stop_queue(hdev,
2000                         mmMME_CMDQ_GLBL_CFG1,
2001                         mmMME_CMDQ_CP_STS,
2002                         mmMME_CMDQ_GLBL_STS0);
2003
2004         if (rc) {
2005                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2006                 retval = -EIO;
2007         }
2008
2009         rc = goya_stop_queue(hdev,
2010                         mmTPC0_QM_GLBL_CFG1,
2011                         mmTPC0_QM_CP_STS,
2012                         mmTPC0_QM_GLBL_STS0);
2013
2014         if (rc) {
2015                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2016                 retval = -EIO;
2017         }
2018
2019         rc = goya_stop_queue(hdev,
2020                         mmTPC0_CMDQ_GLBL_CFG1,
2021                         mmTPC0_CMDQ_CP_STS,
2022                         mmTPC0_CMDQ_GLBL_STS0);
2023
2024         if (rc) {
2025                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2026                 retval = -EIO;
2027         }
2028
2029         rc = goya_stop_queue(hdev,
2030                         mmTPC1_QM_GLBL_CFG1,
2031                         mmTPC1_QM_CP_STS,
2032                         mmTPC1_QM_GLBL_STS0);
2033
2034         if (rc) {
2035                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2036                 retval = -EIO;
2037         }
2038
2039         rc = goya_stop_queue(hdev,
2040                         mmTPC1_CMDQ_GLBL_CFG1,
2041                         mmTPC1_CMDQ_CP_STS,
2042                         mmTPC1_CMDQ_GLBL_STS0);
2043
2044         if (rc) {
2045                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2046                 retval = -EIO;
2047         }
2048
2049         rc = goya_stop_queue(hdev,
2050                         mmTPC2_QM_GLBL_CFG1,
2051                         mmTPC2_QM_CP_STS,
2052                         mmTPC2_QM_GLBL_STS0);
2053
2054         if (rc) {
2055                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2056                 retval = -EIO;
2057         }
2058
2059         rc = goya_stop_queue(hdev,
2060                         mmTPC2_CMDQ_GLBL_CFG1,
2061                         mmTPC2_CMDQ_CP_STS,
2062                         mmTPC2_CMDQ_GLBL_STS0);
2063
2064         if (rc) {
2065                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2066                 retval = -EIO;
2067         }
2068
2069         rc = goya_stop_queue(hdev,
2070                         mmTPC3_QM_GLBL_CFG1,
2071                         mmTPC3_QM_CP_STS,
2072                         mmTPC3_QM_GLBL_STS0);
2073
2074         if (rc) {
2075                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2076                 retval = -EIO;
2077         }
2078
2079         rc = goya_stop_queue(hdev,
2080                         mmTPC3_CMDQ_GLBL_CFG1,
2081                         mmTPC3_CMDQ_CP_STS,
2082                         mmTPC3_CMDQ_GLBL_STS0);
2083
2084         if (rc) {
2085                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2086                 retval = -EIO;
2087         }
2088
2089         rc = goya_stop_queue(hdev,
2090                         mmTPC4_QM_GLBL_CFG1,
2091                         mmTPC4_QM_CP_STS,
2092                         mmTPC4_QM_GLBL_STS0);
2093
2094         if (rc) {
2095                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2096                 retval = -EIO;
2097         }
2098
2099         rc = goya_stop_queue(hdev,
2100                         mmTPC4_CMDQ_GLBL_CFG1,
2101                         mmTPC4_CMDQ_CP_STS,
2102                         mmTPC4_CMDQ_GLBL_STS0);
2103
2104         if (rc) {
2105                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2106                 retval = -EIO;
2107         }
2108
2109         rc = goya_stop_queue(hdev,
2110                         mmTPC5_QM_GLBL_CFG1,
2111                         mmTPC5_QM_CP_STS,
2112                         mmTPC5_QM_GLBL_STS0);
2113
2114         if (rc) {
2115                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2116                 retval = -EIO;
2117         }
2118
2119         rc = goya_stop_queue(hdev,
2120                         mmTPC5_CMDQ_GLBL_CFG1,
2121                         mmTPC5_CMDQ_CP_STS,
2122                         mmTPC5_CMDQ_GLBL_STS0);
2123
2124         if (rc) {
2125                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2126                 retval = -EIO;
2127         }
2128
2129         rc = goya_stop_queue(hdev,
2130                         mmTPC6_QM_GLBL_CFG1,
2131                         mmTPC6_QM_CP_STS,
2132                         mmTPC6_QM_GLBL_STS0);
2133
2134         if (rc) {
2135                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2136                 retval = -EIO;
2137         }
2138
2139         rc = goya_stop_queue(hdev,
2140                         mmTPC6_CMDQ_GLBL_CFG1,
2141                         mmTPC6_CMDQ_CP_STS,
2142                         mmTPC6_CMDQ_GLBL_STS0);
2143
2144         if (rc) {
2145                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2146                 retval = -EIO;
2147         }
2148
2149         rc = goya_stop_queue(hdev,
2150                         mmTPC7_QM_GLBL_CFG1,
2151                         mmTPC7_QM_CP_STS,
2152                         mmTPC7_QM_GLBL_STS0);
2153
2154         if (rc) {
2155                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2156                 retval = -EIO;
2157         }
2158
2159         rc = goya_stop_queue(hdev,
2160                         mmTPC7_CMDQ_GLBL_CFG1,
2161                         mmTPC7_CMDQ_CP_STS,
2162                         mmTPC7_CMDQ_GLBL_STS0);
2163
2164         if (rc) {
2165                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2166                 retval = -EIO;
2167         }
2168
2169         return retval;
2170 }
2171
2172 static void goya_dma_stall(struct hl_device *hdev)
2173 {
2174         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2175         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2176         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2177         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2178         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2179 }
2180
2181 static void goya_tpc_stall(struct hl_device *hdev)
2182 {
2183         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2184         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2185         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2186         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2187         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2188         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2189         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2190         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2191 }
2192
2193 static void goya_mme_stall(struct hl_device *hdev)
2194 {
2195         WREG32(mmMME_STALL, 0xFFFFFFFF);
2196 }
2197
2198 static int goya_enable_msix(struct hl_device *hdev)
2199 {
2200         struct goya_device *goya = hdev->asic_specific;
2201         int cq_cnt = hdev->asic_prop.completion_queues_count;
2202         int rc, i, irq_cnt_init, irq;
2203
2204         if (goya->hw_cap_initialized & HW_CAP_MSIX)
2205                 return 0;
2206
2207         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2208                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2209         if (rc < 0) {
2210                 dev_err(hdev->dev,
2211                         "MSI-X: Failed to enable support -- %d/%d\n",
2212                         GOYA_MSIX_ENTRIES, rc);
2213                 return rc;
2214         }
2215
2216         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2217                 irq = pci_irq_vector(hdev->pdev, i);
2218                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2219                                 &hdev->completion_queue[i]);
2220                 if (rc) {
2221                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2222                         goto free_irqs;
2223                 }
2224         }
2225
2226         irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
2227
2228         rc = request_irq(irq, hl_irq_handler_eq, 0,
2229                         goya_irq_name[EVENT_QUEUE_MSIX_IDX],
2230                         &hdev->event_queue);
2231         if (rc) {
2232                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2233                 goto free_irqs;
2234         }
2235
2236         goya->hw_cap_initialized |= HW_CAP_MSIX;
2237         return 0;
2238
2239 free_irqs:
2240         for (i = 0 ; i < irq_cnt_init ; i++)
2241                 free_irq(pci_irq_vector(hdev->pdev, i),
2242                         &hdev->completion_queue[i]);
2243
2244         pci_free_irq_vectors(hdev->pdev);
2245         return rc;
2246 }
2247
2248 static void goya_sync_irqs(struct hl_device *hdev)
2249 {
2250         struct goya_device *goya = hdev->asic_specific;
2251         int i;
2252
2253         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2254                 return;
2255
2256         /* Wait for all pending IRQs to be finished */
2257         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2258                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2259
2260         synchronize_irq(pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX));
2261 }
2262
2263 static void goya_disable_msix(struct hl_device *hdev)
2264 {
2265         struct goya_device *goya = hdev->asic_specific;
2266         int i, irq;
2267
2268         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2269                 return;
2270
2271         goya_sync_irqs(hdev);
2272
2273         irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
2274         free_irq(irq, &hdev->event_queue);
2275
2276         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2277                 irq = pci_irq_vector(hdev->pdev, i);
2278                 free_irq(irq, &hdev->completion_queue[i]);
2279         }
2280
2281         pci_free_irq_vectors(hdev->pdev);
2282
2283         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2284 }
2285
2286 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
2287 {
2288         u32 wait_timeout_ms, cpu_timeout_ms;
2289
2290         dev_info(hdev->dev,
2291                 "Halting compute engines and disabling interrupts\n");
2292
2293         if (hdev->pldm) {
2294                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2295                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2296         } else {
2297                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2298                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2299         }
2300
2301         if (hard_reset) {
2302                 /*
2303                  * I don't know what is the state of the CPU so make sure it is
2304                  * stopped in any means necessary
2305                  */
2306                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2307                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2308                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2309                 msleep(cpu_timeout_ms);
2310         }
2311
2312         goya_stop_external_queues(hdev);
2313         goya_stop_internal_queues(hdev);
2314
2315         msleep(wait_timeout_ms);
2316
2317         goya_dma_stall(hdev);
2318         goya_tpc_stall(hdev);
2319         goya_mme_stall(hdev);
2320
2321         msleep(wait_timeout_ms);
2322
2323         goya_disable_external_queues(hdev);
2324         goya_disable_internal_queues(hdev);
2325
2326         if (hard_reset)
2327                 goya_disable_msix(hdev);
2328         else
2329                 goya_sync_irqs(hdev);
2330 }
2331
2332 /*
2333  * goya_push_fw_to_device - Push FW code to device
2334  *
2335  * @hdev: pointer to hl_device structure
2336  *
2337  * Copy fw code from firmware file to device memory.
2338  * Returns 0 on success
2339  *
2340  */
2341 static int goya_push_fw_to_device(struct hl_device *hdev, const char *fw_name,
2342                                         void __iomem *dst)
2343 {
2344         const struct firmware *fw;
2345         const u64 *fw_data;
2346         size_t fw_size, i;
2347         int rc;
2348
2349         rc = request_firmware(&fw, fw_name, hdev->dev);
2350
2351         if (rc) {
2352                 dev_err(hdev->dev, "Failed to request %s\n", fw_name);
2353                 goto out;
2354         }
2355
2356         fw_size = fw->size;
2357         if ((fw_size % 4) != 0) {
2358                 dev_err(hdev->dev, "illegal %s firmware size %zu\n",
2359                         fw_name, fw_size);
2360                 rc = -EINVAL;
2361                 goto out;
2362         }
2363
2364         dev_dbg(hdev->dev, "%s firmware size == %zu\n", fw_name, fw_size);
2365
2366         fw_data = (const u64 *) fw->data;
2367
2368         if ((fw->size % 8) != 0)
2369                 fw_size -= 8;
2370
2371         for (i = 0 ; i < fw_size ; i += 8, fw_data++, dst += 8) {
2372                 if (!(i & (0x80000 - 1))) {
2373                         dev_dbg(hdev->dev,
2374                                 "copied so far %zu out of %zu for %s firmware",
2375                                 i, fw_size, fw_name);
2376                         usleep_range(20, 100);
2377                 }
2378
2379                 writeq(*fw_data, dst);
2380         }
2381
2382         if ((fw->size % 8) != 0)
2383                 writel(*(const u32 *) fw_data, dst);
2384
2385 out:
2386         release_firmware(fw);
2387         return rc;
2388 }
2389
2390 static int goya_pldm_init_cpu(struct hl_device *hdev)
2391 {
2392         char fw_name[200];
2393         void __iomem *dst;
2394         u32 val, unit_rst_val;
2395         int rc;
2396
2397         /* Must initialize SRAM scrambler before pushing u-boot to SRAM */
2398         goya_init_golden_registers(hdev);
2399
2400         /* Put ARM cores into reset */
2401         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT);
2402         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2403
2404         /* Reset the CA53 MACRO */
2405         unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2406         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET);
2407         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2408         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val);
2409         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2410
2411         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-u-boot.bin");
2412         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET;
2413         rc = goya_push_fw_to_device(hdev, fw_name, dst);
2414         if (rc)
2415                 return rc;
2416
2417         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb");
2418         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2419         rc = goya_push_fw_to_device(hdev, fw_name, dst);
2420         if (rc)
2421                 return rc;
2422
2423         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2424         WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA);
2425
2426         WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0,
2427                 lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2428         WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0,
2429                 upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2430
2431         /* Release ARM core 0 from reset */
2432         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL,
2433                                         CPU_RESET_CORE0_DEASSERT);
2434         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2435
2436         return 0;
2437 }
2438
2439 /*
2440  * FW component passes an offset from SRAM_BASE_ADDR in SCRATCHPAD_xx.
2441  * The version string should be located by that offset.
2442  */
2443 static void goya_read_device_fw_version(struct hl_device *hdev,
2444                                         enum goya_fw_component fwc)
2445 {
2446         const char *name;
2447         u32 ver_off;
2448         char *dest;
2449
2450         switch (fwc) {
2451         case FW_COMP_UBOOT:
2452                 ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_29);
2453                 dest = hdev->asic_prop.uboot_ver;
2454                 name = "U-Boot";
2455                 break;
2456         case FW_COMP_PREBOOT:
2457                 ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_28);
2458                 dest = hdev->asic_prop.preboot_ver;
2459                 name = "Preboot";
2460                 break;
2461         default:
2462                 dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
2463                 return;
2464         }
2465
2466         ver_off &= ~((u32)SRAM_BASE_ADDR);
2467
2468         if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) {
2469                 memcpy_fromio(dest, hdev->pcie_bar[SRAM_CFG_BAR_ID] + ver_off,
2470                                                         VERSION_MAX_LEN);
2471         } else {
2472                 dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n",
2473                                                                 name, ver_off);
2474                 strcpy(dest, "unavailable");
2475         }
2476 }
2477
2478 static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout)
2479 {
2480         struct goya_device *goya = hdev->asic_specific;
2481         char fw_name[200];
2482         void __iomem *dst;
2483         u32 status;
2484         int rc;
2485
2486         if (!hdev->cpu_enable)
2487                 return 0;
2488
2489         if (goya->hw_cap_initialized & HW_CAP_CPU)
2490                 return 0;
2491
2492         /*
2493          * Before pushing u-boot/linux to device, need to set the ddr bar to
2494          * base address of dram
2495          */
2496         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2497         if (rc) {
2498                 dev_err(hdev->dev,
2499                         "failed to map DDR bar to DRAM base address\n");
2500                 return rc;
2501         }
2502
2503         if (hdev->pldm) {
2504                 rc = goya_pldm_init_cpu(hdev);
2505                 if (rc)
2506                         return rc;
2507
2508                 goto out;
2509         }
2510
2511         /* Make sure CPU boot-loader is running */
2512         rc = hl_poll_timeout(
2513                 hdev,
2514                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2515                 status,
2516                 (status == CPU_BOOT_STATUS_DRAM_RDY) ||
2517                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2518                 10000,
2519                 cpu_timeout);
2520
2521         if (rc) {
2522                 dev_err(hdev->dev, "Error in ARM u-boot!");
2523                 switch (status) {
2524                 case CPU_BOOT_STATUS_NA:
2525                         dev_err(hdev->dev,
2526                                 "ARM status %d - BTL did NOT run\n", status);
2527                         break;
2528                 case CPU_BOOT_STATUS_IN_WFE:
2529                         dev_err(hdev->dev,
2530                                 "ARM status %d - Inside WFE loop\n", status);
2531                         break;
2532                 case CPU_BOOT_STATUS_IN_BTL:
2533                         dev_err(hdev->dev,
2534                                 "ARM status %d - Stuck in BTL\n", status);
2535                         break;
2536                 case CPU_BOOT_STATUS_IN_PREBOOT:
2537                         dev_err(hdev->dev,
2538                                 "ARM status %d - Stuck in Preboot\n", status);
2539                         break;
2540                 case CPU_BOOT_STATUS_IN_SPL:
2541                         dev_err(hdev->dev,
2542                                 "ARM status %d - Stuck in SPL\n", status);
2543                         break;
2544                 case CPU_BOOT_STATUS_IN_UBOOT:
2545                         dev_err(hdev->dev,
2546                                 "ARM status %d - Stuck in u-boot\n", status);
2547                         break;
2548                 case CPU_BOOT_STATUS_DRAM_INIT_FAIL:
2549                         dev_err(hdev->dev,
2550                                 "ARM status %d - DDR initialization failed\n",
2551                                 status);
2552                         break;
2553                 default:
2554                         dev_err(hdev->dev,
2555                                 "ARM status %d - Invalid status code\n",
2556                                 status);
2557                         break;
2558                 }
2559                 return -EIO;
2560         }
2561
2562         /* Read U-Boot version now in case we will later fail */
2563         goya_read_device_fw_version(hdev, FW_COMP_UBOOT);
2564         goya_read_device_fw_version(hdev, FW_COMP_PREBOOT);
2565
2566         if (status == CPU_BOOT_STATUS_SRAM_AVAIL)
2567                 goto out;
2568
2569         if (!hdev->fw_loading) {
2570                 dev_info(hdev->dev, "Skip loading FW\n");
2571                 goto out;
2572         }
2573
2574         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb");
2575         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2576         rc = goya_push_fw_to_device(hdev, fw_name, dst);
2577         if (rc)
2578                 return rc;
2579
2580         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2581
2582         rc = hl_poll_timeout(
2583                 hdev,
2584                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2585                 status,
2586                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2587                 10000,
2588                 cpu_timeout);
2589
2590         if (rc) {
2591                 if (status == CPU_BOOT_STATUS_FIT_CORRUPTED)
2592                         dev_err(hdev->dev,
2593                                 "ARM u-boot reports FIT image is corrupted\n");
2594                 else
2595                         dev_err(hdev->dev,
2596                                 "ARM Linux failed to load, %d\n", status);
2597                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA);
2598                 return -EIO;
2599         }
2600
2601         dev_info(hdev->dev, "Successfully loaded firmware to device\n");
2602
2603 out:
2604         goya->hw_cap_initialized |= HW_CAP_CPU;
2605
2606         return 0;
2607 }
2608
2609 static int goya_mmu_init(struct hl_device *hdev)
2610 {
2611         struct asic_fixed_properties *prop = &hdev->asic_prop;
2612         struct goya_device *goya = hdev->asic_specific;
2613         u64 hop0_addr;
2614         int rc, i;
2615
2616         if (!hdev->mmu_enable)
2617                 return 0;
2618
2619         if (goya->hw_cap_initialized & HW_CAP_MMU)
2620                 return 0;
2621
2622         hdev->dram_supports_virtual_memory = true;
2623         hdev->dram_default_page_mapping = true;
2624
2625         for (i = 0 ; i < prop->max_asid ; i++) {
2626                 hop0_addr = prop->mmu_pgt_addr +
2627                                 (i * prop->mmu_hop_table_size);
2628
2629                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2630                 if (rc) {
2631                         dev_err(hdev->dev,
2632                                 "failed to set hop0 addr for asid %d\n", i);
2633                         goto err;
2634                 }
2635         }
2636
2637         goya->hw_cap_initialized |= HW_CAP_MMU;
2638
2639         /* init MMU cache manage page */
2640         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2641                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2642         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2643
2644         /* Remove follower feature due to performance bug */
2645         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2646                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2647
2648         hdev->asic_funcs->mmu_invalidate_cache(hdev, true);
2649
2650         WREG32(mmMMU_MMU_ENABLE, 1);
2651         WREG32(mmMMU_SPI_MASK, 0xF);
2652
2653         return 0;
2654
2655 err:
2656         return rc;
2657 }
2658
2659 /*
2660  * goya_hw_init - Goya hardware initialization code
2661  *
2662  * @hdev: pointer to hl_device structure
2663  *
2664  * Returns 0 on success
2665  *
2666  */
2667 static int goya_hw_init(struct hl_device *hdev)
2668 {
2669         struct asic_fixed_properties *prop = &hdev->asic_prop;
2670         u32 val;
2671         int rc;
2672
2673         dev_info(hdev->dev, "Starting initialization of H/W\n");
2674
2675         /* Perform read from the device to make sure device is up */
2676         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2677
2678         /*
2679          * Let's mark in the H/W that we have reached this point. We check
2680          * this value in the reset_before_init function to understand whether
2681          * we need to reset the chip before doing H/W init. This register is
2682          * cleared by the H/W upon H/W reset
2683          */
2684         WREG32(mmPSOC_GLOBAL_CONF_APP_STATUS, HL_DEVICE_HW_STATE_DIRTY);
2685
2686         rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC);
2687         if (rc) {
2688                 dev_err(hdev->dev, "failed to initialize CPU\n");
2689                 return rc;
2690         }
2691
2692         goya_tpc_mbist_workaround(hdev);
2693
2694         goya_init_golden_registers(hdev);
2695
2696         /*
2697          * After CPU initialization is finished, change DDR bar mapping inside
2698          * iATU to point to the start address of the MMU page tables
2699          */
2700         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
2701                 (MMU_PAGE_TABLES_ADDR & ~(prop->dram_pci_bar_size - 0x1ull)));
2702         if (rc) {
2703                 dev_err(hdev->dev,
2704                         "failed to map DDR bar to MMU page tables\n");
2705                 return rc;
2706         }
2707
2708         rc = goya_mmu_init(hdev);
2709         if (rc)
2710                 return rc;
2711
2712         goya_init_security(hdev);
2713
2714         goya_init_dma_qmans(hdev);
2715
2716         goya_init_mme_qmans(hdev);
2717
2718         goya_init_tpc_qmans(hdev);
2719
2720         /* MSI-X must be enabled before CPU queues are initialized */
2721         rc = goya_enable_msix(hdev);
2722         if (rc)
2723                 goto disable_queues;
2724
2725         rc = goya_init_cpu_queues(hdev);
2726         if (rc) {
2727                 dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n",
2728                         rc);
2729                 goto disable_msix;
2730         }
2731
2732         /* CPU initialization is finished, we can now move to 48 bit DMA mask */
2733         rc = pci_set_dma_mask(hdev->pdev, DMA_BIT_MASK(48));
2734         if (rc) {
2735                 dev_warn(hdev->dev, "Unable to set pci dma mask to 48 bits\n");
2736                 rc = pci_set_dma_mask(hdev->pdev, DMA_BIT_MASK(32));
2737                 if (rc) {
2738                         dev_err(hdev->dev,
2739                                 "Unable to set pci dma mask to 32 bits\n");
2740                         goto disable_pci_access;
2741                 }
2742         }
2743
2744         rc = pci_set_consistent_dma_mask(hdev->pdev, DMA_BIT_MASK(48));
2745         if (rc) {
2746                 dev_warn(hdev->dev,
2747                         "Unable to set pci consistent dma mask to 48 bits\n");
2748                 rc = pci_set_consistent_dma_mask(hdev->pdev, DMA_BIT_MASK(32));
2749                 if (rc) {
2750                         dev_err(hdev->dev,
2751                                 "Unable to set pci consistent dma mask to 32 bits\n");
2752                         goto disable_pci_access;
2753                 }
2754         }
2755
2756         /* Perform read from the device to flush all MSI-X configuration */
2757         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2758
2759         return 0;
2760
2761 disable_pci_access:
2762         goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
2763 disable_msix:
2764         goya_disable_msix(hdev);
2765 disable_queues:
2766         goya_disable_internal_queues(hdev);
2767         goya_disable_external_queues(hdev);
2768
2769         return rc;
2770 }
2771
2772 /*
2773  * goya_hw_fini - Goya hardware tear-down code
2774  *
2775  * @hdev: pointer to hl_device structure
2776  * @hard_reset: should we do hard reset to all engines or just reset the
2777  *              compute/dma engines
2778  */
2779 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
2780 {
2781         struct goya_device *goya = hdev->asic_specific;
2782         u32 reset_timeout_ms, status;
2783
2784         if (hdev->pldm)
2785                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2786         else
2787                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2788
2789         if (hard_reset) {
2790                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2791                 goya_disable_clk_rlx(hdev);
2792                 goya_set_pll_refclk(hdev);
2793
2794                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2795                 dev_info(hdev->dev,
2796                         "Issued HARD reset command, going to wait %dms\n",
2797                         reset_timeout_ms);
2798         } else {
2799                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2800                 dev_info(hdev->dev,
2801                         "Issued SOFT reset command, going to wait %dms\n",
2802                         reset_timeout_ms);
2803         }
2804
2805         /*
2806          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2807          * itself is in reset. In either reset we need to wait until the reset
2808          * is deasserted
2809          */
2810         msleep(reset_timeout_ms);
2811
2812         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2813         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2814                 dev_err(hdev->dev,
2815                         "Timeout while waiting for device to reset 0x%x\n",
2816                         status);
2817
2818         if (!hard_reset) {
2819                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2820                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2821                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2822                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2823                 return;
2824         }
2825
2826         /* Chicken bit to re-initiate boot sequencer flow */
2827         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2828                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2829         /* Move boot manager FSM to pre boot sequencer init state */
2830         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2831                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2832
2833         goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2834                                         HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2835                                         HW_CAP_DMA | HW_CAP_MME |
2836                                         HW_CAP_MMU | HW_CAP_TPC_MBIST |
2837                                         HW_CAP_GOLDEN | HW_CAP_TPC);
2838         memset(goya->events_stat, 0, sizeof(goya->events_stat));
2839
2840         if (!hdev->pldm) {
2841                 int rc;
2842                 /* In case we are running inside VM and the VM is
2843                  * shutting down, we need to make sure CPU boot-loader
2844                  * is running before we can continue the VM shutdown.
2845                  * That is because the VM will send an FLR signal that
2846                  * we must answer
2847                  */
2848                 dev_info(hdev->dev,
2849                         "Going to wait up to %ds for CPU boot loader\n",
2850                         GOYA_CPU_TIMEOUT_USEC / 1000 / 1000);
2851
2852                 rc = hl_poll_timeout(
2853                         hdev,
2854                         mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2855                         status,
2856                         (status == CPU_BOOT_STATUS_DRAM_RDY),
2857                         10000,
2858                         GOYA_CPU_TIMEOUT_USEC);
2859                 if (rc)
2860                         dev_err(hdev->dev,
2861                                 "failed to wait for CPU boot loader\n");
2862         }
2863 }
2864
2865 int goya_suspend(struct hl_device *hdev)
2866 {
2867         int rc;
2868
2869         rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
2870         if (rc)
2871                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2872
2873         return rc;
2874 }
2875
2876 int goya_resume(struct hl_device *hdev)
2877 {
2878         return goya_init_iatu(hdev);
2879 }
2880
2881 static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2882                 u64 kaddress, phys_addr_t paddress, u32 size)
2883 {
2884         int rc;
2885
2886         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2887                         VM_DONTCOPY | VM_NORESERVE;
2888
2889         rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT,
2890                                 size, vma->vm_page_prot);
2891         if (rc)
2892                 dev_err(hdev->dev, "remap_pfn_range error %d", rc);
2893
2894         return rc;
2895 }
2896
2897 static void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2898 {
2899         u32 db_reg_offset, db_value;
2900         bool invalid_queue = false;
2901
2902         switch (hw_queue_id) {
2903         case GOYA_QUEUE_ID_DMA_0:
2904                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2905                 break;
2906
2907         case GOYA_QUEUE_ID_DMA_1:
2908                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2909                 break;
2910
2911         case GOYA_QUEUE_ID_DMA_2:
2912                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2913                 break;
2914
2915         case GOYA_QUEUE_ID_DMA_3:
2916                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2917                 break;
2918
2919         case GOYA_QUEUE_ID_DMA_4:
2920                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2921                 break;
2922
2923         case GOYA_QUEUE_ID_CPU_PQ:
2924                 if (hdev->cpu_queues_enable)
2925                         db_reg_offset = mmCPU_IF_PF_PQ_PI;
2926                 else
2927                         invalid_queue = true;
2928                 break;
2929
2930         case GOYA_QUEUE_ID_MME:
2931                 db_reg_offset = mmMME_QM_PQ_PI;
2932                 break;
2933
2934         case GOYA_QUEUE_ID_TPC0:
2935                 db_reg_offset = mmTPC0_QM_PQ_PI;
2936                 break;
2937
2938         case GOYA_QUEUE_ID_TPC1:
2939                 db_reg_offset = mmTPC1_QM_PQ_PI;
2940                 break;
2941
2942         case GOYA_QUEUE_ID_TPC2:
2943                 db_reg_offset = mmTPC2_QM_PQ_PI;
2944                 break;
2945
2946         case GOYA_QUEUE_ID_TPC3:
2947                 db_reg_offset = mmTPC3_QM_PQ_PI;
2948                 break;
2949
2950         case GOYA_QUEUE_ID_TPC4:
2951                 db_reg_offset = mmTPC4_QM_PQ_PI;
2952                 break;
2953
2954         case GOYA_QUEUE_ID_TPC5:
2955                 db_reg_offset = mmTPC5_QM_PQ_PI;
2956                 break;
2957
2958         case GOYA_QUEUE_ID_TPC6:
2959                 db_reg_offset = mmTPC6_QM_PQ_PI;
2960                 break;
2961
2962         case GOYA_QUEUE_ID_TPC7:
2963                 db_reg_offset = mmTPC7_QM_PQ_PI;
2964                 break;
2965
2966         default:
2967                 invalid_queue = true;
2968         }
2969
2970         if (invalid_queue) {
2971                 /* Should never get here */
2972                 dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n",
2973                         hw_queue_id);
2974                 return;
2975         }
2976
2977         db_value = pi;
2978
2979         /* ring the doorbell */
2980         WREG32(db_reg_offset, db_value);
2981
2982         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ)
2983                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2984                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2985 }
2986
2987 void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val)
2988 {
2989         /* Not needed in Goya */
2990 }
2991
2992 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2993                                         dma_addr_t *dma_handle, gfp_t flags)
2994 {
2995         return dma_alloc_coherent(&hdev->pdev->dev, size, dma_handle, flags);
2996 }
2997
2998 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2999                                         void *cpu_addr, dma_addr_t dma_handle)
3000 {
3001         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, dma_handle);
3002 }
3003
3004 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
3005                                 dma_addr_t *dma_handle, u16 *queue_len)
3006 {
3007         void *base;
3008         u32 offset;
3009
3010         *dma_handle = hdev->asic_prop.sram_base_address;
3011
3012         base = (void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
3013
3014         switch (queue_id) {
3015         case GOYA_QUEUE_ID_MME:
3016                 offset = MME_QMAN_BASE_OFFSET;
3017                 *queue_len = MME_QMAN_LENGTH;
3018                 break;
3019         case GOYA_QUEUE_ID_TPC0:
3020                 offset = TPC0_QMAN_BASE_OFFSET;
3021                 *queue_len = TPC_QMAN_LENGTH;
3022                 break;
3023         case GOYA_QUEUE_ID_TPC1:
3024                 offset = TPC1_QMAN_BASE_OFFSET;
3025                 *queue_len = TPC_QMAN_LENGTH;
3026                 break;
3027         case GOYA_QUEUE_ID_TPC2:
3028                 offset = TPC2_QMAN_BASE_OFFSET;
3029                 *queue_len = TPC_QMAN_LENGTH;
3030                 break;
3031         case GOYA_QUEUE_ID_TPC3:
3032                 offset = TPC3_QMAN_BASE_OFFSET;
3033                 *queue_len = TPC_QMAN_LENGTH;
3034                 break;
3035         case GOYA_QUEUE_ID_TPC4:
3036                 offset = TPC4_QMAN_BASE_OFFSET;
3037                 *queue_len = TPC_QMAN_LENGTH;
3038                 break;
3039         case GOYA_QUEUE_ID_TPC5:
3040                 offset = TPC5_QMAN_BASE_OFFSET;
3041                 *queue_len = TPC_QMAN_LENGTH;
3042                 break;
3043         case GOYA_QUEUE_ID_TPC6:
3044                 offset = TPC6_QMAN_BASE_OFFSET;
3045                 *queue_len = TPC_QMAN_LENGTH;
3046                 break;
3047         case GOYA_QUEUE_ID_TPC7:
3048                 offset = TPC7_QMAN_BASE_OFFSET;
3049                 *queue_len = TPC_QMAN_LENGTH;
3050                 break;
3051         default:
3052                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
3053                 return NULL;
3054         }
3055
3056         base += offset;
3057         *dma_handle += offset;
3058
3059         return base;
3060 }
3061
3062 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
3063 {
3064         struct goya_device *goya = hdev->asic_specific;
3065         struct packet_msg_prot *fence_pkt;
3066         u32 *fence_ptr;
3067         dma_addr_t fence_dma_addr;
3068         struct hl_cb *cb;
3069         u32 tmp, timeout;
3070         int rc;
3071
3072         if (hdev->pldm)
3073                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3074         else
3075                 timeout = HL_DEVICE_TIMEOUT_USEC;
3076
3077         if (!hdev->asic_funcs->is_device_idle(hdev)) {
3078                 dev_err_ratelimited(hdev->dev,
3079                         "Can't send KMD job on QMAN0 if device is not idle\n");
3080                 return -EBUSY;
3081         }
3082
3083         fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3084                                                         &fence_dma_addr);
3085         if (!fence_ptr) {
3086                 dev_err(hdev->dev,
3087                         "Failed to allocate fence memory for QMAN0\n");
3088                 return -ENOMEM;
3089         }
3090
3091         *fence_ptr = 0;
3092
3093         if (goya->hw_cap_initialized & HW_CAP_MMU) {
3094                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
3095                 RREG32(mmDMA_QM_0_GLBL_PROT);
3096         }
3097
3098         /*
3099          * goya cs parser saves space for 2xpacket_msg_prot at end of CB. For
3100          * synchronized kernel jobs we only need space for 1 packet_msg_prot
3101          */
3102         job->job_cb_size -= sizeof(struct packet_msg_prot);
3103
3104         cb = job->patched_cb;
3105
3106         fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address +
3107                         job->job_cb_size - sizeof(struct packet_msg_prot));
3108
3109         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3110                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3111                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3112         fence_pkt->ctl = cpu_to_le32(tmp);
3113         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3114         fence_pkt->addr = cpu_to_le64(fence_dma_addr +
3115                                         hdev->asic_prop.host_phys_base_address);
3116
3117         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3118                                         job->job_cb_size, cb->bus_address);
3119         if (rc) {
3120                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3121                 goto free_fence_ptr;
3122         }
3123
3124         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr, timeout,
3125                                         &tmp);
3126
3127         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3128
3129         if ((rc) || (tmp != GOYA_QMAN0_FENCE_VAL)) {
3130                 dev_err(hdev->dev, "QMAN0 Job hasn't finished in time\n");
3131                 rc = -ETIMEDOUT;
3132         }
3133
3134 free_fence_ptr:
3135         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr,
3136                                         fence_dma_addr);
3137
3138         if (goya->hw_cap_initialized & HW_CAP_MMU) {
3139                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
3140                 RREG32(mmDMA_QM_0_GLBL_PROT);
3141         }
3142
3143         return rc;
3144 }
3145
3146 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3147                                 u32 timeout, long *result)
3148 {
3149         struct goya_device *goya = hdev->asic_specific;
3150         struct armcp_packet *pkt;
3151         dma_addr_t pkt_dma_addr;
3152         u32 tmp;
3153         int rc = 0;
3154
3155         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3156                 if (result)
3157                         *result = 0;
3158                 return 0;
3159         }
3160
3161         if (len > CPU_CB_SIZE) {
3162                 dev_err(hdev->dev, "Invalid CPU message size of %d bytes\n",
3163                         len);
3164                 return -ENOMEM;
3165         }
3166
3167         pkt = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, len,
3168                                                                 &pkt_dma_addr);
3169         if (!pkt) {
3170                 dev_err(hdev->dev,
3171                         "Failed to allocate DMA memory for packet to CPU\n");
3172                 return -ENOMEM;
3173         }
3174
3175         memcpy(pkt, msg, len);
3176
3177         mutex_lock(&hdev->send_cpu_message_lock);
3178
3179         if (hdev->disabled)
3180                 goto out;
3181
3182         if (hdev->device_cpu_disabled) {
3183                 rc = -EIO;
3184                 goto out;
3185         }
3186
3187         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_CPU_PQ, len,
3188                         pkt_dma_addr);
3189         if (rc) {
3190                 dev_err(hdev->dev, "Failed to send CB on CPU PQ (%d)\n", rc);
3191                 goto out;
3192         }
3193
3194         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) &pkt->fence,
3195                                         timeout, &tmp);
3196
3197         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_CPU_PQ);
3198
3199         if (rc == -ETIMEDOUT) {
3200                 dev_err(hdev->dev, "Timeout while waiting for device CPU\n");
3201                 hdev->device_cpu_disabled = true;
3202                 goto out;
3203         }
3204
3205         if (tmp == ARMCP_PACKET_FENCE_VAL) {
3206                 u32 ctl = le32_to_cpu(pkt->ctl);
3207
3208                 rc = (ctl & ARMCP_PKT_CTL_RC_MASK) >> ARMCP_PKT_CTL_RC_SHIFT;
3209                 if (rc) {
3210                         dev_err(hdev->dev,
3211                                 "F/W ERROR %d for CPU packet %d\n",
3212                                 rc, (ctl & ARMCP_PKT_CTL_OPCODE_MASK)
3213                                                 >> ARMCP_PKT_CTL_OPCODE_SHIFT);
3214                         rc = -EINVAL;
3215                 } else if (result) {
3216                         *result = (long) le64_to_cpu(pkt->result);
3217                 }
3218         } else {
3219                 dev_err(hdev->dev, "CPU packet wrong fence value\n");
3220                 rc = -EINVAL;
3221         }
3222
3223 out:
3224         mutex_unlock(&hdev->send_cpu_message_lock);
3225
3226         hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, len, pkt);
3227
3228         return rc;
3229 }
3230
3231 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3232 {
3233         struct packet_msg_prot *fence_pkt;
3234         dma_addr_t pkt_dma_addr;
3235         u32 fence_val, tmp;
3236         dma_addr_t fence_dma_addr;
3237         u32 *fence_ptr;
3238         int rc;
3239
3240         fence_val = GOYA_QMAN0_FENCE_VAL;
3241
3242         fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3243                                                         &fence_dma_addr);
3244         if (!fence_ptr) {
3245                 dev_err(hdev->dev,
3246                         "Failed to allocate memory for queue testing\n");
3247                 return -ENOMEM;
3248         }
3249
3250         *fence_ptr = 0;
3251
3252         fence_pkt = hdev->asic_funcs->dma_pool_zalloc(hdev,
3253                                         sizeof(struct packet_msg_prot),
3254                                         GFP_KERNEL, &pkt_dma_addr);
3255         if (!fence_pkt) {
3256                 dev_err(hdev->dev,
3257                         "Failed to allocate packet for queue testing\n");
3258                 rc = -ENOMEM;
3259                 goto free_fence_ptr;
3260         }
3261
3262         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3263                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3264                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3265         fence_pkt->ctl = cpu_to_le32(tmp);
3266         fence_pkt->value = cpu_to_le32(fence_val);
3267         fence_pkt->addr = cpu_to_le64(fence_dma_addr +
3268                                         hdev->asic_prop.host_phys_base_address);
3269
3270         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3271                                         sizeof(struct packet_msg_prot),
3272                                         pkt_dma_addr);
3273         if (rc) {
3274                 dev_err(hdev->dev,
3275                         "Failed to send fence packet\n");
3276                 goto free_pkt;
3277         }
3278
3279         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr,
3280                                         GOYA_TEST_QUEUE_WAIT_USEC, &tmp);
3281
3282         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3283
3284         if ((!rc) && (tmp == fence_val)) {
3285                 dev_info(hdev->dev,
3286                         "queue test on H/W queue %d succeeded\n",
3287                         hw_queue_id);
3288         } else {
3289                 dev_err(hdev->dev,
3290                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3291                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3292                 rc = -EINVAL;
3293         }
3294
3295 free_pkt:
3296         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_pkt,
3297                                         pkt_dma_addr);
3298 free_fence_ptr:
3299         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr,
3300                                         fence_dma_addr);
3301         return rc;
3302 }
3303
3304 int goya_test_cpu_queue(struct hl_device *hdev)
3305 {
3306         struct armcp_packet test_pkt;
3307         long result;
3308         int rc;
3309
3310         /* cpu_queues_enable flag is always checked in send cpu message */
3311
3312         memset(&test_pkt, 0, sizeof(test_pkt));
3313
3314         test_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST <<
3315                                         ARMCP_PKT_CTL_OPCODE_SHIFT);
3316         test_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL);
3317
3318         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &test_pkt,
3319                         sizeof(test_pkt), HL_DEVICE_TIMEOUT_USEC, &result);
3320
3321         if (!rc) {
3322                 if (result == ARMCP_PACKET_FENCE_VAL)
3323                         dev_info(hdev->dev,
3324                                 "queue test on CPU queue succeeded\n");
3325                 else
3326                         dev_err(hdev->dev,
3327                                 "CPU queue test failed (0x%08lX)\n", result);
3328         } else {
3329                 dev_err(hdev->dev, "CPU queue test failed, error %d\n", rc);
3330         }
3331
3332         return rc;
3333 }
3334
3335 static int goya_test_queues(struct hl_device *hdev)
3336 {
3337         struct goya_device *goya = hdev->asic_specific;
3338         int i, rc, ret_val = 0;
3339
3340         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3341                 rc = goya_test_queue(hdev, i);
3342                 if (rc)
3343                         ret_val = -EINVAL;
3344         }
3345
3346         if (hdev->cpu_queues_enable) {
3347                 rc = goya->test_cpu_queue(hdev);
3348                 if (rc)
3349                         ret_val = -EINVAL;
3350         }
3351
3352         return ret_val;
3353 }
3354
3355 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3356                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3357 {
3358         if (size > GOYA_DMA_POOL_BLK_SIZE)
3359                 return NULL;
3360
3361         return dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3362 }
3363
3364 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3365                                 dma_addr_t dma_addr)
3366 {
3367         dma_pool_free(hdev->dma_pool, vaddr, dma_addr);
3368 }
3369
3370 static void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev,
3371                                         size_t size, dma_addr_t *dma_handle)
3372 {
3373         u64 kernel_addr;
3374
3375         /* roundup to CPU_PKT_SIZE */
3376         size = (size + (CPU_PKT_SIZE - 1)) & CPU_PKT_MASK;
3377
3378         kernel_addr = gen_pool_alloc(hdev->cpu_accessible_dma_pool, size);
3379
3380         *dma_handle = hdev->cpu_accessible_dma_address +
3381                 (kernel_addr - (u64) (uintptr_t) hdev->cpu_accessible_dma_mem);
3382
3383         return (void *) (uintptr_t) kernel_addr;
3384 }
3385
3386 static void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev,
3387                                                 size_t size, void *vaddr)
3388 {
3389         /* roundup to CPU_PKT_SIZE */
3390         size = (size + (CPU_PKT_SIZE - 1)) & CPU_PKT_MASK;
3391
3392         gen_pool_free(hdev->cpu_accessible_dma_pool, (u64) (uintptr_t) vaddr,
3393                         size);
3394 }
3395
3396 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sg,
3397                                 int nents, enum dma_data_direction dir)
3398 {
3399         if (!dma_map_sg(&hdev->pdev->dev, sg, nents, dir))
3400                 return -ENOMEM;
3401
3402         return 0;
3403 }
3404
3405 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sg,
3406                                 int nents, enum dma_data_direction dir)
3407 {
3408         dma_unmap_sg(&hdev->pdev->dev, sg, nents, dir);
3409 }
3410
3411 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3412 {
3413         struct scatterlist *sg, *sg_next_iter;
3414         u32 count, dma_desc_cnt;
3415         u64 len, len_next;
3416         dma_addr_t addr, addr_next;
3417
3418         dma_desc_cnt = 0;
3419
3420         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3421
3422                 len = sg_dma_len(sg);
3423                 addr = sg_dma_address(sg);
3424
3425                 if (len == 0)
3426                         break;
3427
3428                 while ((count + 1) < sgt->nents) {
3429                         sg_next_iter = sg_next(sg);
3430                         len_next = sg_dma_len(sg_next_iter);
3431                         addr_next = sg_dma_address(sg_next_iter);
3432
3433                         if (len_next == 0)
3434                                 break;
3435
3436                         if ((addr + len == addr_next) &&
3437                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3438                                 len += len_next;
3439                                 count++;
3440                                 sg = sg_next_iter;
3441                         } else {
3442                                 break;
3443                         }
3444                 }
3445
3446                 dma_desc_cnt++;
3447         }
3448
3449         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3450 }
3451
3452 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3453                                 struct hl_cs_parser *parser,
3454                                 struct packet_lin_dma *user_dma_pkt,
3455                                 u64 addr, enum dma_data_direction dir)
3456 {
3457         struct hl_userptr *userptr;
3458         int rc;
3459
3460         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3461                         parser->job_userptr_list, &userptr))
3462                 goto already_pinned;
3463
3464         userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC);
3465         if (!userptr)
3466                 return -ENOMEM;
3467
3468         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3469                                 userptr);
3470         if (rc)
3471                 goto free_userptr;
3472
3473         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3474
3475         rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3476                                         userptr->sgt->nents, dir);
3477         if (rc) {
3478                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3479                 goto unpin_memory;
3480         }
3481
3482         userptr->dma_mapped = true;
3483         userptr->dir = dir;
3484
3485 already_pinned:
3486         parser->patched_cb_size +=
3487                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3488
3489         return 0;
3490
3491 unpin_memory:
3492         hl_unpin_host_memory(hdev, userptr);
3493 free_userptr:
3494         kfree(userptr);
3495         return rc;
3496 }
3497
3498 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3499                                 struct hl_cs_parser *parser,
3500                                 struct packet_lin_dma *user_dma_pkt)
3501 {
3502         u64 device_memory_addr, addr;
3503         enum dma_data_direction dir;
3504         enum goya_dma_direction user_dir;
3505         bool sram_addr = true;
3506         bool skip_host_mem_pin = false;
3507         bool user_memset;
3508         u32 ctl;
3509         int rc = 0;
3510
3511         ctl = le32_to_cpu(user_dma_pkt->ctl);
3512
3513         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3514                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3515
3516         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3517                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3518
3519         switch (user_dir) {
3520         case DMA_HOST_TO_DRAM:
3521                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3522                 dir = DMA_TO_DEVICE;
3523                 sram_addr = false;
3524                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3525                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3526                 if (user_memset)
3527                         skip_host_mem_pin = true;
3528                 break;
3529
3530         case DMA_DRAM_TO_HOST:
3531                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3532                 dir = DMA_FROM_DEVICE;
3533                 sram_addr = false;
3534                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3535                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3536                 break;
3537
3538         case DMA_HOST_TO_SRAM:
3539                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3540                 dir = DMA_TO_DEVICE;
3541                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3542                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3543                 if (user_memset)
3544                         skip_host_mem_pin = true;
3545                 break;
3546
3547         case DMA_SRAM_TO_HOST:
3548                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3549                 dir = DMA_FROM_DEVICE;
3550                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3551                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3552                 break;
3553         default:
3554                 dev_err(hdev->dev, "DMA direction is undefined\n");
3555                 return -EFAULT;
3556         }
3557
3558         if (parser->ctx_id != HL_KERNEL_ASID_ID) {
3559                 if (sram_addr) {
3560                         if (!hl_mem_area_inside_range(device_memory_addr,
3561                                         le32_to_cpu(user_dma_pkt->tsize),
3562                                         hdev->asic_prop.sram_user_base_address,
3563                                         hdev->asic_prop.sram_end_address)) {
3564
3565                                 dev_err(hdev->dev,
3566                                         "SRAM address 0x%llx + 0x%x is invalid\n",
3567                                         device_memory_addr,
3568                                         user_dma_pkt->tsize);
3569                                 return -EFAULT;
3570                         }
3571                 } else {
3572                         if (!hl_mem_area_inside_range(device_memory_addr,
3573                                         le32_to_cpu(user_dma_pkt->tsize),
3574                                         hdev->asic_prop.dram_user_base_address,
3575                                         hdev->asic_prop.dram_end_address)) {
3576
3577                                 dev_err(hdev->dev,
3578                                         "DRAM address 0x%llx + 0x%x is invalid\n",
3579                                         device_memory_addr,
3580                                         user_dma_pkt->tsize);
3581                                 return -EFAULT;
3582                         }
3583                 }
3584         }
3585
3586         if (skip_host_mem_pin)
3587                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3588         else {
3589                 if ((dir == DMA_TO_DEVICE) &&
3590                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3591                         dev_err(hdev->dev,
3592                                 "Can't DMA from host on queue other then 1\n");
3593                         return -EFAULT;
3594                 }
3595
3596                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3597                                                 addr, dir);
3598         }
3599
3600         return rc;
3601 }
3602
3603 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3604                                 struct hl_cs_parser *parser,
3605                                 struct packet_lin_dma *user_dma_pkt)
3606 {
3607         u64 sram_memory_addr, dram_memory_addr;
3608         enum goya_dma_direction user_dir;
3609         u32 ctl;
3610
3611         ctl = le32_to_cpu(user_dma_pkt->ctl);
3612         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3613                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3614
3615         if (user_dir == DMA_DRAM_TO_SRAM) {
3616                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3617                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3618                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3619         } else {
3620                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3621                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3622                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3623         }
3624
3625         if (!hl_mem_area_inside_range(sram_memory_addr,
3626                                 le32_to_cpu(user_dma_pkt->tsize),
3627                                 hdev->asic_prop.sram_user_base_address,
3628                                 hdev->asic_prop.sram_end_address)) {
3629                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3630                         sram_memory_addr, user_dma_pkt->tsize);
3631                 return -EFAULT;
3632         }
3633
3634         if (!hl_mem_area_inside_range(dram_memory_addr,
3635                                 le32_to_cpu(user_dma_pkt->tsize),
3636                                 hdev->asic_prop.dram_user_base_address,
3637                                 hdev->asic_prop.dram_end_address)) {
3638                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3639                         dram_memory_addr, user_dma_pkt->tsize);
3640                 return -EFAULT;
3641         }
3642
3643         parser->patched_cb_size += sizeof(*user_dma_pkt);
3644
3645         return 0;
3646 }
3647
3648 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3649                                 struct hl_cs_parser *parser,
3650                                 struct packet_lin_dma *user_dma_pkt)
3651 {
3652         enum goya_dma_direction user_dir;
3653         u32 ctl;
3654         int rc;
3655
3656         dev_dbg(hdev->dev, "DMA packet details:\n");
3657         dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3658         dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3659         dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3660
3661         ctl = le32_to_cpu(user_dma_pkt->ctl);
3662         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3663                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3664
3665         /*
3666          * Special handling for DMA with size 0. The H/W has a bug where
3667          * this can cause the QMAN DMA to get stuck, so block it here.
3668          */
3669         if (user_dma_pkt->tsize == 0) {
3670                 dev_err(hdev->dev,
3671                         "Got DMA with size 0, might reset the device\n");
3672                 return -EINVAL;
3673         }
3674
3675         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3676                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3677         else
3678                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3679
3680         return rc;
3681 }
3682
3683 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3684                                 struct hl_cs_parser *parser,
3685                                 struct packet_lin_dma *user_dma_pkt)
3686 {
3687         dev_dbg(hdev->dev, "DMA packet details:\n");
3688         dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3689         dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3690         dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3691
3692         /*
3693          * WA for HW-23.
3694          * We can't allow user to read from Host using QMANs other than 1.
3695          */
3696         if (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1 &&
3697                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3698                                 le32_to_cpu(user_dma_pkt->tsize),
3699                                 hdev->asic_prop.va_space_host_start_address,
3700                                 hdev->asic_prop.va_space_host_end_address)) {
3701                 dev_err(hdev->dev,
3702                         "Can't DMA from host on queue other then 1\n");
3703                 return -EFAULT;
3704         }
3705
3706         if (user_dma_pkt->tsize == 0) {
3707                 dev_err(hdev->dev,
3708                         "Got DMA with size 0, might reset the device\n");
3709                 return -EINVAL;
3710         }
3711
3712         parser->patched_cb_size += sizeof(*user_dma_pkt);
3713
3714         return 0;
3715 }
3716
3717 static int goya_validate_wreg32(struct hl_device *hdev,
3718                                 struct hl_cs_parser *parser,
3719                                 struct packet_wreg32 *wreg_pkt)
3720 {
3721         struct goya_device *goya = hdev->asic_specific;
3722         u32 sob_start_addr, sob_end_addr;
3723         u16 reg_offset;
3724
3725         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3726                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3727
3728         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3729         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3730         dev_dbg(hdev->dev, "value      == 0x%x\n", wreg_pkt->value);
3731
3732         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3733                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3734                         reg_offset);
3735                 return -EPERM;
3736         }
3737
3738         /*
3739          * With MMU, DMA channels are not secured, so it doesn't matter where
3740          * the WR COMP will be written to because it will go out with
3741          * non-secured property
3742          */
3743         if (goya->hw_cap_initialized & HW_CAP_MMU)
3744                 return 0;
3745
3746         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3747         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3748
3749         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3750                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3751
3752                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3753                         wreg_pkt->value);
3754                 return -EPERM;
3755         }
3756
3757         return 0;
3758 }
3759
3760 static int goya_validate_cb(struct hl_device *hdev,
3761                         struct hl_cs_parser *parser, bool is_mmu)
3762 {
3763         u32 cb_parsed_length = 0;
3764         int rc = 0;
3765
3766         parser->patched_cb_size = 0;
3767
3768         /* cb_user_size is more than 0 so loop will always be executed */
3769         while (cb_parsed_length < parser->user_cb_size) {
3770                 enum packet_id pkt_id;
3771                 u16 pkt_size;
3772                 void *user_pkt;
3773
3774                 user_pkt = (void *) (uintptr_t)
3775                         (parser->user_cb->kernel_address + cb_parsed_length);
3776
3777                 pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
3778                                 PACKET_HEADER_PACKET_ID_MASK) >>
3779                                         PACKET_HEADER_PACKET_ID_SHIFT);
3780
3781                 pkt_size = goya_packet_sizes[pkt_id];
3782                 cb_parsed_length += pkt_size;
3783                 if (cb_parsed_length > parser->user_cb_size) {
3784                         dev_err(hdev->dev,
3785                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3786                         rc = -EINVAL;
3787                         break;
3788                 }
3789
3790                 switch (pkt_id) {
3791                 case PACKET_WREG_32:
3792                         /*
3793                          * Although it is validated after copy in patch_cb(),
3794                          * need to validate here as well because patch_cb() is
3795                          * not called in MMU path while this function is called
3796                          */
3797                         rc = goya_validate_wreg32(hdev, parser, user_pkt);
3798                         break;
3799
3800                 case PACKET_WREG_BULK:
3801                         dev_err(hdev->dev,
3802                                 "User not allowed to use WREG_BULK\n");
3803                         rc = -EPERM;
3804                         break;
3805
3806                 case PACKET_MSG_PROT:
3807                         dev_err(hdev->dev,
3808                                 "User not allowed to use MSG_PROT\n");
3809                         rc = -EPERM;
3810                         break;
3811
3812                 case PACKET_CP_DMA:
3813                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3814                         rc = -EPERM;
3815                         break;
3816
3817                 case PACKET_STOP:
3818                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3819                         rc = -EPERM;
3820                         break;
3821
3822                 case PACKET_LIN_DMA:
3823                         if (is_mmu)
3824                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3825                                                 user_pkt);
3826                         else
3827                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3828                                                 user_pkt);
3829                         break;
3830
3831                 case PACKET_MSG_LONG:
3832                 case PACKET_MSG_SHORT:
3833                 case PACKET_FENCE:
3834                 case PACKET_NOP:
3835                         parser->patched_cb_size += pkt_size;
3836                         break;
3837
3838                 default:
3839                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3840                                 pkt_id);
3841                         rc = -EINVAL;
3842                         break;
3843                 }
3844
3845                 if (rc)
3846                         break;
3847         }
3848
3849         /*
3850          * The new CB should have space at the end for two MSG_PROT packets:
3851          * 1. A packet that will act as a completion packet
3852          * 2. A packet that will generate MSI-X interrupt
3853          */
3854         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3855
3856         return rc;
3857 }
3858
3859 static int goya_patch_dma_packet(struct hl_device *hdev,
3860                                 struct hl_cs_parser *parser,
3861                                 struct packet_lin_dma *user_dma_pkt,
3862                                 struct packet_lin_dma *new_dma_pkt,
3863                                 u32 *new_dma_pkt_size)
3864 {
3865         struct hl_userptr *userptr;
3866         struct scatterlist *sg, *sg_next_iter;
3867         u32 count, dma_desc_cnt;
3868         u64 len, len_next;
3869         dma_addr_t dma_addr, dma_addr_next;
3870         enum goya_dma_direction user_dir;
3871         u64 device_memory_addr, addr;
3872         enum dma_data_direction dir;
3873         struct sg_table *sgt;
3874         bool skip_host_mem_pin = false;
3875         bool user_memset;
3876         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3877
3878         ctl = le32_to_cpu(user_dma_pkt->ctl);
3879
3880         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3881                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3882
3883         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3884                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3885
3886         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3887                         (user_dma_pkt->tsize == 0)) {
3888                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3889                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3890                 return 0;
3891         }
3892
3893         if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3894                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3895                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3896                 dir = DMA_TO_DEVICE;
3897                 if (user_memset)
3898                         skip_host_mem_pin = true;
3899         } else {
3900                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3901                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3902                 dir = DMA_FROM_DEVICE;
3903         }
3904
3905         if ((!skip_host_mem_pin) &&
3906                 (hl_userptr_is_pinned(hdev, addr,
3907                         le32_to_cpu(user_dma_pkt->tsize),
3908                         parser->job_userptr_list, &userptr) == false)) {
3909                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3910                                 addr, user_dma_pkt->tsize);
3911                 return -EFAULT;
3912         }
3913
3914         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3915                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3916                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3917                 return 0;
3918         }
3919
3920         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3921
3922         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3923
3924         sgt = userptr->sgt;
3925         dma_desc_cnt = 0;
3926
3927         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3928                 len = sg_dma_len(sg);
3929                 dma_addr = sg_dma_address(sg);
3930
3931                 if (len == 0)
3932                         break;
3933
3934                 while ((count + 1) < sgt->nents) {
3935                         sg_next_iter = sg_next(sg);
3936                         len_next = sg_dma_len(sg_next_iter);
3937                         dma_addr_next = sg_dma_address(sg_next_iter);
3938
3939                         if (len_next == 0)
3940                                 break;
3941
3942                         if ((dma_addr + len == dma_addr_next) &&
3943                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3944                                 len += len_next;
3945                                 count++;
3946                                 sg = sg_next_iter;
3947                         } else {
3948                                 break;
3949                         }
3950                 }
3951
3952                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3953                 if (likely(dma_desc_cnt))
3954                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3955                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3956                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3957                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3958                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3959
3960                 dma_addr += hdev->asic_prop.host_phys_base_address;
3961
3962                 if (dir == DMA_TO_DEVICE) {
3963                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3964                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3965                 } else {
3966                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3967                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3968                 }
3969
3970                 if (!user_memset)
3971                         device_memory_addr += len;
3972                 dma_desc_cnt++;
3973                 new_dma_pkt++;
3974         }
3975
3976         if (!dma_desc_cnt) {
3977                 dev_err(hdev->dev,
3978                         "Error of 0 SG entries when patching DMA packet\n");
3979                 return -EFAULT;
3980         }
3981
3982         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3983         new_dma_pkt--;
3984         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3985
3986         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3987
3988         return 0;
3989 }
3990
3991 static int goya_patch_cb(struct hl_device *hdev,
3992                                 struct hl_cs_parser *parser)
3993 {
3994         u32 cb_parsed_length = 0;
3995         u32 cb_patched_cur_length = 0;
3996         int rc = 0;
3997
3998         /* cb_user_size is more than 0 so loop will always be executed */
3999         while (cb_parsed_length < parser->user_cb_size) {
4000                 enum packet_id pkt_id;
4001                 u16 pkt_size;
4002                 u32 new_pkt_size = 0;
4003                 void *user_pkt, *kernel_pkt;
4004
4005                 user_pkt = (void *) (uintptr_t)
4006                         (parser->user_cb->kernel_address + cb_parsed_length);
4007                 kernel_pkt = (void *) (uintptr_t)
4008                         (parser->patched_cb->kernel_address +
4009                                         cb_patched_cur_length);
4010
4011                 pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
4012                                 PACKET_HEADER_PACKET_ID_MASK) >>
4013                                         PACKET_HEADER_PACKET_ID_SHIFT);
4014
4015                 pkt_size = goya_packet_sizes[pkt_id];
4016                 cb_parsed_length += pkt_size;
4017                 if (cb_parsed_length > parser->user_cb_size) {
4018                         dev_err(hdev->dev,
4019                                 "packet 0x%x is out of CB boundary\n", pkt_id);
4020                         rc = -EINVAL;
4021                         break;
4022                 }
4023
4024                 switch (pkt_id) {
4025                 case PACKET_LIN_DMA:
4026                         rc = goya_patch_dma_packet(hdev, parser, user_pkt,
4027                                                 kernel_pkt, &new_pkt_size);
4028                         cb_patched_cur_length += new_pkt_size;
4029                         break;
4030
4031                 case PACKET_WREG_32:
4032                         memcpy(kernel_pkt, user_pkt, pkt_size);
4033                         cb_patched_cur_length += pkt_size;
4034                         rc = goya_validate_wreg32(hdev, parser, kernel_pkt);
4035                         break;
4036
4037                 case PACKET_WREG_BULK:
4038                         dev_err(hdev->dev,
4039                                 "User not allowed to use WREG_BULK\n");
4040                         rc = -EPERM;
4041                         break;
4042
4043                 case PACKET_MSG_PROT:
4044                         dev_err(hdev->dev,
4045                                 "User not allowed to use MSG_PROT\n");
4046                         rc = -EPERM;
4047                         break;
4048
4049                 case PACKET_CP_DMA:
4050                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
4051                         rc = -EPERM;
4052                         break;
4053
4054                 case PACKET_STOP:
4055                         dev_err(hdev->dev, "User not allowed to use STOP\n");
4056                         rc = -EPERM;
4057                         break;
4058
4059                 case PACKET_MSG_LONG:
4060                 case PACKET_MSG_SHORT:
4061                 case PACKET_FENCE:
4062                 case PACKET_NOP:
4063                         memcpy(kernel_pkt, user_pkt, pkt_size);
4064                         cb_patched_cur_length += pkt_size;
4065                         break;
4066
4067                 default:
4068                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
4069                                 pkt_id);
4070                         rc = -EINVAL;
4071                         break;
4072                 }
4073
4074                 if (rc)
4075                         break;
4076         }
4077
4078         return rc;
4079 }
4080
4081 static int goya_parse_cb_mmu(struct hl_device *hdev,
4082                 struct hl_cs_parser *parser)
4083 {
4084         u64 patched_cb_handle;
4085         u32 patched_cb_size;
4086         struct hl_cb *user_cb;
4087         int rc;
4088
4089         /*
4090          * The new CB should have space at the end for two MSG_PROT pkt:
4091          * 1. A packet that will act as a completion packet
4092          * 2. A packet that will generate MSI-X interrupt
4093          */
4094         parser->patched_cb_size = parser->user_cb_size +
4095                         sizeof(struct packet_msg_prot) * 2;
4096
4097         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
4098                                 parser->patched_cb_size,
4099                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
4100
4101         if (rc) {
4102                 dev_err(hdev->dev,
4103                         "Failed to allocate patched CB for DMA CS %d\n",
4104                         rc);
4105                 return rc;
4106         }
4107
4108         patched_cb_handle >>= PAGE_SHIFT;
4109         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4110                                 (u32) patched_cb_handle);
4111         /* hl_cb_get should never fail here so use kernel WARN */
4112         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
4113                         (u32) patched_cb_handle);
4114         if (!parser->patched_cb) {
4115                 rc = -EFAULT;
4116                 goto out;
4117         }
4118
4119         /*
4120          * The check that parser->user_cb_size <= parser->user_cb->size was done
4121          * in validate_queue_index().
4122          */
4123         memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address,
4124                 (void *) (uintptr_t) parser->user_cb->kernel_address,
4125                 parser->user_cb_size);
4126
4127         patched_cb_size = parser->patched_cb_size;
4128
4129         /* validate patched CB instead of user CB */
4130         user_cb = parser->user_cb;
4131         parser->user_cb = parser->patched_cb;
4132         rc = goya_validate_cb(hdev, parser, true);
4133         parser->user_cb = user_cb;
4134
4135         if (rc) {
4136                 hl_cb_put(parser->patched_cb);
4137                 goto out;
4138         }
4139
4140         if (patched_cb_size != parser->patched_cb_size) {
4141                 dev_err(hdev->dev, "user CB size mismatch\n");
4142                 hl_cb_put(parser->patched_cb);
4143                 rc = -EINVAL;
4144                 goto out;
4145         }
4146
4147 out:
4148         /*
4149          * Always call cb destroy here because we still have 1 reference
4150          * to it by calling cb_get earlier. After the job will be completed,
4151          * cb_put will release it, but here we want to remove it from the
4152          * idr
4153          */
4154         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4155                                         patched_cb_handle << PAGE_SHIFT);
4156
4157         return rc;
4158 }
4159
4160 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4161                                 struct hl_cs_parser *parser)
4162 {
4163         u64 patched_cb_handle;
4164         int rc;
4165
4166         rc = goya_validate_cb(hdev, parser, false);
4167
4168         if (rc)
4169                 goto free_userptr;
4170
4171         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
4172                                 parser->patched_cb_size,
4173                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
4174         if (rc) {
4175                 dev_err(hdev->dev,
4176                         "Failed to allocate patched CB for DMA CS %d\n", rc);
4177                 goto free_userptr;
4178         }
4179
4180         patched_cb_handle >>= PAGE_SHIFT;
4181         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4182                                 (u32) patched_cb_handle);
4183         /* hl_cb_get should never fail here so use kernel WARN */
4184         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
4185                         (u32) patched_cb_handle);
4186         if (!parser->patched_cb) {
4187                 rc = -EFAULT;
4188                 goto out;
4189         }
4190
4191         rc = goya_patch_cb(hdev, parser);
4192
4193         if (rc)
4194                 hl_cb_put(parser->patched_cb);
4195
4196 out:
4197         /*
4198          * Always call cb destroy here because we still have 1 reference
4199          * to it by calling cb_get earlier. After the job will be completed,
4200          * cb_put will release it, but here we want to remove it from the
4201          * idr
4202          */
4203         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4204                                 patched_cb_handle << PAGE_SHIFT);
4205
4206 free_userptr:
4207         if (rc)
4208                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4209         return rc;
4210 }
4211
4212 static int goya_parse_cb_no_ext_quque(struct hl_device *hdev,
4213                                         struct hl_cs_parser *parser)
4214 {
4215         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4216         struct goya_device *goya = hdev->asic_specific;
4217
4218         if (!(goya->hw_cap_initialized & HW_CAP_MMU)) {
4219                 /* For internal queue jobs, just check if cb address is valid */
4220                 if (hl_mem_area_inside_range(
4221                                 (u64) (uintptr_t) parser->user_cb,
4222                                 parser->user_cb_size,
4223                                 asic_prop->sram_user_base_address,
4224                                 asic_prop->sram_end_address))
4225                         return 0;
4226
4227                 if (hl_mem_area_inside_range(
4228                                 (u64) (uintptr_t) parser->user_cb,
4229                                 parser->user_cb_size,
4230                                 asic_prop->dram_user_base_address,
4231                                 asic_prop->dram_end_address))
4232                         return 0;
4233
4234                 dev_err(hdev->dev,
4235                         "Internal CB address %px + 0x%x is not in SRAM nor in DRAM\n",
4236                         parser->user_cb, parser->user_cb_size);
4237
4238                 return -EFAULT;
4239         }
4240
4241         return 0;
4242 }
4243
4244 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4245 {
4246         struct goya_device *goya = hdev->asic_specific;
4247
4248         if (!parser->ext_queue)
4249                 return goya_parse_cb_no_ext_quque(hdev, parser);
4250
4251         if ((goya->hw_cap_initialized & HW_CAP_MMU) && parser->use_virt_addr)
4252                 return goya_parse_cb_mmu(hdev, parser);
4253         else
4254                 return goya_parse_cb_no_mmu(hdev, parser);
4255 }
4256
4257 void goya_add_end_of_cb_packets(u64 kernel_address, u32 len, u64 cq_addr,
4258                                 u32 cq_val, u32 msix_vec)
4259 {
4260         struct packet_msg_prot *cq_pkt;
4261         u32 tmp;
4262
4263         cq_pkt = (struct packet_msg_prot *) (uintptr_t)
4264                 (kernel_address + len - (sizeof(struct packet_msg_prot) * 2));
4265
4266         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4267                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
4268                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4269         cq_pkt->ctl = cpu_to_le32(tmp);
4270         cq_pkt->value = cpu_to_le32(cq_val);
4271         cq_pkt->addr = cpu_to_le64(cq_addr);
4272
4273         cq_pkt++;
4274
4275         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4276                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4277         cq_pkt->ctl = cpu_to_le32(tmp);
4278         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4279         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4280 }
4281
4282 static void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4283 {
4284         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, val);
4285 }
4286
4287 static void goya_restore_phase_topology(struct hl_device *hdev)
4288 {
4289         int i, num_of_sob_in_longs, num_of_mon_in_longs;
4290
4291         num_of_sob_in_longs =
4292                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4293
4294         num_of_mon_in_longs =
4295                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4296
4297         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4298                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4299
4300         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4301                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4302
4303         /* Flush all WREG to prevent race */
4304         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4305 }
4306
4307 /*
4308  * goya_debugfs_read32 - read a 32bit value from a given device address
4309  *
4310  * @hdev:       pointer to hl_device structure
4311  * @addr:       address in device
4312  * @val:        returned value
4313  *
4314  * In case of DDR address that is not mapped into the default aperture that
4315  * the DDR bar exposes, the function will configure the iATU so that the DDR
4316  * bar will be positioned at a base address that allows reading from the
4317  * required address. Configuring the iATU during normal operation can
4318  * lead to undefined behavior and therefore, should be done with extreme care
4319  *
4320  */
4321 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
4322 {
4323         struct asic_fixed_properties *prop = &hdev->asic_prop;
4324         int rc = 0;
4325
4326         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4327                 *val = RREG32(addr - CFG_BASE);
4328
4329         } else if ((addr >= SRAM_BASE_ADDR) &&
4330                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4331
4332                 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4333                                 (addr - SRAM_BASE_ADDR));
4334
4335         } else if ((addr >= DRAM_PHYS_BASE) &&
4336                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
4337
4338                 u64 bar_base_addr = DRAM_PHYS_BASE +
4339                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4340
4341                 rc = goya_set_ddr_bar_base(hdev, bar_base_addr);
4342                 if (!rc) {
4343                         *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4344                                                 (addr - bar_base_addr));
4345
4346                         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
4347                                 (MMU_PAGE_TABLES_ADDR &
4348                                         ~(prop->dram_pci_bar_size - 0x1ull)));
4349                 }
4350         } else {
4351                 rc = -EFAULT;
4352         }
4353
4354         return rc;
4355 }
4356
4357 /*
4358  * goya_debugfs_write32 - write a 32bit value to a given device address
4359  *
4360  * @hdev:       pointer to hl_device structure
4361  * @addr:       address in device
4362  * @val:        returned value
4363  *
4364  * In case of DDR address that is not mapped into the default aperture that
4365  * the DDR bar exposes, the function will configure the iATU so that the DDR
4366  * bar will be positioned at a base address that allows writing to the
4367  * required address. Configuring the iATU during normal operation can
4368  * lead to undefined behavior and therefore, should be done with extreme care
4369  *
4370  */
4371 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
4372 {
4373         struct asic_fixed_properties *prop = &hdev->asic_prop;
4374         int rc = 0;
4375
4376         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4377                 WREG32(addr - CFG_BASE, val);
4378
4379         } else if ((addr >= SRAM_BASE_ADDR) &&
4380                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4381
4382                 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4383                                         (addr - SRAM_BASE_ADDR));
4384
4385         } else if ((addr >= DRAM_PHYS_BASE) &&
4386                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
4387
4388                 u64 bar_base_addr = DRAM_PHYS_BASE +
4389                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4390
4391                 rc = goya_set_ddr_bar_base(hdev, bar_base_addr);
4392                 if (!rc) {
4393                         writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4394                                                 (addr - bar_base_addr));
4395
4396                         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
4397                                 (MMU_PAGE_TABLES_ADDR &
4398                                         ~(prop->dram_pci_bar_size - 0x1ull)));
4399                 }
4400         } else {
4401                 rc = -EFAULT;
4402         }
4403
4404         return rc;
4405 }
4406
4407 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4408 {
4409         struct goya_device *goya = hdev->asic_specific;
4410
4411         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4412                         (addr - goya->ddr_bar_cur_addr));
4413 }
4414
4415 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4416 {
4417         struct goya_device *goya = hdev->asic_specific;
4418
4419         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4420                         (addr - goya->ddr_bar_cur_addr));
4421 }
4422
4423 static const char *_goya_get_event_desc(u16 event_type)
4424 {
4425         switch (event_type) {
4426         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4427                 return "PCIe_dec";
4428         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4429         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4430         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4431         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4432         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4433         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4434         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4435         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4436                 return "TPC%d_dec";
4437         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4438                 return "MME_wacs";
4439         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4440                 return "MME_wacsd";
4441         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4442                 return "CPU_axi_splitter";
4443         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4444                 return "PSOC_axi_dec";
4445         case GOYA_ASYNC_EVENT_ID_PSOC:
4446                 return "PSOC";
4447         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4448         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4449         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4450         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4451         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4452         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4453         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4454         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4455                 return "TPC%d_krn_err";
4456         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4457                 return "TPC%d_cq";
4458         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4459                 return "TPC%d_qm";
4460         case GOYA_ASYNC_EVENT_ID_MME_QM:
4461                 return "MME_qm";
4462         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4463                 return "MME_cq";
4464         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4465                 return "DMA%d_qm";
4466         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4467                 return "DMA%d_ch";
4468         default:
4469                 return "N/A";
4470         }
4471 }
4472
4473 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4474 {
4475         u8 index;
4476
4477         switch (event_type) {
4478         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4479         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4480         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4481         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4482         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4483         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4484         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4485         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4486                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4487                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4488                 break;
4489         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4490         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4491         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4492         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4493         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4494         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4495         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4496         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4497                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4498                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4499                 break;
4500         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4501                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4502                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4503                 break;
4504         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4505                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4506                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4507                 break;
4508         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4509                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4510                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4511                 break;
4512         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4513                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4514                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4515                 break;
4516         default:
4517                 snprintf(desc, size, _goya_get_event_desc(event_type));
4518                 break;
4519         }
4520 }
4521
4522 static void goya_print_razwi_info(struct hl_device *hdev)
4523 {
4524         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4525                 dev_err(hdev->dev, "Illegal write to LBW\n");
4526                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4527         }
4528
4529         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4530                 dev_err(hdev->dev, "Illegal read from LBW\n");
4531                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4532         }
4533
4534         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4535                 dev_err(hdev->dev, "Illegal write to HBW\n");
4536                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4537         }
4538
4539         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4540                 dev_err(hdev->dev, "Illegal read from HBW\n");
4541                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4542         }
4543 }
4544
4545 static void goya_print_mmu_error_info(struct hl_device *hdev)
4546 {
4547         struct goya_device *goya = hdev->asic_specific;
4548         u64 addr;
4549         u32 val;
4550
4551         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4552                 return;
4553
4554         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4555         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4556                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4557                 addr <<= 32;
4558                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4559
4560                 dev_err(hdev->dev, "MMU page fault on va 0x%llx\n", addr);
4561
4562                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4563         }
4564 }
4565
4566 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type)
4567 {
4568         char desc[20] = "";
4569
4570         goya_get_event_desc(event_type, desc, sizeof(desc));
4571         dev_err(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4572                 event_type, desc);
4573
4574         goya_print_razwi_info(hdev);
4575         goya_print_mmu_error_info(hdev);
4576 }
4577
4578 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4579                 size_t irq_arr_size)
4580 {
4581         struct armcp_unmask_irq_arr_packet *pkt;
4582         size_t total_pkt_size;
4583         long result;
4584         int rc;
4585
4586         total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) +
4587                         irq_arr_size;
4588
4589         /* data should be aligned to 8 bytes in order to ArmCP to copy it */
4590         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4591
4592         /* total_pkt_size is casted to u16 later on */
4593         if (total_pkt_size > USHRT_MAX) {
4594                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4595                 return -EINVAL;
4596         }
4597
4598         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4599         if (!pkt)
4600                 return -ENOMEM;
4601
4602         pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0]));
4603         memcpy(&pkt->irqs, irq_arr, irq_arr_size);
4604
4605         pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4606                                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4607
4608         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4609                         total_pkt_size, HL_DEVICE_TIMEOUT_USEC, &result);
4610
4611         if (rc)
4612                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4613
4614         kfree(pkt);
4615
4616         return rc;
4617 }
4618
4619 static int goya_soft_reset_late_init(struct hl_device *hdev)
4620 {
4621         /*
4622          * Unmask all IRQs since some could have been received
4623          * during the soft reset
4624          */
4625         return goya_unmask_irq_arr(hdev, goya_non_fatal_events,
4626                         sizeof(goya_non_fatal_events));
4627 }
4628
4629 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4630 {
4631         struct armcp_packet pkt;
4632         long result;
4633         int rc;
4634
4635         memset(&pkt, 0, sizeof(pkt));
4636
4637         pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ <<
4638                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4639         pkt.value = cpu_to_le64(event_type);
4640
4641         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4642                         HL_DEVICE_TIMEOUT_USEC, &result);
4643
4644         if (rc)
4645                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4646
4647         return rc;
4648 }
4649
4650 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4651 {
4652         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4653         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4654                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4655         struct goya_device *goya = hdev->asic_specific;
4656
4657         goya->events_stat[event_type]++;
4658
4659         switch (event_type) {
4660         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4661         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4662         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4663         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4664         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4665         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4666         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4667         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4668         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4669         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4670         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4671         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4672         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4673         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4674         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4675         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4676         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4677         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4678         case GOYA_ASYNC_EVENT_ID_GIC500:
4679         case GOYA_ASYNC_EVENT_ID_PLL0:
4680         case GOYA_ASYNC_EVENT_ID_PLL1:
4681         case GOYA_ASYNC_EVENT_ID_PLL3:
4682         case GOYA_ASYNC_EVENT_ID_PLL4:
4683         case GOYA_ASYNC_EVENT_ID_PLL5:
4684         case GOYA_ASYNC_EVENT_ID_PLL6:
4685         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4686         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4687         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4688         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4689                 dev_err(hdev->dev,
4690                         "Received H/W interrupt %d, reset the chip\n",
4691                         event_type);
4692                 hl_device_reset(hdev, true, false);
4693                 break;
4694
4695         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4696         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4697         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4698         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4699         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4700         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4701         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4702         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4703         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4704         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4705         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4706         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4707         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4708         case GOYA_ASYNC_EVENT_ID_PSOC:
4709         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4710         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4711         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4712         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4713         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4714         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4715         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4716         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4717         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4718         case GOYA_ASYNC_EVENT_ID_MME_QM:
4719         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4720         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4721         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4722                 goya_print_irq_info(hdev, event_type);
4723                 goya_unmask_irq(hdev, event_type);
4724                 break;
4725
4726         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4727         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4728         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4729         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4730         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4731         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4732         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4733         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4734         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0:
4735         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH1:
4736         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH2:
4737         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH3:
4738         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4739                 dev_info(hdev->dev, "Received H/W interrupt %d\n", event_type);
4740                 break;
4741
4742         default:
4743                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4744                                 event_type);
4745                 break;
4746         }
4747 }
4748
4749 void *goya_get_events_stat(struct hl_device *hdev, u32 *size)
4750 {
4751         struct goya_device *goya = hdev->asic_specific;
4752
4753         *size = (u32) sizeof(goya->events_stat);
4754
4755         return goya->events_stat;
4756 }
4757
4758 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u32 size,
4759                                 u64 val, bool is_dram)
4760 {
4761         struct packet_lin_dma *lin_dma_pkt;
4762         struct hl_cs_parser parser;
4763         struct hl_cs_job *job;
4764         u32 cb_size, ctl;
4765         struct hl_cb *cb;
4766         int rc;
4767
4768         cb = hl_cb_kernel_create(hdev, PAGE_SIZE);
4769         if (!cb)
4770                 return -EFAULT;
4771
4772         lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address;
4773
4774         memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4775         cb_size = sizeof(*lin_dma_pkt);
4776
4777         ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4778                         (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4779                         (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4780                         (1 << GOYA_PKT_CTL_RB_SHIFT) |
4781                         (1 << GOYA_PKT_CTL_MB_SHIFT));
4782         ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4783                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4784         lin_dma_pkt->ctl = cpu_to_le32(ctl);
4785
4786         lin_dma_pkt->src_addr = cpu_to_le64(val);
4787         lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4788         lin_dma_pkt->tsize = cpu_to_le32(size);
4789
4790         job = hl_cs_allocate_job(hdev, true);
4791         if (!job) {
4792                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4793                 rc = -ENOMEM;
4794                 goto release_cb;
4795         }
4796
4797         job->id = 0;
4798         job->user_cb = cb;
4799         job->user_cb->cs_cnt++;
4800         job->user_cb_size = cb_size;
4801         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4802
4803         hl_debugfs_add_job(hdev, job);
4804
4805         parser.ctx_id = HL_KERNEL_ASID_ID;
4806         parser.cs_sequence = 0;
4807         parser.job_id = job->id;
4808         parser.hw_queue_id = job->hw_queue_id;
4809         parser.job_userptr_list = &job->userptr_list;
4810         parser.user_cb = job->user_cb;
4811         parser.user_cb_size = job->user_cb_size;
4812         parser.ext_queue = job->ext_queue;
4813         parser.use_virt_addr = hdev->mmu_enable;
4814
4815         rc = hdev->asic_funcs->cs_parser(hdev, &parser);
4816         if (rc) {
4817                 dev_err(hdev->dev, "Failed to parse kernel CB\n");
4818                 goto free_job;
4819         }
4820
4821         job->patched_cb = parser.patched_cb;
4822         job->job_cb_size = parser.patched_cb_size;
4823         job->patched_cb->cs_cnt++;
4824
4825         rc = goya_send_job_on_qman0(hdev, job);
4826
4827         job->patched_cb->cs_cnt--;
4828         hl_cb_put(job->patched_cb);
4829
4830 free_job:
4831         hl_userptr_delete_list(hdev, &job->userptr_list);
4832         hl_debugfs_remove_job(hdev, job);
4833         kfree(job);
4834         cb->cs_cnt--;
4835
4836 release_cb:
4837         hl_cb_put(cb);
4838         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4839
4840         return rc;
4841 }
4842
4843 static int goya_context_switch(struct hl_device *hdev, u32 asid)
4844 {
4845         struct asic_fixed_properties *prop = &hdev->asic_prop;
4846         u64 addr = prop->sram_base_address;
4847         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4848         u64 val = 0x7777777777777777ull;
4849         int rc;
4850
4851         rc = goya_memset_device_memory(hdev, addr, size, val, false);
4852         if (rc) {
4853                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4854                 return rc;
4855         }
4856
4857         goya_mmu_prepare(hdev, asid);
4858
4859         return 0;
4860 }
4861
4862 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4863 {
4864         struct asic_fixed_properties *prop = &hdev->asic_prop;
4865         struct goya_device *goya = hdev->asic_specific;
4866         u64 addr = prop->mmu_pgt_addr;
4867         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
4868                         MMU_CACHE_MNG_SIZE;
4869
4870         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4871                 return 0;
4872
4873         return goya_memset_device_memory(hdev, addr, size, 0, true);
4874 }
4875
4876 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4877 {
4878         struct goya_device *goya = hdev->asic_specific;
4879         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4880         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
4881         u64 val = 0x9999999999999999ull;
4882
4883         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4884                 return 0;
4885
4886         return goya_memset_device_memory(hdev, addr, size, val, true);
4887 }
4888
4889 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
4890 {
4891         struct goya_device *goya = hdev->asic_specific;
4892         int i;
4893
4894         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4895                 return;
4896
4897         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
4898                 WARN(1, "asid %u is too big\n", asid);
4899                 return;
4900         }
4901
4902         /* zero the MMBP and ASID bits and then set the ASID */
4903         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++) {
4904                 WREG32_AND(goya_mmu_regs[i], ~0x7FF);
4905                 WREG32_OR(goya_mmu_regs[i], asid);
4906         }
4907 }
4908
4909 static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard)
4910 {
4911         struct goya_device *goya = hdev->asic_specific;
4912         u32 status, timeout_usec;
4913         int rc;
4914
4915         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4916                 return;
4917
4918         /* no need in L1 only invalidation in Goya */
4919         if (!is_hard)
4920                 return;
4921
4922         if (hdev->pldm)
4923                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4924         else
4925                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4926
4927         mutex_lock(&hdev->mmu_cache_lock);
4928
4929         /* L0 & L1 invalidation */
4930         WREG32(mmSTLB_INV_ALL_START, 1);
4931
4932         rc = hl_poll_timeout(
4933                 hdev,
4934                 mmSTLB_INV_ALL_START,
4935                 status,
4936                 !status,
4937                 1000,
4938                 timeout_usec);
4939
4940         mutex_unlock(&hdev->mmu_cache_lock);
4941
4942         if (rc)
4943                 dev_notice_ratelimited(hdev->dev,
4944                         "Timeout when waiting for MMU cache invalidation\n");
4945 }
4946
4947 static void goya_mmu_invalidate_cache_range(struct hl_device *hdev,
4948                 bool is_hard, u32 asid, u64 va, u64 size)
4949 {
4950         struct goya_device *goya = hdev->asic_specific;
4951         u32 status, timeout_usec, inv_data, pi;
4952         int rc;
4953
4954         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4955                 return;
4956
4957         /* no need in L1 only invalidation in Goya */
4958         if (!is_hard)
4959                 return;
4960
4961         if (hdev->pldm)
4962                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4963         else
4964                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4965
4966         mutex_lock(&hdev->mmu_cache_lock);
4967
4968         /*
4969          * TODO: currently invalidate entire L0 & L1 as in regular hard
4970          * invalidation. Need to apply invalidation of specific cache lines with
4971          * mask of ASID & VA & size.
4972          * Note that L1 with be flushed entirely in any case.
4973          */
4974
4975         /* L0 & L1 invalidation */
4976         inv_data = RREG32(mmSTLB_CACHE_INV);
4977         /* PI is 8 bit */
4978         pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF;
4979         WREG32(mmSTLB_CACHE_INV,
4980                         (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi);
4981
4982         rc = hl_poll_timeout(
4983                 hdev,
4984                 mmSTLB_INV_CONSUMER_INDEX,
4985                 status,
4986                 status == pi,
4987                 1000,
4988                 timeout_usec);
4989
4990         mutex_unlock(&hdev->mmu_cache_lock);
4991
4992         if (rc)
4993                 dev_notice_ratelimited(hdev->dev,
4994                         "Timeout when waiting for MMU cache invalidation\n");
4995 }
4996
4997 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
4998                                                 u64 phys_addr)
4999 {
5000         u32 status, timeout_usec;
5001         int rc;
5002
5003         if (hdev->pldm)
5004                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5005         else
5006                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5007
5008         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
5009         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
5010         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
5011
5012         rc = hl_poll_timeout(
5013                 hdev,
5014                 MMU_ASID_BUSY,
5015                 status,
5016                 !(status & 0x80000000),
5017                 1000,
5018                 timeout_usec);
5019
5020         if (rc) {
5021                 dev_err(hdev->dev,
5022                         "Timeout during MMU hop0 config of asid %d\n", asid);
5023                 return rc;
5024         }
5025
5026         return 0;
5027 }
5028
5029 int goya_send_heartbeat(struct hl_device *hdev)
5030 {
5031         struct goya_device *goya = hdev->asic_specific;
5032         struct armcp_packet hb_pkt;
5033         long result;
5034         int rc;
5035
5036         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5037                 return 0;
5038
5039         memset(&hb_pkt, 0, sizeof(hb_pkt));
5040
5041         hb_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST <<
5042                                         ARMCP_PKT_CTL_OPCODE_SHIFT);
5043         hb_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL);
5044
5045         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &hb_pkt,
5046                         sizeof(hb_pkt), HL_DEVICE_TIMEOUT_USEC, &result);
5047
5048         if ((rc) || (result != ARMCP_PACKET_FENCE_VAL))
5049                 rc = -EIO;
5050
5051         return rc;
5052 }
5053
5054 static int goya_armcp_info_get(struct hl_device *hdev)
5055 {
5056         struct goya_device *goya = hdev->asic_specific;
5057         struct asic_fixed_properties *prop = &hdev->asic_prop;
5058         struct armcp_packet pkt;
5059         void *armcp_info_cpu_addr;
5060         dma_addr_t armcp_info_dma_addr;
5061         u64 dram_size;
5062         long result;
5063         int rc;
5064
5065         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5066                 return 0;
5067
5068         armcp_info_cpu_addr =
5069                         hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev,
5070                         sizeof(struct armcp_info), &armcp_info_dma_addr);
5071         if (!armcp_info_cpu_addr) {
5072                 dev_err(hdev->dev,
5073                         "Failed to allocate DMA memory for ArmCP info packet\n");
5074                 return -ENOMEM;
5075         }
5076
5077         memset(armcp_info_cpu_addr, 0, sizeof(struct armcp_info));
5078
5079         memset(&pkt, 0, sizeof(pkt));
5080
5081         pkt.ctl = cpu_to_le32(ARMCP_PACKET_INFO_GET <<
5082                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
5083         pkt.addr = cpu_to_le64(armcp_info_dma_addr +
5084                                 prop->host_phys_base_address);
5085         pkt.data_max_size = cpu_to_le32(sizeof(struct armcp_info));
5086
5087         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
5088                         GOYA_ARMCP_INFO_TIMEOUT, &result);
5089
5090         if (rc) {
5091                 dev_err(hdev->dev,
5092                         "Failed to send armcp info pkt, error %d\n", rc);
5093                 goto out;
5094         }
5095
5096         memcpy(&prop->armcp_info, armcp_info_cpu_addr,
5097                         sizeof(prop->armcp_info));
5098
5099         dram_size = le64_to_cpu(prop->armcp_info.dram_size);
5100         if (dram_size) {
5101                 if ((!is_power_of_2(dram_size)) ||
5102                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5103                         dev_err(hdev->dev,
5104                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5105                                 dram_size);
5106                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
5107                 }
5108
5109                 prop->dram_size = dram_size;
5110                 prop->dram_end_address = prop->dram_base_address + dram_size;
5111         }
5112
5113         rc = hl_build_hwmon_channel_info(hdev, prop->armcp_info.sensors);
5114         if (rc) {
5115                 dev_err(hdev->dev,
5116                         "Failed to build hwmon channel info, error %d\n", rc);
5117                 rc = -EFAULT;
5118                 goto out;
5119         }
5120
5121 out:
5122         hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev,
5123                         sizeof(struct armcp_info), armcp_info_cpu_addr);
5124
5125         return rc;
5126 }
5127
5128 static void goya_init_clock_gating(struct hl_device *hdev)
5129 {
5130
5131 }
5132
5133 static void goya_disable_clock_gating(struct hl_device *hdev)
5134 {
5135
5136 }
5137
5138 static bool goya_is_device_idle(struct hl_device *hdev)
5139 {
5140         u64 offset, dma_qm_reg, tpc_qm_reg, tpc_cmdq_reg, tpc_cfg_reg;
5141         int i;
5142
5143         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5144
5145         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5146                 dma_qm_reg = mmDMA_QM_0_GLBL_STS0 + i * offset;
5147
5148                 if ((RREG32(dma_qm_reg) & DMA_QM_IDLE_MASK) !=
5149                                 DMA_QM_IDLE_MASK)
5150                         return false;
5151         }
5152
5153         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5154
5155         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5156                 tpc_qm_reg = mmTPC0_QM_GLBL_STS0 + i * offset;
5157                 tpc_cmdq_reg = mmTPC0_CMDQ_GLBL_STS0 + i * offset;
5158                 tpc_cfg_reg = mmTPC0_CFG_STATUS + i * offset;
5159
5160                 if ((RREG32(tpc_qm_reg) & TPC_QM_IDLE_MASK) !=
5161                                 TPC_QM_IDLE_MASK)
5162                         return false;
5163
5164                 if ((RREG32(tpc_cmdq_reg) & TPC_CMDQ_IDLE_MASK) !=
5165                                 TPC_CMDQ_IDLE_MASK)
5166                         return false;
5167
5168                 if ((RREG32(tpc_cfg_reg) & TPC_CFG_IDLE_MASK) !=
5169                                 TPC_CFG_IDLE_MASK)
5170                         return false;
5171         }
5172
5173         if ((RREG32(mmMME_QM_GLBL_STS0) & MME_QM_IDLE_MASK) !=
5174                         MME_QM_IDLE_MASK)
5175                 return false;
5176
5177         if ((RREG32(mmMME_CMDQ_GLBL_STS0) & MME_CMDQ_IDLE_MASK) !=
5178                         MME_CMDQ_IDLE_MASK)
5179                 return false;
5180
5181         if ((RREG32(mmMME_ARCH_STATUS) & MME_ARCH_IDLE_MASK) !=
5182                         MME_ARCH_IDLE_MASK)
5183                 return false;
5184
5185         if (RREG32(mmMME_SHADOW_0_STATUS) & MME_SHADOW_IDLE_MASK)
5186                 return false;
5187
5188         return true;
5189 }
5190
5191 static void goya_hw_queues_lock(struct hl_device *hdev)
5192 {
5193         struct goya_device *goya = hdev->asic_specific;
5194
5195         spin_lock(&goya->hw_queues_lock);
5196 }
5197
5198 static void goya_hw_queues_unlock(struct hl_device *hdev)
5199 {
5200         struct goya_device *goya = hdev->asic_specific;
5201
5202         spin_unlock(&goya->hw_queues_lock);
5203 }
5204
5205 static u32 goya_get_pci_id(struct hl_device *hdev)
5206 {
5207         return hdev->pdev->device;
5208 }
5209
5210 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5211                                 size_t max_size)
5212 {
5213         struct goya_device *goya = hdev->asic_specific;
5214         struct asic_fixed_properties *prop = &hdev->asic_prop;
5215         struct armcp_packet pkt;
5216         void *eeprom_info_cpu_addr;
5217         dma_addr_t eeprom_info_dma_addr;
5218         long result;
5219         int rc;
5220
5221         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5222                 return 0;
5223
5224         eeprom_info_cpu_addr =
5225                         hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev,
5226                                         max_size, &eeprom_info_dma_addr);
5227         if (!eeprom_info_cpu_addr) {
5228                 dev_err(hdev->dev,
5229                         "Failed to allocate DMA memory for EEPROM info packet\n");
5230                 return -ENOMEM;
5231         }
5232
5233         memset(eeprom_info_cpu_addr, 0, max_size);
5234
5235         memset(&pkt, 0, sizeof(pkt));
5236
5237         pkt.ctl = cpu_to_le32(ARMCP_PACKET_EEPROM_DATA_GET <<
5238                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
5239         pkt.addr = cpu_to_le64(eeprom_info_dma_addr +
5240                                 prop->host_phys_base_address);
5241         pkt.data_max_size = cpu_to_le32(max_size);
5242
5243         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
5244                         GOYA_ARMCP_EEPROM_TIMEOUT, &result);
5245
5246         if (rc) {
5247                 dev_err(hdev->dev,
5248                         "Failed to send armcp EEPROM pkt, error %d\n", rc);
5249                 goto out;
5250         }
5251
5252         /* result contains the actual size */
5253         memcpy(data, eeprom_info_cpu_addr, min((size_t)result, max_size));
5254
5255 out:
5256         hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, max_size,
5257                         eeprom_info_cpu_addr);
5258
5259         return rc;
5260 }
5261
5262 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
5263 {
5264         return RREG32(mmPSOC_GLOBAL_CONF_APP_STATUS);
5265 }
5266
5267 static const struct hl_asic_funcs goya_funcs = {
5268         .early_init = goya_early_init,
5269         .early_fini = goya_early_fini,
5270         .late_init = goya_late_init,
5271         .late_fini = goya_late_fini,
5272         .sw_init = goya_sw_init,
5273         .sw_fini = goya_sw_fini,
5274         .hw_init = goya_hw_init,
5275         .hw_fini = goya_hw_fini,
5276         .halt_engines = goya_halt_engines,
5277         .suspend = goya_suspend,
5278         .resume = goya_resume,
5279         .cb_mmap = goya_cb_mmap,
5280         .ring_doorbell = goya_ring_doorbell,
5281         .flush_pq_write = goya_flush_pq_write,
5282         .dma_alloc_coherent = goya_dma_alloc_coherent,
5283         .dma_free_coherent = goya_dma_free_coherent,
5284         .get_int_queue_base = goya_get_int_queue_base,
5285         .test_queues = goya_test_queues,
5286         .dma_pool_zalloc = goya_dma_pool_zalloc,
5287         .dma_pool_free = goya_dma_pool_free,
5288         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5289         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5290         .hl_dma_unmap_sg = goya_dma_unmap_sg,
5291         .cs_parser = goya_cs_parser,
5292         .asic_dma_map_sg = goya_dma_map_sg,
5293         .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5294         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5295         .update_eq_ci = goya_update_eq_ci,
5296         .context_switch = goya_context_switch,
5297         .restore_phase_topology = goya_restore_phase_topology,
5298         .debugfs_read32 = goya_debugfs_read32,
5299         .debugfs_write32 = goya_debugfs_write32,
5300         .add_device_attr = goya_add_device_attr,
5301         .handle_eqe = goya_handle_eqe,
5302         .set_pll_profile = goya_set_pll_profile,
5303         .get_events_stat = goya_get_events_stat,
5304         .read_pte = goya_read_pte,
5305         .write_pte = goya_write_pte,
5306         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5307         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5308         .send_heartbeat = goya_send_heartbeat,
5309         .enable_clock_gating = goya_init_clock_gating,
5310         .disable_clock_gating = goya_disable_clock_gating,
5311         .is_device_idle = goya_is_device_idle,
5312         .soft_reset_late_init = goya_soft_reset_late_init,
5313         .hw_queues_lock = goya_hw_queues_lock,
5314         .hw_queues_unlock = goya_hw_queues_unlock,
5315         .get_pci_id = goya_get_pci_id,
5316         .get_eeprom_data = goya_get_eeprom_data,
5317         .send_cpu_message = goya_send_cpu_message,
5318         .get_hw_state = goya_get_hw_state
5319 };
5320
5321 /*
5322  * goya_set_asic_funcs - set Goya function pointers
5323  *
5324  * @*hdev: pointer to hl_device structure
5325  *
5326  */
5327 void goya_set_asic_funcs(struct hl_device *hdev)
5328 {
5329         hdev->asic_funcs = &goya_funcs;
5330 }