drivers/misc/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2019 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "include/hw_ip/mmu/mmu_general.h"
  10 #include "include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "include/goya/asic_reg/goya_masks.h"
  12
  13 #include <linux/pci.h>
  14 #include <linux/genalloc.h>
  15 #include <linux/firmware.h>
  16 #include <linux/hwmon.h>
  17 #include <linux/io-64-nonatomic-lo-hi.h>
  18 #include <linux/io-64-nonatomic-hi-lo.h>
  19
  20 /*
  21  * GOYA security scheme:
  22  *
  23  * 1. Host is protected by:
  24  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  25  *        - MMU
  26  *
  27  * 2. DRAM is protected by:
  28  *        - Range registers (protect the first 512MB)
  29  *        - MMU (isolation between users)
  30  *
  31  * 3. Configuration is protected by:
  32  *        - Range registers
  33  *        - Protection bits
  34  *
  35  * When MMU is disabled:
  36  *
  37  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  38  * PQ, CB and the data are on the host.
  39  *
  40  * QMAN TPC/MME:
  41  * PQ, CQ and CP are not secured.
  42  * PQ, CB and the data are on the SRAM/DRAM.
  43  *
  44  * Since QMAN DMA is secured, KMD is parsing the DMA CB:
  45  *     - KMD checks DMA pointer
  46  *     - WREG, MSG_PROT are not allowed.
  47  *     - MSG_LONG/SHORT are allowed.
  48  *
  49  * A read/write transaction by the QMAN to a protected area will succeed if
  50  * and only if the QMAN's CP is secured and MSG_PROT is used
  51  *
  52  *
  53  * When MMU is enabled:
  54  *
  55  * QMAN DMA: PQ, CQ and CP are secured.
  56  * MMU is set to bypass on the Secure props register of the QMAN.
  57  * The reasons we don't enable MMU for PQ, CQ and CP are:
  58  *     - PQ entry is in kernel address space and KMD doesn't map it.
  59  *     - CP writes to MSIX register and to kernel address space (completion
  60  *       queue).
  61  *
  62  * DMA is not secured but because CP is secured, KMD still needs to parse the
  63  * CB, but doesn't need to check the DMA addresses.
  64  *
  65  * For QMAN DMA 0, DMA is also secured because only KMD uses this DMA and KMD
  66  * doesn't map memory in MMU.
  67  *
  68  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  69  *
  70  * DMA RR does NOT protect host because DMA is not secured
  71  *
  72  */
  73
  74 #define GOYA_MMU_REGS_NUM               61
  75
  76 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  77
  78 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  79 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  80 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  81 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  82 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  83 #define GOYA_CPU_TIMEOUT_USEC           10000000        /* 10s */
  84 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  85 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  86 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  87
  88 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  89
  90 #define GOYA_MAX_INITIATORS             20
  91
  92 #define GOYA_MAX_STRING_LEN             20
  93
  94 #define GOYA_CB_POOL_CB_CNT             512
  95 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  96
  97 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
  98                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
  99                 "goya cq 4", "goya cpu eq"
 100 };
 101
 102 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 103         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
 104         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 105         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 106         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 107         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 108         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 109         [PACKET_FENCE]          = sizeof(struct packet_fence),
 110         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 111         [PACKET_NOP]            = sizeof(struct packet_nop),
 112         [PACKET_STOP]           = sizeof(struct packet_stop)
 113 };
 114
 115 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 116         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 117         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 118         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 119         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 120         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 121         mmTPC0_QM_GLBL_SECURE_PROPS,
 122         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 123         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 124         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 125         mmTPC0_CFG_ARUSER,
 126         mmTPC0_CFG_AWUSER,
 127         mmTPC1_QM_GLBL_SECURE_PROPS,
 128         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 129         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 130         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 131         mmTPC1_CFG_ARUSER,
 132         mmTPC1_CFG_AWUSER,
 133         mmTPC2_QM_GLBL_SECURE_PROPS,
 134         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 135         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 136         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 137         mmTPC2_CFG_ARUSER,
 138         mmTPC2_CFG_AWUSER,
 139         mmTPC3_QM_GLBL_SECURE_PROPS,
 140         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 141         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 142         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 143         mmTPC3_CFG_ARUSER,
 144         mmTPC3_CFG_AWUSER,
 145         mmTPC4_QM_GLBL_SECURE_PROPS,
 146         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 147         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 148         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 149         mmTPC4_CFG_ARUSER,
 150         mmTPC4_CFG_AWUSER,
 151         mmTPC5_QM_GLBL_SECURE_PROPS,
 152         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 153         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 154         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 155         mmTPC5_CFG_ARUSER,
 156         mmTPC5_CFG_AWUSER,
 157         mmTPC6_QM_GLBL_SECURE_PROPS,
 158         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 159         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 160         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 161         mmTPC6_CFG_ARUSER,
 162         mmTPC6_CFG_AWUSER,
 163         mmTPC7_QM_GLBL_SECURE_PROPS,
 164         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 165         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 166         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 167         mmTPC7_CFG_ARUSER,
 168         mmTPC7_CFG_AWUSER,
 169         mmMME_QM_GLBL_SECURE_PROPS,
 170         mmMME_QM_GLBL_NON_SECURE_PROPS,
 171         mmMME_CMDQ_GLBL_SECURE_PROPS,
 172         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 173         mmMME_SBA_CONTROL_DATA,
 174         mmMME_SBB_CONTROL_DATA,
 175         mmMME_SBC_CONTROL_DATA,
 176         mmMME_WBC_CONTROL_DATA
 177 };
 178
 179 #define GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE 121
 180
 181 static u32 goya_non_fatal_events[GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE] = {
 182         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 183         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 184         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 185         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 186         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 187         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 188         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 189         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 190         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 191         GOYA_ASYNC_EVENT_ID_MME_ECC,
 192         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 193         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 194         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 195         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 196         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 197         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 198         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 199         GOYA_ASYNC_EVENT_ID_SRAM0,
 200         GOYA_ASYNC_EVENT_ID_SRAM1,
 201         GOYA_ASYNC_EVENT_ID_SRAM2,
 202         GOYA_ASYNC_EVENT_ID_SRAM3,
 203         GOYA_ASYNC_EVENT_ID_SRAM4,
 204         GOYA_ASYNC_EVENT_ID_SRAM5,
 205         GOYA_ASYNC_EVENT_ID_SRAM6,
 206         GOYA_ASYNC_EVENT_ID_SRAM7,
 207         GOYA_ASYNC_EVENT_ID_SRAM8,
 208         GOYA_ASYNC_EVENT_ID_SRAM9,
 209         GOYA_ASYNC_EVENT_ID_SRAM10,
 210         GOYA_ASYNC_EVENT_ID_SRAM11,
 211         GOYA_ASYNC_EVENT_ID_SRAM12,
 212         GOYA_ASYNC_EVENT_ID_SRAM13,
 213         GOYA_ASYNC_EVENT_ID_SRAM14,
 214         GOYA_ASYNC_EVENT_ID_SRAM15,
 215         GOYA_ASYNC_EVENT_ID_SRAM16,
 216         GOYA_ASYNC_EVENT_ID_SRAM17,
 217         GOYA_ASYNC_EVENT_ID_SRAM18,
 218         GOYA_ASYNC_EVENT_ID_SRAM19,
 219         GOYA_ASYNC_EVENT_ID_SRAM20,
 220         GOYA_ASYNC_EVENT_ID_SRAM21,
 221         GOYA_ASYNC_EVENT_ID_SRAM22,
 222         GOYA_ASYNC_EVENT_ID_SRAM23,
 223         GOYA_ASYNC_EVENT_ID_SRAM24,
 224         GOYA_ASYNC_EVENT_ID_SRAM25,
 225         GOYA_ASYNC_EVENT_ID_SRAM26,
 226         GOYA_ASYNC_EVENT_ID_SRAM27,
 227         GOYA_ASYNC_EVENT_ID_SRAM28,
 228         GOYA_ASYNC_EVENT_ID_SRAM29,
 229         GOYA_ASYNC_EVENT_ID_GIC500,
 230         GOYA_ASYNC_EVENT_ID_PLL0,
 231         GOYA_ASYNC_EVENT_ID_PLL1,
 232         GOYA_ASYNC_EVENT_ID_PLL3,
 233         GOYA_ASYNC_EVENT_ID_PLL4,
 234         GOYA_ASYNC_EVENT_ID_PLL5,
 235         GOYA_ASYNC_EVENT_ID_PLL6,
 236         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 237         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 238         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 239         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 240         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 241         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 242         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 243         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 244         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 245         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 246         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 247         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 248         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 249         GOYA_ASYNC_EVENT_ID_MME_WACS,
 250         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 251         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 252         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 253         GOYA_ASYNC_EVENT_ID_PSOC,
 254         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 255         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 256         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 257         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 258         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 259         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 260         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 261         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 262         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 263         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 264         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 265         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 266         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 267         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 268         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 269         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 270         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 271         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 272         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 273         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 274         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 275         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 276         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 277         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 278         GOYA_ASYNC_EVENT_ID_MME_QM,
 279         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 280         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 281         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 282         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 283         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 284         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 285         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 286         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 287         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 288         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 289         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 290         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 291         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 292         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 293         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 294         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 295         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 296         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 297         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 298         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 299         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 300         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 301         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 302         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4
 303 };
 304
 305 static int goya_armcp_info_get(struct hl_device *hdev);
 306 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 307 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 308 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 309 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
 310                                         u64 phys_addr);
 311
 312 static void goya_get_fixed_properties(struct hl_device *hdev)
 313 {
 314         struct asic_fixed_properties *prop = &hdev->asic_prop;
 315         int i;
 316
 317         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 318                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 319                 prop->hw_queues_props[i].kmd_only = 0;
 320         }
 321
 322         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 323                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 324                 prop->hw_queues_props[i].kmd_only = 1;
 325         }
 326
 327         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 328                         NUMBER_OF_INT_HW_QUEUES; i++) {
 329                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 330                 prop->hw_queues_props[i].kmd_only = 0;
 331         }
 332
 333         for (; i < HL_MAX_QUEUES; i++)
 334                 prop->hw_queues_props[i].type = QUEUE_TYPE_NA;
 335
 336         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 337
 338         prop->dram_base_address = DRAM_PHYS_BASE;
 339         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 340         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 341         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 342
 343         prop->sram_base_address = SRAM_BASE_ADDR;
 344         prop->sram_size = SRAM_SIZE;
 345         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 346         prop->sram_user_base_address = prop->sram_base_address +
 347                                                 SRAM_USER_BASE_OFFSET;
 348
 349         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 350         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 351         if (hdev->pldm)
 352                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 353         else
 354                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 355         prop->mmu_pte_size = HL_PTE_SIZE;
 356         prop->mmu_hop_table_size = HOP_TABLE_SIZE;
 357         prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 358         prop->dram_page_size = PAGE_SIZE_2MB;
 359
 360         prop->host_phys_base_address = HOST_PHYS_BASE;
 361         prop->va_space_host_start_address = VA_HOST_SPACE_START;
 362         prop->va_space_host_end_address = VA_HOST_SPACE_END;
 363         prop->va_space_dram_start_address = VA_DDR_SPACE_START;
 364         prop->va_space_dram_end_address = VA_DDR_SPACE_END;
 365         prop->dram_size_for_default_page_mapping =
 366                         prop->va_space_dram_end_address;
 367         prop->cfg_size = CFG_SIZE;
 368         prop->max_asid = MAX_ASID;
 369         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 370         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 371         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 372         prop->max_power_default = MAX_POWER_DEFAULT;
 373         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 374
 375         prop->high_pll = PLL_HIGH_DEFAULT;
 376 }
 377
 378 int goya_send_pci_access_msg(struct hl_device *hdev, u32 opcode)
 379 {
 380         struct armcp_packet pkt;
 381
 382         memset(&pkt, 0, sizeof(pkt));
 383
 384         pkt.ctl = cpu_to_le32(opcode << ARMCP_PKT_CTL_OPCODE_SHIFT);
 385
 386         return hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt,
 387                         sizeof(pkt), HL_DEVICE_TIMEOUT_USEC, NULL);
 388 }
 389
 390 /*
 391  * goya_pci_bars_map - Map PCI BARS of Goya device
 392  *
 393  * @hdev: pointer to hl_device structure
 394  *
 395  * Request PCI regions and map them to kernel virtual addresses.
 396  * Returns 0 on success
 397  *
 398  */
 399 static int goya_pci_bars_map(struct hl_device *hdev)
 400 {
 401         struct pci_dev *pdev = hdev->pdev;
 402         int rc;
 403
 404         rc = pci_request_regions(pdev, HL_NAME);
 405         if (rc) {
 406                 dev_err(hdev->dev, "Cannot obtain PCI resources\n");
 407                 return rc;
 408         }
 409
 410         hdev->pcie_bar[SRAM_CFG_BAR_ID] =
 411                         pci_ioremap_bar(pdev, SRAM_CFG_BAR_ID);
 412         if (!hdev->pcie_bar[SRAM_CFG_BAR_ID]) {
 413                 dev_err(hdev->dev, "pci_ioremap_bar failed for CFG\n");
 414                 rc = -ENODEV;
 415                 goto err_release_regions;
 416         }
 417
 418         hdev->pcie_bar[MSIX_BAR_ID] = pci_ioremap_bar(pdev, MSIX_BAR_ID);
 419         if (!hdev->pcie_bar[MSIX_BAR_ID]) {
 420                 dev_err(hdev->dev, "pci_ioremap_bar failed for MSIX\n");
 421                 rc = -ENODEV;
 422                 goto err_unmap_sram_cfg;
 423         }
 424
 425         hdev->pcie_bar[DDR_BAR_ID] = pci_ioremap_wc_bar(pdev, DDR_BAR_ID);
 426         if (!hdev->pcie_bar[DDR_BAR_ID]) {
 427                 dev_err(hdev->dev, "pci_ioremap_bar failed for DDR\n");
 428                 rc = -ENODEV;
 429                 goto err_unmap_msix;
 430         }
 431
 432         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 433                                 (CFG_BASE - SRAM_BASE_ADDR);
 434
 435         return 0;
 436
 437 err_unmap_msix:
 438         iounmap(hdev->pcie_bar[MSIX_BAR_ID]);
 439 err_unmap_sram_cfg:
 440         iounmap(hdev->pcie_bar[SRAM_CFG_BAR_ID]);
 441 err_release_regions:
 442         pci_release_regions(pdev);
 443
 444         return rc;
 445 }
 446
 447 /*
 448  * goya_pci_bars_unmap - Unmap PCI BARS of Goya device
 449  *
 450  * @hdev: pointer to hl_device structure
 451  *
 452  * Release all PCI BARS and unmap their virtual addresses
 453  *
 454  */
 455 static void goya_pci_bars_unmap(struct hl_device *hdev)
 456 {
 457         struct pci_dev *pdev = hdev->pdev;
 458
 459         iounmap(hdev->pcie_bar[DDR_BAR_ID]);
 460         iounmap(hdev->pcie_bar[MSIX_BAR_ID]);
 461         iounmap(hdev->pcie_bar[SRAM_CFG_BAR_ID]);
 462         pci_release_regions(pdev);
 463 }
 464
 465 /*
 466  * goya_elbi_write - Write through the ELBI interface
 467  *
 468  * @hdev: pointer to hl_device structure
 469  *
 470  * return 0 on success, -1 on failure
 471  *
 472  */
 473 static int goya_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
 474 {
 475         struct pci_dev *pdev = hdev->pdev;
 476         ktime_t timeout;
 477         u32 val;
 478
 479         /* Clear previous status */
 480         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
 481
 482         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
 483         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
 484         pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
 485                                 PCI_CONFIG_ELBI_CTRL_WRITE);
 486
 487         timeout = ktime_add_ms(ktime_get(), 10);
 488         for (;;) {
 489                 pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
 490                 if (val & PCI_CONFIG_ELBI_STS_MASK)
 491                         break;
 492                 if (ktime_compare(ktime_get(), timeout) > 0) {
 493                         pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
 494                                                 &val);
 495                         break;
 496                 }
 497                 usleep_range(300, 500);
 498         }
 499
 500         if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
 501                 return 0;
 502
 503         if (val & PCI_CONFIG_ELBI_STS_ERR) {
 504                 dev_err(hdev->dev, "Error writing to ELBI\n");
 505                 return -EIO;
 506         }
 507
 508         if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
 509                 dev_err(hdev->dev, "ELBI write didn't finish in time\n");
 510                 return -EIO;
 511         }
 512
 513         dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
 514         return -EIO;
 515 }
 516
 517 /*
 518  * goya_iatu_write - iatu write routine
 519  *
 520  * @hdev: pointer to hl_device structure
 521  *
 522  */
 523 static int goya_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
 524 {
 525         u32 dbi_offset;
 526         int rc;
 527
 528         dbi_offset = addr & 0xFFF;
 529
 530         rc = goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0x00300000);
 531         rc |= goya_elbi_write(hdev, mmPCIE_DBI_BASE + dbi_offset, data);
 532
 533         if (rc)
 534                 return -EIO;
 535
 536         return 0;
 537 }
 538
 539 static void goya_reset_link_through_bridge(struct hl_device *hdev)
 540 {
 541         struct pci_dev *pdev = hdev->pdev;
 542         struct pci_dev *parent_port;
 543         u16 val;
 544
 545         parent_port = pdev->bus->self;
 546         pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val);
 547         val |= PCI_BRIDGE_CTL_BUS_RESET;
 548         pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
 549         ssleep(1);
 550
 551         val &= ~(PCI_BRIDGE_CTL_BUS_RESET);
 552         pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
 553         ssleep(3);
 554 }
 555
 556 /*
 557  * goya_set_ddr_bar_base - set DDR bar to map specific device address
 558  *
 559  * @hdev: pointer to hl_device structure
 560  * @addr: address in DDR. Must be aligned to DDR bar size
 561  *
 562  * This function configures the iATU so that the DDR bar will start at the
 563  * specified addr.
 564  *
 565  */
 566 static int goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 567 {
 568         struct goya_device *goya = hdev->asic_specific;
 569         int rc;
 570
 571         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 572                 return 0;
 573
 574         /* Inbound Region 1 - Bar 4 - Point to DDR */
 575         rc = goya_iatu_write(hdev, 0x314, lower_32_bits(addr));
 576         rc |= goya_iatu_write(hdev, 0x318, upper_32_bits(addr));
 577         rc |= goya_iatu_write(hdev, 0x300, 0);
 578         /* Enable + Bar match + match enable + Bar 4 */
 579         rc |= goya_iatu_write(hdev, 0x304, 0xC0080400);
 580
 581         /* Return the DBI window to the default location */
 582         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0);
 583         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI_32, 0);
 584
 585         if (rc) {
 586                 dev_err(hdev->dev, "failed to map DDR bar to 0x%08llx\n", addr);
 587                 return -EIO;
 588         }
 589
 590         if (goya)
 591                 goya->ddr_bar_cur_addr = addr;
 592
 593         return 0;
 594 }
 595
 596 /*
 597  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 598  *
 599  * @hdev: pointer to hl_device structure
 600  *
 601  * This is needed in case the firmware doesn't initialize the iATU
 602  *
 603  */
 604 static int goya_init_iatu(struct hl_device *hdev)
 605 {
 606         int rc;
 607
 608         /* Inbound Region 0 - Bar 0 - Point to SRAM_BASE_ADDR */
 609         rc  = goya_iatu_write(hdev, 0x114, lower_32_bits(SRAM_BASE_ADDR));
 610         rc |= goya_iatu_write(hdev, 0x118, upper_32_bits(SRAM_BASE_ADDR));
 611         rc |= goya_iatu_write(hdev, 0x100, 0);
 612         /* Enable + Bar match + match enable */
 613         rc |= goya_iatu_write(hdev, 0x104, 0xC0080000);
 614
 615         /* Inbound Region 1 - Bar 4 - Point to DDR */
 616         rc |= goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
 617
 618         /* Outbound Region 0 - Point to Host */
 619         rc |= goya_iatu_write(hdev, 0x008, lower_32_bits(HOST_PHYS_BASE));
 620         rc |= goya_iatu_write(hdev, 0x00C, upper_32_bits(HOST_PHYS_BASE));
 621         rc |= goya_iatu_write(hdev, 0x010,
 622                 lower_32_bits(HOST_PHYS_BASE + HOST_PHYS_SIZE - 1));
 623         rc |= goya_iatu_write(hdev, 0x014, 0);
 624         rc |= goya_iatu_write(hdev, 0x018, 0);
 625         rc |= goya_iatu_write(hdev, 0x020,
 626                 upper_32_bits(HOST_PHYS_BASE + HOST_PHYS_SIZE - 1));
 627         /* Increase region size */
 628         rc |= goya_iatu_write(hdev, 0x000, 0x00002000);
 629         /* Enable */
 630         rc |= goya_iatu_write(hdev, 0x004, 0x80000000);
 631
 632         /* Return the DBI window to the default location */
 633         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI, 0);
 634         rc |= goya_elbi_write(hdev, CFG_BASE + mmPCIE_AUX_DBI_32, 0);
 635
 636         if (rc)
 637                 return -EIO;
 638
 639         return 0;
 640 }
 641
 642 /*
 643  * goya_early_init - GOYA early initialization code
 644  *
 645  * @hdev: pointer to hl_device structure
 646  *
 647  * Verify PCI bars
 648  * Set DMA masks
 649  * PCI controller initialization
 650  * Map PCI bars
 651  *
 652  */
 653 static int goya_early_init(struct hl_device *hdev)
 654 {
 655         struct asic_fixed_properties *prop = &hdev->asic_prop;
 656         struct pci_dev *pdev = hdev->pdev;
 657         u32 val;
 658         int rc;
 659
 660         goya_get_fixed_properties(hdev);
 661
 662         /* Check BAR sizes */
 663         if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
 664                 dev_err(hdev->dev,
 665                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 666                         SRAM_CFG_BAR_ID,
 667                         (unsigned long long) pci_resource_len(pdev,
 668                                                         SRAM_CFG_BAR_ID),
 669                         CFG_BAR_SIZE);
 670                 return -ENODEV;
 671         }
 672
 673         if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
 674                 dev_err(hdev->dev,
 675                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 676                         MSIX_BAR_ID,
 677                         (unsigned long long) pci_resource_len(pdev,
 678                                                                 MSIX_BAR_ID),
 679                         MSIX_BAR_SIZE);
 680                 return -ENODEV;
 681         }
 682
 683         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 684
 685         /* set DMA mask for GOYA */
 686         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
 687         if (rc) {
 688                 dev_warn(hdev->dev, "Unable to set pci dma mask to 39 bits\n");
 689                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 690                 if (rc) {
 691                         dev_err(hdev->dev,
 692                                 "Unable to set pci dma mask to 32 bits\n");
 693                         return rc;
 694                 }
 695         }
 696
 697         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
 698         if (rc) {
 699                 dev_warn(hdev->dev,
 700                         "Unable to set pci consistent dma mask to 39 bits\n");
 701                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 702                 if (rc) {
 703                         dev_err(hdev->dev,
 704                                 "Unable to set pci consistent dma mask to 32 bits\n");
 705                         return rc;
 706                 }
 707         }
 708
 709         if (hdev->reset_pcilink)
 710                 goya_reset_link_through_bridge(hdev);
 711
 712         rc = pci_enable_device_mem(pdev);
 713         if (rc) {
 714                 dev_err(hdev->dev, "can't enable PCI device\n");
 715                 return rc;
 716         }
 717
 718         pci_set_master(pdev);
 719
 720         rc = goya_init_iatu(hdev);
 721         if (rc) {
 722                 dev_err(hdev->dev, "Failed to initialize iATU\n");
 723                 goto disable_device;
 724         }
 725
 726         rc = goya_pci_bars_map(hdev);
 727         if (rc) {
 728                 dev_err(hdev->dev, "Failed to initialize PCI BARS\n");
 729                 goto disable_device;
 730         }
 731
 732         if (!hdev->pldm) {
 733                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 734                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 735                         dev_warn(hdev->dev,
 736                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 737         }
 738
 739         return 0;
 740
 741 disable_device:
 742         pci_clear_master(pdev);
 743         pci_disable_device(pdev);
 744
 745         return rc;
 746 }
 747
 748 /*
 749  * goya_early_fini - GOYA early finalization code
 750  *
 751  * @hdev: pointer to hl_device structure
 752  *
 753  * Unmap PCI bars
 754  *
 755  */
 756 static int goya_early_fini(struct hl_device *hdev)
 757 {
 758         goya_pci_bars_unmap(hdev);
 759
 760         pci_clear_master(hdev->pdev);
 761         pci_disable_device(hdev->pdev);
 762
 763         return 0;
 764 }
 765
 766 /*
 767  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 768  *
 769  * @hdev: pointer to hl_device structure
 770  *
 771  */
 772 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 773 {
 774         struct asic_fixed_properties *prop = &hdev->asic_prop;
 775
 776         prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR);
 777         prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF);
 778         prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD);
 779         prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 780 }
 781
 782 /*
 783  * goya_late_init - GOYA late initialization code
 784  *
 785  * @hdev: pointer to hl_device structure
 786  *
 787  * Get ArmCP info and send message to CPU to enable PCI access
 788  */
 789 static int goya_late_init(struct hl_device *hdev)
 790 {
 791         struct asic_fixed_properties *prop = &hdev->asic_prop;
 792         struct goya_device *goya = hdev->asic_specific;
 793         int rc;
 794
 795         rc = goya->armcp_info_get(hdev);
 796         if (rc) {
 797                 dev_err(hdev->dev, "Failed to get armcp info\n");
 798                 return rc;
 799         }
 800
 801         /* Now that we have the DRAM size in ASIC prop, we need to check
 802          * its size and configure the DMA_IF DDR wrap protection (which is in
 803          * the MMU block) accordingly. The value is the log2 of the DRAM size
 804          */
 805         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 806
 807         rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS);
 808         if (rc) {
 809                 dev_err(hdev->dev, "Failed to enable PCI access from CPU\n");
 810                 return rc;
 811         }
 812
 813         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
 814                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
 815
 816         goya_fetch_psoc_frequency(hdev);
 817
 818         rc = goya_mmu_clear_pgt_range(hdev);
 819         if (rc) {
 820                 dev_err(hdev->dev, "Failed to clear MMU page tables range\n");
 821                 goto disable_pci_access;
 822         }
 823
 824         rc = goya_mmu_set_dram_default_page(hdev);
 825         if (rc) {
 826                 dev_err(hdev->dev, "Failed to set DRAM default page\n");
 827                 goto disable_pci_access;
 828         }
 829
 830         return 0;
 831
 832 disable_pci_access:
 833         goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
 834
 835         return rc;
 836 }
 837
 838 /*
 839  * goya_late_fini - GOYA late tear-down code
 840  *
 841  * @hdev: pointer to hl_device structure
 842  *
 843  * Free sensors allocated structures
 844  */
 845 void goya_late_fini(struct hl_device *hdev)
 846 {
 847         const struct hwmon_channel_info **channel_info_arr;
 848         int i = 0;
 849
 850         if (!hdev->hl_chip_info->info)
 851                 return;
 852
 853         channel_info_arr = hdev->hl_chip_info->info;
 854
 855         while (channel_info_arr[i]) {
 856                 kfree(channel_info_arr[i]->config);
 857                 kfree(channel_info_arr[i]);
 858                 i++;
 859         }
 860
 861         kfree(channel_info_arr);
 862
 863         hdev->hl_chip_info->info = NULL;
 864 }
 865
 866 /*
 867  * goya_sw_init - Goya software initialization code
 868  *
 869  * @hdev: pointer to hl_device structure
 870  *
 871  */
 872 static int goya_sw_init(struct hl_device *hdev)
 873 {
 874         struct goya_device *goya;
 875         int rc;
 876
 877         /* Allocate device structure */
 878         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 879         if (!goya)
 880                 return -ENOMEM;
 881
 882         goya->test_cpu_queue = goya_test_cpu_queue;
 883         goya->armcp_info_get = goya_armcp_info_get;
 884
 885         /* according to goya_init_iatu */
 886         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 887
 888         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 889         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 890         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 891
 892         hdev->asic_specific = goya;
 893
 894         /* Create DMA pool for small allocations */
 895         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 896                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 897         if (!hdev->dma_pool) {
 898                 dev_err(hdev->dev, "failed to create DMA pool\n");
 899                 rc = -ENOMEM;
 900                 goto free_goya_device;
 901         }
 902
 903         hdev->cpu_accessible_dma_mem =
 904                         hdev->asic_funcs->dma_alloc_coherent(hdev,
 905                                         CPU_ACCESSIBLE_MEM_SIZE,
 906                                         &hdev->cpu_accessible_dma_address,
 907                                         GFP_KERNEL | __GFP_ZERO);
 908
 909         if (!hdev->cpu_accessible_dma_mem) {
 910                 dev_err(hdev->dev,
 911                         "failed to allocate %d of dma memory for CPU accessible memory space\n",
 912                         CPU_ACCESSIBLE_MEM_SIZE);
 913                 rc = -ENOMEM;
 914                 goto free_dma_pool;
 915         }
 916
 917         hdev->cpu_accessible_dma_pool = gen_pool_create(CPU_PKT_SHIFT, -1);
 918         if (!hdev->cpu_accessible_dma_pool) {
 919                 dev_err(hdev->dev,
 920                         "Failed to create CPU accessible DMA pool\n");
 921                 rc = -ENOMEM;
 922                 goto free_cpu_pq_dma_mem;
 923         }
 924
 925         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
 926                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
 927                                 CPU_ACCESSIBLE_MEM_SIZE, -1);
 928         if (rc) {
 929                 dev_err(hdev->dev,
 930                         "Failed to add memory to CPU accessible DMA pool\n");
 931                 rc = -EFAULT;
 932                 goto free_cpu_pq_pool;
 933         }
 934
 935         spin_lock_init(&goya->hw_queues_lock);
 936
 937         return 0;
 938
 939 free_cpu_pq_pool:
 940         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 941 free_cpu_pq_dma_mem:
 942         hdev->asic_funcs->dma_free_coherent(hdev, CPU_ACCESSIBLE_MEM_SIZE,
 943                         hdev->cpu_accessible_dma_mem,
 944                         hdev->cpu_accessible_dma_address);
 945 free_dma_pool:
 946         dma_pool_destroy(hdev->dma_pool);
 947 free_goya_device:
 948         kfree(goya);
 949
 950         return rc;
 951 }
 952
 953 /*
 954  * goya_sw_fini - Goya software tear-down code
 955  *
 956  * @hdev: pointer to hl_device structure
 957  *
 958  */
 959 static int goya_sw_fini(struct hl_device *hdev)
 960 {
 961         struct goya_device *goya = hdev->asic_specific;
 962
 963         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 964
 965         hdev->asic_funcs->dma_free_coherent(hdev, CPU_ACCESSIBLE_MEM_SIZE,
 966                         hdev->cpu_accessible_dma_mem,
 967                         hdev->cpu_accessible_dma_address);
 968
 969         dma_pool_destroy(hdev->dma_pool);
 970
 971         kfree(goya);
 972
 973         return 0;
 974 }
 975
 976 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
 977                 dma_addr_t bus_address)
 978 {
 979         struct goya_device *goya = hdev->asic_specific;
 980         u32 mtr_base_lo, mtr_base_hi;
 981         u32 so_base_lo, so_base_hi;
 982         u32 gic_base_lo, gic_base_hi;
 983         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
 984
 985         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 986         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 987         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 988         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 989
 990         gic_base_lo =
 991                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 992         gic_base_hi =
 993                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 994
 995         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
 996         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
 997
 998         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
 999         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1000         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1001
1002         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1003         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1004         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1005         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1006         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1007         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1008         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1009                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1010
1011         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1012         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1013         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1014
1015         if (goya->hw_cap_initialized & HW_CAP_MMU)
1016                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1017         else
1018                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1019
1020         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN);
1021         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1022 }
1023
1024 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1025 {
1026         u32 gic_base_lo, gic_base_hi;
1027         u64 sob_addr;
1028         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1029
1030         gic_base_lo =
1031                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1032         gic_base_hi =
1033                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1034
1035         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1036         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1037         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1038                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1039
1040         if (dma_id)
1041                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1042                                 (dma_id - 1) * 4;
1043         else
1044                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1045
1046         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + reg_off, lower_32_bits(sob_addr));
1047         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1048         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1049 }
1050
1051 /*
1052  * goya_init_dma_qmans - Initialize QMAN DMA registers
1053  *
1054  * @hdev: pointer to hl_device structure
1055  *
1056  * Initialize the H/W registers of the QMAN DMA channels
1057  *
1058  */
1059 static void goya_init_dma_qmans(struct hl_device *hdev)
1060 {
1061         struct goya_device *goya = hdev->asic_specific;
1062         struct hl_hw_queue *q;
1063         dma_addr_t bus_address;
1064         int i;
1065
1066         if (goya->hw_cap_initialized & HW_CAP_DMA)
1067                 return;
1068
1069         q = &hdev->kernel_queues[0];
1070
1071         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1072                 bus_address = q->bus_address +
1073                                 hdev->asic_prop.host_phys_base_address;
1074
1075                 goya_init_dma_qman(hdev, i, bus_address);
1076                 goya_init_dma_ch(hdev, i);
1077         }
1078
1079         goya->hw_cap_initialized |= HW_CAP_DMA;
1080 }
1081
1082 /*
1083  * goya_disable_external_queues - Disable external queues
1084  *
1085  * @hdev: pointer to hl_device structure
1086  *
1087  */
1088 static void goya_disable_external_queues(struct hl_device *hdev)
1089 {
1090         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1091         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1092         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1093         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1094         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1095 }
1096
1097 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1098                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
1099 {
1100         int rc;
1101         u32 status;
1102
1103         /* use the values of TPC0 as they are all the same*/
1104
1105         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1106
1107         status = RREG32(cp_sts_reg);
1108         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1109                 rc = hl_poll_timeout(
1110                         hdev,
1111                         cp_sts_reg,
1112                         status,
1113                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1114                         1000,
1115                         QMAN_FENCE_TIMEOUT_USEC);
1116
1117                 /* if QMAN is stuck in fence no need to check for stop */
1118                 if (rc)
1119                         return 0;
1120         }
1121
1122         rc = hl_poll_timeout(
1123                 hdev,
1124                 glbl_sts0_reg,
1125                 status,
1126                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1127                 1000,
1128                 QMAN_STOP_TIMEOUT_USEC);
1129
1130         if (rc) {
1131                 dev_err(hdev->dev,
1132                         "Timeout while waiting for QMAN to stop\n");
1133                 return -EINVAL;
1134         }
1135
1136         return 0;
1137 }
1138
1139 /*
1140  * goya_stop_external_queues - Stop external queues
1141  *
1142  * @hdev: pointer to hl_device structure
1143  *
1144  * Returns 0 on success
1145  *
1146  */
1147 static int goya_stop_external_queues(struct hl_device *hdev)
1148 {
1149         int rc, retval = 0;
1150
1151         rc = goya_stop_queue(hdev,
1152                         mmDMA_QM_0_GLBL_CFG1,
1153                         mmDMA_QM_0_CP_STS,
1154                         mmDMA_QM_0_GLBL_STS0);
1155
1156         if (rc) {
1157                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1158                 retval = -EIO;
1159         }
1160
1161         rc = goya_stop_queue(hdev,
1162                         mmDMA_QM_1_GLBL_CFG1,
1163                         mmDMA_QM_1_CP_STS,
1164                         mmDMA_QM_1_GLBL_STS0);
1165
1166         if (rc) {
1167                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1168                 retval = -EIO;
1169         }
1170
1171         rc = goya_stop_queue(hdev,
1172                         mmDMA_QM_2_GLBL_CFG1,
1173                         mmDMA_QM_2_CP_STS,
1174                         mmDMA_QM_2_GLBL_STS0);
1175
1176         if (rc) {
1177                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1178                 retval = -EIO;
1179         }
1180
1181         rc = goya_stop_queue(hdev,
1182                         mmDMA_QM_3_GLBL_CFG1,
1183                         mmDMA_QM_3_CP_STS,
1184                         mmDMA_QM_3_GLBL_STS0);
1185
1186         if (rc) {
1187                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1188                 retval = -EIO;
1189         }
1190
1191         rc = goya_stop_queue(hdev,
1192                         mmDMA_QM_4_GLBL_CFG1,
1193                         mmDMA_QM_4_CP_STS,
1194                         mmDMA_QM_4_GLBL_STS0);
1195
1196         if (rc) {
1197                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1198                 retval = -EIO;
1199         }
1200
1201         return retval;
1202 }
1203
1204 /*
1205  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1206  *
1207  * @hdev: pointer to hl_device structure
1208  *
1209  * Returns 0 on success
1210  *
1211  */
1212 static int goya_init_cpu_queues(struct hl_device *hdev)
1213 {
1214         struct goya_device *goya = hdev->asic_specific;
1215         struct hl_eq *eq;
1216         dma_addr_t bus_address;
1217         u32 status;
1218         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1219         int err;
1220
1221         if (!hdev->cpu_queues_enable)
1222                 return 0;
1223
1224         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1225                 return 0;
1226
1227         eq = &hdev->event_queue;
1228
1229         bus_address = cpu_pq->bus_address +
1230                         hdev->asic_prop.host_phys_base_address;
1231         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_0, lower_32_bits(bus_address));
1232         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_1, upper_32_bits(bus_address));
1233
1234         bus_address = eq->bus_address + hdev->asic_prop.host_phys_base_address;
1235         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_2, lower_32_bits(bus_address));
1236         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_3, upper_32_bits(bus_address));
1237
1238         bus_address = hdev->cpu_accessible_dma_address +
1239                         hdev->asic_prop.host_phys_base_address;
1240         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_8, lower_32_bits(bus_address));
1241         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_9, upper_32_bits(bus_address));
1242
1243         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_5, HL_QUEUE_SIZE_IN_BYTES);
1244         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_4, HL_EQ_SIZE_IN_BYTES);
1245         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_10, CPU_ACCESSIBLE_MEM_SIZE);
1246
1247         /* Used for EQ CI */
1248         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, 0);
1249
1250         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1251
1252         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_7, PQ_INIT_STATUS_READY_FOR_CP);
1253
1254         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1255                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1256
1257         err = hl_poll_timeout(
1258                 hdev,
1259                 mmPSOC_GLOBAL_CONF_SCRATCHPAD_7,
1260                 status,
1261                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1262                 1000,
1263                 GOYA_CPU_TIMEOUT_USEC);
1264
1265         if (err) {
1266                 dev_err(hdev->dev,
1267                         "Failed to communicate with ARM CPU (ArmCP timeout)\n");
1268                 return -EIO;
1269         }
1270
1271         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1272         return 0;
1273 }
1274
1275 static void goya_set_pll_refclk(struct hl_device *hdev)
1276 {
1277         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1278         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1279         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1280         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1281
1282         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1283         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1284         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1285         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1286
1287         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1288         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1289         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1290         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1291
1292         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1293         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1294         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1295         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1296
1297         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1298         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1299         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1300         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1301
1302         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1303         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1304         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1305         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1306
1307         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1308         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1309         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1310         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1311 }
1312
1313 static void goya_disable_clk_rlx(struct hl_device *hdev)
1314 {
1315         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1316         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1317 }
1318
1319 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1320 {
1321         u64 tpc_eml_address;
1322         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1323         int err, slm_index;
1324
1325         tpc_offset = tpc_id * 0x40000;
1326         tpc_eml_offset = tpc_id * 0x200000;
1327         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1328         tpc_slm_offset = tpc_eml_address + 0x100000;
1329
1330         /*
1331          * Workaround for Bug H2 #2443 :
1332          * "TPC SB is not initialized on chip reset"
1333          */
1334
1335         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1336         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1337                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1338                         tpc_id);
1339
1340         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1341
1342         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1343         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1344         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1345         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1346         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1347         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1348         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1349         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1350         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1351         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1352
1353         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1354                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1355
1356         err = hl_poll_timeout(
1357                 hdev,
1358                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1359                 val,
1360                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1361                 1000,
1362                 HL_DEVICE_TIMEOUT_USEC);
1363
1364         if (err)
1365                 dev_err(hdev->dev,
1366                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1367
1368         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1369                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1370
1371         msleep(GOYA_RESET_WAIT_MSEC);
1372
1373         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1374                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1375
1376         msleep(GOYA_RESET_WAIT_MSEC);
1377
1378         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1379                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1380
1381         val = RREG32(tpc_slm_offset);
1382 }
1383
1384 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1385 {
1386         struct goya_device *goya = hdev->asic_specific;
1387         int i;
1388
1389         if (hdev->pldm)
1390                 return;
1391
1392         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1393                 return;
1394
1395         /* Workaround for H2 #2443 */
1396
1397         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1398                 _goya_tpc_mbist_workaround(hdev, i);
1399
1400         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1401 }
1402
1403 /*
1404  * goya_init_golden_registers - Initialize golden registers
1405  *
1406  * @hdev: pointer to hl_device structure
1407  *
1408  * Initialize the H/W registers of the device
1409  *
1410  */
1411 static void goya_init_golden_registers(struct hl_device *hdev)
1412 {
1413         struct goya_device *goya = hdev->asic_specific;
1414         u32 polynom[10], tpc_intr_mask, offset;
1415         int i;
1416
1417         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1418                 return;
1419
1420         polynom[0] = 0x00020080;
1421         polynom[1] = 0x00401000;
1422         polynom[2] = 0x00200800;
1423         polynom[3] = 0x00002000;
1424         polynom[4] = 0x00080200;
1425         polynom[5] = 0x00040100;
1426         polynom[6] = 0x00100400;
1427         polynom[7] = 0x00004000;
1428         polynom[8] = 0x00010000;
1429         polynom[9] = 0x00008000;
1430
1431         /* Mask all arithmetic interrupts from TPC */
1432         tpc_intr_mask = 0x7FFF;
1433
1434         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1435                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1436                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1437                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1438                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1439                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1440
1441                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1442                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1443                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1444                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1445                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1446
1447
1448                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1449                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1450                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1451                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1452                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1453
1454                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1455                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1456                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1457                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1458                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1459
1460                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1461                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1462                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1463                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1464                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1465
1466                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1467                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1468                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1469                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1470                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1471         }
1472
1473         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1474         WREG32(mmMME_AGU, 0x0f0f0f10);
1475         WREG32(mmMME_SEI_MASK, ~0x0);
1476
1477         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1478         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1479         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1480         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1481         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1482         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1483         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1484         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1485         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1486         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1487         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1488         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1489         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1490         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1491         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1492         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1493         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1494         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1495         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1496         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1497         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1498         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1499         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1500         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1501         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1502         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1503         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1504         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1505         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1506         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1507         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1508         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1509         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1510         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1511         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1512         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1513         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1514         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1515         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1516         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1517         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1518         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1519         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1520         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1521         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1522         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1523         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1524         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1525         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1526         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1527         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1528         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1529         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1530         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1531         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1532         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1533         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1534         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1535         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1536         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1537         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1538         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1539         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1540         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1541         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1542         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1543         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1544         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1545         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1546         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1547         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1548         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1549         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1550         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1551         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1552         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1553         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1554         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1555         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1556         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1557         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1558         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1559         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1560         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1561
1562         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1563         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1564         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1565         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1566         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1567         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1568         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1569         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1570         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1571         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1572         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1573         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1574
1575         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1576         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1577         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1578         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1579         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1580         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1581         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1582         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1583         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1584         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1585         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1586         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1587
1588         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1589         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1590         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1591         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1592         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1593         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1594         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1595         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1596         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1597         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1598         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1599         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1600
1601         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1602         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1603         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1604         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1605         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1606         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1607         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1608         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1609         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1610         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1611         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1612         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1613
1614         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1615         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1616         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1617         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1618         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1619         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1620         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1621         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1622         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1623         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1624         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1625         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1626
1627         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1628         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1629         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1630         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1631         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1632         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1633         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1634         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1635         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1636         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1637         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1638         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1639
1640         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1641                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1642                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1643                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1644                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1645                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1646                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1647
1648                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1649                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1650                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1651                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1652                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1653                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1654                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1655                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1656
1657                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1658                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1659         }
1660
1661         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1662                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1663                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1664                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1665                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1666         }
1667
1668         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1669                 /*
1670                  * Workaround for Bug H2 #2441 :
1671                  * "ST.NOP set trace event illegal opcode"
1672                  */
1673                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1674
1675                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1676                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1677                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1678                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1679         }
1680
1681         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1682         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1683                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1684
1685         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1686         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1687                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1688
1689         /*
1690          * Workaround for H2 #HW-23 bug
1691          * Set DMA max outstanding read requests to 240 on DMA CH 1.
1692          * This limitation is still large enough to not affect Gen4 bandwidth.
1693          * We need to only limit that DMA channel because the user can only read
1694          * from Host using DMA CH 1
1695          */
1696         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1697
1698         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1699 }
1700
1701 static void goya_init_mme_qman(struct hl_device *hdev)
1702 {
1703         u32 mtr_base_lo, mtr_base_hi;
1704         u32 so_base_lo, so_base_hi;
1705         u32 gic_base_lo, gic_base_hi;
1706         u64 qman_base_addr;
1707
1708         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1709         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1710         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1711         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1712
1713         gic_base_lo =
1714                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1715         gic_base_hi =
1716                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1717
1718         qman_base_addr = hdev->asic_prop.sram_base_address +
1719                                 MME_QMAN_BASE_OFFSET;
1720
1721         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1722         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1723         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1724         WREG32(mmMME_QM_PQ_PI, 0);
1725         WREG32(mmMME_QM_PQ_CI, 0);
1726         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1727         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1728         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1729         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1730
1731         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1732         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1733         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1734         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1735
1736         /* QMAN CQ has 8 cache lines */
1737         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1738
1739         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1740         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1741
1742         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1743
1744         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1745
1746         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1747
1748         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1749 }
1750
1751 static void goya_init_mme_cmdq(struct hl_device *hdev)
1752 {
1753         u32 mtr_base_lo, mtr_base_hi;
1754         u32 so_base_lo, so_base_hi;
1755         u32 gic_base_lo, gic_base_hi;
1756         u64 qman_base_addr;
1757
1758         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1759         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1760         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1761         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1762
1763         gic_base_lo =
1764                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1765         gic_base_hi =
1766                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1767
1768         qman_base_addr = hdev->asic_prop.sram_base_address +
1769                                 MME_QMAN_BASE_OFFSET;
1770
1771         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1772         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1773         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1774         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1775
1776         /* CMDQ CQ has 20 cache lines */
1777         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1778
1779         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1780         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1781
1782         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1783
1784         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1785
1786         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1787
1788         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1789 }
1790
1791 static void goya_init_mme_qmans(struct hl_device *hdev)
1792 {
1793         struct goya_device *goya = hdev->asic_specific;
1794         u32 so_base_lo, so_base_hi;
1795
1796         if (goya->hw_cap_initialized & HW_CAP_MME)
1797                 return;
1798
1799         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1800         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1801
1802         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1803         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1804
1805         goya_init_mme_qman(hdev);
1806         goya_init_mme_cmdq(hdev);
1807
1808         goya->hw_cap_initialized |= HW_CAP_MME;
1809 }
1810
1811 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1812 {
1813         u32 mtr_base_lo, mtr_base_hi;
1814         u32 so_base_lo, so_base_hi;
1815         u32 gic_base_lo, gic_base_hi;
1816         u64 qman_base_addr;
1817         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1818
1819         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1820         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1821         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1822         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1823
1824         gic_base_lo =
1825                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1826         gic_base_hi =
1827                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1828
1829         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1830
1831         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1832         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1833         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1834         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1835         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1836         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1837         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1838         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1839         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1840
1841         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1842         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1843         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1844         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1845
1846         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1847
1848         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1849         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1850
1851         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1852                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1853
1854         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1855
1856         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1857
1858         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1859 }
1860
1861 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1862 {
1863         u32 mtr_base_lo, mtr_base_hi;
1864         u32 so_base_lo, so_base_hi;
1865         u32 gic_base_lo, gic_base_hi;
1866         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1867
1868         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1869         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1870         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1871         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1872
1873         gic_base_lo =
1874                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1875         gic_base_hi =
1876                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1877
1878         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1879         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1880         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1881         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1882
1883         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1884
1885         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1886         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1887
1888         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1889                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1890
1891         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1892
1893         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1894
1895         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1896 }
1897
1898 static void goya_init_tpc_qmans(struct hl_device *hdev)
1899 {
1900         struct goya_device *goya = hdev->asic_specific;
1901         u32 so_base_lo, so_base_hi;
1902         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1903                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1904         int i;
1905
1906         if (goya->hw_cap_initialized & HW_CAP_TPC)
1907                 return;
1908
1909         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1910         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1911
1912         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1913                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1914                                 so_base_lo);
1915                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1916                                 so_base_hi);
1917         }
1918
1919         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1920         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1921         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1922         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1923         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1924         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1925         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1926         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1927
1928         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1929                 goya_init_tpc_cmdq(hdev, i);
1930
1931         goya->hw_cap_initialized |= HW_CAP_TPC;
1932 }
1933
1934 /*
1935  * goya_disable_internal_queues - Disable internal queues
1936  *
1937  * @hdev: pointer to hl_device structure
1938  *
1939  */
1940 static void goya_disable_internal_queues(struct hl_device *hdev)
1941 {
1942         WREG32(mmMME_QM_GLBL_CFG0, 0);
1943         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1944
1945         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
1946         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
1947
1948         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
1949         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
1950
1951         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
1952         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
1953
1954         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
1955         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
1956
1957         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
1958         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
1959
1960         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
1961         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
1962
1963         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
1964         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
1965
1966         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
1967         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
1968 }
1969
1970 /*
1971  * goya_stop_internal_queues - Stop internal queues
1972  *
1973  * @hdev: pointer to hl_device structure
1974  *
1975  * Returns 0 on success
1976  *
1977  */
1978 static int goya_stop_internal_queues(struct hl_device *hdev)
1979 {
1980         int rc, retval = 0;
1981
1982         /*
1983          * Each queue (QMAN) is a separate H/W logic. That means that each
1984          * QMAN can be stopped independently and failure to stop one does NOT
1985          * mandate we should not try to stop other QMANs
1986          */
1987
1988         rc = goya_stop_queue(hdev,
1989                         mmMME_QM_GLBL_CFG1,
1990                         mmMME_QM_CP_STS,
1991                         mmMME_QM_GLBL_STS0);
1992
1993         if (rc) {
1994                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
1995                 retval = -EIO;
1996         }
1997
1998         rc = goya_stop_queue(hdev,
1999                         mmMME_CMDQ_GLBL_CFG1,
2000                         mmMME_CMDQ_CP_STS,
2001                         mmMME_CMDQ_GLBL_STS0);
2002
2003         if (rc) {
2004                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2005                 retval = -EIO;
2006         }
2007
2008         rc = goya_stop_queue(hdev,
2009                         mmTPC0_QM_GLBL_CFG1,
2010                         mmTPC0_QM_CP_STS,
2011                         mmTPC0_QM_GLBL_STS0);
2012
2013         if (rc) {
2014                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2015                 retval = -EIO;
2016         }
2017
2018         rc = goya_stop_queue(hdev,
2019                         mmTPC0_CMDQ_GLBL_CFG1,
2020                         mmTPC0_CMDQ_CP_STS,
2021                         mmTPC0_CMDQ_GLBL_STS0);
2022
2023         if (rc) {
2024                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2025                 retval = -EIO;
2026         }
2027
2028         rc = goya_stop_queue(hdev,
2029                         mmTPC1_QM_GLBL_CFG1,
2030                         mmTPC1_QM_CP_STS,
2031                         mmTPC1_QM_GLBL_STS0);
2032
2033         if (rc) {
2034                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2035                 retval = -EIO;
2036         }
2037
2038         rc = goya_stop_queue(hdev,
2039                         mmTPC1_CMDQ_GLBL_CFG1,
2040                         mmTPC1_CMDQ_CP_STS,
2041                         mmTPC1_CMDQ_GLBL_STS0);
2042
2043         if (rc) {
2044                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2045                 retval = -EIO;
2046         }
2047
2048         rc = goya_stop_queue(hdev,
2049                         mmTPC2_QM_GLBL_CFG1,
2050                         mmTPC2_QM_CP_STS,
2051                         mmTPC2_QM_GLBL_STS0);
2052
2053         if (rc) {
2054                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2055                 retval = -EIO;
2056         }
2057
2058         rc = goya_stop_queue(hdev,
2059                         mmTPC2_CMDQ_GLBL_CFG1,
2060                         mmTPC2_CMDQ_CP_STS,
2061                         mmTPC2_CMDQ_GLBL_STS0);
2062
2063         if (rc) {
2064                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2065                 retval = -EIO;
2066         }
2067
2068         rc = goya_stop_queue(hdev,
2069                         mmTPC3_QM_GLBL_CFG1,
2070                         mmTPC3_QM_CP_STS,
2071                         mmTPC3_QM_GLBL_STS0);
2072
2073         if (rc) {
2074                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2075                 retval = -EIO;
2076         }
2077
2078         rc = goya_stop_queue(hdev,
2079                         mmTPC3_CMDQ_GLBL_CFG1,
2080                         mmTPC3_CMDQ_CP_STS,
2081                         mmTPC3_CMDQ_GLBL_STS0);
2082
2083         if (rc) {
2084                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2085                 retval = -EIO;
2086         }
2087
2088         rc = goya_stop_queue(hdev,
2089                         mmTPC4_QM_GLBL_CFG1,
2090                         mmTPC4_QM_CP_STS,
2091                         mmTPC4_QM_GLBL_STS0);
2092
2093         if (rc) {
2094                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2095                 retval = -EIO;
2096         }
2097
2098         rc = goya_stop_queue(hdev,
2099                         mmTPC4_CMDQ_GLBL_CFG1,
2100                         mmTPC4_CMDQ_CP_STS,
2101                         mmTPC4_CMDQ_GLBL_STS0);
2102
2103         if (rc) {
2104                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2105                 retval = -EIO;
2106         }
2107
2108         rc = goya_stop_queue(hdev,
2109                         mmTPC5_QM_GLBL_CFG1,
2110                         mmTPC5_QM_CP_STS,
2111                         mmTPC5_QM_GLBL_STS0);
2112
2113         if (rc) {
2114                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2115                 retval = -EIO;
2116         }
2117
2118         rc = goya_stop_queue(hdev,
2119                         mmTPC5_CMDQ_GLBL_CFG1,
2120                         mmTPC5_CMDQ_CP_STS,
2121                         mmTPC5_CMDQ_GLBL_STS0);
2122
2123         if (rc) {
2124                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2125                 retval = -EIO;
2126         }
2127
2128         rc = goya_stop_queue(hdev,
2129                         mmTPC6_QM_GLBL_CFG1,
2130                         mmTPC6_QM_CP_STS,
2131                         mmTPC6_QM_GLBL_STS0);
2132
2133         if (rc) {
2134                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2135                 retval = -EIO;
2136         }
2137
2138         rc = goya_stop_queue(hdev,
2139                         mmTPC6_CMDQ_GLBL_CFG1,
2140                         mmTPC6_CMDQ_CP_STS,
2141                         mmTPC6_CMDQ_GLBL_STS0);
2142
2143         if (rc) {
2144                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2145                 retval = -EIO;
2146         }
2147
2148         rc = goya_stop_queue(hdev,
2149                         mmTPC7_QM_GLBL_CFG1,
2150                         mmTPC7_QM_CP_STS,
2151                         mmTPC7_QM_GLBL_STS0);
2152
2153         if (rc) {
2154                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2155                 retval = -EIO;
2156         }
2157
2158         rc = goya_stop_queue(hdev,
2159                         mmTPC7_CMDQ_GLBL_CFG1,
2160                         mmTPC7_CMDQ_CP_STS,
2161                         mmTPC7_CMDQ_GLBL_STS0);
2162
2163         if (rc) {
2164                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2165                 retval = -EIO;
2166         }
2167
2168         return retval;
2169 }
2170
2171 static void goya_dma_stall(struct hl_device *hdev)
2172 {
2173         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2174         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2175         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2176         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2177         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2178 }
2179
2180 static void goya_tpc_stall(struct hl_device *hdev)
2181 {
2182         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2183         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2184         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2185         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2186         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2187         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2188         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2189         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2190 }
2191
2192 static void goya_mme_stall(struct hl_device *hdev)
2193 {
2194         WREG32(mmMME_STALL, 0xFFFFFFFF);
2195 }
2196
2197 static int goya_enable_msix(struct hl_device *hdev)
2198 {
2199         struct goya_device *goya = hdev->asic_specific;
2200         int cq_cnt = hdev->asic_prop.completion_queues_count;
2201         int rc, i, irq_cnt_init, irq;
2202
2203         if (goya->hw_cap_initialized & HW_CAP_MSIX)
2204                 return 0;
2205
2206         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2207                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2208         if (rc < 0) {
2209                 dev_err(hdev->dev,
2210                         "MSI-X: Failed to enable support -- %d/%d\n",
2211                         GOYA_MSIX_ENTRIES, rc);
2212                 return rc;
2213         }
2214
2215         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2216                 irq = pci_irq_vector(hdev->pdev, i);
2217                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2218                                 &hdev->completion_queue[i]);
2219                 if (rc) {
2220                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2221                         goto free_irqs;
2222                 }
2223         }
2224
2225         irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
2226
2227         rc = request_irq(irq, hl_irq_handler_eq, 0,
2228                         goya_irq_name[EVENT_QUEUE_MSIX_IDX],
2229                         &hdev->event_queue);
2230         if (rc) {
2231                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2232                 goto free_irqs;
2233         }
2234
2235         goya->hw_cap_initialized |= HW_CAP_MSIX;
2236         return 0;
2237
2238 free_irqs:
2239         for (i = 0 ; i < irq_cnt_init ; i++)
2240                 free_irq(pci_irq_vector(hdev->pdev, i),
2241                         &hdev->completion_queue[i]);
2242
2243         pci_free_irq_vectors(hdev->pdev);
2244         return rc;
2245 }
2246
2247 static void goya_sync_irqs(struct hl_device *hdev)
2248 {
2249         struct goya_device *goya = hdev->asic_specific;
2250         int i;
2251
2252         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2253                 return;
2254
2255         /* Wait for all pending IRQs to be finished */
2256         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2257                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2258
2259         synchronize_irq(pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX));
2260 }
2261
2262 static void goya_disable_msix(struct hl_device *hdev)
2263 {
2264         struct goya_device *goya = hdev->asic_specific;
2265         int i, irq;
2266
2267         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2268                 return;
2269
2270         goya_sync_irqs(hdev);
2271
2272         irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
2273         free_irq(irq, &hdev->event_queue);
2274
2275         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2276                 irq = pci_irq_vector(hdev->pdev, i);
2277                 free_irq(irq, &hdev->completion_queue[i]);
2278         }
2279
2280         pci_free_irq_vectors(hdev->pdev);
2281
2282         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2283 }
2284
2285 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
2286 {
2287         u32 wait_timeout_ms, cpu_timeout_ms;
2288
2289         dev_info(hdev->dev,
2290                 "Halting compute engines and disabling interrupts\n");
2291
2292         if (hdev->pldm) {
2293                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2294                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2295         } else {
2296                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2297                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2298         }
2299
2300         if (hard_reset) {
2301                 /*
2302                  * I don't know what is the state of the CPU so make sure it is
2303                  * stopped in any means necessary
2304                  */
2305                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2306                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2307                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2308                 msleep(cpu_timeout_ms);
2309         }
2310
2311         goya_stop_external_queues(hdev);
2312         goya_stop_internal_queues(hdev);
2313
2314         msleep(wait_timeout_ms);
2315
2316         goya_dma_stall(hdev);
2317         goya_tpc_stall(hdev);
2318         goya_mme_stall(hdev);
2319
2320         msleep(wait_timeout_ms);
2321
2322         goya_disable_external_queues(hdev);
2323         goya_disable_internal_queues(hdev);
2324
2325         if (hard_reset)
2326                 goya_disable_msix(hdev);
2327         else
2328                 goya_sync_irqs(hdev);
2329 }
2330
2331 /*
2332  * goya_push_fw_to_device - Push FW code to device
2333  *
2334  * @hdev: pointer to hl_device structure
2335  *
2336  * Copy fw code from firmware file to device memory.
2337  * Returns 0 on success
2338  *
2339  */
2340 static int goya_push_fw_to_device(struct hl_device *hdev, const char *fw_name,
2341                                         void __iomem *dst)
2342 {
2343         const struct firmware *fw;
2344         const u64 *fw_data;
2345         size_t fw_size, i;
2346         int rc;
2347
2348         rc = request_firmware(&fw, fw_name, hdev->dev);
2349
2350         if (rc) {
2351                 dev_err(hdev->dev, "Failed to request %s\n", fw_name);
2352                 goto out;
2353         }
2354
2355         fw_size = fw->size;
2356         if ((fw_size % 4) != 0) {
2357                 dev_err(hdev->dev, "illegal %s firmware size %zu\n",
2358                         fw_name, fw_size);
2359                 rc = -EINVAL;
2360                 goto out;
2361         }
2362
2363         dev_dbg(hdev->dev, "%s firmware size == %zu\n", fw_name, fw_size);
2364
2365         fw_data = (const u64 *) fw->data;
2366
2367         if ((fw->size % 8) != 0)
2368                 fw_size -= 8;
2369
2370         for (i = 0 ; i < fw_size ; i += 8, fw_data++, dst += 8) {
2371                 if (!(i & (0x80000 - 1))) {
2372                         dev_dbg(hdev->dev,
2373                                 "copied so far %zu out of %zu for %s firmware",
2374                                 i, fw_size, fw_name);
2375                         usleep_range(20, 100);
2376                 }
2377
2378                 writeq(*fw_data, dst);
2379         }
2380
2381         if ((fw->size % 8) != 0)
2382                 writel(*(const u32 *) fw_data, dst);
2383
2384 out:
2385         release_firmware(fw);
2386         return rc;
2387 }
2388
2389 static int goya_pldm_init_cpu(struct hl_device *hdev)
2390 {
2391         char fw_name[200];
2392         void __iomem *dst;
2393         u32 val, unit_rst_val;
2394         int rc;
2395
2396         /* Must initialize SRAM scrambler before pushing u-boot to SRAM */
2397         goya_init_golden_registers(hdev);
2398
2399         /* Put ARM cores into reset */
2400         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT);
2401         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2402
2403         /* Reset the CA53 MACRO */
2404         unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2405         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET);
2406         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2407         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val);
2408         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2409
2410         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-u-boot.bin");
2411         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET;
2412         rc = goya_push_fw_to_device(hdev, fw_name, dst);
2413         if (rc)
2414                 return rc;
2415
2416         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb");
2417         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2418         rc = goya_push_fw_to_device(hdev, fw_name, dst);
2419         if (rc)
2420                 return rc;
2421
2422         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2423         WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA);
2424
2425         WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0,
2426                 lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2427         WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0,
2428                 upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2429
2430         /* Release ARM core 0 from reset */
2431         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL,
2432                                         CPU_RESET_CORE0_DEASSERT);
2433         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2434
2435         return 0;
2436 }
2437
2438 /*
2439  * FW component passes an offset from SRAM_BASE_ADDR in SCRATCHPAD_xx.
2440  * The version string should be located by that offset.
2441  */
2442 static void goya_read_device_fw_version(struct hl_device *hdev,
2443                                         enum goya_fw_component fwc)
2444 {
2445         const char *name;
2446         u32 ver_off;
2447         char *dest;
2448
2449         switch (fwc) {
2450         case FW_COMP_UBOOT:
2451                 ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_29);
2452                 dest = hdev->asic_prop.uboot_ver;
2453                 name = "U-Boot";
2454                 break;
2455         case FW_COMP_PREBOOT:
2456                 ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_28);
2457                 dest = hdev->asic_prop.preboot_ver;
2458                 name = "Preboot";
2459                 break;
2460         default:
2461                 dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
2462                 return;
2463         }
2464
2465         ver_off &= ~((u32)SRAM_BASE_ADDR);
2466
2467         if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) {
2468                 memcpy_fromio(dest, hdev->pcie_bar[SRAM_CFG_BAR_ID] + ver_off,
2469                                                         VERSION_MAX_LEN);
2470         } else {
2471                 dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n",
2472                                                                 name, ver_off);
2473                 strcpy(dest, "unavailable");
2474         }
2475 }
2476
2477 static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout)
2478 {
2479         struct goya_device *goya = hdev->asic_specific;
2480         char fw_name[200];
2481         void __iomem *dst;
2482         u32 status;
2483         int rc;
2484
2485         if (!hdev->cpu_enable)
2486                 return 0;
2487
2488         if (goya->hw_cap_initialized & HW_CAP_CPU)
2489                 return 0;
2490
2491         /*
2492          * Before pushing u-boot/linux to device, need to set the ddr bar to
2493          * base address of dram
2494          */
2495         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2496         if (rc) {
2497                 dev_err(hdev->dev,
2498                         "failed to map DDR bar to DRAM base address\n");
2499                 return rc;
2500         }
2501
2502         if (hdev->pldm) {
2503                 rc = goya_pldm_init_cpu(hdev);
2504                 if (rc)
2505                         return rc;
2506
2507                 goto out;
2508         }
2509
2510         /* Make sure CPU boot-loader is running */
2511         rc = hl_poll_timeout(
2512                 hdev,
2513                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2514                 status,
2515                 (status == CPU_BOOT_STATUS_DRAM_RDY) ||
2516                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2517                 10000,
2518                 cpu_timeout);
2519
2520         if (rc) {
2521                 dev_err(hdev->dev, "Error in ARM u-boot!");
2522                 switch (status) {
2523                 case CPU_BOOT_STATUS_NA:
2524                         dev_err(hdev->dev,
2525                                 "ARM status %d - BTL did NOT run\n", status);
2526                         break;
2527                 case CPU_BOOT_STATUS_IN_WFE:
2528                         dev_err(hdev->dev,
2529                                 "ARM status %d - Inside WFE loop\n", status);
2530                         break;
2531                 case CPU_BOOT_STATUS_IN_BTL:
2532                         dev_err(hdev->dev,
2533                                 "ARM status %d - Stuck in BTL\n", status);
2534                         break;
2535                 case CPU_BOOT_STATUS_IN_PREBOOT:
2536                         dev_err(hdev->dev,
2537                                 "ARM status %d - Stuck in Preboot\n", status);
2538                         break;
2539                 case CPU_BOOT_STATUS_IN_SPL:
2540                         dev_err(hdev->dev,
2541                                 "ARM status %d - Stuck in SPL\n", status);
2542                         break;
2543                 case CPU_BOOT_STATUS_IN_UBOOT:
2544                         dev_err(hdev->dev,
2545                                 "ARM status %d - Stuck in u-boot\n", status);
2546                         break;
2547                 case CPU_BOOT_STATUS_DRAM_INIT_FAIL:
2548                         dev_err(hdev->dev,
2549                                 "ARM status %d - DDR initialization failed\n",
2550                                 status);
2551                         break;
2552                 default:
2553                         dev_err(hdev->dev,
2554                                 "ARM status %d - Invalid status code\n",
2555                                 status);
2556                         break;
2557                 }
2558                 return -EIO;
2559         }
2560
2561         /* Read U-Boot version now in case we will later fail */
2562         goya_read_device_fw_version(hdev, FW_COMP_UBOOT);
2563         goya_read_device_fw_version(hdev, FW_COMP_PREBOOT);
2564
2565         if (status == CPU_BOOT_STATUS_SRAM_AVAIL)
2566                 goto out;
2567
2568         if (!hdev->fw_loading) {
2569                 dev_info(hdev->dev, "Skip loading FW\n");
2570                 goto out;
2571         }
2572
2573         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb");
2574         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2575         rc = goya_push_fw_to_device(hdev, fw_name, dst);
2576         if (rc)
2577                 return rc;
2578
2579         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2580
2581         rc = hl_poll_timeout(
2582                 hdev,
2583                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2584                 status,
2585                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2586                 10000,
2587                 cpu_timeout);
2588
2589         if (rc) {
2590                 if (status == CPU_BOOT_STATUS_FIT_CORRUPTED)
2591                         dev_err(hdev->dev,
2592                                 "ARM u-boot reports FIT image is corrupted\n");
2593                 else
2594                         dev_err(hdev->dev,
2595                                 "ARM Linux failed to load, %d\n", status);
2596                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA);
2597                 return -EIO;
2598         }
2599
2600         dev_info(hdev->dev, "Successfully loaded firmware to device\n");
2601
2602 out:
2603         goya->hw_cap_initialized |= HW_CAP_CPU;
2604
2605         return 0;
2606 }
2607
2608 static int goya_mmu_init(struct hl_device *hdev)
2609 {
2610         struct asic_fixed_properties *prop = &hdev->asic_prop;
2611         struct goya_device *goya = hdev->asic_specific;
2612         u64 hop0_addr;
2613         int rc, i;
2614
2615         if (!hdev->mmu_enable)
2616                 return 0;
2617
2618         if (goya->hw_cap_initialized & HW_CAP_MMU)
2619                 return 0;
2620
2621         hdev->dram_supports_virtual_memory = true;
2622         hdev->dram_default_page_mapping = true;
2623
2624         for (i = 0 ; i < prop->max_asid ; i++) {
2625                 hop0_addr = prop->mmu_pgt_addr +
2626                                 (i * prop->mmu_hop_table_size);
2627
2628                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2629                 if (rc) {
2630                         dev_err(hdev->dev,
2631                                 "failed to set hop0 addr for asid %d\n", i);
2632                         goto err;
2633                 }
2634         }
2635
2636         goya->hw_cap_initialized |= HW_CAP_MMU;
2637
2638         /* init MMU cache manage page */
2639         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2640                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2641         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2642
2643         /* Remove follower feature due to performance bug */
2644         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2645                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2646
2647         hdev->asic_funcs->mmu_invalidate_cache(hdev, true);
2648
2649         WREG32(mmMMU_MMU_ENABLE, 1);
2650         WREG32(mmMMU_SPI_MASK, 0xF);
2651
2652         return 0;
2653
2654 err:
2655         return rc;
2656 }
2657
2658 /*
2659  * goya_hw_init - Goya hardware initialization code
2660  *
2661  * @hdev: pointer to hl_device structure
2662  *
2663  * Returns 0 on success
2664  *
2665  */
2666 static int goya_hw_init(struct hl_device *hdev)
2667 {
2668         struct asic_fixed_properties *prop = &hdev->asic_prop;
2669         u32 val;
2670         int rc;
2671
2672         dev_info(hdev->dev, "Starting initialization of H/W\n");
2673
2674         /* Perform read from the device to make sure device is up */
2675         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2676
2677         /*
2678          * Let's mark in the H/W that we have reached this point. We check
2679          * this value in the reset_before_init function to understand whether
2680          * we need to reset the chip before doing H/W init. This register is
2681          * cleared by the H/W upon H/W reset
2682          */
2683         WREG32(mmPSOC_GLOBAL_CONF_APP_STATUS, HL_DEVICE_HW_STATE_DIRTY);
2684
2685         rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC);
2686         if (rc) {
2687                 dev_err(hdev->dev, "failed to initialize CPU\n");
2688                 return rc;
2689         }
2690
2691         goya_tpc_mbist_workaround(hdev);
2692
2693         goya_init_golden_registers(hdev);
2694
2695         /*
2696          * After CPU initialization is finished, change DDR bar mapping inside
2697          * iATU to point to the start address of the MMU page tables
2698          */
2699         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
2700                 (MMU_PAGE_TABLES_ADDR & ~(prop->dram_pci_bar_size - 0x1ull)));
2701         if (rc) {
2702                 dev_err(hdev->dev,
2703                         "failed to map DDR bar to MMU page tables\n");
2704                 return rc;
2705         }
2706
2707         rc = goya_mmu_init(hdev);
2708         if (rc)
2709                 return rc;
2710
2711         goya_init_security(hdev);
2712
2713         goya_init_dma_qmans(hdev);
2714
2715         goya_init_mme_qmans(hdev);
2716
2717         goya_init_tpc_qmans(hdev);
2718
2719         /* MSI-X must be enabled before CPU queues are initialized */
2720         rc = goya_enable_msix(hdev);
2721         if (rc)
2722                 goto disable_queues;
2723
2724         rc = goya_init_cpu_queues(hdev);
2725         if (rc) {
2726                 dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n",
2727                         rc);
2728                 goto disable_msix;
2729         }
2730
2731         /* CPU initialization is finished, we can now move to 48 bit DMA mask */
2732         rc = pci_set_dma_mask(hdev->pdev, DMA_BIT_MASK(48));
2733         if (rc) {
2734                 dev_warn(hdev->dev, "Unable to set pci dma mask to 48 bits\n");
2735                 rc = pci_set_dma_mask(hdev->pdev, DMA_BIT_MASK(32));
2736                 if (rc) {
2737                         dev_err(hdev->dev,
2738                                 "Unable to set pci dma mask to 32 bits\n");
2739                         goto disable_pci_access;
2740                 }
2741         }
2742
2743         rc = pci_set_consistent_dma_mask(hdev->pdev, DMA_BIT_MASK(48));
2744         if (rc) {
2745                 dev_warn(hdev->dev,
2746                         "Unable to set pci consistent dma mask to 48 bits\n");
2747                 rc = pci_set_consistent_dma_mask(hdev->pdev, DMA_BIT_MASK(32));
2748                 if (rc) {
2749                         dev_err(hdev->dev,
2750                                 "Unable to set pci consistent dma mask to 32 bits\n");
2751                         goto disable_pci_access;
2752                 }
2753         }
2754
2755         /* Perform read from the device to flush all MSI-X configuration */
2756         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2757
2758         return 0;
2759
2760 disable_pci_access:
2761         goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
2762 disable_msix:
2763         goya_disable_msix(hdev);
2764 disable_queues:
2765         goya_disable_internal_queues(hdev);
2766         goya_disable_external_queues(hdev);
2767
2768         return rc;
2769 }
2770
2771 /*
2772  * goya_hw_fini - Goya hardware tear-down code
2773  *
2774  * @hdev: pointer to hl_device structure
2775  * @hard_reset: should we do hard reset to all engines or just reset the
2776  *              compute/dma engines
2777  */
2778 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
2779 {
2780         struct goya_device *goya = hdev->asic_specific;
2781         u32 reset_timeout_ms, status;
2782
2783         if (hdev->pldm)
2784                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2785         else
2786                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2787
2788         if (hard_reset) {
2789                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2790                 goya_disable_clk_rlx(hdev);
2791                 goya_set_pll_refclk(hdev);
2792
2793                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2794                 dev_info(hdev->dev,
2795                         "Issued HARD reset command, going to wait %dms\n",
2796                         reset_timeout_ms);
2797         } else {
2798                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2799                 dev_info(hdev->dev,
2800                         "Issued SOFT reset command, going to wait %dms\n",
2801                         reset_timeout_ms);
2802         }
2803
2804         /*
2805          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2806          * itself is in reset. In either reset we need to wait until the reset
2807          * is deasserted
2808          */
2809         msleep(reset_timeout_ms);
2810
2811         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2812         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2813                 dev_err(hdev->dev,
2814                         "Timeout while waiting for device to reset 0x%x\n",
2815                         status);
2816
2817         if (!hard_reset) {
2818                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2819                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2820                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2821                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2822                 return;
2823         }
2824
2825         /* Chicken bit to re-initiate boot sequencer flow */
2826         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2827                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2828         /* Move boot manager FSM to pre boot sequencer init state */
2829         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2830                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2831
2832         goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2833                                         HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2834                                         HW_CAP_DMA | HW_CAP_MME |
2835                                         HW_CAP_MMU | HW_CAP_TPC_MBIST |
2836                                         HW_CAP_GOLDEN | HW_CAP_TPC);
2837         memset(goya->events_stat, 0, sizeof(goya->events_stat));
2838
2839         if (!hdev->pldm) {
2840                 int rc;
2841                 /* In case we are running inside VM and the VM is
2842                  * shutting down, we need to make sure CPU boot-loader
2843                  * is running before we can continue the VM shutdown.
2844                  * That is because the VM will send an FLR signal that
2845                  * we must answer
2846                  */
2847                 dev_info(hdev->dev,
2848                         "Going to wait up to %ds for CPU boot loader\n",
2849                         GOYA_CPU_TIMEOUT_USEC / 1000 / 1000);
2850
2851                 rc = hl_poll_timeout(
2852                         hdev,
2853                         mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2854                         status,
2855                         (status == CPU_BOOT_STATUS_DRAM_RDY),
2856                         10000,
2857                         GOYA_CPU_TIMEOUT_USEC);
2858                 if (rc)
2859                         dev_err(hdev->dev,
2860                                 "failed to wait for CPU boot loader\n");
2861         }
2862 }
2863
2864 int goya_suspend(struct hl_device *hdev)
2865 {
2866         int rc;
2867
2868         rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
2869         if (rc)
2870                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2871
2872         return rc;
2873 }
2874
2875 int goya_resume(struct hl_device *hdev)
2876 {
2877         return goya_init_iatu(hdev);
2878 }
2879
2880 static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2881                 u64 kaddress, phys_addr_t paddress, u32 size)
2882 {
2883         int rc;
2884
2885         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2886                         VM_DONTCOPY | VM_NORESERVE;
2887
2888         rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT,
2889                                 size, vma->vm_page_prot);
2890         if (rc)
2891                 dev_err(hdev->dev, "remap_pfn_range error %d", rc);
2892
2893         return rc;
2894 }
2895
2896 static void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2897 {
2898         u32 db_reg_offset, db_value;
2899         bool invalid_queue = false;
2900
2901         switch (hw_queue_id) {
2902         case GOYA_QUEUE_ID_DMA_0:
2903                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2904                 break;
2905
2906         case GOYA_QUEUE_ID_DMA_1:
2907                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2908                 break;
2909
2910         case GOYA_QUEUE_ID_DMA_2:
2911                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2912                 break;
2913
2914         case GOYA_QUEUE_ID_DMA_3:
2915                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2916                 break;
2917
2918         case GOYA_QUEUE_ID_DMA_4:
2919                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2920                 break;
2921
2922         case GOYA_QUEUE_ID_CPU_PQ:
2923                 if (hdev->cpu_queues_enable)
2924                         db_reg_offset = mmCPU_IF_PF_PQ_PI;
2925                 else
2926                         invalid_queue = true;
2927                 break;
2928
2929         case GOYA_QUEUE_ID_MME:
2930                 db_reg_offset = mmMME_QM_PQ_PI;
2931                 break;
2932
2933         case GOYA_QUEUE_ID_TPC0:
2934                 db_reg_offset = mmTPC0_QM_PQ_PI;
2935                 break;
2936
2937         case GOYA_QUEUE_ID_TPC1:
2938                 db_reg_offset = mmTPC1_QM_PQ_PI;
2939                 break;
2940
2941         case GOYA_QUEUE_ID_TPC2:
2942                 db_reg_offset = mmTPC2_QM_PQ_PI;
2943                 break;
2944
2945         case GOYA_QUEUE_ID_TPC3:
2946                 db_reg_offset = mmTPC3_QM_PQ_PI;
2947                 break;
2948
2949         case GOYA_QUEUE_ID_TPC4:
2950                 db_reg_offset = mmTPC4_QM_PQ_PI;
2951                 break;
2952
2953         case GOYA_QUEUE_ID_TPC5:
2954                 db_reg_offset = mmTPC5_QM_PQ_PI;
2955                 break;
2956
2957         case GOYA_QUEUE_ID_TPC6:
2958                 db_reg_offset = mmTPC6_QM_PQ_PI;
2959                 break;
2960
2961         case GOYA_QUEUE_ID_TPC7:
2962                 db_reg_offset = mmTPC7_QM_PQ_PI;
2963                 break;
2964
2965         default:
2966                 invalid_queue = true;
2967         }
2968
2969         if (invalid_queue) {
2970                 /* Should never get here */
2971                 dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n",
2972                         hw_queue_id);
2973                 return;
2974         }
2975
2976         db_value = pi;
2977
2978         /* ring the doorbell */
2979         WREG32(db_reg_offset, db_value);
2980
2981         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ)
2982                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2983                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2984 }
2985
2986 void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val)
2987 {
2988         /* Not needed in Goya */
2989 }
2990
2991 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2992                                         dma_addr_t *dma_handle, gfp_t flags)
2993 {
2994         return dma_alloc_coherent(&hdev->pdev->dev, size, dma_handle, flags);
2995 }
2996
2997 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2998                                         void *cpu_addr, dma_addr_t dma_handle)
2999 {
3000         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, dma_handle);
3001 }
3002
3003 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
3004                                 dma_addr_t *dma_handle, u16 *queue_len)
3005 {
3006         void *base;
3007         u32 offset;
3008
3009         *dma_handle = hdev->asic_prop.sram_base_address;
3010
3011         base = (void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
3012
3013         switch (queue_id) {
3014         case GOYA_QUEUE_ID_MME:
3015                 offset = MME_QMAN_BASE_OFFSET;
3016                 *queue_len = MME_QMAN_LENGTH;
3017                 break;
3018         case GOYA_QUEUE_ID_TPC0:
3019                 offset = TPC0_QMAN_BASE_OFFSET;
3020                 *queue_len = TPC_QMAN_LENGTH;
3021                 break;
3022         case GOYA_QUEUE_ID_TPC1:
3023                 offset = TPC1_QMAN_BASE_OFFSET;
3024                 *queue_len = TPC_QMAN_LENGTH;
3025                 break;
3026         case GOYA_QUEUE_ID_TPC2:
3027                 offset = TPC2_QMAN_BASE_OFFSET;
3028                 *queue_len = TPC_QMAN_LENGTH;
3029                 break;
3030         case GOYA_QUEUE_ID_TPC3:
3031                 offset = TPC3_QMAN_BASE_OFFSET;
3032                 *queue_len = TPC_QMAN_LENGTH;
3033                 break;
3034         case GOYA_QUEUE_ID_TPC4:
3035                 offset = TPC4_QMAN_BASE_OFFSET;
3036                 *queue_len = TPC_QMAN_LENGTH;
3037                 break;
3038         case GOYA_QUEUE_ID_TPC5:
3039                 offset = TPC5_QMAN_BASE_OFFSET;
3040                 *queue_len = TPC_QMAN_LENGTH;
3041                 break;
3042         case GOYA_QUEUE_ID_TPC6:
3043                 offset = TPC6_QMAN_BASE_OFFSET;
3044                 *queue_len = TPC_QMAN_LENGTH;
3045                 break;
3046         case GOYA_QUEUE_ID_TPC7:
3047                 offset = TPC7_QMAN_BASE_OFFSET;
3048                 *queue_len = TPC_QMAN_LENGTH;
3049                 break;
3050         default:
3051                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
3052                 return NULL;
3053         }
3054
3055         base += offset;
3056         *dma_handle += offset;
3057
3058         return base;
3059 }
3060
3061 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
3062 {
3063         struct goya_device *goya = hdev->asic_specific;
3064         struct packet_msg_prot *fence_pkt;
3065         u32 *fence_ptr;
3066         dma_addr_t fence_dma_addr;
3067         struct hl_cb *cb;
3068         u32 tmp, timeout;
3069         int rc;
3070
3071         if (hdev->pldm)
3072                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3073         else
3074                 timeout = HL_DEVICE_TIMEOUT_USEC;
3075
3076         if (!hdev->asic_funcs->is_device_idle(hdev)) {
3077                 dev_err_ratelimited(hdev->dev,
3078                         "Can't send KMD job on QMAN0 if device is not idle\n");
3079                 return -EBUSY;
3080         }
3081
3082         fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3083                                                         &fence_dma_addr);
3084         if (!fence_ptr) {
3085                 dev_err(hdev->dev,
3086                         "Failed to allocate fence memory for QMAN0\n");
3087                 return -ENOMEM;
3088         }
3089
3090         *fence_ptr = 0;
3091
3092         if (goya->hw_cap_initialized & HW_CAP_MMU) {
3093                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
3094                 RREG32(mmDMA_QM_0_GLBL_PROT);
3095         }
3096
3097         /*
3098          * goya cs parser saves space for 2xpacket_msg_prot at end of CB. For
3099          * synchronized kernel jobs we only need space for 1 packet_msg_prot
3100          */
3101         job->job_cb_size -= sizeof(struct packet_msg_prot);
3102
3103         cb = job->patched_cb;
3104
3105         fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address +
3106                         job->job_cb_size - sizeof(struct packet_msg_prot));
3107
3108         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3109                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3110                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3111         fence_pkt->ctl = cpu_to_le32(tmp);
3112         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3113         fence_pkt->addr = cpu_to_le64(fence_dma_addr +
3114                                         hdev->asic_prop.host_phys_base_address);
3115
3116         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3117                                         job->job_cb_size, cb->bus_address);
3118         if (rc) {
3119                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3120                 goto free_fence_ptr;
3121         }
3122
3123         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr, timeout,
3124                                         &tmp);
3125
3126         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3127
3128         if ((rc) || (tmp != GOYA_QMAN0_FENCE_VAL)) {
3129                 dev_err(hdev->dev, "QMAN0 Job hasn't finished in time\n");
3130                 rc = -ETIMEDOUT;
3131         }
3132
3133 free_fence_ptr:
3134         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr,
3135                                         fence_dma_addr);
3136
3137         if (goya->hw_cap_initialized & HW_CAP_MMU) {
3138                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
3139                 RREG32(mmDMA_QM_0_GLBL_PROT);
3140         }
3141
3142         return rc;
3143 }
3144
3145 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3146                                 u32 timeout, long *result)
3147 {
3148         struct goya_device *goya = hdev->asic_specific;
3149         struct armcp_packet *pkt;
3150         dma_addr_t pkt_dma_addr;
3151         u32 tmp;
3152         int rc = 0;
3153
3154         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3155                 if (result)
3156                         *result = 0;
3157                 return 0;
3158         }
3159
3160         if (len > CPU_CB_SIZE) {
3161                 dev_err(hdev->dev, "Invalid CPU message size of %d bytes\n",
3162                         len);
3163                 return -ENOMEM;
3164         }
3165
3166         pkt = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, len,
3167                                                                 &pkt_dma_addr);
3168         if (!pkt) {
3169                 dev_err(hdev->dev,
3170                         "Failed to allocate DMA memory for packet to CPU\n");
3171                 return -ENOMEM;
3172         }
3173
3174         memcpy(pkt, msg, len);
3175
3176         mutex_lock(&hdev->send_cpu_message_lock);
3177
3178         if (hdev->disabled)
3179                 goto out;
3180
3181         if (hdev->device_cpu_disabled) {
3182                 rc = -EIO;
3183                 goto out;
3184         }
3185
3186         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_CPU_PQ, len,
3187                         pkt_dma_addr);
3188         if (rc) {
3189                 dev_err(hdev->dev, "Failed to send CB on CPU PQ (%d)\n", rc);
3190                 goto out;
3191         }
3192
3193         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) &pkt->fence,
3194                                         timeout, &tmp);
3195
3196         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_CPU_PQ);
3197
3198         if (rc == -ETIMEDOUT) {
3199                 dev_err(hdev->dev, "Timeout while waiting for device CPU\n");
3200                 hdev->device_cpu_disabled = true;
3201                 goto out;
3202         }
3203
3204         if (tmp == ARMCP_PACKET_FENCE_VAL) {
3205                 u32 ctl = le32_to_cpu(pkt->ctl);
3206
3207                 rc = (ctl & ARMCP_PKT_CTL_RC_MASK) >> ARMCP_PKT_CTL_RC_SHIFT;
3208                 if (rc) {
3209                         dev_err(hdev->dev,
3210                                 "F/W ERROR %d for CPU packet %d\n",
3211                                 rc, (ctl & ARMCP_PKT_CTL_OPCODE_MASK)
3212                                                 >> ARMCP_PKT_CTL_OPCODE_SHIFT);
3213                         rc = -EINVAL;
3214                 } else if (result) {
3215                         *result = (long) le64_to_cpu(pkt->result);
3216                 }
3217         } else {
3218                 dev_err(hdev->dev, "CPU packet wrong fence value\n");
3219                 rc = -EINVAL;
3220         }
3221
3222 out:
3223         mutex_unlock(&hdev->send_cpu_message_lock);
3224
3225         hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, len, pkt);
3226
3227         return rc;
3228 }
3229
3230 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3231 {
3232         struct packet_msg_prot *fence_pkt;
3233         dma_addr_t pkt_dma_addr;
3234         u32 fence_val, tmp;
3235         dma_addr_t fence_dma_addr;
3236         u32 *fence_ptr;
3237         int rc;
3238
3239         fence_val = GOYA_QMAN0_FENCE_VAL;
3240
3241         fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3242                                                         &fence_dma_addr);
3243         if (!fence_ptr) {
3244                 dev_err(hdev->dev,
3245                         "Failed to allocate memory for queue testing\n");
3246                 return -ENOMEM;
3247         }
3248
3249         *fence_ptr = 0;
3250
3251         fence_pkt = hdev->asic_funcs->dma_pool_zalloc(hdev,
3252                                         sizeof(struct packet_msg_prot),
3253                                         GFP_KERNEL, &pkt_dma_addr);
3254         if (!fence_pkt) {
3255                 dev_err(hdev->dev,
3256                         "Failed to allocate packet for queue testing\n");
3257                 rc = -ENOMEM;
3258                 goto free_fence_ptr;
3259         }
3260
3261         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3262                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3263                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3264         fence_pkt->ctl = cpu_to_le32(tmp);
3265         fence_pkt->value = cpu_to_le32(fence_val);
3266         fence_pkt->addr = cpu_to_le64(fence_dma_addr +
3267                                         hdev->asic_prop.host_phys_base_address);
3268
3269         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3270                                         sizeof(struct packet_msg_prot),
3271                                         pkt_dma_addr);
3272         if (rc) {
3273                 dev_err(hdev->dev,
3274                         "Failed to send fence packet\n");
3275                 goto free_pkt;
3276         }
3277
3278         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr,
3279                                         GOYA_TEST_QUEUE_WAIT_USEC, &tmp);
3280
3281         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3282
3283         if ((!rc) && (tmp == fence_val)) {
3284                 dev_info(hdev->dev,
3285                         "queue test on H/W queue %d succeeded\n",
3286                         hw_queue_id);
3287         } else {
3288                 dev_err(hdev->dev,
3289                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3290                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3291                 rc = -EINVAL;
3292         }
3293
3294 free_pkt:
3295         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_pkt,
3296                                         pkt_dma_addr);
3297 free_fence_ptr:
3298         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr,
3299                                         fence_dma_addr);
3300         return rc;
3301 }
3302
3303 int goya_test_cpu_queue(struct hl_device *hdev)
3304 {
3305         struct armcp_packet test_pkt;
3306         long result;
3307         int rc;
3308
3309         /* cpu_queues_enable flag is always checked in send cpu message */
3310
3311         memset(&test_pkt, 0, sizeof(test_pkt));
3312
3313         test_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST <<
3314                                         ARMCP_PKT_CTL_OPCODE_SHIFT);
3315         test_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL);
3316
3317         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &test_pkt,
3318                         sizeof(test_pkt), HL_DEVICE_TIMEOUT_USEC, &result);
3319
3320         if (!rc) {
3321                 if (result == ARMCP_PACKET_FENCE_VAL)
3322                         dev_info(hdev->dev,
3323                                 "queue test on CPU queue succeeded\n");
3324                 else
3325                         dev_err(hdev->dev,
3326                                 "CPU queue test failed (0x%08lX)\n", result);
3327         } else {
3328                 dev_err(hdev->dev, "CPU queue test failed, error %d\n", rc);
3329         }
3330
3331         return rc;
3332 }
3333
3334 static int goya_test_queues(struct hl_device *hdev)
3335 {
3336         struct goya_device *goya = hdev->asic_specific;
3337         int i, rc, ret_val = 0;
3338
3339         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3340                 rc = goya_test_queue(hdev, i);
3341                 if (rc)
3342                         ret_val = -EINVAL;
3343         }
3344
3345         if (hdev->cpu_queues_enable) {
3346                 rc = goya->test_cpu_queue(hdev);
3347                 if (rc)
3348                         ret_val = -EINVAL;
3349         }
3350
3351         return ret_val;
3352 }
3353
3354 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3355                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3356 {
3357         if (size > GOYA_DMA_POOL_BLK_SIZE)
3358                 return NULL;
3359
3360         return dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3361 }
3362
3363 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3364                                 dma_addr_t dma_addr)
3365 {
3366         dma_pool_free(hdev->dma_pool, vaddr, dma_addr);
3367 }
3368
3369 static void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev,
3370                                         size_t size, dma_addr_t *dma_handle)
3371 {
3372         u64 kernel_addr;
3373
3374         /* roundup to CPU_PKT_SIZE */
3375         size = (size + (CPU_PKT_SIZE - 1)) & CPU_PKT_MASK;
3376
3377         kernel_addr = gen_pool_alloc(hdev->cpu_accessible_dma_pool, size);
3378
3379         *dma_handle = hdev->cpu_accessible_dma_address +
3380                 (kernel_addr - (u64) (uintptr_t) hdev->cpu_accessible_dma_mem);
3381
3382         return (void *) (uintptr_t) kernel_addr;
3383 }
3384
3385 static void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev,
3386                                                 size_t size, void *vaddr)
3387 {
3388         /* roundup to CPU_PKT_SIZE */
3389         size = (size + (CPU_PKT_SIZE - 1)) & CPU_PKT_MASK;
3390
3391         gen_pool_free(hdev->cpu_accessible_dma_pool, (u64) (uintptr_t) vaddr,
3392                         size);
3393 }
3394
3395 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sg,
3396                                 int nents, enum dma_data_direction dir)
3397 {
3398         if (!dma_map_sg(&hdev->pdev->dev, sg, nents, dir))
3399                 return -ENOMEM;
3400
3401         return 0;
3402 }
3403
3404 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sg,
3405                                 int nents, enum dma_data_direction dir)
3406 {
3407         dma_unmap_sg(&hdev->pdev->dev, sg, nents, dir);
3408 }
3409
3410 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3411 {
3412         struct scatterlist *sg, *sg_next_iter;
3413         u32 count, dma_desc_cnt;
3414         u64 len, len_next;
3415         dma_addr_t addr, addr_next;
3416
3417         dma_desc_cnt = 0;
3418
3419         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3420
3421                 len = sg_dma_len(sg);
3422                 addr = sg_dma_address(sg);
3423
3424                 if (len == 0)
3425                         break;
3426
3427                 while ((count + 1) < sgt->nents) {
3428                         sg_next_iter = sg_next(sg);
3429                         len_next = sg_dma_len(sg_next_iter);
3430                         addr_next = sg_dma_address(sg_next_iter);
3431
3432                         if (len_next == 0)
3433                                 break;
3434
3435                         if ((addr + len == addr_next) &&
3436                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3437                                 len += len_next;
3438                                 count++;
3439                                 sg = sg_next_iter;
3440                         } else {
3441                                 break;
3442                         }
3443                 }
3444
3445                 dma_desc_cnt++;
3446         }
3447
3448         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3449 }
3450
3451 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3452                                 struct hl_cs_parser *parser,
3453                                 struct packet_lin_dma *user_dma_pkt,
3454                                 u64 addr, enum dma_data_direction dir)
3455 {
3456         struct hl_userptr *userptr;
3457         int rc;
3458
3459         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3460                         parser->job_userptr_list, &userptr))
3461                 goto already_pinned;
3462
3463         userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC);
3464         if (!userptr)
3465                 return -ENOMEM;
3466
3467         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3468                                 userptr);
3469         if (rc)
3470                 goto free_userptr;
3471
3472         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3473
3474         rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3475                                         userptr->sgt->nents, dir);
3476         if (rc) {
3477                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3478                 goto unpin_memory;
3479         }
3480
3481         userptr->dma_mapped = true;
3482         userptr->dir = dir;
3483
3484 already_pinned:
3485         parser->patched_cb_size +=
3486                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3487
3488         return 0;
3489
3490 unpin_memory:
3491         hl_unpin_host_memory(hdev, userptr);
3492 free_userptr:
3493         kfree(userptr);
3494         return rc;
3495 }
3496
3497 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3498                                 struct hl_cs_parser *parser,
3499                                 struct packet_lin_dma *user_dma_pkt)
3500 {
3501         u64 device_memory_addr, addr;
3502         enum dma_data_direction dir;
3503         enum goya_dma_direction user_dir;
3504         bool sram_addr = true;
3505         bool skip_host_mem_pin = false;
3506         bool user_memset;
3507         u32 ctl;
3508         int rc = 0;
3509
3510         ctl = le32_to_cpu(user_dma_pkt->ctl);
3511
3512         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3513                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3514
3515         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3516                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3517
3518         switch (user_dir) {
3519         case DMA_HOST_TO_DRAM:
3520                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3521                 dir = DMA_TO_DEVICE;
3522                 sram_addr = false;
3523                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3524                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3525                 if (user_memset)
3526                         skip_host_mem_pin = true;
3527                 break;
3528
3529         case DMA_DRAM_TO_HOST:
3530                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3531                 dir = DMA_FROM_DEVICE;
3532                 sram_addr = false;
3533                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3534                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3535                 break;
3536
3537         case DMA_HOST_TO_SRAM:
3538                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3539                 dir = DMA_TO_DEVICE;
3540                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3541                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3542                 if (user_memset)
3543                         skip_host_mem_pin = true;
3544                 break;
3545
3546         case DMA_SRAM_TO_HOST:
3547                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3548                 dir = DMA_FROM_DEVICE;
3549                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3550                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3551                 break;
3552         default:
3553                 dev_err(hdev->dev, "DMA direction is undefined\n");
3554                 return -EFAULT;
3555         }
3556
3557         if (parser->ctx_id != HL_KERNEL_ASID_ID) {
3558                 if (sram_addr) {
3559                         if (!hl_mem_area_inside_range(device_memory_addr,
3560                                         le32_to_cpu(user_dma_pkt->tsize),
3561                                         hdev->asic_prop.sram_user_base_address,
3562                                         hdev->asic_prop.sram_end_address)) {
3563
3564                                 dev_err(hdev->dev,
3565                                         "SRAM address 0x%llx + 0x%x is invalid\n",
3566                                         device_memory_addr,
3567                                         user_dma_pkt->tsize);
3568                                 return -EFAULT;
3569                         }
3570                 } else {
3571                         if (!hl_mem_area_inside_range(device_memory_addr,
3572                                         le32_to_cpu(user_dma_pkt->tsize),
3573                                         hdev->asic_prop.dram_user_base_address,
3574                                         hdev->asic_prop.dram_end_address)) {
3575
3576                                 dev_err(hdev->dev,
3577                                         "DRAM address 0x%llx + 0x%x is invalid\n",
3578                                         device_memory_addr,
3579                                         user_dma_pkt->tsize);
3580                                 return -EFAULT;
3581                         }
3582                 }
3583         }
3584
3585         if (skip_host_mem_pin)
3586                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3587         else {
3588                 if ((dir == DMA_TO_DEVICE) &&
3589                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3590                         dev_err(hdev->dev,
3591                                 "Can't DMA from host on queue other then 1\n");
3592                         return -EFAULT;
3593                 }
3594
3595                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3596                                                 addr, dir);
3597         }
3598
3599         return rc;
3600 }
3601
3602 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3603                                 struct hl_cs_parser *parser,
3604                                 struct packet_lin_dma *user_dma_pkt)
3605 {
3606         u64 sram_memory_addr, dram_memory_addr;
3607         enum goya_dma_direction user_dir;
3608         u32 ctl;
3609
3610         ctl = le32_to_cpu(user_dma_pkt->ctl);
3611         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3612                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3613
3614         if (user_dir == DMA_DRAM_TO_SRAM) {
3615                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3616                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3617                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3618         } else {
3619                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3620                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3621                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3622         }
3623
3624         if (!hl_mem_area_inside_range(sram_memory_addr,
3625                                 le32_to_cpu(user_dma_pkt->tsize),
3626                                 hdev->asic_prop.sram_user_base_address,
3627                                 hdev->asic_prop.sram_end_address)) {
3628                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3629                         sram_memory_addr, user_dma_pkt->tsize);
3630                 return -EFAULT;
3631         }
3632
3633         if (!hl_mem_area_inside_range(dram_memory_addr,
3634                                 le32_to_cpu(user_dma_pkt->tsize),
3635                                 hdev->asic_prop.dram_user_base_address,
3636                                 hdev->asic_prop.dram_end_address)) {
3637                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3638                         dram_memory_addr, user_dma_pkt->tsize);
3639                 return -EFAULT;
3640         }
3641
3642         parser->patched_cb_size += sizeof(*user_dma_pkt);
3643
3644         return 0;
3645 }
3646
3647 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3648                                 struct hl_cs_parser *parser,
3649                                 struct packet_lin_dma *user_dma_pkt)
3650 {
3651         enum goya_dma_direction user_dir;
3652         u32 ctl;
3653         int rc;
3654
3655         dev_dbg(hdev->dev, "DMA packet details:\n");
3656         dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3657         dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3658         dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3659
3660         ctl = le32_to_cpu(user_dma_pkt->ctl);
3661         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3662                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3663
3664         /*
3665          * Special handling for DMA with size 0. The H/W has a bug where
3666          * this can cause the QMAN DMA to get stuck, so block it here.
3667          */
3668         if (user_dma_pkt->tsize == 0) {
3669                 dev_err(hdev->dev,
3670                         "Got DMA with size 0, might reset the device\n");
3671                 return -EINVAL;
3672         }
3673
3674         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3675                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3676         else
3677                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3678
3679         return rc;
3680 }
3681
3682 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3683                                 struct hl_cs_parser *parser,
3684                                 struct packet_lin_dma *user_dma_pkt)
3685 {
3686         dev_dbg(hdev->dev, "DMA packet details:\n");
3687         dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3688         dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3689         dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3690
3691         /*
3692          * WA for HW-23.
3693          * We can't allow user to read from Host using QMANs other than 1.
3694          */
3695         if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3696                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3697                                 le32_to_cpu(user_dma_pkt->tsize),
3698                                 hdev->asic_prop.va_space_host_start_address,
3699                                 hdev->asic_prop.va_space_host_end_address)) {
3700                 dev_err(hdev->dev,
3701                         "Can't DMA from host on queue other then 1\n");
3702                 return -EFAULT;
3703         }
3704
3705         if (user_dma_pkt->tsize == 0) {
3706                 dev_err(hdev->dev,
3707                         "Got DMA with size 0, might reset the device\n");
3708                 return -EINVAL;
3709         }
3710
3711         parser->patched_cb_size += sizeof(*user_dma_pkt);
3712
3713         return 0;
3714 }
3715
3716 static int goya_validate_wreg32(struct hl_device *hdev,
3717                                 struct hl_cs_parser *parser,
3718                                 struct packet_wreg32 *wreg_pkt)
3719 {
3720         struct goya_device *goya = hdev->asic_specific;
3721         u32 sob_start_addr, sob_end_addr;
3722         u16 reg_offset;
3723
3724         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3725                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3726
3727         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3728         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3729         dev_dbg(hdev->dev, "value      == 0x%x\n", wreg_pkt->value);
3730
3731         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3732                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3733                         reg_offset);
3734                 return -EPERM;
3735         }
3736
3737         /*
3738          * With MMU, DMA channels are not secured, so it doesn't matter where
3739          * the WR COMP will be written to because it will go out with
3740          * non-secured property
3741          */
3742         if (goya->hw_cap_initialized & HW_CAP_MMU)
3743                 return 0;
3744
3745         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3746         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3747
3748         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3749                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3750
3751                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3752                         wreg_pkt->value);
3753                 return -EPERM;
3754         }
3755
3756         return 0;
3757 }
3758
3759 static int goya_validate_cb(struct hl_device *hdev,
3760                         struct hl_cs_parser *parser, bool is_mmu)
3761 {
3762         u32 cb_parsed_length = 0;
3763         int rc = 0;
3764
3765         parser->patched_cb_size = 0;
3766
3767         /* cb_user_size is more than 0 so loop will always be executed */
3768         while (cb_parsed_length < parser->user_cb_size) {
3769                 enum packet_id pkt_id;
3770                 u16 pkt_size;
3771                 void *user_pkt;
3772
3773                 user_pkt = (void *) (uintptr_t)
3774                         (parser->user_cb->kernel_address + cb_parsed_length);
3775
3776                 pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
3777                                 PACKET_HEADER_PACKET_ID_MASK) >>
3778                                         PACKET_HEADER_PACKET_ID_SHIFT);
3779
3780                 pkt_size = goya_packet_sizes[pkt_id];
3781                 cb_parsed_length += pkt_size;
3782                 if (cb_parsed_length > parser->user_cb_size) {
3783                         dev_err(hdev->dev,
3784                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3785                         rc = -EINVAL;
3786                         break;
3787                 }
3788
3789                 switch (pkt_id) {
3790                 case PACKET_WREG_32:
3791                         /*
3792                          * Although it is validated after copy in patch_cb(),
3793                          * need to validate here as well because patch_cb() is
3794                          * not called in MMU path while this function is called
3795                          */
3796                         rc = goya_validate_wreg32(hdev, parser, user_pkt);
3797                         break;
3798
3799                 case PACKET_WREG_BULK:
3800                         dev_err(hdev->dev,
3801                                 "User not allowed to use WREG_BULK\n");
3802                         rc = -EPERM;
3803                         break;
3804
3805                 case PACKET_MSG_PROT:
3806                         dev_err(hdev->dev,
3807                                 "User not allowed to use MSG_PROT\n");
3808                         rc = -EPERM;
3809                         break;
3810
3811                 case PACKET_CP_DMA:
3812                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3813                         rc = -EPERM;
3814                         break;
3815
3816                 case PACKET_STOP:
3817                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3818                         rc = -EPERM;
3819                         break;
3820
3821                 case PACKET_LIN_DMA:
3822                         if (is_mmu)
3823                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3824                                                 user_pkt);
3825                         else
3826                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3827                                                 user_pkt);
3828                         break;
3829
3830                 case PACKET_MSG_LONG:
3831                 case PACKET_MSG_SHORT:
3832                 case PACKET_FENCE:
3833                 case PACKET_NOP:
3834                         parser->patched_cb_size += pkt_size;
3835                         break;
3836
3837                 default:
3838                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3839                                 pkt_id);
3840                         rc = -EINVAL;
3841                         break;
3842                 }
3843
3844                 if (rc)
3845                         break;
3846         }
3847
3848         /*
3849          * The new CB should have space at the end for two MSG_PROT packets:
3850          * 1. A packet that will act as a completion packet
3851          * 2. A packet that will generate MSI-X interrupt
3852          */
3853         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3854
3855         return rc;
3856 }
3857
3858 static int goya_patch_dma_packet(struct hl_device *hdev,
3859                                 struct hl_cs_parser *parser,
3860                                 struct packet_lin_dma *user_dma_pkt,
3861                                 struct packet_lin_dma *new_dma_pkt,
3862                                 u32 *new_dma_pkt_size)
3863 {
3864         struct hl_userptr *userptr;
3865         struct scatterlist *sg, *sg_next_iter;
3866         u32 count, dma_desc_cnt;
3867         u64 len, len_next;
3868         dma_addr_t dma_addr, dma_addr_next;
3869         enum goya_dma_direction user_dir;
3870         u64 device_memory_addr, addr;
3871         enum dma_data_direction dir;
3872         struct sg_table *sgt;
3873         bool skip_host_mem_pin = false;
3874         bool user_memset;
3875         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3876
3877         ctl = le32_to_cpu(user_dma_pkt->ctl);
3878
3879         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3880                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3881
3882         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3883                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3884
3885         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3886                         (user_dma_pkt->tsize == 0)) {
3887                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3888                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3889                 return 0;
3890         }
3891
3892         if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3893                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3894                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3895                 dir = DMA_TO_DEVICE;
3896                 if (user_memset)
3897                         skip_host_mem_pin = true;
3898         } else {
3899                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3900                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3901                 dir = DMA_FROM_DEVICE;
3902         }
3903
3904         if ((!skip_host_mem_pin) &&
3905                 (hl_userptr_is_pinned(hdev, addr,
3906                         le32_to_cpu(user_dma_pkt->tsize),
3907                         parser->job_userptr_list, &userptr) == false)) {
3908                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3909                                 addr, user_dma_pkt->tsize);
3910                 return -EFAULT;
3911         }
3912
3913         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3914                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3915                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3916                 return 0;
3917         }
3918
3919         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3920
3921         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3922
3923         sgt = userptr->sgt;
3924         dma_desc_cnt = 0;
3925
3926         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3927                 len = sg_dma_len(sg);
3928                 dma_addr = sg_dma_address(sg);
3929
3930                 if (len == 0)
3931                         break;
3932
3933                 while ((count + 1) < sgt->nents) {
3934                         sg_next_iter = sg_next(sg);
3935                         len_next = sg_dma_len(sg_next_iter);
3936                         dma_addr_next = sg_dma_address(sg_next_iter);
3937
3938                         if (len_next == 0)
3939                                 break;
3940
3941                         if ((dma_addr + len == dma_addr_next) &&
3942                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3943                                 len += len_next;
3944                                 count++;
3945                                 sg = sg_next_iter;
3946                         } else {
3947                                 break;
3948                         }
3949                 }
3950
3951                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3952                 if (likely(dma_desc_cnt))
3953                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3954                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3955                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3956                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3957                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3958
3959                 dma_addr += hdev->asic_prop.host_phys_base_address;
3960
3961                 if (dir == DMA_TO_DEVICE) {
3962                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3963                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3964                 } else {
3965                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3966                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3967                 }
3968
3969                 if (!user_memset)
3970                         device_memory_addr += len;
3971                 dma_desc_cnt++;
3972                 new_dma_pkt++;
3973         }
3974
3975         if (!dma_desc_cnt) {
3976                 dev_err(hdev->dev,
3977                         "Error of 0 SG entries when patching DMA packet\n");
3978                 return -EFAULT;
3979         }
3980
3981         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3982         new_dma_pkt--;
3983         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3984
3985         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3986
3987         return 0;
3988 }
3989
3990 static int goya_patch_cb(struct hl_device *hdev,
3991                                 struct hl_cs_parser *parser)
3992 {
3993         u32 cb_parsed_length = 0;
3994         u32 cb_patched_cur_length = 0;
3995         int rc = 0;
3996
3997         /* cb_user_size is more than 0 so loop will always be executed */
3998         while (cb_parsed_length < parser->user_cb_size) {
3999                 enum packet_id pkt_id;
4000                 u16 pkt_size;
4001                 u32 new_pkt_size = 0;
4002                 void *user_pkt, *kernel_pkt;
4003
4004                 user_pkt = (void *) (uintptr_t)
4005                         (parser->user_cb->kernel_address + cb_parsed_length);
4006                 kernel_pkt = (void *) (uintptr_t)
4007                         (parser->patched_cb->kernel_address +
4008                                         cb_patched_cur_length);
4009
4010                 pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
4011                                 PACKET_HEADER_PACKET_ID_MASK) >>
4012                                         PACKET_HEADER_PACKET_ID_SHIFT);
4013
4014                 pkt_size = goya_packet_sizes[pkt_id];
4015                 cb_parsed_length += pkt_size;
4016                 if (cb_parsed_length > parser->user_cb_size) {
4017                         dev_err(hdev->dev,
4018                                 "packet 0x%x is out of CB boundary\n", pkt_id);
4019                         rc = -EINVAL;
4020                         break;
4021                 }
4022
4023                 switch (pkt_id) {
4024                 case PACKET_LIN_DMA:
4025                         rc = goya_patch_dma_packet(hdev, parser, user_pkt,
4026                                                 kernel_pkt, &new_pkt_size);
4027                         cb_patched_cur_length += new_pkt_size;
4028                         break;
4029
4030                 case PACKET_WREG_32:
4031                         memcpy(kernel_pkt, user_pkt, pkt_size);
4032                         cb_patched_cur_length += pkt_size;
4033                         rc = goya_validate_wreg32(hdev, parser, kernel_pkt);
4034                         break;
4035
4036                 case PACKET_WREG_BULK:
4037                         dev_err(hdev->dev,
4038                                 "User not allowed to use WREG_BULK\n");
4039                         rc = -EPERM;
4040                         break;
4041
4042                 case PACKET_MSG_PROT:
4043                         dev_err(hdev->dev,
4044                                 "User not allowed to use MSG_PROT\n");
4045                         rc = -EPERM;
4046                         break;
4047
4048                 case PACKET_CP_DMA:
4049                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
4050                         rc = -EPERM;
4051                         break;
4052
4053                 case PACKET_STOP:
4054                         dev_err(hdev->dev, "User not allowed to use STOP\n");
4055                         rc = -EPERM;
4056                         break;
4057
4058                 case PACKET_MSG_LONG:
4059                 case PACKET_MSG_SHORT:
4060                 case PACKET_FENCE:
4061                 case PACKET_NOP:
4062                         memcpy(kernel_pkt, user_pkt, pkt_size);
4063                         cb_patched_cur_length += pkt_size;
4064                         break;
4065
4066                 default:
4067                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
4068                                 pkt_id);
4069                         rc = -EINVAL;
4070                         break;
4071                 }
4072
4073                 if (rc)
4074                         break;
4075         }
4076
4077         return rc;
4078 }
4079
4080 static int goya_parse_cb_mmu(struct hl_device *hdev,
4081                 struct hl_cs_parser *parser)
4082 {
4083         u64 patched_cb_handle;
4084         u32 patched_cb_size;
4085         struct hl_cb *user_cb;
4086         int rc;
4087
4088         /*
4089          * The new CB should have space at the end for two MSG_PROT pkt:
4090          * 1. A packet that will act as a completion packet
4091          * 2. A packet that will generate MSI-X interrupt
4092          */
4093         parser->patched_cb_size = parser->user_cb_size +
4094                         sizeof(struct packet_msg_prot) * 2;
4095
4096         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
4097                                 parser->patched_cb_size,
4098                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
4099
4100         if (rc) {
4101                 dev_err(hdev->dev,
4102                         "Failed to allocate patched CB for DMA CS %d\n",
4103                         rc);
4104                 return rc;
4105         }
4106
4107         patched_cb_handle >>= PAGE_SHIFT;
4108         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4109                                 (u32) patched_cb_handle);
4110         /* hl_cb_get should never fail here so use kernel WARN */
4111         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
4112                         (u32) patched_cb_handle);
4113         if (!parser->patched_cb) {
4114                 rc = -EFAULT;
4115                 goto out;
4116         }
4117
4118         /*
4119          * The check that parser->user_cb_size <= parser->user_cb->size was done
4120          * in validate_queue_index().
4121          */
4122         memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address,
4123                 (void *) (uintptr_t) parser->user_cb->kernel_address,
4124                 parser->user_cb_size);
4125
4126         patched_cb_size = parser->patched_cb_size;
4127
4128         /* validate patched CB instead of user CB */
4129         user_cb = parser->user_cb;
4130         parser->user_cb = parser->patched_cb;
4131         rc = goya_validate_cb(hdev, parser, true);
4132         parser->user_cb = user_cb;
4133
4134         if (rc) {
4135                 hl_cb_put(parser->patched_cb);
4136                 goto out;
4137         }
4138
4139         if (patched_cb_size != parser->patched_cb_size) {
4140                 dev_err(hdev->dev, "user CB size mismatch\n");
4141                 hl_cb_put(parser->patched_cb);
4142                 rc = -EINVAL;
4143                 goto out;
4144         }
4145
4146 out:
4147         /*
4148          * Always call cb destroy here because we still have 1 reference
4149          * to it by calling cb_get earlier. After the job will be completed,
4150          * cb_put will release it, but here we want to remove it from the
4151          * idr
4152          */
4153         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4154                                         patched_cb_handle << PAGE_SHIFT);
4155
4156         return rc;
4157 }
4158
4159 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4160                                 struct hl_cs_parser *parser)
4161 {
4162         u64 patched_cb_handle;
4163         int rc;
4164
4165         rc = goya_validate_cb(hdev, parser, false);
4166
4167         if (rc)
4168                 goto free_userptr;
4169
4170         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
4171                                 parser->patched_cb_size,
4172                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
4173         if (rc) {
4174                 dev_err(hdev->dev,
4175                         "Failed to allocate patched CB for DMA CS %d\n", rc);
4176                 goto free_userptr;
4177         }
4178
4179         patched_cb_handle >>= PAGE_SHIFT;
4180         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4181                                 (u32) patched_cb_handle);
4182         /* hl_cb_get should never fail here so use kernel WARN */
4183         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
4184                         (u32) patched_cb_handle);
4185         if (!parser->patched_cb) {
4186                 rc = -EFAULT;
4187                 goto out;
4188         }
4189
4190         rc = goya_patch_cb(hdev, parser);
4191
4192         if (rc)
4193                 hl_cb_put(parser->patched_cb);
4194
4195 out:
4196         /*
4197          * Always call cb destroy here because we still have 1 reference
4198          * to it by calling cb_get earlier. After the job will be completed,
4199          * cb_put will release it, but here we want to remove it from the
4200          * idr
4201          */
4202         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4203                                 patched_cb_handle << PAGE_SHIFT);
4204
4205 free_userptr:
4206         if (rc)
4207                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4208         return rc;
4209 }
4210
4211 static int goya_parse_cb_no_ext_quque(struct hl_device *hdev,
4212                                         struct hl_cs_parser *parser)
4213 {
4214         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4215         struct goya_device *goya = hdev->asic_specific;
4216
4217         if (!(goya->hw_cap_initialized & HW_CAP_MMU)) {
4218                 /* For internal queue jobs, just check if cb address is valid */
4219                 if (hl_mem_area_inside_range(
4220                                 (u64) (uintptr_t) parser->user_cb,
4221                                 parser->user_cb_size,
4222                                 asic_prop->sram_user_base_address,
4223                                 asic_prop->sram_end_address))
4224                         return 0;
4225
4226                 if (hl_mem_area_inside_range(
4227                                 (u64) (uintptr_t) parser->user_cb,
4228                                 parser->user_cb_size,
4229                                 asic_prop->dram_user_base_address,
4230                                 asic_prop->dram_end_address))
4231                         return 0;
4232
4233                 dev_err(hdev->dev,
4234                         "Internal CB address %px + 0x%x is not in SRAM nor in DRAM\n",
4235                         parser->user_cb, parser->user_cb_size);
4236
4237                 return -EFAULT;
4238         }
4239
4240         return 0;
4241 }
4242
4243 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4244 {
4245         struct goya_device *goya = hdev->asic_specific;
4246
4247         if (!parser->ext_queue)
4248                 return goya_parse_cb_no_ext_quque(hdev, parser);
4249
4250         if ((goya->hw_cap_initialized & HW_CAP_MMU) && parser->use_virt_addr)
4251                 return goya_parse_cb_mmu(hdev, parser);
4252         else
4253                 return goya_parse_cb_no_mmu(hdev, parser);
4254 }
4255
4256 void goya_add_end_of_cb_packets(u64 kernel_address, u32 len, u64 cq_addr,
4257                                 u32 cq_val, u32 msix_vec)
4258 {
4259         struct packet_msg_prot *cq_pkt;
4260         u32 tmp;
4261
4262         cq_pkt = (struct packet_msg_prot *) (uintptr_t)
4263                 (kernel_address + len - (sizeof(struct packet_msg_prot) * 2));
4264
4265         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4266                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
4267                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4268         cq_pkt->ctl = cpu_to_le32(tmp);
4269         cq_pkt->value = cpu_to_le32(cq_val);
4270         cq_pkt->addr = cpu_to_le64(cq_addr);
4271
4272         cq_pkt++;
4273
4274         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4275                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4276         cq_pkt->ctl = cpu_to_le32(tmp);
4277         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4278         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4279 }
4280
4281 static void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4282 {
4283         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, val);
4284 }
4285
4286 static void goya_restore_phase_topology(struct hl_device *hdev)
4287 {
4288         int i, num_of_sob_in_longs, num_of_mon_in_longs;
4289
4290         num_of_sob_in_longs =
4291                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4292
4293         num_of_mon_in_longs =
4294                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4295
4296         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4297                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4298
4299         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4300                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4301
4302         /* Flush all WREG to prevent race */
4303         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4304 }
4305
4306 /*
4307  * goya_debugfs_read32 - read a 32bit value from a given device address
4308  *
4309  * @hdev:       pointer to hl_device structure
4310  * @addr:       address in device
4311  * @val:        returned value
4312  *
4313  * In case of DDR address that is not mapped into the default aperture that
4314  * the DDR bar exposes, the function will configure the iATU so that the DDR
4315  * bar will be positioned at a base address that allows reading from the
4316  * required address. Configuring the iATU during normal operation can
4317  * lead to undefined behavior and therefore, should be done with extreme care
4318  *
4319  */
4320 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
4321 {
4322         struct asic_fixed_properties *prop = &hdev->asic_prop;
4323         int rc = 0;
4324
4325         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4326                 *val = RREG32(addr - CFG_BASE);
4327
4328         } else if ((addr >= SRAM_BASE_ADDR) &&
4329                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4330
4331                 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4332                                 (addr - SRAM_BASE_ADDR));
4333
4334         } else if ((addr >= DRAM_PHYS_BASE) &&
4335                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
4336
4337                 u64 bar_base_addr = DRAM_PHYS_BASE +
4338                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4339
4340                 rc = goya_set_ddr_bar_base(hdev, bar_base_addr);
4341                 if (!rc) {
4342                         *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4343                                                 (addr - bar_base_addr));
4344
4345                         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
4346                                 (MMU_PAGE_TABLES_ADDR &
4347                                         ~(prop->dram_pci_bar_size - 0x1ull)));
4348                 }
4349         } else {
4350                 rc = -EFAULT;
4351         }
4352
4353         return rc;
4354 }
4355
4356 /*
4357  * goya_debugfs_write32 - write a 32bit value to a given device address
4358  *
4359  * @hdev:       pointer to hl_device structure
4360  * @addr:       address in device
4361  * @val:        returned value
4362  *
4363  * In case of DDR address that is not mapped into the default aperture that
4364  * the DDR bar exposes, the function will configure the iATU so that the DDR
4365  * bar will be positioned at a base address that allows writing to the
4366  * required address. Configuring the iATU during normal operation can
4367  * lead to undefined behavior and therefore, should be done with extreme care
4368  *
4369  */
4370 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
4371 {
4372         struct asic_fixed_properties *prop = &hdev->asic_prop;
4373         int rc = 0;
4374
4375         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4376                 WREG32(addr - CFG_BASE, val);
4377
4378         } else if ((addr >= SRAM_BASE_ADDR) &&
4379                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4380
4381                 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4382                                         (addr - SRAM_BASE_ADDR));
4383
4384         } else if ((addr >= DRAM_PHYS_BASE) &&
4385                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
4386
4387                 u64 bar_base_addr = DRAM_PHYS_BASE +
4388                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4389
4390                 rc = goya_set_ddr_bar_base(hdev, bar_base_addr);
4391                 if (!rc) {
4392                         writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4393                                                 (addr - bar_base_addr));
4394
4395                         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
4396                                 (MMU_PAGE_TABLES_ADDR &
4397                                         ~(prop->dram_pci_bar_size - 0x1ull)));
4398                 }
4399         } else {
4400                 rc = -EFAULT;
4401         }
4402
4403         return rc;
4404 }
4405
4406 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4407 {
4408         struct goya_device *goya = hdev->asic_specific;
4409
4410         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4411                         (addr - goya->ddr_bar_cur_addr));
4412 }
4413
4414 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4415 {
4416         struct goya_device *goya = hdev->asic_specific;
4417
4418         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4419                         (addr - goya->ddr_bar_cur_addr));
4420 }
4421
4422 static const char *_goya_get_event_desc(u16 event_type)
4423 {
4424         switch (event_type) {
4425         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4426                 return "PCIe_dec";
4427         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4428         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4429         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4430         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4431         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4432         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4433         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4434         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4435                 return "TPC%d_dec";
4436         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4437                 return "MME_wacs";
4438         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4439                 return "MME_wacsd";
4440         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4441                 return "CPU_axi_splitter";
4442         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4443                 return "PSOC_axi_dec";
4444         case GOYA_ASYNC_EVENT_ID_PSOC:
4445                 return "PSOC";
4446         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4447         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4448         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4449         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4450         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4451         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4452         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4453         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4454                 return "TPC%d_krn_err";
4455         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4456                 return "TPC%d_cq";
4457         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4458                 return "TPC%d_qm";
4459         case GOYA_ASYNC_EVENT_ID_MME_QM:
4460                 return "MME_qm";
4461         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4462                 return "MME_cq";
4463         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4464                 return "DMA%d_qm";
4465         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4466                 return "DMA%d_ch";
4467         default:
4468                 return "N/A";
4469         }
4470 }
4471
4472 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4473 {
4474         u8 index;
4475
4476         switch (event_type) {
4477         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4478         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4479         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4480         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4481         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4482         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4483         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4484         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4485                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4486                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4487                 break;
4488         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4489         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4490         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4491         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4492         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4493         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4494         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4495         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4496                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4497                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4498                 break;
4499         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4500                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4501                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4502                 break;
4503         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4504                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4505                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4506                 break;
4507         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4508                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4509                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4510                 break;
4511         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4512                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4513                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4514                 break;
4515         default:
4516                 snprintf(desc, size, _goya_get_event_desc(event_type));
4517                 break;
4518         }
4519 }
4520
4521 static void goya_print_razwi_info(struct hl_device *hdev)
4522 {
4523         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4524                 dev_err(hdev->dev, "Illegal write to LBW\n");
4525                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4526         }
4527
4528         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4529                 dev_err(hdev->dev, "Illegal read from LBW\n");
4530                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4531         }
4532
4533         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4534                 dev_err(hdev->dev, "Illegal write to HBW\n");
4535                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4536         }
4537
4538         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4539                 dev_err(hdev->dev, "Illegal read from HBW\n");
4540                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4541         }
4542 }
4543
4544 static void goya_print_mmu_error_info(struct hl_device *hdev)
4545 {
4546         struct goya_device *goya = hdev->asic_specific;
4547         u64 addr;
4548         u32 val;
4549
4550         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4551                 return;
4552
4553         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4554         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4555                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4556                 addr <<= 32;
4557                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4558
4559                 dev_err(hdev->dev, "MMU page fault on va 0x%llx\n", addr);
4560
4561                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4562         }
4563 }
4564
4565 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type)
4566 {
4567         char desc[20] = "";
4568
4569         goya_get_event_desc(event_type, desc, sizeof(desc));
4570         dev_err(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4571                 event_type, desc);
4572
4573         goya_print_razwi_info(hdev);
4574         goya_print_mmu_error_info(hdev);
4575 }
4576
4577 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4578                 size_t irq_arr_size)
4579 {
4580         struct armcp_unmask_irq_arr_packet *pkt;
4581         size_t total_pkt_size;
4582         long result;
4583         int rc;
4584
4585         total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) +
4586                         irq_arr_size;
4587
4588         /* data should be aligned to 8 bytes in order to ArmCP to copy it */
4589         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4590
4591         /* total_pkt_size is casted to u16 later on */
4592         if (total_pkt_size > USHRT_MAX) {
4593                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4594                 return -EINVAL;
4595         }
4596
4597         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4598         if (!pkt)
4599                 return -ENOMEM;
4600
4601         pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0]));
4602         memcpy(&pkt->irqs, irq_arr, irq_arr_size);
4603
4604         pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4605                                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4606
4607         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4608                         total_pkt_size, HL_DEVICE_TIMEOUT_USEC, &result);
4609
4610         if (rc)
4611                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4612
4613         kfree(pkt);
4614
4615         return rc;
4616 }
4617
4618 static int goya_soft_reset_late_init(struct hl_device *hdev)
4619 {
4620         /*
4621          * Unmask all IRQs since some could have been received
4622          * during the soft reset
4623          */
4624         return goya_unmask_irq_arr(hdev, goya_non_fatal_events,
4625                         sizeof(goya_non_fatal_events));
4626 }
4627
4628 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4629 {
4630         struct armcp_packet pkt;
4631         long result;
4632         int rc;
4633
4634         memset(&pkt, 0, sizeof(pkt));
4635
4636         pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ <<
4637                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4638         pkt.value = cpu_to_le64(event_type);
4639
4640         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4641                         HL_DEVICE_TIMEOUT_USEC, &result);
4642
4643         if (rc)
4644                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4645
4646         return rc;
4647 }
4648
4649 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4650 {
4651         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4652         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4653                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4654         struct goya_device *goya = hdev->asic_specific;
4655
4656         goya->events_stat[event_type]++;
4657
4658         switch (event_type) {
4659         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4660         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4661         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4662         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4663         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4664         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4665         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4666         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4667         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4668         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4669         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4670         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4671         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4672         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4673         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4674         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4675         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4676         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4677         case GOYA_ASYNC_EVENT_ID_GIC500:
4678         case GOYA_ASYNC_EVENT_ID_PLL0:
4679         case GOYA_ASYNC_EVENT_ID_PLL1:
4680         case GOYA_ASYNC_EVENT_ID_PLL3:
4681         case GOYA_ASYNC_EVENT_ID_PLL4:
4682         case GOYA_ASYNC_EVENT_ID_PLL5:
4683         case GOYA_ASYNC_EVENT_ID_PLL6:
4684         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4685         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4686         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4687         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4688                 dev_err(hdev->dev,
4689                         "Received H/W interrupt %d, reset the chip\n",
4690                         event_type);
4691                 hl_device_reset(hdev, true, false);
4692                 break;
4693
4694         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4695         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4696         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4697         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4698         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4699         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4700         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4701         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4702         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4703         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4704         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4705         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4706         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4707         case GOYA_ASYNC_EVENT_ID_PSOC:
4708         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4709         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4710         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4711         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4712         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4713         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4714         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4715         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4716         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4717         case GOYA_ASYNC_EVENT_ID_MME_QM:
4718         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4719         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4720         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4721                 goya_print_irq_info(hdev, event_type);
4722                 goya_unmask_irq(hdev, event_type);
4723                 break;
4724
4725         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4726         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4727         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4728         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4729         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4730         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4731         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4732         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4733         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0:
4734         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH1:
4735         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH2:
4736         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH3:
4737         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4738                 dev_info(hdev->dev, "Received H/W interrupt %d\n", event_type);
4739                 break;
4740
4741         default:
4742                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4743                                 event_type);
4744                 break;
4745         }
4746 }
4747
4748 void *goya_get_events_stat(struct hl_device *hdev, u32 *size)
4749 {
4750         struct goya_device *goya = hdev->asic_specific;
4751
4752         *size = (u32) sizeof(goya->events_stat);
4753
4754         return goya->events_stat;
4755 }
4756
4757 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u32 size,
4758                                 u64 val, bool is_dram)
4759 {
4760         struct packet_lin_dma *lin_dma_pkt;
4761         struct hl_cs_parser parser;
4762         struct hl_cs_job *job;
4763         u32 cb_size, ctl;
4764         struct hl_cb *cb;
4765         int rc;
4766
4767         cb = hl_cb_kernel_create(hdev, PAGE_SIZE);
4768         if (!cb)
4769                 return -EFAULT;
4770
4771         lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address;
4772
4773         memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4774         cb_size = sizeof(*lin_dma_pkt);
4775
4776         ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4777                         (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4778                         (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4779                         (1 << GOYA_PKT_CTL_RB_SHIFT) |
4780                         (1 << GOYA_PKT_CTL_MB_SHIFT));
4781         ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4782                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4783         lin_dma_pkt->ctl = cpu_to_le32(ctl);
4784
4785         lin_dma_pkt->src_addr = cpu_to_le64(val);
4786         lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4787         lin_dma_pkt->tsize = cpu_to_le32(size);
4788
4789         job = hl_cs_allocate_job(hdev, true);
4790         if (!job) {
4791                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4792                 rc = -ENOMEM;
4793                 goto release_cb;
4794         }
4795
4796         job->id = 0;
4797         job->user_cb = cb;
4798         job->user_cb->cs_cnt++;
4799         job->user_cb_size = cb_size;
4800         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4801
4802         hl_debugfs_add_job(hdev, job);
4803
4804         parser.ctx_id = HL_KERNEL_ASID_ID;
4805         parser.cs_sequence = 0;
4806         parser.job_id = job->id;
4807         parser.hw_queue_id = job->hw_queue_id;
4808         parser.job_userptr_list = &job->userptr_list;
4809         parser.user_cb = job->user_cb;
4810         parser.user_cb_size = job->user_cb_size;
4811         parser.ext_queue = job->ext_queue;
4812         parser.use_virt_addr = hdev->mmu_enable;
4813
4814         rc = hdev->asic_funcs->cs_parser(hdev, &parser);
4815         if (rc) {
4816                 dev_err(hdev->dev, "Failed to parse kernel CB\n");
4817                 goto free_job;
4818         }
4819
4820         job->patched_cb = parser.patched_cb;
4821         job->job_cb_size = parser.patched_cb_size;
4822         job->patched_cb->cs_cnt++;
4823
4824         rc = goya_send_job_on_qman0(hdev, job);
4825
4826         job->patched_cb->cs_cnt--;
4827         hl_cb_put(job->patched_cb);
4828
4829 free_job:
4830         hl_userptr_delete_list(hdev, &job->userptr_list);
4831         hl_debugfs_remove_job(hdev, job);
4832         kfree(job);
4833         cb->cs_cnt--;
4834
4835 release_cb:
4836         hl_cb_put(cb);
4837         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4838
4839         return rc;
4840 }
4841
4842 static int goya_context_switch(struct hl_device *hdev, u32 asid)
4843 {
4844         struct asic_fixed_properties *prop = &hdev->asic_prop;
4845         u64 addr = prop->sram_base_address;
4846         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4847         u64 val = 0x7777777777777777ull;
4848         int rc;
4849
4850         rc = goya_memset_device_memory(hdev, addr, size, val, false);
4851         if (rc) {
4852                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4853                 return rc;
4854         }
4855
4856         goya_mmu_prepare(hdev, asid);
4857
4858         return 0;
4859 }
4860
4861 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4862 {
4863         struct asic_fixed_properties *prop = &hdev->asic_prop;
4864         struct goya_device *goya = hdev->asic_specific;
4865         u64 addr = prop->mmu_pgt_addr;
4866         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
4867                         MMU_CACHE_MNG_SIZE;
4868
4869         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4870                 return 0;
4871
4872         return goya_memset_device_memory(hdev, addr, size, 0, true);
4873 }
4874
4875 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4876 {
4877         struct goya_device *goya = hdev->asic_specific;
4878         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4879         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
4880         u64 val = 0x9999999999999999ull;
4881
4882         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4883                 return 0;
4884
4885         return goya_memset_device_memory(hdev, addr, size, val, true);
4886 }
4887
4888 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
4889 {
4890         struct goya_device *goya = hdev->asic_specific;
4891         int i;
4892
4893         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4894                 return;
4895
4896         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
4897                 WARN(1, "asid %u is too big\n", asid);
4898                 return;
4899         }
4900
4901         /* zero the MMBP and ASID bits and then set the ASID */
4902         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++) {
4903                 WREG32_AND(goya_mmu_regs[i], ~0x7FF);
4904                 WREG32_OR(goya_mmu_regs[i], asid);
4905         }
4906 }
4907
4908 static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard)
4909 {
4910         struct goya_device *goya = hdev->asic_specific;
4911         u32 status, timeout_usec;
4912         int rc;
4913
4914         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4915                 return;
4916
4917         /* no need in L1 only invalidation in Goya */
4918         if (!is_hard)
4919                 return;
4920
4921         if (hdev->pldm)
4922                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4923         else
4924                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4925
4926         mutex_lock(&hdev->mmu_cache_lock);
4927
4928         /* L0 & L1 invalidation */
4929         WREG32(mmSTLB_INV_ALL_START, 1);
4930
4931         rc = hl_poll_timeout(
4932                 hdev,
4933                 mmSTLB_INV_ALL_START,
4934                 status,
4935                 !status,
4936                 1000,
4937                 timeout_usec);
4938
4939         mutex_unlock(&hdev->mmu_cache_lock);
4940
4941         if (rc)
4942                 dev_notice_ratelimited(hdev->dev,
4943                         "Timeout when waiting for MMU cache invalidation\n");
4944 }
4945
4946 static void goya_mmu_invalidate_cache_range(struct hl_device *hdev,
4947                 bool is_hard, u32 asid, u64 va, u64 size)
4948 {
4949         struct goya_device *goya = hdev->asic_specific;
4950         u32 status, timeout_usec, inv_data, pi;
4951         int rc;
4952
4953         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4954                 return;
4955
4956         /* no need in L1 only invalidation in Goya */
4957         if (!is_hard)
4958                 return;
4959
4960         if (hdev->pldm)
4961                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4962         else
4963                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4964
4965         mutex_lock(&hdev->mmu_cache_lock);
4966
4967         /*
4968          * TODO: currently invalidate entire L0 & L1 as in regular hard
4969          * invalidation. Need to apply invalidation of specific cache lines with
4970          * mask of ASID & VA & size.
4971          * Note that L1 with be flushed entirely in any case.
4972          */
4973
4974         /* L0 & L1 invalidation */
4975         inv_data = RREG32(mmSTLB_CACHE_INV);
4976         /* PI is 8 bit */
4977         pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF;
4978         WREG32(mmSTLB_CACHE_INV,
4979                         (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi);
4980
4981         rc = hl_poll_timeout(
4982                 hdev,
4983                 mmSTLB_INV_CONSUMER_INDEX,
4984                 status,
4985                 status == pi,
4986                 1000,
4987                 timeout_usec);
4988
4989         mutex_unlock(&hdev->mmu_cache_lock);
4990
4991         if (rc)
4992                 dev_notice_ratelimited(hdev->dev,
4993                         "Timeout when waiting for MMU cache invalidation\n");
4994 }
4995
4996 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
4997                                                 u64 phys_addr)
4998 {
4999         u32 status, timeout_usec;
5000         int rc;
5001
5002         if (hdev->pldm)
5003                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5004         else
5005                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5006
5007         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
5008         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
5009         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
5010
5011         rc = hl_poll_timeout(
5012                 hdev,
5013                 MMU_ASID_BUSY,
5014                 status,
5015                 !(status & 0x80000000),
5016                 1000,
5017                 timeout_usec);
5018
5019         if (rc) {
5020                 dev_err(hdev->dev,
5021                         "Timeout during MMU hop0 config of asid %d\n", asid);
5022                 return rc;
5023         }
5024
5025         return 0;
5026 }
5027
5028 int goya_send_heartbeat(struct hl_device *hdev)
5029 {
5030         struct goya_device *goya = hdev->asic_specific;
5031         struct armcp_packet hb_pkt;
5032         long result;
5033         int rc;
5034
5035         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5036                 return 0;
5037
5038         memset(&hb_pkt, 0, sizeof(hb_pkt));
5039
5040         hb_pkt.ctl = cpu_to_le32(ARMCP_PACKET_TEST <<
5041                                         ARMCP_PKT_CTL_OPCODE_SHIFT);
5042         hb_pkt.value = cpu_to_le64(ARMCP_PACKET_FENCE_VAL);
5043
5044         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &hb_pkt,
5045                         sizeof(hb_pkt), HL_DEVICE_TIMEOUT_USEC, &result);
5046
5047         if ((rc) || (result != ARMCP_PACKET_FENCE_VAL))
5048                 rc = -EIO;
5049
5050         return rc;
5051 }
5052
5053 static int goya_armcp_info_get(struct hl_device *hdev)
5054 {
5055         struct goya_device *goya = hdev->asic_specific;
5056         struct asic_fixed_properties *prop = &hdev->asic_prop;
5057         struct armcp_packet pkt;
5058         void *armcp_info_cpu_addr;
5059         dma_addr_t armcp_info_dma_addr;
5060         u64 dram_size;
5061         long result;
5062         int rc;
5063
5064         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5065                 return 0;
5066
5067         armcp_info_cpu_addr =
5068                         hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev,
5069                         sizeof(struct armcp_info), &armcp_info_dma_addr);
5070         if (!armcp_info_cpu_addr) {
5071                 dev_err(hdev->dev,
5072                         "Failed to allocate DMA memory for ArmCP info packet\n");
5073                 return -ENOMEM;
5074         }
5075
5076         memset(armcp_info_cpu_addr, 0, sizeof(struct armcp_info));
5077
5078         memset(&pkt, 0, sizeof(pkt));
5079
5080         pkt.ctl = cpu_to_le32(ARMCP_PACKET_INFO_GET <<
5081                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
5082         pkt.addr = cpu_to_le64(armcp_info_dma_addr +
5083                                 prop->host_phys_base_address);
5084         pkt.data_max_size = cpu_to_le32(sizeof(struct armcp_info));
5085
5086         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
5087                         GOYA_ARMCP_INFO_TIMEOUT, &result);
5088
5089         if (rc) {
5090                 dev_err(hdev->dev,
5091                         "Failed to send armcp info pkt, error %d\n", rc);
5092                 goto out;
5093         }
5094
5095         memcpy(&prop->armcp_info, armcp_info_cpu_addr,
5096                         sizeof(prop->armcp_info));
5097
5098         dram_size = le64_to_cpu(prop->armcp_info.dram_size);
5099         if (dram_size) {
5100                 if ((!is_power_of_2(dram_size)) ||
5101                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5102                         dev_err(hdev->dev,
5103                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5104                                 dram_size);
5105                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
5106                 }
5107
5108                 prop->dram_size = dram_size;
5109                 prop->dram_end_address = prop->dram_base_address + dram_size;
5110         }
5111
5112         rc = hl_build_hwmon_channel_info(hdev, prop->armcp_info.sensors);
5113         if (rc) {
5114                 dev_err(hdev->dev,
5115                         "Failed to build hwmon channel info, error %d\n", rc);
5116                 rc = -EFAULT;
5117                 goto out;
5118         }
5119
5120 out:
5121         hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev,
5122                         sizeof(struct armcp_info), armcp_info_cpu_addr);
5123
5124         return rc;
5125 }
5126
5127 static void goya_init_clock_gating(struct hl_device *hdev)
5128 {
5129
5130 }
5131
5132 static void goya_disable_clock_gating(struct hl_device *hdev)
5133 {
5134
5135 }
5136
5137 static bool goya_is_device_idle(struct hl_device *hdev)
5138 {
5139         u64 offset, dma_qm_reg, tpc_qm_reg, tpc_cmdq_reg, tpc_cfg_reg;
5140         int i;
5141
5142         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5143
5144         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5145                 dma_qm_reg = mmDMA_QM_0_GLBL_STS0 + i * offset;
5146
5147                 if ((RREG32(dma_qm_reg) & DMA_QM_IDLE_MASK) !=
5148                                 DMA_QM_IDLE_MASK)
5149                         return false;
5150         }
5151
5152         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5153
5154         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5155                 tpc_qm_reg = mmTPC0_QM_GLBL_STS0 + i * offset;
5156                 tpc_cmdq_reg = mmTPC0_CMDQ_GLBL_STS0 + i * offset;
5157                 tpc_cfg_reg = mmTPC0_CFG_STATUS + i * offset;
5158
5159                 if ((RREG32(tpc_qm_reg) & TPC_QM_IDLE_MASK) !=
5160                                 TPC_QM_IDLE_MASK)
5161                         return false;
5162
5163                 if ((RREG32(tpc_cmdq_reg) & TPC_CMDQ_IDLE_MASK) !=
5164                                 TPC_CMDQ_IDLE_MASK)
5165                         return false;
5166
5167                 if ((RREG32(tpc_cfg_reg) & TPC_CFG_IDLE_MASK) !=
5168                                 TPC_CFG_IDLE_MASK)
5169                         return false;
5170         }
5171
5172         if ((RREG32(mmMME_QM_GLBL_STS0) & MME_QM_IDLE_MASK) !=
5173                         MME_QM_IDLE_MASK)
5174                 return false;
5175
5176         if ((RREG32(mmMME_CMDQ_GLBL_STS0) & MME_CMDQ_IDLE_MASK) !=
5177                         MME_CMDQ_IDLE_MASK)
5178                 return false;
5179
5180         if ((RREG32(mmMME_ARCH_STATUS) & MME_ARCH_IDLE_MASK) !=
5181                         MME_ARCH_IDLE_MASK)
5182                 return false;
5183
5184         if (RREG32(mmMME_SHADOW_0_STATUS) & MME_SHADOW_IDLE_MASK)
5185                 return false;
5186
5187         return true;
5188 }
5189
5190 static void goya_hw_queues_lock(struct hl_device *hdev)
5191 {
5192         struct goya_device *goya = hdev->asic_specific;
5193
5194         spin_lock(&goya->hw_queues_lock);
5195 }
5196
5197 static void goya_hw_queues_unlock(struct hl_device *hdev)
5198 {
5199         struct goya_device *goya = hdev->asic_specific;
5200
5201         spin_unlock(&goya->hw_queues_lock);
5202 }
5203
5204 static u32 goya_get_pci_id(struct hl_device *hdev)
5205 {
5206         return hdev->pdev->device;
5207 }
5208
5209 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5210                                 size_t max_size)
5211 {
5212         struct goya_device *goya = hdev->asic_specific;
5213         struct asic_fixed_properties *prop = &hdev->asic_prop;
5214         struct armcp_packet pkt;
5215         void *eeprom_info_cpu_addr;
5216         dma_addr_t eeprom_info_dma_addr;
5217         long result;
5218         int rc;
5219
5220         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5221                 return 0;
5222
5223         eeprom_info_cpu_addr =
5224                         hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev,
5225                                         max_size, &eeprom_info_dma_addr);
5226         if (!eeprom_info_cpu_addr) {
5227                 dev_err(hdev->dev,
5228                         "Failed to allocate DMA memory for EEPROM info packet\n");
5229                 return -ENOMEM;
5230         }
5231
5232         memset(eeprom_info_cpu_addr, 0, max_size);
5233
5234         memset(&pkt, 0, sizeof(pkt));
5235
5236         pkt.ctl = cpu_to_le32(ARMCP_PACKET_EEPROM_DATA_GET <<
5237                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
5238         pkt.addr = cpu_to_le64(eeprom_info_dma_addr +
5239                                 prop->host_phys_base_address);
5240         pkt.data_max_size = cpu_to_le32(max_size);
5241
5242         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
5243                         GOYA_ARMCP_EEPROM_TIMEOUT, &result);
5244
5245         if (rc) {
5246                 dev_err(hdev->dev,
5247                         "Failed to send armcp EEPROM pkt, error %d\n", rc);
5248                 goto out;
5249         }
5250
5251         /* result contains the actual size */
5252         memcpy(data, eeprom_info_cpu_addr, min((size_t)result, max_size));
5253
5254 out:
5255         hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, max_size,
5256                         eeprom_info_cpu_addr);
5257
5258         return rc;
5259 }
5260
5261 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
5262 {
5263         return RREG32(mmPSOC_GLOBAL_CONF_APP_STATUS);
5264 }
5265
5266 static const struct hl_asic_funcs goya_funcs = {
5267         .early_init = goya_early_init,
5268         .early_fini = goya_early_fini,
5269         .late_init = goya_late_init,
5270         .late_fini = goya_late_fini,
5271         .sw_init = goya_sw_init,
5272         .sw_fini = goya_sw_fini,
5273         .hw_init = goya_hw_init,
5274         .hw_fini = goya_hw_fini,
5275         .halt_engines = goya_halt_engines,
5276         .suspend = goya_suspend,
5277         .resume = goya_resume,
5278         .cb_mmap = goya_cb_mmap,
5279         .ring_doorbell = goya_ring_doorbell,
5280         .flush_pq_write = goya_flush_pq_write,
5281         .dma_alloc_coherent = goya_dma_alloc_coherent,
5282         .dma_free_coherent = goya_dma_free_coherent,
5283         .get_int_queue_base = goya_get_int_queue_base,
5284         .test_queues = goya_test_queues,
5285         .dma_pool_zalloc = goya_dma_pool_zalloc,
5286         .dma_pool_free = goya_dma_pool_free,
5287         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5288         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5289         .hl_dma_unmap_sg = goya_dma_unmap_sg,
5290         .cs_parser = goya_cs_parser,
5291         .asic_dma_map_sg = goya_dma_map_sg,
5292         .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5293         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5294         .update_eq_ci = goya_update_eq_ci,
5295         .context_switch = goya_context_switch,
5296         .restore_phase_topology = goya_restore_phase_topology,
5297         .debugfs_read32 = goya_debugfs_read32,
5298         .debugfs_write32 = goya_debugfs_write32,
5299         .add_device_attr = goya_add_device_attr,
5300         .handle_eqe = goya_handle_eqe,
5301         .set_pll_profile = goya_set_pll_profile,
5302         .get_events_stat = goya_get_events_stat,
5303         .read_pte = goya_read_pte,
5304         .write_pte = goya_write_pte,
5305         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5306         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5307         .send_heartbeat = goya_send_heartbeat,
5308         .enable_clock_gating = goya_init_clock_gating,
5309         .disable_clock_gating = goya_disable_clock_gating,
5310         .is_device_idle = goya_is_device_idle,
5311         .soft_reset_late_init = goya_soft_reset_late_init,
5312         .hw_queues_lock = goya_hw_queues_lock,
5313         .hw_queues_unlock = goya_hw_queues_unlock,
5314         .get_pci_id = goya_get_pci_id,
5315         .get_eeprom_data = goya_get_eeprom_data,
5316         .send_cpu_message = goya_send_cpu_message,
5317         .get_hw_state = goya_get_hw_state
5318 };
5319
5320 /*
5321  * goya_set_asic_funcs - set Goya function pointers
5322  *
5323  * @*hdev: pointer to hl_device structure
5324  *
5325  */
5326 void goya_set_asic_funcs(struct hl_device *hdev)
5327 {
5328         hdev->asic_funcs = &goya_funcs;
5329 }