drivers/mfd/intel-lpss.c

   1 /*
   2  * Intel Sunrisepoint LPSS core support.
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  *
   6  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
   9  *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clkdev.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/debugfs.h>
  20 #include <linux/idr.h>
  21 #include <linux/ioport.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/mfd/core.h>
  25 #include <linux/pm_qos.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/property.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/io-64-nonatomic-lo-hi.h>
  30
  31 #include "intel-lpss.h"
  32
  33 #define LPSS_DEV_OFFSET         0x000
  34 #define LPSS_DEV_SIZE           0x200
  35 #define LPSS_PRIV_OFFSET        0x200
  36 #define LPSS_PRIV_SIZE          0x100
  37 #define LPSS_PRIV_REG_COUNT     (LPSS_PRIV_SIZE / 4)
  38 #define LPSS_IDMA64_OFFSET      0x800
  39 #define LPSS_IDMA64_SIZE        0x800
  40
  41 /* Offsets from lpss->priv */
  42 #define LPSS_PRIV_RESETS                0x04
  43 #define LPSS_PRIV_RESETS_FUNC           BIT(2)
  44 #define LPSS_PRIV_RESETS_IDMA           0x3
  45
  46 #define LPSS_PRIV_ACTIVELTR             0x10
  47 #define LPSS_PRIV_IDLELTR               0x14
  48
  49 #define LPSS_PRIV_LTR_REQ               BIT(15)
  50 #define LPSS_PRIV_LTR_SCALE_MASK        0xc00
  51 #define LPSS_PRIV_LTR_SCALE_1US         0x800
  52 #define LPSS_PRIV_LTR_SCALE_32US        0xc00
  53 #define LPSS_PRIV_LTR_VALUE_MASK        0x3ff
  54
  55 #define LPSS_PRIV_SSP_REG               0x20
  56 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN   BIT(0)
  57
  58 #define LPSS_PRIV_REMAP_ADDR            0x40
  59
  60 #define LPSS_PRIV_CAPS                  0xfc
  61 #define LPSS_PRIV_CAPS_NO_IDMA          BIT(8)
  62 #define LPSS_PRIV_CAPS_TYPE_SHIFT       4
  63 #define LPSS_PRIV_CAPS_TYPE_MASK        (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
  64
  65 /* This matches the type field in CAPS register */
  66 enum intel_lpss_dev_type {
  67         LPSS_DEV_I2C = 0,
  68         LPSS_DEV_UART,
  69         LPSS_DEV_SPI,
  70 };
  71
  72 struct intel_lpss {
  73         const struct intel_lpss_platform_info *info;
  74         enum intel_lpss_dev_type type;
  75         struct clk *clk;
  76         struct clk_lookup *clock;
  77         struct mfd_cell *cell;
  78         struct device *dev;
  79         void __iomem *priv;
  80         u32 priv_ctx[LPSS_PRIV_REG_COUNT];
  81         int devid;
  82         u32 caps;
  83         u32 active_ltr;
  84         u32 idle_ltr;
  85         struct dentry *debugfs;
  86 };
  87
  88 static const struct resource intel_lpss_dev_resources[] = {
  89         DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
  90         DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
  91         DEFINE_RES_IRQ(0),
  92 };
  93
  94 static const struct resource intel_lpss_idma64_resources[] = {
  95         DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
  96         DEFINE_RES_IRQ(0),
  97 };
  98
  99 #define LPSS_IDMA64_DRIVER_NAME         "idma64"
 100
 101 /*
 102  * Cells needs to be ordered so that the iDMA is created first. This is
 103  * because we need to be sure the DMA is available when the host controller
 104  * driver is probed.
 105  */
 106 static const struct mfd_cell intel_lpss_idma64_cell = {
 107         .name = LPSS_IDMA64_DRIVER_NAME,
 108         .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
 109         .resources = intel_lpss_idma64_resources,
 110 };
 111
 112 static const struct mfd_cell intel_lpss_i2c_cell = {
 113         .name = "i2c_designware",
 114         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 115         .resources = intel_lpss_dev_resources,
 116 };
 117
 118 static const struct mfd_cell intel_lpss_uart_cell = {
 119         .name = "dw-apb-uart",
 120         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 121         .resources = intel_lpss_dev_resources,
 122 };
 123
 124 static const struct mfd_cell intel_lpss_spi_cell = {
 125         .name = "pxa2xx-spi",
 126         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 127         .resources = intel_lpss_dev_resources,
 128 };
 129
 130 static DEFINE_IDA(intel_lpss_devid_ida);
 131 static struct dentry *intel_lpss_debugfs;
 132
 133 static int intel_lpss_request_dma_module(const char *name)
 134 {
 135         static bool intel_lpss_dma_requested;
 136
 137         if (intel_lpss_dma_requested)
 138                 return 0;
 139
 140         intel_lpss_dma_requested = true;
 141         return request_module("%s", name);
 142 }
 143
 144 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
 145 {
 146         lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
 147         lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
 148 }
 149
 150 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
 151 {
 152         struct dentry *dir;
 153
 154         dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
 155         if (IS_ERR(dir))
 156                 return PTR_ERR(dir);
 157
 158         /* Cache the values into lpss structure */
 159         intel_lpss_cache_ltr(lpss);
 160
 161         debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
 162         debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
 163         debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
 164
 165         lpss->debugfs = dir;
 166         return 0;
 167 }
 168
 169 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
 170 {
 171         debugfs_remove_recursive(lpss->debugfs);
 172 }
 173
 174 static void intel_lpss_ltr_set(struct device *dev, s32 val)
 175 {
 176         struct intel_lpss *lpss = dev_get_drvdata(dev);
 177         u32 ltr;
 178
 179         /*
 180          * Program latency tolerance (LTR) accordingly what has been asked
 181          * by the PM QoS layer or disable it in case we were passed
 182          * negative value or PM_QOS_LATENCY_ANY.
 183          */
 184         ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
 185
 186         if (val == PM_QOS_LATENCY_ANY || val < 0) {
 187                 ltr &= ~LPSS_PRIV_LTR_REQ;
 188         } else {
 189                 ltr |= LPSS_PRIV_LTR_REQ;
 190                 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
 191                 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
 192
 193                 if (val > LPSS_PRIV_LTR_VALUE_MASK)
 194                         ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
 195                 else
 196                         ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
 197         }
 198
 199         if (ltr == lpss->active_ltr)
 200                 return;
 201
 202         writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
 203         writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
 204
 205         /* Cache the values into lpss structure */
 206         intel_lpss_cache_ltr(lpss);
 207 }
 208
 209 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
 210 {
 211         lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
 212         dev_pm_qos_expose_latency_tolerance(lpss->dev);
 213 }
 214
 215 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
 216 {
 217         dev_pm_qos_hide_latency_tolerance(lpss->dev);
 218         lpss->dev->power.set_latency_tolerance = NULL;
 219 }
 220
 221 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
 222 {
 223         const struct mfd_cell *cell;
 224         unsigned int type;
 225
 226         type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
 227         type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
 228
 229         switch (type) {
 230         case LPSS_DEV_I2C:
 231                 cell = &intel_lpss_i2c_cell;
 232                 break;
 233         case LPSS_DEV_UART:
 234                 cell = &intel_lpss_uart_cell;
 235                 break;
 236         case LPSS_DEV_SPI:
 237                 cell = &intel_lpss_spi_cell;
 238                 break;
 239         default:
 240                 return -ENODEV;
 241         }
 242
 243         lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
 244         if (!lpss->cell)
 245                 return -ENOMEM;
 246
 247         lpss->type = type;
 248
 249         return 0;
 250 }
 251
 252 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
 253 {
 254         return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
 255 }
 256
 257 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
 258 {
 259         resource_size_t addr = lpss->info->mem->start;
 260
 261         lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
 262 }
 263
 264 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
 265 {
 266         u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
 267
 268         /* Bring out the device from reset */
 269         writel(value, lpss->priv + LPSS_PRIV_RESETS);
 270 }
 271
 272 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
 273 {
 274         u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
 275
 276         intel_lpss_deassert_reset(lpss);
 277
 278         if (!intel_lpss_has_idma(lpss))
 279                 return;
 280
 281         intel_lpss_set_remap_addr(lpss);
 282
 283         /* Make sure that SPI multiblock DMA transfers are re-enabled */
 284         if (lpss->type == LPSS_DEV_SPI)
 285                 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
 286 }
 287
 288 static void intel_lpss_unregister_clock_tree(struct clk *clk)
 289 {
 290         struct clk *parent;
 291
 292         while (clk) {
 293                 parent = clk_get_parent(clk);
 294                 clk_unregister(clk);
 295                 clk = parent;
 296         }
 297 }
 298
 299 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
 300                                              const char *devname,
 301                                              struct clk **clk)
 302 {
 303         char name[32];
 304         struct clk *tmp = *clk;
 305
 306         snprintf(name, sizeof(name), "%s-enable", devname);
 307         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
 308                                 lpss->priv, 0, 0, NULL);
 309         if (IS_ERR(tmp))
 310                 return PTR_ERR(tmp);
 311
 312         snprintf(name, sizeof(name), "%s-div", devname);
 313         tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
 314                                               0, lpss->priv, 1, 15, 16, 15, 0,
 315                                               NULL);
 316         if (IS_ERR(tmp))
 317                 return PTR_ERR(tmp);
 318         *clk = tmp;
 319
 320         snprintf(name, sizeof(name), "%s-update", devname);
 321         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
 322                                 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
 323         if (IS_ERR(tmp))
 324                 return PTR_ERR(tmp);
 325         *clk = tmp;
 326
 327         return 0;
 328 }
 329
 330 static int intel_lpss_register_clock(struct intel_lpss *lpss)
 331 {
 332         const struct mfd_cell *cell = lpss->cell;
 333         struct clk *clk;
 334         char devname[24];
 335         int ret;
 336
 337         if (!lpss->info->clk_rate)
 338                 return 0;
 339
 340         /* Root clock */
 341         clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
 342                                       lpss->info->clk_rate);
 343         if (IS_ERR(clk))
 344                 return PTR_ERR(clk);
 345
 346         snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
 347
 348         /*
 349          * Support for clock divider only if it has some preset value.
 350          * Otherwise we assume that the divider is not used.
 351          */
 352         if (lpss->type != LPSS_DEV_I2C) {
 353                 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
 354                 if (ret)
 355                         goto err_clk_register;
 356         }
 357
 358         ret = -ENOMEM;
 359
 360         /* Clock for the host controller */
 361         lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
 362         if (!lpss->clock)
 363                 goto err_clk_register;
 364
 365         lpss->clk = clk;
 366
 367         return 0;
 368
 369 err_clk_register:
 370         intel_lpss_unregister_clock_tree(clk);
 371
 372         return ret;
 373 }
 374
 375 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
 376 {
 377         if (IS_ERR_OR_NULL(lpss->clk))
 378                 return;
 379
 380         clkdev_drop(lpss->clock);
 381         intel_lpss_unregister_clock_tree(lpss->clk);
 382 }
 383
 384 int intel_lpss_probe(struct device *dev,
 385                      const struct intel_lpss_platform_info *info)
 386 {
 387         struct intel_lpss *lpss;
 388         int ret;
 389
 390         if (!info || !info->mem || info->irq <= 0)
 391                 return -EINVAL;
 392
 393         lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
 394         if (!lpss)
 395                 return -ENOMEM;
 396
 397         lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
 398                                   LPSS_PRIV_SIZE);
 399         if (!lpss->priv)
 400                 return -ENOMEM;
 401
 402         lpss->info = info;
 403         lpss->dev = dev;
 404         lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
 405
 406         dev_set_drvdata(dev, lpss);
 407
 408         ret = intel_lpss_assign_devs(lpss);
 409         if (ret)
 410                 return ret;
 411
 412         lpss->cell->properties = info->properties;
 413
 414         intel_lpss_init_dev(lpss);
 415
 416         lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
 417         if (lpss->devid < 0)
 418                 return lpss->devid;
 419
 420         ret = intel_lpss_register_clock(lpss);
 421         if (ret)
 422                 goto err_clk_register;
 423
 424         intel_lpss_ltr_expose(lpss);
 425
 426         ret = intel_lpss_debugfs_add(lpss);
 427         if (ret)
 428                 dev_warn(dev, "Failed to create debugfs entries\n");
 429
 430         if (intel_lpss_has_idma(lpss)) {
 431                 /*
 432                  * Ensure the DMA driver is loaded before the host
 433                  * controller device appears, so that the host controller
 434                  * driver can request its DMA channels as early as
 435                  * possible.
 436                  *
 437                  * If the DMA module is not there that's OK as well.
 438                  */
 439                 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
 440
 441                 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
 442                                       1, info->mem, info->irq, NULL);
 443                 if (ret)
 444                         dev_warn(dev, "Failed to add %s, fallback to PIO\n",
 445                                  LPSS_IDMA64_DRIVER_NAME);
 446         }
 447
 448         ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
 449                               1, info->mem, info->irq, NULL);
 450         if (ret)
 451                 goto err_remove_ltr;
 452
 453         dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
 454
 455         return 0;
 456
 457 err_remove_ltr:
 458         intel_lpss_debugfs_remove(lpss);
 459         intel_lpss_ltr_hide(lpss);
 460         intel_lpss_unregister_clock(lpss);
 461
 462 err_clk_register:
 463         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
 464
 465         return ret;
 466 }
 467 EXPORT_SYMBOL_GPL(intel_lpss_probe);
 468
 469 void intel_lpss_remove(struct device *dev)
 470 {
 471         struct intel_lpss *lpss = dev_get_drvdata(dev);
 472
 473         mfd_remove_devices(dev);
 474         intel_lpss_debugfs_remove(lpss);
 475         intel_lpss_ltr_hide(lpss);
 476         intel_lpss_unregister_clock(lpss);
 477         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
 478 }
 479 EXPORT_SYMBOL_GPL(intel_lpss_remove);
 480
 481 static int resume_lpss_device(struct device *dev, void *data)
 482 {
 483         if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
 484                 pm_runtime_resume(dev);
 485
 486         return 0;
 487 }
 488
 489 int intel_lpss_prepare(struct device *dev)
 490 {
 491         /*
 492          * Resume both child devices before entering system sleep. This
 493          * ensures that they are in proper state before they get suspended.
 494          */
 495         device_for_each_child_reverse(dev, NULL, resume_lpss_device);
 496         return 0;
 497 }
 498 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
 499
 500 int intel_lpss_suspend(struct device *dev)
 501 {
 502         struct intel_lpss *lpss = dev_get_drvdata(dev);
 503         unsigned int i;
 504
 505         /* Save device context */
 506         for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
 507                 lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
 508
 509         /*
 510          * If the device type is not UART, then put the controller into
 511          * reset. UART cannot be put into reset since S3/S0ix fail when
 512          * no_console_suspend flag is enabled.
 513          */
 514         if (lpss->type != LPSS_DEV_UART)
 515                 writel(0, lpss->priv + LPSS_PRIV_RESETS);
 516
 517         return 0;
 518 }
 519 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
 520
 521 int intel_lpss_resume(struct device *dev)
 522 {
 523         struct intel_lpss *lpss = dev_get_drvdata(dev);
 524         unsigned int i;
 525
 526         intel_lpss_deassert_reset(lpss);
 527
 528         /* Restore device context */
 529         for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
 530                 writel(lpss->priv_ctx[i], lpss->priv + i * 4);
 531
 532         return 0;
 533 }
 534 EXPORT_SYMBOL_GPL(intel_lpss_resume);
 535
 536 static int __init intel_lpss_init(void)
 537 {
 538         intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
 539         return 0;
 540 }
 541 module_init(intel_lpss_init);
 542
 543 static void __exit intel_lpss_exit(void)
 544 {
 545         debugfs_remove(intel_lpss_debugfs);
 546 }
 547 module_exit(intel_lpss_exit);
 548
 549 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 550 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 551 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
 552 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
 553 MODULE_DESCRIPTION("Intel LPSS core driver");
 554 MODULE_LICENSE("GPL v2");