drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34 #include "cimax2.h"
  35 #include "cx23888-ir.h"
  36 #include "cx23885-ir.h"
  37 #include "cx23885-input.h"
  38
  39 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  40 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
  41 MODULE_LICENSE("GPL");
  42
  43 static unsigned int debug;
  44 module_param(debug, int, 0644);
  45 MODULE_PARM_DESC(debug, "enable debug messages");
  46
  47 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  48 module_param_array(card,  int, NULL, 0444);
  49 MODULE_PARM_DESC(card, "card type");
  50
  51 #define dprintk(level, fmt, arg...)\
  52         do { if (debug >= level)\
  53                 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  54         } while (0)
  55
  56 static unsigned int cx23885_devcount;
  57
  58 #define NO_SYNC_LINE (-1U)
  59
  60 /* FIXME, these allocations will change when
  61  * analog arrives. The be reviewed.
  62  * CX23887 Assumptions
  63  * 1 line = 16 bytes of CDT
  64  * cmds size = 80
  65  * cdt size = 16 * linesize
  66  * iqsize = 64
  67  * maxlines = 6
  68  *
  69  * Address Space:
  70  * 0x00000000 0x00008fff FIFO clusters
  71  * 0x00010000 0x000104af Channel Management Data Structures
  72  * 0x000104b0 0x000104ff Free
  73  * 0x00010500 0x000108bf 15 channels * iqsize
  74  * 0x000108c0 0x000108ff Free
  75  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  76  *                       15 channels * (iqsize + (maxlines * linesize))
  77  * 0x00010ea0 0x00010xxx Free
  78  */
  79
  80 static struct sram_channel cx23885_sram_channels[] = {
  81         [SRAM_CH01] = {
  82                 .name           = "VID A",
  83                 .cmds_start     = 0x10000,
  84                 .ctrl_start     = 0x10380,
  85                 .cdt            = 0x104c0,
  86                 .fifo_start     = 0x40,
  87                 .fifo_size      = 0x2800,
  88                 .ptr1_reg       = DMA1_PTR1,
  89                 .ptr2_reg       = DMA1_PTR2,
  90                 .cnt1_reg       = DMA1_CNT1,
  91                 .cnt2_reg       = DMA1_CNT2,
  92         },
  93         [SRAM_CH02] = {
  94                 .name           = "ch2",
  95                 .cmds_start     = 0x0,
  96                 .ctrl_start     = 0x0,
  97                 .cdt            = 0x0,
  98                 .fifo_start     = 0x0,
  99                 .fifo_size      = 0x0,
 100                 .ptr1_reg       = DMA2_PTR1,
 101                 .ptr2_reg       = DMA2_PTR2,
 102                 .cnt1_reg       = DMA2_CNT1,
 103                 .cnt2_reg       = DMA2_CNT2,
 104         },
 105         [SRAM_CH03] = {
 106                 .name           = "TS1 B",
 107                 .cmds_start     = 0x100A0,
 108                 .ctrl_start     = 0x10400,
 109                 .cdt            = 0x10580,
 110                 .fifo_start     = 0x5000,
 111                 .fifo_size      = 0x1000,
 112                 .ptr1_reg       = DMA3_PTR1,
 113                 .ptr2_reg       = DMA3_PTR2,
 114                 .cnt1_reg       = DMA3_CNT1,
 115                 .cnt2_reg       = DMA3_CNT2,
 116         },
 117         [SRAM_CH04] = {
 118                 .name           = "ch4",
 119                 .cmds_start     = 0x0,
 120                 .ctrl_start     = 0x0,
 121                 .cdt            = 0x0,
 122                 .fifo_start     = 0x0,
 123                 .fifo_size      = 0x0,
 124                 .ptr1_reg       = DMA4_PTR1,
 125                 .ptr2_reg       = DMA4_PTR2,
 126                 .cnt1_reg       = DMA4_CNT1,
 127                 .cnt2_reg       = DMA4_CNT2,
 128         },
 129         [SRAM_CH05] = {
 130                 .name           = "ch5",
 131                 .cmds_start     = 0x0,
 132                 .ctrl_start     = 0x0,
 133                 .cdt            = 0x0,
 134                 .fifo_start     = 0x0,
 135                 .fifo_size      = 0x0,
 136                 .ptr1_reg       = DMA5_PTR1,
 137                 .ptr2_reg       = DMA5_PTR2,
 138                 .cnt1_reg       = DMA5_CNT1,
 139                 .cnt2_reg       = DMA5_CNT2,
 140         },
 141         [SRAM_CH06] = {
 142                 .name           = "TS2 C",
 143                 .cmds_start     = 0x10140,
 144                 .ctrl_start     = 0x10440,
 145                 .cdt            = 0x105e0,
 146                 .fifo_start     = 0x6000,
 147                 .fifo_size      = 0x1000,
 148                 .ptr1_reg       = DMA5_PTR1,
 149                 .ptr2_reg       = DMA5_PTR2,
 150                 .cnt1_reg       = DMA5_CNT1,
 151                 .cnt2_reg       = DMA5_CNT2,
 152         },
 153         [SRAM_CH07] = {
 154                 .name           = "ch7",
 155                 .cmds_start     = 0x0,
 156                 .ctrl_start     = 0x0,
 157                 .cdt            = 0x0,
 158                 .fifo_start     = 0x0,
 159                 .fifo_size      = 0x0,
 160                 .ptr1_reg       = DMA6_PTR1,
 161                 .ptr2_reg       = DMA6_PTR2,
 162                 .cnt1_reg       = DMA6_CNT1,
 163                 .cnt2_reg       = DMA6_CNT2,
 164         },
 165         [SRAM_CH08] = {
 166                 .name           = "ch8",
 167                 .cmds_start     = 0x0,
 168                 .ctrl_start     = 0x0,
 169                 .cdt            = 0x0,
 170                 .fifo_start     = 0x0,
 171                 .fifo_size      = 0x0,
 172                 .ptr1_reg       = DMA7_PTR1,
 173                 .ptr2_reg       = DMA7_PTR2,
 174                 .cnt1_reg       = DMA7_CNT1,
 175                 .cnt2_reg       = DMA7_CNT2,
 176         },
 177         [SRAM_CH09] = {
 178                 .name           = "ch9",
 179                 .cmds_start     = 0x0,
 180                 .ctrl_start     = 0x0,
 181                 .cdt            = 0x0,
 182                 .fifo_start     = 0x0,
 183                 .fifo_size      = 0x0,
 184                 .ptr1_reg       = DMA8_PTR1,
 185                 .ptr2_reg       = DMA8_PTR2,
 186                 .cnt1_reg       = DMA8_CNT1,
 187                 .cnt2_reg       = DMA8_CNT2,
 188         },
 189 };
 190
 191 static struct sram_channel cx23887_sram_channels[] = {
 192         [SRAM_CH01] = {
 193                 .name           = "VID A",
 194                 .cmds_start     = 0x10000,
 195                 .ctrl_start     = 0x105b0,
 196                 .cdt            = 0x107b0,
 197                 .fifo_start     = 0x40,
 198                 .fifo_size      = 0x2800,
 199                 .ptr1_reg       = DMA1_PTR1,
 200                 .ptr2_reg       = DMA1_PTR2,
 201                 .cnt1_reg       = DMA1_CNT1,
 202                 .cnt2_reg       = DMA1_CNT2,
 203         },
 204         [SRAM_CH02] = {
 205                 .name           = "ch2",
 206                 .cmds_start     = 0x0,
 207                 .ctrl_start     = 0x0,
 208                 .cdt            = 0x0,
 209                 .fifo_start     = 0x0,
 210                 .fifo_size      = 0x0,
 211                 .ptr1_reg       = DMA2_PTR1,
 212                 .ptr2_reg       = DMA2_PTR2,
 213                 .cnt1_reg       = DMA2_CNT1,
 214                 .cnt2_reg       = DMA2_CNT2,
 215         },
 216         [SRAM_CH03] = {
 217                 .name           = "TS1 B",
 218                 .cmds_start     = 0x100A0,
 219                 .ctrl_start     = 0x10630,
 220                 .cdt            = 0x10870,
 221                 .fifo_start     = 0x5000,
 222                 .fifo_size      = 0x1000,
 223                 .ptr1_reg       = DMA3_PTR1,
 224                 .ptr2_reg       = DMA3_PTR2,
 225                 .cnt1_reg       = DMA3_CNT1,
 226                 .cnt2_reg       = DMA3_CNT2,
 227         },
 228         [SRAM_CH04] = {
 229                 .name           = "ch4",
 230                 .cmds_start     = 0x0,
 231                 .ctrl_start     = 0x0,
 232                 .cdt            = 0x0,
 233                 .fifo_start     = 0x0,
 234                 .fifo_size      = 0x0,
 235                 .ptr1_reg       = DMA4_PTR1,
 236                 .ptr2_reg       = DMA4_PTR2,
 237                 .cnt1_reg       = DMA4_CNT1,
 238                 .cnt2_reg       = DMA4_CNT2,
 239         },
 240         [SRAM_CH05] = {
 241                 .name           = "ch5",
 242                 .cmds_start     = 0x0,
 243                 .ctrl_start     = 0x0,
 244                 .cdt            = 0x0,
 245                 .fifo_start     = 0x0,
 246                 .fifo_size      = 0x0,
 247                 .ptr1_reg       = DMA5_PTR1,
 248                 .ptr2_reg       = DMA5_PTR2,
 249                 .cnt1_reg       = DMA5_CNT1,
 250                 .cnt2_reg       = DMA5_CNT2,
 251         },
 252         [SRAM_CH06] = {
 253                 .name           = "TS2 C",
 254                 .cmds_start     = 0x10140,
 255                 .ctrl_start     = 0x10670,
 256                 .cdt            = 0x108d0,
 257                 .fifo_start     = 0x6000,
 258                 .fifo_size      = 0x1000,
 259                 .ptr1_reg       = DMA5_PTR1,
 260                 .ptr2_reg       = DMA5_PTR2,
 261                 .cnt1_reg       = DMA5_CNT1,
 262                 .cnt2_reg       = DMA5_CNT2,
 263         },
 264         [SRAM_CH07] = {
 265                 .name           = "ch7",
 266                 .cmds_start     = 0x0,
 267                 .ctrl_start     = 0x0,
 268                 .cdt            = 0x0,
 269                 .fifo_start     = 0x0,
 270                 .fifo_size      = 0x0,
 271                 .ptr1_reg       = DMA6_PTR1,
 272                 .ptr2_reg       = DMA6_PTR2,
 273                 .cnt1_reg       = DMA6_CNT1,
 274                 .cnt2_reg       = DMA6_CNT2,
 275         },
 276         [SRAM_CH08] = {
 277                 .name           = "ch8",
 278                 .cmds_start     = 0x0,
 279                 .ctrl_start     = 0x0,
 280                 .cdt            = 0x0,
 281                 .fifo_start     = 0x0,
 282                 .fifo_size      = 0x0,
 283                 .ptr1_reg       = DMA7_PTR1,
 284                 .ptr2_reg       = DMA7_PTR2,
 285                 .cnt1_reg       = DMA7_CNT1,
 286                 .cnt2_reg       = DMA7_CNT2,
 287         },
 288         [SRAM_CH09] = {
 289                 .name           = "ch9",
 290                 .cmds_start     = 0x0,
 291                 .ctrl_start     = 0x0,
 292                 .cdt            = 0x0,
 293                 .fifo_start     = 0x0,
 294                 .fifo_size      = 0x0,
 295                 .ptr1_reg       = DMA8_PTR1,
 296                 .ptr2_reg       = DMA8_PTR2,
 297                 .cnt1_reg       = DMA8_CNT1,
 298                 .cnt2_reg       = DMA8_CNT2,
 299         },
 300 };
 301
 302 static int cx23885_risc_decode(u32 risc)
 303 {
 304         static char *instr[16] = {
 305                 [RISC_SYNC    >> 28] = "sync",
 306                 [RISC_WRITE   >> 28] = "write",
 307                 [RISC_WRITEC  >> 28] = "writec",
 308                 [RISC_READ    >> 28] = "read",
 309                 [RISC_READC   >> 28] = "readc",
 310                 [RISC_JUMP    >> 28] = "jump",
 311                 [RISC_SKIP    >> 28] = "skip",
 312                 [RISC_WRITERM >> 28] = "writerm",
 313                 [RISC_WRITECM >> 28] = "writecm",
 314                 [RISC_WRITECR >> 28] = "writecr",
 315         };
 316         static int incr[16] = {
 317                 [RISC_WRITE   >> 28] = 3,
 318                 [RISC_JUMP    >> 28] = 3,
 319                 [RISC_SKIP    >> 28] = 1,
 320                 [RISC_SYNC    >> 28] = 1,
 321                 [RISC_WRITERM >> 28] = 3,
 322                 [RISC_WRITECM >> 28] = 3,
 323                 [RISC_WRITECR >> 28] = 4,
 324         };
 325         static char *bits[] = {
 326                 "12",   "13",   "14",   "resync",
 327                 "cnt0", "cnt1", "18",   "19",
 328                 "20",   "21",   "22",   "23",
 329                 "irq1", "irq2", "eol",  "sol",
 330         };
 331         int i;
 332
 333         printk("0x%08x [ %s", risc,
 334                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 335         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 336                 if (risc & (1 << (i + 12)))
 337                         printk(" %s", bits[i]);
 338         printk(" count=%d ]\n", risc & 0xfff);
 339         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 340 }
 341
 342 void cx23885_wakeup(struct cx23885_tsport *port,
 343                            struct cx23885_dmaqueue *q, u32 count)
 344 {
 345         struct cx23885_dev *dev = port->dev;
 346         struct cx23885_buffer *buf;
 347         int bc;
 348
 349         for (bc = 0;; bc++) {
 350                 if (list_empty(&q->active))
 351                         break;
 352                 buf = list_entry(q->active.next,
 353                                  struct cx23885_buffer, vb.queue);
 354
 355                 /* count comes from the hw and is is 16bit wide --
 356                  * this trick handles wrap-arounds correctly for
 357                  * up to 32767 buffers in flight... */
 358                 if ((s16) (count - buf->count) < 0)
 359                         break;
 360
 361                 do_gettimeofday(&buf->vb.ts);
 362                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 363                         count, buf->count);
 364                 buf->vb.state = VIDEOBUF_DONE;
 365                 list_del(&buf->vb.queue);
 366                 wake_up(&buf->vb.done);
 367         }
 368         if (list_empty(&q->active))
 369                 del_timer(&q->timeout);
 370         else
 371                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 372         if (bc != 1)
 373                 printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
 374                        __func__, bc);
 375 }
 376
 377 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 378                                       struct sram_channel *ch,
 379                                       unsigned int bpl, u32 risc)
 380 {
 381         unsigned int i, lines;
 382         u32 cdt;
 383
 384         if (ch->cmds_start == 0) {
 385                 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
 386                         ch->name);
 387                 cx_write(ch->ptr1_reg, 0);
 388                 cx_write(ch->ptr2_reg, 0);
 389                 cx_write(ch->cnt2_reg, 0);
 390                 cx_write(ch->cnt1_reg, 0);
 391                 return 0;
 392         } else {
 393                 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
 394                         ch->name);
 395         }
 396
 397         bpl   = (bpl + 7) & ~7; /* alignment */
 398         cdt   = ch->cdt;
 399         lines = ch->fifo_size / bpl;
 400         if (lines > 6)
 401                 lines = 6;
 402         BUG_ON(lines < 2);
 403
 404         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 405         cx_write(8 + 4, 8);
 406         cx_write(8 + 8, 0);
 407
 408         /* write CDT */
 409         for (i = 0; i < lines; i++) {
 410                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
 411                         ch->fifo_start + bpl*i);
 412                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 413                 cx_write(cdt + 16*i +  4, 0);
 414                 cx_write(cdt + 16*i +  8, 0);
 415                 cx_write(cdt + 16*i + 12, 0);
 416         }
 417
 418         /* write CMDS */
 419         if (ch->jumponly)
 420                 cx_write(ch->cmds_start + 0, 8);
 421         else
 422                 cx_write(ch->cmds_start + 0, risc);
 423         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 424         cx_write(ch->cmds_start +  8, cdt);
 425         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 426         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 427         if (ch->jumponly)
 428                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 429         else
 430                 cx_write(ch->cmds_start + 20, 64 >> 2);
 431         for (i = 24; i < 80; i += 4)
 432                 cx_write(ch->cmds_start + i, 0);
 433
 434         /* fill registers */
 435         cx_write(ch->ptr1_reg, ch->fifo_start);
 436         cx_write(ch->ptr2_reg, cdt);
 437         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 438         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 439
 440         dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 441                 dev->bridge,
 442                 ch->name,
 443                 bpl,
 444                 lines);
 445
 446         return 0;
 447 }
 448
 449 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 450                                       struct sram_channel *ch)
 451 {
 452         static char *name[] = {
 453                 "init risc lo",
 454                 "init risc hi",
 455                 "cdt base",
 456                 "cdt size",
 457                 "iq base",
 458                 "iq size",
 459                 "risc pc lo",
 460                 "risc pc hi",
 461                 "iq wr ptr",
 462                 "iq rd ptr",
 463                 "cdt current",
 464                 "pci target lo",
 465                 "pci target hi",
 466                 "line / byte",
 467         };
 468         u32 risc;
 469         unsigned int i, j, n;
 470
 471         printk(KERN_WARNING "%s: %s - dma channel status dump\n",
 472                dev->name, ch->name);
 473         for (i = 0; i < ARRAY_SIZE(name); i++)
 474                 printk(KERN_WARNING "%s:   cmds: %-15s: 0x%08x\n",
 475                        dev->name, name[i],
 476                        cx_read(ch->cmds_start + 4*i));
 477
 478         for (i = 0; i < 4; i++) {
 479                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 480                 printk(KERN_WARNING "%s:   risc%d: ", dev->name, i);
 481                 cx23885_risc_decode(risc);
 482         }
 483         for (i = 0; i < (64 >> 2); i += n) {
 484                 risc = cx_read(ch->ctrl_start + 4 * i);
 485                 /* No consideration for bits 63-32 */
 486
 487                 printk(KERN_WARNING "%s:   (0x%08x) iq %x: ", dev->name,
 488                        ch->ctrl_start + 4 * i, i);
 489                 n = cx23885_risc_decode(risc);
 490                 for (j = 1; j < n; j++) {
 491                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 492                         printk(KERN_WARNING "%s:   iq %x: 0x%08x [ arg #%d ]\n",
 493                                dev->name, i+j, risc, j);
 494                 }
 495         }
 496
 497         printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
 498                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 499         printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
 500                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 501         printk(KERN_WARNING "%s:   ptr1_reg: 0x%08x\n",
 502                dev->name, cx_read(ch->ptr1_reg));
 503         printk(KERN_WARNING "%s:   ptr2_reg: 0x%08x\n",
 504                dev->name, cx_read(ch->ptr2_reg));
 505         printk(KERN_WARNING "%s:   cnt1_reg: 0x%08x\n",
 506                dev->name, cx_read(ch->cnt1_reg));
 507         printk(KERN_WARNING "%s:   cnt2_reg: 0x%08x\n",
 508                dev->name, cx_read(ch->cnt2_reg));
 509 }
 510
 511 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 512                                 struct btcx_riscmem *risc)
 513 {
 514         struct cx23885_dev *dev = port->dev;
 515         unsigned int i, j, n;
 516
 517         printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
 518                dev->name, risc->cpu, (unsigned long)risc->dma);
 519         for (i = 0; i < (risc->size >> 2); i += n) {
 520                 printk(KERN_INFO "%s:   %04d: ", dev->name, i);
 521                 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
 522                 for (j = 1; j < n; j++)
 523                         printk(KERN_INFO "%s:   %04d: 0x%08x [ arg #%d ]\n",
 524                                dev->name, i + j, risc->cpu[i + j], j);
 525                 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
 526                         break;
 527         }
 528 }
 529
 530 static void cx23885_shutdown(struct cx23885_dev *dev)
 531 {
 532         /* disable RISC controller */
 533         cx_write(DEV_CNTRL2, 0);
 534
 535         /* Disable all IR activity */
 536         cx_write(IR_CNTRL_REG, 0);
 537
 538         /* Disable Video A/B activity */
 539         cx_write(VID_A_DMA_CTL, 0);
 540         cx_write(VID_B_DMA_CTL, 0);
 541         cx_write(VID_C_DMA_CTL, 0);
 542
 543         /* Disable Audio activity */
 544         cx_write(AUD_INT_DMA_CTL, 0);
 545         cx_write(AUD_EXT_DMA_CTL, 0);
 546
 547         /* Disable Serial port */
 548         cx_write(UART_CTL, 0);
 549
 550         /* Disable Interrupts */
 551         cx_write(PCI_INT_MSK, 0);
 552         cx_write(VID_A_INT_MSK, 0);
 553         cx_write(VID_B_INT_MSK, 0);
 554         cx_write(VID_C_INT_MSK, 0);
 555         cx_write(AUDIO_INT_INT_MSK, 0);
 556         cx_write(AUDIO_EXT_INT_MSK, 0);
 557
 558 }
 559
 560 static void cx23885_reset(struct cx23885_dev *dev)
 561 {
 562         dprintk(1, "%s()\n", __func__);
 563
 564         cx23885_shutdown(dev);
 565
 566         cx_write(PCI_INT_STAT, 0xffffffff);
 567         cx_write(VID_A_INT_STAT, 0xffffffff);
 568         cx_write(VID_B_INT_STAT, 0xffffffff);
 569         cx_write(VID_C_INT_STAT, 0xffffffff);
 570         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 571         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 572         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 573         cx_write(PAD_CTRL, 0x00500300);
 574
 575         mdelay(100);
 576
 577         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 578                 720*4, 0);
 579         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 580         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 581                 188*4, 0);
 582         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 583         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 584         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 585                 188*4, 0);
 586         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 587         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 588         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 589
 590         cx23885_gpio_setup(dev);
 591 }
 592
 593
 594 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 595 {
 596         dprintk(1, "%s()\n", __func__);
 597
 598         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 599          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 600          * occur on the cx23887 bridge.
 601          */
 602         if (dev->bridge == CX23885_BRIDGE_885)
 603                 cx_clear(RDR_TLCTL0, 1 << 4);
 604
 605         return 0;
 606 }
 607
 608 static int get_resources(struct cx23885_dev *dev)
 609 {
 610         if (request_mem_region(pci_resource_start(dev->pci, 0),
 611                                pci_resource_len(dev->pci, 0),
 612                                dev->name))
 613                 return 0;
 614
 615         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 616                 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
 617
 618         return -EBUSY;
 619 }
 620
 621 static void cx23885_timeout(unsigned long data);
 622 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 623                                 u32 reg, u32 mask, u32 value);
 624
 625 static int cx23885_init_tsport(struct cx23885_dev *dev,
 626         struct cx23885_tsport *port, int portno)
 627 {
 628         dprintk(1, "%s(portno=%d)\n", __func__, portno);
 629
 630         /* Transport bus init dma queue  - Common settings */
 631         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 632         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 633         port->vld_misc_val       = 0x0;
 634         port->hw_sop_ctrl_val    = (0x47 << 16 | 188 << 4);
 635
 636         spin_lock_init(&port->slock);
 637         port->dev = dev;
 638         port->nr = portno;
 639
 640         INIT_LIST_HEAD(&port->mpegq.active);
 641         INIT_LIST_HEAD(&port->mpegq.queued);
 642         port->mpegq.timeout.function = cx23885_timeout;
 643         port->mpegq.timeout.data = (unsigned long)port;
 644         init_timer(&port->mpegq.timeout);
 645
 646         mutex_init(&port->frontends.lock);
 647         INIT_LIST_HEAD(&port->frontends.felist);
 648         port->frontends.active_fe_id = 0;
 649
 650         /* This should be hardcoded allow a single frontend
 651          * attachment to this tsport, keeping the -dvb.c
 652          * code clean and safe.
 653          */
 654         if (!port->num_frontends)
 655                 port->num_frontends = 1;
 656
 657         switch (portno) {
 658         case 1:
 659                 port->reg_gpcnt          = VID_B_GPCNT;
 660                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 661                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 662                 port->reg_lngth          = VID_B_LNGTH;
 663                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 664                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 665                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 666                 port->reg_sop_status     = VID_B_SOP_STATUS;
 667                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 668                 port->reg_vld_misc       = VID_B_VLD_MISC;
 669                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 670                 port->reg_src_sel        = VID_B_SRC_SEL;
 671                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 672                 port->reg_ts_int_stat    = VID_B_INT_STAT;
 673                 port->sram_chno          = SRAM_CH03; /* VID_B */
 674                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 675                 break;
 676         case 2:
 677                 port->reg_gpcnt          = VID_C_GPCNT;
 678                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 679                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 680                 port->reg_lngth          = VID_C_LNGTH;
 681                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 682                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 683                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 684                 port->reg_sop_status     = VID_C_SOP_STATUS;
 685                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 686                 port->reg_vld_misc       = VID_C_VLD_MISC;
 687                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 688                 port->reg_src_sel        = 0;
 689                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 690                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 691                 port->sram_chno          = SRAM_CH06; /* VID_C */
 692                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 693                 break;
 694         default:
 695                 BUG();
 696         }
 697
 698         cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
 699                      port->reg_dma_ctl, port->dma_ctl_val, 0x00);
 700
 701         return 0;
 702 }
 703
 704 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 705 {
 706         switch (cx_read(RDR_CFG2) & 0xff) {
 707         case 0x00:
 708                 /* cx23885 */
 709                 dev->hwrevision = 0xa0;
 710                 break;
 711         case 0x01:
 712                 /* CX23885-12Z */
 713                 dev->hwrevision = 0xa1;
 714                 break;
 715         case 0x02:
 716                 /* CX23885-13Z/14Z */
 717                 dev->hwrevision = 0xb0;
 718                 break;
 719         case 0x03:
 720                 if (dev->pci->device == 0x8880) {
 721                         /* CX23888-21Z/22Z */
 722                         dev->hwrevision = 0xc0;
 723                 } else {
 724                         /* CX23885-14Z */
 725                         dev->hwrevision = 0xa4;
 726                 }
 727                 break;
 728         case 0x04:
 729                 if (dev->pci->device == 0x8880) {
 730                         /* CX23888-31Z */
 731                         dev->hwrevision = 0xd0;
 732                 } else {
 733                         /* CX23885-15Z, CX23888-31Z */
 734                         dev->hwrevision = 0xa5;
 735                 }
 736                 break;
 737         case 0x0e:
 738                 /* CX23887-15Z */
 739                 dev->hwrevision = 0xc0;
 740         case 0x0f:
 741                 /* CX23887-14Z */
 742                 dev->hwrevision = 0xb1;
 743                 break;
 744         default:
 745                 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
 746                         __func__, dev->hwrevision);
 747         }
 748         if (dev->hwrevision)
 749                 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
 750                         __func__, dev->hwrevision);
 751         else
 752                 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
 753                         __func__, dev->hwrevision);
 754 }
 755
 756 /* Find the first v4l2_subdev member of the group id in hw */
 757 struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw)
 758 {
 759         struct v4l2_subdev *result = NULL;
 760         struct v4l2_subdev *sd;
 761
 762         spin_lock(&dev->v4l2_dev.lock);
 763         v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) {
 764                 if (sd->grp_id == hw) {
 765                         result = sd;
 766                         break;
 767                 }
 768         }
 769         spin_unlock(&dev->v4l2_dev.lock);
 770         return result;
 771 }
 772
 773 static int cx23885_dev_setup(struct cx23885_dev *dev)
 774 {
 775         int i;
 776
 777         mutex_init(&dev->lock);
 778         mutex_init(&dev->gpio_lock);
 779
 780         atomic_inc(&dev->refcount);
 781
 782         dev->nr = cx23885_devcount++;
 783         sprintf(dev->name, "cx23885[%d]", dev->nr);
 784
 785         /* Configure the internal memory */
 786         if (dev->pci->device == 0x8880) {
 787                 /* Could be 887 or 888, assume a default */
 788                 dev->bridge = CX23885_BRIDGE_887;
 789                 /* Apply a sensible clock frequency for the PCIe bridge */
 790                 dev->clk_freq = 25000000;
 791                 dev->sram_channels = cx23887_sram_channels;
 792         } else
 793         if (dev->pci->device == 0x8852) {
 794                 dev->bridge = CX23885_BRIDGE_885;
 795                 /* Apply a sensible clock frequency for the PCIe bridge */
 796                 dev->clk_freq = 28000000;
 797                 dev->sram_channels = cx23885_sram_channels;
 798         } else
 799                 BUG();
 800
 801         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 802                 __func__, dev->bridge);
 803
 804         /* board config */
 805         dev->board = UNSET;
 806         if (card[dev->nr] < cx23885_bcount)
 807                 dev->board = card[dev->nr];
 808         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 809                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 810                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 811                         dev->board = cx23885_subids[i].card;
 812         if (UNSET == dev->board) {
 813                 dev->board = CX23885_BOARD_UNKNOWN;
 814                 cx23885_card_list(dev);
 815         }
 816
 817         /* If the user specific a clk freq override, apply it */
 818         if (cx23885_boards[dev->board].clk_freq > 0)
 819                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 820
 821         dev->pci_bus  = dev->pci->bus->number;
 822         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 823         dev->pci_irqmask = 0x001f00;
 824         if (cx23885_boards[dev->board].cimax > 0)
 825                 dev->pci_irqmask |= 0x01800000; /* for CiMaxes */
 826
 827         /* External Master 1 Bus */
 828         dev->i2c_bus[0].nr = 0;
 829         dev->i2c_bus[0].dev = dev;
 830         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 831         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 832         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 833         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 834         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 835         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 836
 837         /* External Master 2 Bus */
 838         dev->i2c_bus[1].nr = 1;
 839         dev->i2c_bus[1].dev = dev;
 840         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 841         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 842         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 843         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 844         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 845         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 846
 847         /* Internal Master 3 Bus */
 848         dev->i2c_bus[2].nr = 2;
 849         dev->i2c_bus[2].dev = dev;
 850         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 851         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 852         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 853         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 854         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 855         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 856
 857         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
 858                 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
 859                 cx23885_init_tsport(dev, &dev->ts1, 1);
 860
 861         if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
 862                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 863                 cx23885_init_tsport(dev, &dev->ts2, 2);
 864
 865         if (get_resources(dev) < 0) {
 866                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 867                        "subsystem: %04x:%04x\n",
 868                        dev->name, dev->pci->subsystem_vendor,
 869                        dev->pci->subsystem_device);
 870
 871                 cx23885_devcount--;
 872                 return -ENODEV;
 873         }
 874
 875         /* PCIe stuff */
 876         dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
 877                              pci_resource_len(dev->pci, 0));
 878
 879         dev->bmmio = (u8 __iomem *)dev->lmmio;
 880
 881         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 882                dev->name, dev->pci->subsystem_vendor,
 883                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 884                dev->board, card[dev->nr] == dev->board ?
 885                "insmod option" : "autodetected");
 886
 887         cx23885_pci_quirks(dev);
 888
 889         /* Assume some sensible defaults */
 890         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 891         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 892         dev->radio_type = cx23885_boards[dev->board].radio_type;
 893         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 894
 895         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
 896                 __func__, dev->tuner_type, dev->tuner_addr);
 897         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 898                 __func__, dev->radio_type, dev->radio_addr);
 899
 900         /* The cx23417 encoder has GPIO's that need to be initialised
 901          * before DVB, so that demodulators and tuners are out of
 902          * reset before DVB uses them.
 903          */
 904         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
 905                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 906                         cx23885_mc417_init(dev);
 907
 908         /* init hardware */
 909         cx23885_reset(dev);
 910
 911         cx23885_i2c_register(&dev->i2c_bus[0]);
 912         cx23885_i2c_register(&dev->i2c_bus[1]);
 913         cx23885_i2c_register(&dev->i2c_bus[2]);
 914         cx23885_card_setup(dev);
 915         call_all(dev, core, s_power, 0);
 916         cx23885_ir_init(dev);
 917
 918         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
 919                 if (cx23885_video_register(dev) < 0) {
 920                         printk(KERN_ERR "%s() Failed to register analog "
 921                                 "video adapters on VID_A\n", __func__);
 922                 }
 923         }
 924
 925         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
 926                 if (cx23885_dvb_register(&dev->ts1) < 0) {
 927                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
 928                                __func__);
 929                 }
 930         } else
 931         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
 932                 if (cx23885_417_register(dev) < 0) {
 933                         printk(KERN_ERR
 934                                 "%s() Failed to register 417 on VID_B\n",
 935                                __func__);
 936                 }
 937         }
 938
 939         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
 940                 if (cx23885_dvb_register(&dev->ts2) < 0) {
 941                         printk(KERN_ERR
 942                                 "%s() Failed to register dvb on VID_C\n",
 943                                __func__);
 944                 }
 945         } else
 946         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
 947                 if (cx23885_417_register(dev) < 0) {
 948                         printk(KERN_ERR
 949                                 "%s() Failed to register 417 on VID_C\n",
 950                                __func__);
 951                 }
 952         }
 953
 954         cx23885_dev_checkrevision(dev);
 955
 956         return 0;
 957 }
 958
 959 static void cx23885_dev_unregister(struct cx23885_dev *dev)
 960 {
 961         release_mem_region(pci_resource_start(dev->pci, 0),
 962                            pci_resource_len(dev->pci, 0));
 963
 964         if (!atomic_dec_and_test(&dev->refcount))
 965                 return;
 966
 967         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
 968                 cx23885_video_unregister(dev);
 969
 970         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 971                 cx23885_dvb_unregister(&dev->ts1);
 972
 973         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
 974                 cx23885_417_unregister(dev);
 975
 976         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 977                 cx23885_dvb_unregister(&dev->ts2);
 978
 979         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
 980                 cx23885_417_unregister(dev);
 981
 982         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 983         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 984         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 985
 986         iounmap(dev->lmmio);
 987 }
 988
 989 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
 990                                unsigned int offset, u32 sync_line,
 991                                unsigned int bpl, unsigned int padding,
 992                                unsigned int lines)
 993 {
 994         struct scatterlist *sg;
 995         unsigned int line, todo;
 996
 997         /* sync instruction */
 998         if (sync_line != NO_SYNC_LINE)
 999                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1000
1001         /* scan lines */
1002         sg = sglist;
1003         for (line = 0; line < lines; line++) {
1004                 while (offset && offset >= sg_dma_len(sg)) {
1005                         offset -= sg_dma_len(sg);
1006                         sg++;
1007                 }
1008                 if (bpl <= sg_dma_len(sg)-offset) {
1009                         /* fits into current chunk */
1010                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
1011                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1012                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1013                         offset += bpl;
1014                 } else {
1015                         /* scanline needs to be split */
1016                         todo = bpl;
1017                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
1018                                             (sg_dma_len(sg)-offset));
1019                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1020                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1021                         todo -= (sg_dma_len(sg)-offset);
1022                         offset = 0;
1023                         sg++;
1024                         while (todo > sg_dma_len(sg)) {
1025                                 *(rp++) = cpu_to_le32(RISC_WRITE|
1026                                                     sg_dma_len(sg));
1027                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1028                                 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1029                                 todo -= sg_dma_len(sg);
1030                                 sg++;
1031                         }
1032                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1033                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1034                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1035                         offset += todo;
1036                 }
1037                 offset += padding;
1038         }
1039
1040         return rp;
1041 }
1042
1043 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1044                         struct scatterlist *sglist, unsigned int top_offset,
1045                         unsigned int bottom_offset, unsigned int bpl,
1046                         unsigned int padding, unsigned int lines)
1047 {
1048         u32 instructions, fields;
1049         __le32 *rp;
1050         int rc;
1051
1052         fields = 0;
1053         if (UNSET != top_offset)
1054                 fields++;
1055         if (UNSET != bottom_offset)
1056                 fields++;
1057
1058         /* estimate risc mem: worst case is one write per page border +
1059            one write per scan line + syncs + jump (all 2 dwords).  Padding
1060            can cause next bpl to start close to a page border.  First DMA
1061            region may be smaller than PAGE_SIZE */
1062         /* write and jump need and extra dword */
1063         instructions  = fields * (1 + ((bpl + padding) * lines)
1064                 / PAGE_SIZE + lines);
1065         instructions += 2;
1066         rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1067         if (rc < 0)
1068                 return rc;
1069
1070         /* write risc instructions */
1071         rp = risc->cpu;
1072         if (UNSET != top_offset)
1073                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1074                                         bpl, padding, lines);
1075         if (UNSET != bottom_offset)
1076                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1077                                         bpl, padding, lines);
1078
1079         /* save pointer to jmp instruction address */
1080         risc->jmp = rp;
1081         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1082         return 0;
1083 }
1084
1085 static int cx23885_risc_databuffer(struct pci_dev *pci,
1086                                    struct btcx_riscmem *risc,
1087                                    struct scatterlist *sglist,
1088                                    unsigned int bpl,
1089                                    unsigned int lines)
1090 {
1091         u32 instructions;
1092         __le32 *rp;
1093         int rc;
1094
1095         /* estimate risc mem: worst case is one write per page border +
1096            one write per scan line + syncs + jump (all 2 dwords).  Here
1097            there is no padding and no sync.  First DMA region may be smaller
1098            than PAGE_SIZE */
1099         /* Jump and write need an extra dword */
1100         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
1101         instructions += 1;
1102
1103         rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1104         if (rc < 0)
1105                 return rc;
1106
1107         /* write risc instructions */
1108         rp = risc->cpu;
1109         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1110
1111         /* save pointer to jmp instruction address */
1112         risc->jmp = rp;
1113         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1114         return 0;
1115 }
1116
1117 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1118                                 u32 reg, u32 mask, u32 value)
1119 {
1120         __le32 *rp;
1121         int rc;
1122
1123         rc = btcx_riscmem_alloc(pci, risc, 4*16);
1124         if (rc < 0)
1125                 return rc;
1126
1127         /* write risc instructions */
1128         rp = risc->cpu;
1129         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
1130         *(rp++) = cpu_to_le32(reg);
1131         *(rp++) = cpu_to_le32(value);
1132         *(rp++) = cpu_to_le32(mask);
1133         *(rp++) = cpu_to_le32(RISC_JUMP);
1134         *(rp++) = cpu_to_le32(risc->dma);
1135         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1136         return 0;
1137 }
1138
1139 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1140 {
1141         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1142
1143         BUG_ON(in_interrupt());
1144         videobuf_waiton(&buf->vb, 0, 0);
1145         videobuf_dma_unmap(q->dev, dma);
1146         videobuf_dma_free(dma);
1147         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1148         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1149 }
1150
1151 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1152 {
1153         struct cx23885_dev *dev = port->dev;
1154
1155         dprintk(1, "%s() Register Dump\n", __func__);
1156         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __func__,
1157                 cx_read(DEV_CNTRL2));
1158         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __func__,
1159                 cx_read(PCI_INT_MSK));
1160         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __func__,
1161                 cx_read(AUDIO_INT_INT_MSK));
1162         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __func__,
1163                 cx_read(AUD_INT_DMA_CTL));
1164         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __func__,
1165                 cx_read(AUDIO_EXT_INT_MSK));
1166         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __func__,
1167                 cx_read(AUD_EXT_DMA_CTL));
1168         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __func__,
1169                 cx_read(PAD_CTRL));
1170         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __func__,
1171                 cx_read(ALT_PIN_OUT_SEL));
1172         dprintk(1, "%s() GPIO2                    0x%08X\n", __func__,
1173                 cx_read(GPIO2));
1174         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __func__,
1175                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1176         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __func__,
1177                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1178         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __func__,
1179                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1180         if (port->reg_src_sel)
1181                 dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __func__,
1182                         port->reg_src_sel, cx_read(port->reg_src_sel));
1183         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __func__,
1184                 port->reg_lngth, cx_read(port->reg_lngth));
1185         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __func__,
1186                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1187         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __func__,
1188                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1189         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __func__,
1190                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1191         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __func__,
1192                 port->reg_sop_status, cx_read(port->reg_sop_status));
1193         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1194                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1195         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __func__,
1196                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1197         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __func__,
1198                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1199         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __func__,
1200                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1201 }
1202
1203 static int cx23885_start_dma(struct cx23885_tsport *port,
1204                              struct cx23885_dmaqueue *q,
1205                              struct cx23885_buffer   *buf)
1206 {
1207         struct cx23885_dev *dev = port->dev;
1208         u32 reg;
1209
1210         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1211                 buf->vb.width, buf->vb.height, buf->vb.field);
1212
1213         /* Stop the fifo and risc engine for this port */
1214         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1215
1216         /* setup fifo + format */
1217         cx23885_sram_channel_setup(dev,
1218                                    &dev->sram_channels[port->sram_chno],
1219                                    port->ts_packet_size, buf->risc.dma);
1220         if (debug > 5) {
1221                 cx23885_sram_channel_dump(dev,
1222                         &dev->sram_channels[port->sram_chno]);
1223                 cx23885_risc_disasm(port, &buf->risc);
1224         }
1225
1226         /* write TS length to chip */
1227         cx_write(port->reg_lngth, buf->vb.width);
1228
1229         if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1230                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1231                 printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1232                         __func__,
1233                         cx23885_boards[dev->board].portb,
1234                         cx23885_boards[dev->board].portc);
1235                 return -EINVAL;
1236         }
1237
1238         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1239                 cx23885_av_clk(dev, 0);
1240
1241         udelay(100);
1242
1243         /* If the port supports SRC SELECT, configure it */
1244         if (port->reg_src_sel)
1245                 cx_write(port->reg_src_sel, port->src_sel_val);
1246
1247         cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1248         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1249         cx_write(port->reg_vld_misc, port->vld_misc_val);
1250         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1251         udelay(100);
1252
1253         /* NOTE: this is 2 (reserved) for portb, does it matter? */
1254         /* reset counter to zero */
1255         cx_write(port->reg_gpcnt_ctl, 3);
1256         q->count = 1;
1257
1258         /* Set VIDB pins to input */
1259         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1260                 reg = cx_read(PAD_CTRL);
1261                 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1262                 cx_write(PAD_CTRL, reg);
1263         }
1264
1265         /* Set VIDC pins to input */
1266         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1267                 reg = cx_read(PAD_CTRL);
1268                 reg &= ~0x4; /* Clear TS2_SOP_OE */
1269                 cx_write(PAD_CTRL, reg);
1270         }
1271
1272         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1273
1274                 reg = cx_read(PAD_CTRL);
1275                 reg = reg & ~0x1;    /* Clear TS1_OE */
1276
1277                 /* FIXME, bit 2 writing here is questionable */
1278                 /* set TS1_SOP_OE and TS1_OE_HI */
1279                 reg = reg | 0xa;
1280                 cx_write(PAD_CTRL, reg);
1281
1282                 /* FIXME and these two registers should be documented. */
1283                 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1284                 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1285         }
1286
1287         switch (dev->bridge) {
1288         case CX23885_BRIDGE_885:
1289         case CX23885_BRIDGE_887:
1290         case CX23885_BRIDGE_888:
1291                 /* enable irqs */
1292                 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1293                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1294                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1295                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1296                 break;
1297         default:
1298                 BUG();
1299         }
1300
1301         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1302
1303         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1304                 cx23885_av_clk(dev, 1);
1305
1306         if (debug > 4)
1307                 cx23885_tsport_reg_dump(port);
1308
1309         return 0;
1310 }
1311
1312 static int cx23885_stop_dma(struct cx23885_tsport *port)
1313 {
1314         struct cx23885_dev *dev = port->dev;
1315         u32 reg;
1316
1317         dprintk(1, "%s()\n", __func__);
1318
1319         /* Stop interrupts and DMA */
1320         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1321         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1322
1323         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1324
1325                 reg = cx_read(PAD_CTRL);
1326
1327                 /* Set TS1_OE */
1328                 reg = reg | 0x1;
1329
1330                 /* clear TS1_SOP_OE and TS1_OE_HI */
1331                 reg = reg & ~0xa;
1332                 cx_write(PAD_CTRL, reg);
1333                 cx_write(port->reg_src_sel, 0);
1334                 cx_write(port->reg_gen_ctrl, 8);
1335
1336         }
1337
1338         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1339                 cx23885_av_clk(dev, 0);
1340
1341         return 0;
1342 }
1343
1344 int cx23885_restart_queue(struct cx23885_tsport *port,
1345                                 struct cx23885_dmaqueue *q)
1346 {
1347         struct cx23885_dev *dev = port->dev;
1348         struct cx23885_buffer *buf;
1349
1350         dprintk(5, "%s()\n", __func__);
1351         if (list_empty(&q->active)) {
1352                 struct cx23885_buffer *prev;
1353                 prev = NULL;
1354
1355                 dprintk(5, "%s() queue is empty\n", __func__);
1356
1357                 for (;;) {
1358                         if (list_empty(&q->queued))
1359                                 return 0;
1360                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1361                                          vb.queue);
1362                         if (NULL == prev) {
1363                                 list_del(&buf->vb.queue);
1364                                 list_add_tail(&buf->vb.queue, &q->active);
1365                                 cx23885_start_dma(port, q, buf);
1366                                 buf->vb.state = VIDEOBUF_ACTIVE;
1367                                 buf->count    = q->count++;
1368                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1369                                 dprintk(5, "[%p/%d] restart_queue - f/active\n",
1370                                         buf, buf->vb.i);
1371
1372                         } else if (prev->vb.width  == buf->vb.width  &&
1373                                    prev->vb.height == buf->vb.height &&
1374                                    prev->fmt       == buf->fmt) {
1375                                 list_del(&buf->vb.queue);
1376                                 list_add_tail(&buf->vb.queue, &q->active);
1377                                 buf->vb.state = VIDEOBUF_ACTIVE;
1378                                 buf->count    = q->count++;
1379                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1380                                 /* 64 bit bits 63-32 */
1381                                 prev->risc.jmp[2] = cpu_to_le32(0);
1382                                 dprintk(5, "[%p/%d] restart_queue - m/active\n",
1383                                         buf, buf->vb.i);
1384                         } else {
1385                                 return 0;
1386                         }
1387                         prev = buf;
1388                 }
1389                 return 0;
1390         }
1391
1392         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1393         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1394                 buf, buf->vb.i);
1395         cx23885_start_dma(port, q, buf);
1396         list_for_each_entry(buf, &q->active, vb.queue)
1397                 buf->count = q->count++;
1398         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1399         return 0;
1400 }
1401
1402 /* ------------------------------------------------------------------ */
1403
1404 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1405                         struct cx23885_buffer *buf, enum v4l2_field field)
1406 {
1407         struct cx23885_dev *dev = port->dev;
1408         int size = port->ts_packet_size * port->ts_packet_count;
1409         int rc;
1410
1411         dprintk(1, "%s: %p\n", __func__, buf);
1412         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1413                 return -EINVAL;
1414
1415         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1416                 buf->vb.width  = port->ts_packet_size;
1417                 buf->vb.height = port->ts_packet_count;
1418                 buf->vb.size   = size;
1419                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1420
1421                 rc = videobuf_iolock(q, &buf->vb, NULL);
1422                 if (0 != rc)
1423                         goto fail;
1424                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1425                                         videobuf_to_dma(&buf->vb)->sglist,
1426                                         buf->vb.width, buf->vb.height);
1427         }
1428         buf->vb.state = VIDEOBUF_PREPARED;
1429         return 0;
1430
1431  fail:
1432         cx23885_free_buffer(q, buf);
1433         return rc;
1434 }
1435
1436 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1437 {
1438         struct cx23885_buffer    *prev;
1439         struct cx23885_dev *dev = port->dev;
1440         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1441
1442         /* add jump to stopper */
1443         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1444         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1445         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1446
1447         if (list_empty(&cx88q->active)) {
1448                 dprintk(1, "queue is empty - first active\n");
1449                 list_add_tail(&buf->vb.queue, &cx88q->active);
1450                 cx23885_start_dma(port, cx88q, buf);
1451                 buf->vb.state = VIDEOBUF_ACTIVE;
1452                 buf->count    = cx88q->count++;
1453                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1454                 dprintk(1, "[%p/%d] %s - first active\n",
1455                         buf, buf->vb.i, __func__);
1456         } else {
1457                 dprintk(1, "queue is not empty - append to active\n");
1458                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1459                                   vb.queue);
1460                 list_add_tail(&buf->vb.queue, &cx88q->active);
1461                 buf->vb.state = VIDEOBUF_ACTIVE;
1462                 buf->count    = cx88q->count++;
1463                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1464                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1465                 dprintk(1, "[%p/%d] %s - append to active\n",
1466                          buf, buf->vb.i, __func__);
1467         }
1468 }
1469
1470 /* ----------------------------------------------------------- */
1471
1472 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1473                               int restart)
1474 {
1475         struct cx23885_dev *dev = port->dev;
1476         struct cx23885_dmaqueue *q = &port->mpegq;
1477         struct cx23885_buffer *buf;
1478         unsigned long flags;
1479
1480         spin_lock_irqsave(&port->slock, flags);
1481         while (!list_empty(&q->active)) {
1482                 buf = list_entry(q->active.next, struct cx23885_buffer,
1483                                  vb.queue);
1484                 list_del(&buf->vb.queue);
1485                 buf->vb.state = VIDEOBUF_ERROR;
1486                 wake_up(&buf->vb.done);
1487                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1488                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1489         }
1490         if (restart) {
1491                 dprintk(1, "restarting queue\n");
1492                 cx23885_restart_queue(port, q);
1493         }
1494         spin_unlock_irqrestore(&port->slock, flags);
1495 }
1496
1497 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1498 {
1499         struct cx23885_dev *dev = port->dev;
1500         struct cx23885_dmaqueue *q = &port->mpegq;
1501
1502         dprintk(1, "%s()\n", __func__);
1503         del_timer_sync(&q->timeout);
1504         cx23885_stop_dma(port);
1505         do_cancel_buffers(port, "cancel", 0);
1506 }
1507
1508 static void cx23885_timeout(unsigned long data)
1509 {
1510         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1511         struct cx23885_dev *dev = port->dev;
1512
1513         dprintk(1, "%s()\n", __func__);
1514
1515         if (debug > 5)
1516                 cx23885_sram_channel_dump(dev,
1517                         &dev->sram_channels[port->sram_chno]);
1518
1519         cx23885_stop_dma(port);
1520         do_cancel_buffers(port, "timeout", 1);
1521 }
1522
1523 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1524 {
1525         /* FIXME: port1 assumption here. */
1526         struct cx23885_tsport *port = &dev->ts1;
1527         int count = 0;
1528         int handled = 0;
1529
1530         if (status == 0)
1531                 return handled;
1532
1533         count = cx_read(port->reg_gpcnt);
1534         dprintk(7, "status: 0x%08x  mask: 0x%08x count: 0x%x\n",
1535                 status, cx_read(port->reg_ts_int_msk), count);
1536
1537         if ((status & VID_B_MSK_BAD_PKT)         ||
1538                 (status & VID_B_MSK_OPC_ERR)     ||
1539                 (status & VID_B_MSK_VBI_OPC_ERR) ||
1540                 (status & VID_B_MSK_SYNC)        ||
1541                 (status & VID_B_MSK_VBI_SYNC)    ||
1542                 (status & VID_B_MSK_OF)          ||
1543                 (status & VID_B_MSK_VBI_OF)) {
1544                 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1545                         "= 0x%x\n", dev->name, status);
1546                 if (status & VID_B_MSK_BAD_PKT)
1547                         dprintk(1, "        VID_B_MSK_BAD_PKT\n");
1548                 if (status & VID_B_MSK_OPC_ERR)
1549                         dprintk(1, "        VID_B_MSK_OPC_ERR\n");
1550                 if (status & VID_B_MSK_VBI_OPC_ERR)
1551                         dprintk(1, "        VID_B_MSK_VBI_OPC_ERR\n");
1552                 if (status & VID_B_MSK_SYNC)
1553                         dprintk(1, "        VID_B_MSK_SYNC\n");
1554                 if (status & VID_B_MSK_VBI_SYNC)
1555                         dprintk(1, "        VID_B_MSK_VBI_SYNC\n");
1556                 if (status & VID_B_MSK_OF)
1557                         dprintk(1, "        VID_B_MSK_OF\n");
1558                 if (status & VID_B_MSK_VBI_OF)
1559                         dprintk(1, "        VID_B_MSK_VBI_OF\n");
1560
1561                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1562                 cx23885_sram_channel_dump(dev,
1563                         &dev->sram_channels[port->sram_chno]);
1564                 cx23885_417_check_encoder(dev);
1565         } else if (status & VID_B_MSK_RISCI1) {
1566                 dprintk(7, "        VID_B_MSK_RISCI1\n");
1567                 spin_lock(&port->slock);
1568                 cx23885_wakeup(port, &port->mpegq, count);
1569                 spin_unlock(&port->slock);
1570         } else if (status & VID_B_MSK_RISCI2) {
1571                 dprintk(7, "        VID_B_MSK_RISCI2\n");
1572                 spin_lock(&port->slock);
1573                 cx23885_restart_queue(port, &port->mpegq);
1574                 spin_unlock(&port->slock);
1575         }
1576         if (status) {
1577                 cx_write(port->reg_ts_int_stat, status);
1578                 handled = 1;
1579         }
1580
1581         return handled;
1582 }
1583
1584 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1585 {
1586         struct cx23885_dev *dev = port->dev;
1587         int handled = 0;
1588         u32 count;
1589
1590         if ((status & VID_BC_MSK_OPC_ERR) ||
1591                 (status & VID_BC_MSK_BAD_PKT) ||
1592                 (status & VID_BC_MSK_SYNC) ||
1593                 (status & VID_BC_MSK_OF)) {
1594
1595                 if (status & VID_BC_MSK_OPC_ERR)
1596                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1597                                 VID_BC_MSK_OPC_ERR);
1598
1599                 if (status & VID_BC_MSK_BAD_PKT)
1600                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1601                                 VID_BC_MSK_BAD_PKT);
1602
1603                 if (status & VID_BC_MSK_SYNC)
1604                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n",
1605                                 VID_BC_MSK_SYNC);
1606
1607                 if (status & VID_BC_MSK_OF)
1608                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n",
1609                                 VID_BC_MSK_OF);
1610
1611                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1612
1613                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1614                 cx23885_sram_channel_dump(dev,
1615                         &dev->sram_channels[port->sram_chno]);
1616
1617         } else if (status & VID_BC_MSK_RISCI1) {
1618
1619                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1620
1621                 spin_lock(&port->slock);
1622                 count = cx_read(port->reg_gpcnt);
1623                 cx23885_wakeup(port, &port->mpegq, count);
1624                 spin_unlock(&port->slock);
1625
1626         } else if (status & VID_BC_MSK_RISCI2) {
1627
1628                 dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);
1629
1630                 spin_lock(&port->slock);
1631                 cx23885_restart_queue(port, &port->mpegq);
1632                 spin_unlock(&port->slock);
1633
1634         }
1635         if (status) {
1636                 cx_write(port->reg_ts_int_stat, status);
1637                 handled = 1;
1638         }
1639
1640         return handled;
1641 }
1642
1643 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1644 {
1645         struct cx23885_dev *dev = dev_id;
1646         struct cx23885_tsport *ts1 = &dev->ts1;
1647         struct cx23885_tsport *ts2 = &dev->ts2;
1648         u32 pci_status, pci_mask;
1649         u32 vida_status, vida_mask;
1650         u32 ts1_status, ts1_mask;
1651         u32 ts2_status, ts2_mask;
1652         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1653         bool ir_handled = false;
1654
1655         pci_status = cx_read(PCI_INT_STAT);
1656         pci_mask = cx_read(PCI_INT_MSK);
1657         vida_status = cx_read(VID_A_INT_STAT);
1658         vida_mask = cx_read(VID_A_INT_MSK);
1659         ts1_status = cx_read(VID_B_INT_STAT);
1660         ts1_mask = cx_read(VID_B_INT_MSK);
1661         ts2_status = cx_read(VID_C_INT_STAT);
1662         ts2_mask = cx_read(VID_C_INT_MSK);
1663
1664         if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1665                 goto out;
1666
1667         vida_count = cx_read(VID_A_GPCNT);
1668         ts1_count = cx_read(ts1->reg_gpcnt);
1669         ts2_count = cx_read(ts2->reg_gpcnt);
1670         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1671                 pci_status, pci_mask);
1672         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1673                 vida_status, vida_mask, vida_count);
1674         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1675                 ts1_status, ts1_mask, ts1_count);
1676         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1677                 ts2_status, ts2_mask, ts2_count);
1678
1679         if (pci_status & (PCI_MSK_RISC_RD | PCI_MSK_RISC_WR |
1680                           PCI_MSK_AL_RD   | PCI_MSK_AL_WR   | PCI_MSK_APB_DMA |
1681                           PCI_MSK_VID_C   | PCI_MSK_VID_B   | PCI_MSK_VID_A   |
1682                           PCI_MSK_AUD_INT | PCI_MSK_AUD_EXT |
1683                           PCI_MSK_GPIO0   | PCI_MSK_GPIO1   |
1684                           PCI_MSK_IR)) {
1685
1686                 if (pci_status & PCI_MSK_RISC_RD)
1687                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n",
1688                                 PCI_MSK_RISC_RD);
1689
1690                 if (pci_status & PCI_MSK_RISC_WR)
1691                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n",
1692                                 PCI_MSK_RISC_WR);
1693
1694                 if (pci_status & PCI_MSK_AL_RD)
1695                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n",
1696                                 PCI_MSK_AL_RD);
1697
1698                 if (pci_status & PCI_MSK_AL_WR)
1699                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n",
1700                                 PCI_MSK_AL_WR);
1701
1702                 if (pci_status & PCI_MSK_APB_DMA)
1703                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n",
1704                                 PCI_MSK_APB_DMA);
1705
1706                 if (pci_status & PCI_MSK_VID_C)
1707                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n",
1708                                 PCI_MSK_VID_C);
1709
1710                 if (pci_status & PCI_MSK_VID_B)
1711                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n",
1712                                 PCI_MSK_VID_B);
1713
1714                 if (pci_status & PCI_MSK_VID_A)
1715                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n",
1716                                 PCI_MSK_VID_A);
1717
1718                 if (pci_status & PCI_MSK_AUD_INT)
1719                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n",
1720                                 PCI_MSK_AUD_INT);
1721
1722                 if (pci_status & PCI_MSK_AUD_EXT)
1723                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n",
1724                                 PCI_MSK_AUD_EXT);
1725
1726                 if (pci_status & PCI_MSK_GPIO0)
1727                         dprintk(7, " (PCI_MSK_GPIO0     0x%08x)\n",
1728                                 PCI_MSK_GPIO0);
1729
1730                 if (pci_status & PCI_MSK_GPIO1)
1731                         dprintk(7, " (PCI_MSK_GPIO1     0x%08x)\n",
1732                                 PCI_MSK_GPIO1);
1733
1734                 if (pci_status & PCI_MSK_IR)
1735                         dprintk(7, " (PCI_MSK_IR        0x%08x)\n",
1736                                 PCI_MSK_IR);
1737         }
1738
1739         if (cx23885_boards[dev->board].cimax > 0 &&
1740                 ((pci_status & PCI_MSK_GPIO0) ||
1741                         (pci_status & PCI_MSK_GPIO1))) {
1742
1743                 if (cx23885_boards[dev->board].cimax > 0)
1744                         handled += netup_ci_slot_status(dev, pci_status);
1745
1746         }
1747
1748         if (ts1_status) {
1749                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1750                         handled += cx23885_irq_ts(ts1, ts1_status);
1751                 else
1752                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1753                         handled += cx23885_irq_417(dev, ts1_status);
1754         }
1755
1756         if (ts2_status) {
1757                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1758                         handled += cx23885_irq_ts(ts2, ts2_status);
1759                 else
1760                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1761                         handled += cx23885_irq_417(dev, ts2_status);
1762         }
1763
1764         if (vida_status)
1765                 handled += cx23885_video_irq(dev, vida_status);
1766
1767         if (pci_status & PCI_MSK_IR) {
1768                 v4l2_subdev_call(dev->sd_ir, ir, interrupt_service_routine,
1769                                  pci_status, &ir_handled);
1770                 if (ir_handled)
1771                         handled++;
1772         }
1773
1774         if (handled)
1775                 cx_write(PCI_INT_STAT, pci_status);
1776 out:
1777         return IRQ_RETVAL(handled);
1778 }
1779
1780 static void cx23885_v4l2_dev_notify(struct v4l2_subdev *sd,
1781                                     unsigned int notification, void *arg)
1782 {
1783         struct cx23885_dev *dev;
1784
1785         if (sd == NULL)
1786                 return;
1787
1788         dev = to_cx23885(sd->v4l2_dev);
1789
1790         switch (notification) {
1791         case V4L2_SUBDEV_IR_RX_NOTIFY: /* Called in an IRQ context */
1792                 if (sd == dev->sd_ir)
1793                         cx23885_ir_rx_v4l2_dev_notify(sd, *(u32 *)arg);
1794                 break;
1795         case V4L2_SUBDEV_IR_TX_NOTIFY: /* Called in an IRQ context */
1796                 if (sd == dev->sd_ir)
1797                         cx23885_ir_tx_v4l2_dev_notify(sd, *(u32 *)arg);
1798                 break;
1799         }
1800 }
1801
1802 static void cx23885_v4l2_dev_notify_init(struct cx23885_dev *dev)
1803 {
1804         INIT_WORK(&dev->ir_rx_work, cx23885_ir_rx_work_handler);
1805         INIT_WORK(&dev->ir_tx_work, cx23885_ir_tx_work_handler);
1806         dev->v4l2_dev.notify = cx23885_v4l2_dev_notify;
1807 }
1808
1809 static inline int encoder_on_portb(struct cx23885_dev *dev)
1810 {
1811         return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1812 }
1813
1814 static inline int encoder_on_portc(struct cx23885_dev *dev)
1815 {
1816         return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1817 }
1818
1819 /* Mask represents 32 different GPIOs, GPIO's are split into multiple
1820  * registers depending on the board configuration (and whether the
1821  * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1822  * be pushed into the correct hardware register, regardless of the
1823  * physical location. Certain registers are shared so we sanity check
1824  * and report errors if we think we're tampering with a GPIo that might
1825  * be assigned to the encoder (and used for the host bus).
1826  *
1827  * GPIO  2 thru  0 - On the cx23885 bridge
1828  * GPIO 18 thru  3 - On the cx23417 host bus interface
1829  * GPIO 23 thru 19 - On the cx25840 a/v core
1830  */
1831 void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1832 {
1833         if (mask & 0x7)
1834                 cx_set(GP0_IO, mask & 0x7);
1835
1836         if (mask & 0x0007fff8) {
1837                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1838                         printk(KERN_ERR
1839                                 "%s: Setting GPIO on encoder ports\n",
1840                                 dev->name);
1841                 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1842         }
1843
1844         /* TODO: 23-19 */
1845         if (mask & 0x00f80000)
1846                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1847 }
1848
1849 void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1850 {
1851         if (mask & 0x00000007)
1852                 cx_clear(GP0_IO, mask & 0x7);
1853
1854         if (mask & 0x0007fff8) {
1855                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1856                         printk(KERN_ERR
1857                                 "%s: Clearing GPIO moving on encoder ports\n",
1858                                 dev->name);
1859                 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1860         }
1861
1862         /* TODO: 23-19 */
1863         if (mask & 0x00f80000)
1864                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1865 }
1866
1867 u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask)
1868 {
1869         if (mask & 0x00000007)
1870                 return (cx_read(GP0_IO) >> 8) & mask & 0x7;
1871
1872         if (mask & 0x0007fff8) {
1873                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1874                         printk(KERN_ERR
1875                                 "%s: Reading GPIO moving on encoder ports\n",
1876                                 dev->name);
1877                 return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3;
1878         }
1879
1880         /* TODO: 23-19 */
1881         if (mask & 0x00f80000)
1882                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1883
1884         return 0;
1885 }
1886
1887 void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1888 {
1889         if ((mask & 0x00000007) && asoutput)
1890                 cx_set(GP0_IO, (mask & 0x7) << 16);
1891         else if ((mask & 0x00000007) && !asoutput)
1892                 cx_clear(GP0_IO, (mask & 0x7) << 16);
1893
1894         if (mask & 0x0007fff8) {
1895                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1896                         printk(KERN_ERR
1897                                 "%s: Enabling GPIO on encoder ports\n",
1898                                 dev->name);
1899         }
1900
1901         /* MC417_OEN is active low for output, write 1 for an input */
1902         if ((mask & 0x0007fff8) && asoutput)
1903                 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
1904
1905         else if ((mask & 0x0007fff8) && !asoutput)
1906                 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
1907
1908         /* TODO: 23-19 */
1909 }
1910
1911 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1912                                      const struct pci_device_id *pci_id)
1913 {
1914         struct cx23885_dev *dev;
1915         int err;
1916
1917         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1918         if (NULL == dev)
1919                 return -ENOMEM;
1920
1921         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1922         if (err < 0)
1923                 goto fail_free;
1924
1925         /* Prepare to handle notifications from subdevices */
1926         cx23885_v4l2_dev_notify_init(dev);
1927
1928         /* pci init */
1929         dev->pci = pci_dev;
1930         if (pci_enable_device(pci_dev)) {
1931                 err = -EIO;
1932                 goto fail_unreg;
1933         }
1934
1935         if (cx23885_dev_setup(dev) < 0) {
1936                 err = -EINVAL;
1937                 goto fail_unreg;
1938         }
1939
1940         /* print pci info */
1941         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1942         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1943         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1944                "latency: %d, mmio: 0x%llx\n", dev->name,
1945                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1946                dev->pci_lat,
1947                 (unsigned long long)pci_resource_start(pci_dev, 0));
1948
1949         pci_set_master(pci_dev);
1950         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1951                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1952                 err = -EIO;
1953                 goto fail_irq;
1954         }
1955
1956         if (!pci_enable_msi(pci_dev))
1957                 err = request_irq(pci_dev->irq, cx23885_irq,
1958                                   IRQF_DISABLED, dev->name, dev);
1959         else
1960                 err = request_irq(pci_dev->irq, cx23885_irq,
1961                                   IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1962         if (err < 0) {
1963                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1964                        dev->name, pci_dev->irq);
1965                 goto fail_irq;
1966         }
1967
1968         switch (dev->board) {
1969         case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1970                 cx_set(PCI_INT_MSK, 0x01800000); /* for NetUP */
1971                 break;
1972         }
1973
1974         /*
1975          * The CX2388[58] IR controller can start firing interrupts when
1976          * enabled, so these have to take place after the cx23885_irq() handler
1977          * is hooked up by the call to request_irq() above.
1978          */
1979         cx23885_ir_pci_int_enable(dev);
1980         cx23885_input_init(dev);
1981
1982         return 0;
1983
1984 fail_irq:
1985         cx23885_dev_unregister(dev);
1986 fail_unreg:
1987         v4l2_device_unregister(&dev->v4l2_dev);
1988 fail_free:
1989         kfree(dev);
1990         return err;
1991 }
1992
1993 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1994 {
1995         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1996         struct cx23885_dev *dev = to_cx23885(v4l2_dev);
1997
1998         cx23885_input_fini(dev);
1999         cx23885_ir_fini(dev);
2000
2001         cx23885_shutdown(dev);
2002
2003         pci_disable_device(pci_dev);
2004
2005         /* unregister stuff */
2006         free_irq(pci_dev->irq, dev);
2007         pci_disable_msi(pci_dev);
2008
2009         cx23885_dev_unregister(dev);
2010         v4l2_device_unregister(v4l2_dev);
2011         kfree(dev);
2012 }
2013
2014 static struct pci_device_id cx23885_pci_tbl[] = {
2015         {
2016                 /* CX23885 */
2017                 .vendor       = 0x14f1,
2018                 .device       = 0x8852,
2019                 .subvendor    = PCI_ANY_ID,
2020                 .subdevice    = PCI_ANY_ID,
2021         }, {
2022                 /* CX23887 Rev 2 */
2023                 .vendor       = 0x14f1,
2024                 .device       = 0x8880,
2025                 .subvendor    = PCI_ANY_ID,
2026                 .subdevice    = PCI_ANY_ID,
2027         }, {
2028                 /* --- end of list --- */
2029         }
2030 };
2031 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
2032
2033 static struct pci_driver cx23885_pci_driver = {
2034         .name     = "cx23885",
2035         .id_table = cx23885_pci_tbl,
2036         .probe    = cx23885_initdev,
2037         .remove   = __devexit_p(cx23885_finidev),
2038         /* TODO */
2039         .suspend  = NULL,
2040         .resume   = NULL,
2041 };
2042
2043 static int __init cx23885_init(void)
2044 {
2045         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
2046                (CX23885_VERSION_CODE >> 16) & 0xff,
2047                (CX23885_VERSION_CODE >>  8) & 0xff,
2048                CX23885_VERSION_CODE & 0xff);
2049 #ifdef SNAPSHOT
2050         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
2051                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
2052 #endif
2053         return pci_register_driver(&cx23885_pci_driver);
2054 }
2055
2056 static void __exit cx23885_fini(void)
2057 {
2058         pci_unregister_driver(&cx23885_pci_driver);
2059 }
2060
2061 module_init(cx23885_init);
2062 module_exit(cx23885_fini);
2063
2064 /* ----------------------------------------------------------- */