drivers/media/tuners/tda18250.c

   1 /*
   2  * NXP TDA18250 silicon tuner driver
   3  *
   4  * Copyright (C) 2017 Olli Salonen <olli.salonen@iki.fi>
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2 of the License, or
   9  *    (at your option) any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include "tda18250_priv.h"
  19 #include <linux/regmap.h>
  20
  21 static const struct dvb_tuner_ops tda18250_ops;
  22
  23 static int tda18250_power_control(struct dvb_frontend *fe,
  24                 unsigned int power_state)
  25 {
  26         struct i2c_client *client = fe->tuner_priv;
  27         struct tda18250_dev *dev = i2c_get_clientdata(client);
  28         int ret;
  29         unsigned int utmp;
  30
  31         dev_dbg(&client->dev, "power state: %d", power_state);
  32
  33         switch (power_state) {
  34         case TDA18250_POWER_NORMAL:
  35                 ret = regmap_write_bits(dev->regmap, R06_POWER2, 0x07, 0x00);
  36                 if (ret)
  37                         goto err;
  38                 ret = regmap_write_bits(dev->regmap, R25_REF, 0xc0, 0xc0);
  39                 if (ret)
  40                         goto err;
  41                 break;
  42         case TDA18250_POWER_STANDBY:
  43                 if (dev->loopthrough) {
  44                         ret = regmap_write_bits(dev->regmap,
  45                                         R25_REF, 0xc0, 0x80);
  46                         if (ret)
  47                                 goto err;
  48                         ret = regmap_write_bits(dev->regmap,
  49                                         R06_POWER2, 0x07, 0x02);
  50                         if (ret)
  51                                 goto err;
  52                         ret = regmap_write_bits(dev->regmap,
  53                                         R10_LT1, 0x80, 0x00);
  54                         if (ret)
  55                                 goto err;
  56                 } else {
  57                         ret = regmap_write_bits(dev->regmap,
  58                                         R25_REF, 0xc0, 0x80);
  59                         if (ret)
  60                                 goto err;
  61                         ret = regmap_write_bits(dev->regmap,
  62                                         R06_POWER2, 0x07, 0x01);
  63                         if (ret)
  64                                 goto err;
  65                         ret = regmap_read(dev->regmap,
  66                                         R0D_AGC12, &utmp);
  67                         if (ret)
  68                                 goto err;
  69                         ret = regmap_write_bits(dev->regmap,
  70                                         R0D_AGC12, 0x03, 0x03);
  71                         if (ret)
  72                                 goto err;
  73                         ret = regmap_write_bits(dev->regmap,
  74                                         R10_LT1, 0x80, 0x80);
  75                         if (ret)
  76                                 goto err;
  77                         ret = regmap_write_bits(dev->regmap,
  78                                         R0D_AGC12, 0x03, utmp & 0x03);
  79                         if (ret)
  80                                 goto err;
  81                 }
  82                 break;
  83         default:
  84                 ret = -EINVAL;
  85                 goto err;
  86         }
  87
  88         return 0;
  89 err:
  90         return ret;
  91 }
  92
  93 static int tda18250_wait_for_irq(struct dvb_frontend *fe,
  94                 int maxwait, int step, u8 irq)
  95 {
  96         struct i2c_client *client = fe->tuner_priv;
  97         struct tda18250_dev *dev = i2c_get_clientdata(client);
  98         int ret;
  99         unsigned long timeout;
 100         bool triggered;
 101         unsigned int utmp;
 102
 103         triggered = false;
 104         timeout = jiffies + msecs_to_jiffies(maxwait);
 105         while (!time_after(jiffies, timeout)) {
 106                 // check for the IRQ
 107                 ret = regmap_read(dev->regmap, R08_IRQ1, &utmp);
 108                 if (ret)
 109                         goto err;
 110                 if ((utmp & irq) == irq) {
 111                         triggered = true;
 112                         break;
 113                 }
 114                 msleep(step);
 115         }
 116
 117         dev_dbg(&client->dev, "waited IRQ (0x%02x) %d ms, triggered: %s", irq,
 118                         jiffies_to_msecs(jiffies) -
 119                         (jiffies_to_msecs(timeout) - maxwait),
 120                         triggered ? "true" : "false");
 121
 122         if (!triggered)
 123                 return -ETIMEDOUT;
 124
 125         return 0;
 126 err:
 127         return ret;
 128 }
 129
 130 static int tda18250_init(struct dvb_frontend *fe)
 131 {
 132         struct i2c_client *client = fe->tuner_priv;
 133         struct tda18250_dev *dev = i2c_get_clientdata(client);
 134         int ret, i;
 135
 136         /* default values for various regs */
 137         static const u8 init_regs[][2] = {
 138                 { R0C_AGC11, 0xc7 },
 139                 { R0D_AGC12, 0x5d },
 140                 { R0E_AGC13, 0x40 },
 141                 { R0F_AGC14, 0x0e },
 142                 { R10_LT1, 0x47 },
 143                 { R11_LT2, 0x4e },
 144                 { R12_AGC21, 0x26 },
 145                 { R13_AGC22, 0x60 },
 146                 { R18_AGC32, 0x37 },
 147                 { R19_AGC33, 0x09 },
 148                 { R1A_AGCK, 0x00 },
 149                 { R1E_WI_FI, 0x29 },
 150                 { R1F_RF_BPF, 0x06 },
 151                 { R20_IR_MIX, 0xc6 },
 152                 { R21_IF_AGC, 0x00 },
 153                 { R2C_PS1, 0x75 },
 154                 { R2D_PS2, 0x06 },
 155                 { R2E_PS3, 0x07 },
 156                 { R30_RSSI2, 0x0e },
 157                 { R31_IRQ_CTRL, 0x00 },
 158                 { R39_SD5, 0x00 },
 159                 { R3B_REGU, 0x55 },
 160                 { R3C_RCCAL1, 0xa7 },
 161                 { R3F_IRCAL2, 0x85 },
 162                 { R40_IRCAL3, 0x87 },
 163                 { R41_IRCAL4, 0xc0 },
 164                 { R43_PD1, 0x40 },
 165                 { R44_PD2, 0xc0 },
 166                 { R46_CPUMP, 0x0c },
 167                 { R47_LNAPOL, 0x64 },
 168                 { R4B_XTALOSC1, 0x30 },
 169                 { R59_AGC2_UP2, 0x05 },
 170                 { R5B_AGC_AUTO, 0x07 },
 171                 { R5C_AGC_DEBUG, 0x00 },
 172         };
 173
 174         /* crystal related regs depend on frequency */
 175         static const u8 xtal_regs[][5] = {
 176                                         /* reg:   4d    4e    4f    50    51 */
 177                 [TDA18250_XTAL_FREQ_16MHZ]  = { 0x3e, 0x80, 0x50, 0x00, 0x20 },
 178                 [TDA18250_XTAL_FREQ_24MHZ]  = { 0x5d, 0xc0, 0xec, 0x00, 0x18 },
 179                 [TDA18250_XTAL_FREQ_25MHZ]  = { 0x61, 0xa8, 0xec, 0x80, 0x19 },
 180                 [TDA18250_XTAL_FREQ_27MHZ]  = { 0x69, 0x78, 0x8d, 0x80, 0x1b },
 181                 [TDA18250_XTAL_FREQ_30MHZ]  = { 0x75, 0x30, 0x8f, 0x00, 0x1e },
 182         };
 183
 184         dev_dbg(&client->dev, "\n");
 185
 186         ret = tda18250_power_control(fe, TDA18250_POWER_NORMAL);
 187         if (ret)
 188                 goto err;
 189
 190         msleep(20);
 191
 192         if (dev->warm)
 193                 goto warm;
 194
 195         /* set initial register values */
 196         for (i = 0; i < ARRAY_SIZE(init_regs); i++) {
 197                 ret = regmap_write(dev->regmap, init_regs[i][0],
 198                                 init_regs[i][1]);
 199                 if (ret)
 200                         goto err;
 201         }
 202
 203         /* set xtal related regs */
 204         ret = regmap_bulk_write(dev->regmap, R4D_XTALFLX1,
 205                         xtal_regs[dev->xtal_freq], 5);
 206         if (ret)
 207                 goto err;
 208
 209         ret = regmap_write_bits(dev->regmap, R10_LT1, 0x80,
 210                         dev->loopthrough ? 0x00 : 0x80);
 211         if (ret)
 212                 goto err;
 213
 214         /* clear IRQ */
 215         ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_HW_INIT);
 216         if (ret)
 217                 goto err;
 218
 219         /* start HW init */
 220         ret = regmap_write(dev->regmap, R2A_MSM1, 0x70);
 221         if (ret)
 222                 goto err;
 223
 224         ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
 225         if (ret)
 226                 goto err;
 227
 228         ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_HW_INIT);
 229         if (ret)
 230                 goto err;
 231
 232         /* tuner calibration */
 233         ret = regmap_write(dev->regmap, R2A_MSM1, 0x02);
 234         if (ret)
 235                 goto err;
 236
 237         ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
 238         if (ret)
 239                 goto err;
 240
 241         ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_CAL);
 242         if (ret)
 243                 goto err;
 244
 245         dev->warm = true;
 246
 247 warm:
 248         /* power up LNA */
 249         ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
 250         if (ret)
 251                 goto err;
 252
 253         return 0;
 254 err:
 255         dev_dbg(&client->dev, "failed=%d", ret);
 256         return ret;
 257 }
 258
 259 static int tda18250_set_agc(struct dvb_frontend *fe)
 260 {
 261         struct i2c_client *client = fe->tuner_priv;
 262         struct tda18250_dev *dev = i2c_get_clientdata(client);
 263         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 264         int ret;
 265         u8 utmp, utmp2;
 266
 267         dev_dbg(&client->dev, "\n");
 268
 269         ret = regmap_write_bits(dev->regmap, R1F_RF_BPF, 0x87, 0x06);
 270         if (ret)
 271                 goto err;
 272
 273         utmp = ((c->frequency < 100000000) &&
 274                         ((c->delivery_system == SYS_DVBC_ANNEX_A) ||
 275                         (c->delivery_system == SYS_DVBC_ANNEX_C)) &&
 276                         (c->bandwidth_hz == 6000000)) ? 0x80 : 0x00;
 277         ret = regmap_write(dev->regmap, R5A_H3H5, utmp);
 278         if (ret)
 279                 goto err;
 280
 281         /* AGC1 */
 282         switch (c->delivery_system) {
 283         case SYS_ATSC:
 284         case SYS_DVBT:
 285         case SYS_DVBT2:
 286                 utmp = 4;
 287                 break;
 288         default: /* DVB-C/QAM */
 289                 switch (c->bandwidth_hz) {
 290                 case 6000000:
 291                         utmp = (c->frequency < 800000000) ? 6 : 4;
 292                         break;
 293                 default: /* 7.935 and 8 MHz */
 294                         utmp = (c->frequency < 100000000) ? 2 : 3;
 295                         break;
 296                 }
 297                 break;
 298         }
 299
 300         ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x07, utmp);
 301         if (ret)
 302                 goto err;
 303
 304         /* AGC2 */
 305         switch (c->delivery_system) {
 306         case SYS_ATSC:
 307         case SYS_DVBT:
 308         case SYS_DVBT2:
 309                 utmp = (c->frequency < 320000000) ? 20 : 16;
 310                 utmp2 = (c->frequency < 320000000) ? 22 : 18;
 311                 break;
 312         default: /* DVB-C/QAM */
 313                 switch (c->bandwidth_hz) {
 314                 case 6000000:
 315                         if (c->frequency < 600000000) {
 316                                 utmp = 18;
 317                                 utmp2 = 22;
 318                         } else if (c->frequency < 800000000) {
 319                                 utmp = 16;
 320                                 utmp2 = 20;
 321                         } else {
 322                                 utmp = 14;
 323                                 utmp2 = 16;
 324                         }
 325                         break;
 326                 default: /* 7.935 and 8 MHz */
 327                         utmp = (c->frequency < 320000000) ? 16 : 18;
 328                         utmp2 = (c->frequency < 320000000) ? 18 : 20;
 329                         break;
 330                 }
 331                 break;
 332         }
 333         ret = regmap_write_bits(dev->regmap, R58_AGC2_UP1, 0x1f, utmp2+8);
 334         if (ret)
 335                 goto err;
 336         ret = regmap_write_bits(dev->regmap, R13_AGC22, 0x1f, utmp);
 337         if (ret)
 338                 goto err;
 339         ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x1f, utmp2);
 340         if (ret)
 341                 goto err;
 342
 343         switch (c->delivery_system) {
 344         case SYS_ATSC:
 345         case SYS_DVBT:
 346         case SYS_DVBT2:
 347                 utmp = 98;
 348                 break;
 349         default: /* DVB-C/QAM */
 350                 utmp = 90;
 351                 break;
 352         }
 353         ret = regmap_write_bits(dev->regmap, R16_AGC25, 0xf8, utmp);
 354         if (ret)
 355                 goto err;
 356
 357         ret = regmap_write_bits(dev->regmap, R12_AGC21, 0x60,
 358                         (c->frequency > 800000000) ? 0x40 : 0x20);
 359         if (ret)
 360                 goto err;
 361
 362         /* AGC3 */
 363         switch (c->delivery_system) {
 364         case SYS_ATSC:
 365         case SYS_DVBT:
 366         case SYS_DVBT2:
 367                 utmp = (c->frequency < 320000000) ? 5 : 7;
 368                 utmp2 = (c->frequency < 320000000) ? 10 : 12;
 369                 break;
 370         default: /* DVB-C/QAM */
 371                 utmp = 7;
 372                 utmp2 = 12;
 373                 break;
 374         }
 375         ret = regmap_write(dev->regmap, R17_AGC31, (utmp << 4) | utmp2);
 376         if (ret)
 377                 goto err;
 378
 379         /* S2D */
 380         switch (c->delivery_system) {
 381         case SYS_ATSC:
 382         case SYS_DVBT:
 383         case SYS_DVBT2:
 384                 if (c->bandwidth_hz == 8000000)
 385                         utmp = 0x04;
 386                 else
 387                         utmp = (c->frequency < 320000000) ? 0x04 : 0x02;
 388                 break;
 389         default: /* DVB-C/QAM */
 390                 if (c->bandwidth_hz == 6000000)
 391                         utmp = ((c->frequency > 172544000) &&
 392                                 (c->frequency < 320000000)) ? 0x04 : 0x02;
 393                 else /* 7.935 and 8 MHz */
 394                         utmp = ((c->frequency > 320000000) &&
 395                                 (c->frequency < 600000000)) ? 0x02 : 0x04;
 396                 break;
 397         }
 398         ret = regmap_write_bits(dev->regmap, R20_IR_MIX, 0x06, utmp);
 399         if (ret)
 400                 goto err;
 401
 402         switch (c->delivery_system) {
 403         case SYS_ATSC:
 404         case SYS_DVBT:
 405         case SYS_DVBT2:
 406                 utmp = 0;
 407                 break;
 408         default: /* DVB-C/QAM */
 409                 utmp = (c->frequency < 600000000) ? 0 : 3;
 410                 break;
 411         }
 412         ret = regmap_write_bits(dev->regmap, R16_AGC25, 0x03, utmp);
 413         if (ret)
 414                 goto err;
 415
 416         utmp = 0x09;
 417         switch (c->delivery_system) {
 418         case SYS_ATSC:
 419         case SYS_DVBT:
 420         case SYS_DVBT2:
 421                 if (c->bandwidth_hz == 8000000)
 422                         utmp = 0x0c;
 423                 break;
 424         default: /* DVB-C/QAM */
 425                 utmp = 0x0c;
 426                 break;
 427         }
 428         ret = regmap_write_bits(dev->regmap, R0F_AGC14, 0x3f, utmp);
 429         if (ret)
 430                 goto err;
 431
 432         return 0;
 433 err:
 434         dev_dbg(&client->dev, "failed=%d", ret);
 435         return ret;
 436 }
 437
 438 static int tda18250_pll_calc(struct dvb_frontend *fe, u8 *rdiv,
 439                 u8 *ndiv, u8 *icp)
 440 {
 441         struct i2c_client *client = fe->tuner_priv;
 442         struct tda18250_dev *dev = i2c_get_clientdata(client);
 443         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 444         int ret;
 445         unsigned int uval, exp, lopd, scale;
 446         unsigned long fvco;
 447
 448         ret = regmap_read(dev->regmap, R34_MD1, &uval);
 449         if (ret)
 450                 goto err;
 451
 452         exp = (uval & 0x70) >> 4;
 453         if (exp > 5)
 454                 exp = 0;
 455         lopd = 1 << (exp - 1);
 456         scale = uval & 0x0f;
 457         fvco = lopd * scale * ((c->frequency / 1000) + dev->if_frequency);
 458
 459         switch (dev->xtal_freq) {
 460         case TDA18250_XTAL_FREQ_16MHZ:
 461                 *rdiv = 1;
 462                 *ndiv = 0;
 463                 *icp = (fvco < 6622000) ? 0x05 : 0x02;
 464         break;
 465         case TDA18250_XTAL_FREQ_24MHZ:
 466         case TDA18250_XTAL_FREQ_25MHZ:
 467                 *rdiv = 3;
 468                 *ndiv = 1;
 469                 *icp = (fvco < 6622000) ? 0x05 : 0x02;
 470         break;
 471         case TDA18250_XTAL_FREQ_27MHZ:
 472                 if (fvco < 6643000) {
 473                         *rdiv = 2;
 474                         *ndiv = 0;
 475                         *icp = 0x05;
 476                 } else if (fvco < 6811000) {
 477                         *rdiv = 2;
 478                         *ndiv = 0;
 479                         *icp = 0x06;
 480                 } else {
 481                         *rdiv = 3;
 482                         *ndiv = 1;
 483                         *icp = 0x02;
 484                 }
 485         break;
 486         case TDA18250_XTAL_FREQ_30MHZ:
 487                 *rdiv = 2;
 488                 *ndiv = 0;
 489                 *icp = (fvco < 6811000) ? 0x05 : 0x02;
 490         break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         dev_dbg(&client->dev,
 496                         "lopd=%d scale=%u fvco=%lu, rdiv=%d ndiv=%d icp=%d",
 497                         lopd, scale, fvco, *rdiv, *ndiv, *icp);
 498         return 0;
 499 err:
 500         return ret;
 501 }
 502
 503 static int tda18250_set_params(struct dvb_frontend *fe)
 504 {
 505         struct i2c_client *client = fe->tuner_priv;
 506         struct tda18250_dev *dev = i2c_get_clientdata(client);
 507         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 508         u32 if_khz;
 509         int ret;
 510         unsigned int i, j;
 511         u8 utmp;
 512         u8 buf[3];
 513
 514         #define REG      0
 515         #define MASK     1
 516         #define DVBT_6   2
 517         #define DVBT_7   3
 518         #define DVBT_8   4
 519         #define DVBC_6   5
 520         #define DVBC_8   6
 521         #define ATSC     7
 522
 523         static const u8 delsys_params[][16] = {
 524                 [REG]    = { 0x22, 0x23, 0x24, 0x21, 0x0d, 0x0c, 0x0f, 0x14,
 525                              0x0e, 0x12, 0x58, 0x59, 0x1a, 0x19, 0x1e, 0x30 },
 526                 [MASK]   = { 0x77, 0xff, 0xff, 0x87, 0xf0, 0x78, 0x07, 0xe0,
 527                              0x60, 0x0f, 0x60, 0x0f, 0x33, 0x30, 0x80, 0x06 },
 528                 [DVBT_6] = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
 529                              0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
 530                 [DVBT_7] = { 0x52, 0x03, 0x85, 0x82, 0x40, 0x48, 0x01, 0xe0,
 531                              0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
 532                 [DVBT_8] = { 0x53, 0x03, 0x87, 0x82, 0x40, 0x48, 0x06, 0xe0,
 533                              0x60, 0x07, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
 534                 [DVBC_6] = { 0x32, 0x05, 0x86, 0x82, 0x50, 0x00, 0x06, 0x60,
 535                              0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
 536                 [DVBC_8] = { 0x53, 0x03, 0x88, 0x82, 0x50, 0x00, 0x06, 0x60,
 537                              0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
 538                 [ATSC]   = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
 539                              0x40, 0x0e, 0x60, 0x05, 0x03, 0x00, 0x80, 0x04 },
 540         };
 541
 542         dev_dbg(&client->dev,
 543                         "delivery_system=%d frequency=%u bandwidth_hz=%u",
 544                         c->delivery_system, c->frequency, c->bandwidth_hz);
 545
 546
 547         switch (c->delivery_system) {
 548         case SYS_ATSC:
 549                 j = ATSC;
 550                 if_khz = dev->if_atsc;
 551                 break;
 552         case SYS_DVBT:
 553         case SYS_DVBT2:
 554                 if (c->bandwidth_hz == 0) {
 555                         ret = -EINVAL;
 556                         goto err;
 557                 } else if (c->bandwidth_hz <= 6000000) {
 558                         j = DVBT_6;
 559                         if_khz = dev->if_dvbt_6;
 560                 } else if (c->bandwidth_hz <= 7000000) {
 561                         j = DVBT_7;
 562                         if_khz = dev->if_dvbt_7;
 563                 } else if (c->bandwidth_hz <= 8000000) {
 564                         j = DVBT_8;
 565                         if_khz = dev->if_dvbt_8;
 566                 } else {
 567                         ret = -EINVAL;
 568                         goto err;
 569                 }
 570                 break;
 571         case SYS_DVBC_ANNEX_A:
 572         case SYS_DVBC_ANNEX_C:
 573                 if (c->bandwidth_hz == 0) {
 574                         ret = -EINVAL;
 575                         goto err;
 576                 } else if (c->bandwidth_hz <= 6000000) {
 577                         j = DVBC_6;
 578                         if_khz = dev->if_dvbc_6;
 579                 } else if (c->bandwidth_hz <= 8000000) {
 580                         j = DVBC_8;
 581                         if_khz = dev->if_dvbc_8;
 582                 } else {
 583                         ret = -EINVAL;
 584                         goto err;
 585                 }
 586                 break;
 587         default:
 588                 ret = -EINVAL;
 589                 dev_err(&client->dev, "unsupported delivery system=%d",
 590                                 c->delivery_system);
 591                 goto err;
 592         }
 593
 594         /* set delivery system dependent registers */
 595         for (i = 0; i < 16; i++) {
 596                 ret = regmap_write_bits(dev->regmap, delsys_params[REG][i],
 597                          delsys_params[MASK][i],  delsys_params[j][i]);
 598                 if (ret)
 599                         goto err;
 600         }
 601
 602         /* set IF if needed */
 603         if (dev->if_frequency != if_khz) {
 604                 utmp = DIV_ROUND_CLOSEST(if_khz, 50);
 605                 ret = regmap_write(dev->regmap, R26_IF, utmp);
 606                 if (ret)
 607                         goto err;
 608                 dev->if_frequency = if_khz;
 609                 dev_dbg(&client->dev, "set IF=%u kHz", if_khz);
 610
 611         }
 612
 613         ret = tda18250_set_agc(fe);
 614         if (ret)
 615                 goto err;
 616
 617         ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x01);
 618         if (ret)
 619                 goto err;
 620
 621         ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x00);
 622         if (ret)
 623                 goto err;
 624
 625         /* set frequency */
 626         buf[0] = ((c->frequency / 1000) >> 16) & 0xff;
 627         buf[1] = ((c->frequency / 1000) >>  8) & 0xff;
 628         buf[2] = ((c->frequency / 1000) >>  0) & 0xff;
 629         ret = regmap_bulk_write(dev->regmap, R27_RF1, buf, 3);
 630         if (ret)
 631                 goto err;
 632
 633         ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
 634         if (ret)
 635                 goto err;
 636
 637         /* initial tune */
 638         ret = regmap_write(dev->regmap, R2A_MSM1, 0x01);
 639         if (ret)
 640                 goto err;
 641
 642         ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
 643         if (ret)
 644                 goto err;
 645
 646         ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
 647         if (ret)
 648                 goto err;
 649
 650         /* calc ndiv and rdiv */
 651         ret = tda18250_pll_calc(fe, &buf[0], &buf[1], &buf[2]);
 652         if (ret)
 653                 goto err;
 654
 655         ret = regmap_write_bits(dev->regmap, R4F_XTALFLX3, 0xe0,
 656                         (buf[0] << 6) | (buf[1] << 5));
 657         if (ret)
 658                 goto err;
 659
 660         /* clear IRQ */
 661         ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
 662         if (ret)
 663                 goto err;
 664
 665         ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, 0x00);
 666         if (ret)
 667                 goto err;
 668
 669         ret = regmap_write_bits(dev->regmap, R39_SD5, 0x03, 0x00);
 670         if (ret)
 671                 goto err;
 672
 673         /* tune again */
 674         ret = regmap_write(dev->regmap, R2A_MSM1, 0x01); /* tune */
 675         if (ret)
 676                 goto err;
 677
 678         ret = regmap_write(dev->regmap, R2B_MSM2, 0x01); /* go */
 679         if (ret)
 680                 goto err;
 681
 682         ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
 683         if (ret)
 684                 goto err;
 685
 686         /* pll locking */
 687         msleep(20);
 688
 689         ret = regmap_write_bits(dev->regmap, R2B_MSM2, 0x04, 0x04);
 690         if (ret)
 691                 goto err;
 692
 693         msleep(20);
 694
 695         /* restore AGCK */
 696         ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x03);
 697         if (ret)
 698                 goto err;
 699
 700         ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x40);
 701         if (ret)
 702                 goto err;
 703
 704         /* charge pump */
 705         ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, buf[2]);
 706
 707         return 0;
 708 err:
 709         return ret;
 710 }
 711
 712 static int tda18250_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
 713 {
 714         struct i2c_client *client = fe->tuner_priv;
 715         struct tda18250_dev *dev = i2c_get_clientdata(client);
 716
 717         *frequency = dev->if_frequency * 1000;
 718         return 0;
 719 }
 720
 721 static int tda18250_sleep(struct dvb_frontend *fe)
 722 {
 723         struct i2c_client *client = fe->tuner_priv;
 724         struct tda18250_dev *dev = i2c_get_clientdata(client);
 725         int ret;
 726
 727         dev_dbg(&client->dev, "\n");
 728
 729         /* power down LNA */
 730         ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
 731         if (ret)
 732                 return ret;
 733
 734         /* set if freq to 0 in order to make sure it's set after wake up */
 735         dev->if_frequency = 0;
 736
 737         ret = tda18250_power_control(fe, TDA18250_POWER_STANDBY);
 738         return ret;
 739 }
 740
 741 static const struct dvb_tuner_ops tda18250_ops = {
 742         .info = {
 743                 .name              = "NXP TDA18250",
 744                 .frequency_min_hz  =  42 * MHz,
 745                 .frequency_max_hz  = 870 * MHz,
 746         },
 747
 748         .init = tda18250_init,
 749         .set_params = tda18250_set_params,
 750         .get_if_frequency = tda18250_get_if_frequency,
 751         .sleep = tda18250_sleep,
 752 };
 753
 754 static int tda18250_probe(struct i2c_client *client,
 755                 const struct i2c_device_id *id)
 756 {
 757         struct tda18250_config *cfg = client->dev.platform_data;
 758         struct dvb_frontend *fe = cfg->fe;
 759         struct tda18250_dev *dev;
 760         int ret;
 761         unsigned char chip_id[3];
 762
 763         /* some registers are always read from HW */
 764         static const struct regmap_range tda18250_yes_ranges[] = {
 765                 regmap_reg_range(R05_POWER1, R0B_IRQ4),
 766                 regmap_reg_range(R21_IF_AGC, R21_IF_AGC),
 767                 regmap_reg_range(R2A_MSM1, R2B_MSM2),
 768                 regmap_reg_range(R2F_RSSI1, R31_IRQ_CTRL),
 769         };
 770
 771         static const struct regmap_access_table tda18250_volatile_table = {
 772                 .yes_ranges = tda18250_yes_ranges,
 773                 .n_yes_ranges = ARRAY_SIZE(tda18250_yes_ranges),
 774         };
 775
 776         static const struct regmap_config tda18250_regmap_config = {
 777                 .reg_bits = 8,
 778                 .val_bits = 8,
 779                 .max_register = TDA18250_NUM_REGS - 1,
 780                 .volatile_table = &tda18250_volatile_table,
 781         };
 782
 783         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 784         if (!dev) {
 785                 ret = -ENOMEM;
 786                 goto err;
 787         }
 788
 789         i2c_set_clientdata(client, dev);
 790
 791         dev->fe = cfg->fe;
 792         dev->loopthrough = cfg->loopthrough;
 793         if (cfg->xtal_freq < TDA18250_XTAL_FREQ_MAX) {
 794                 dev->xtal_freq = cfg->xtal_freq;
 795         } else {
 796                 ret = -EINVAL;
 797                 dev_err(&client->dev, "xtal_freq invalid=%d", cfg->xtal_freq);
 798                 goto err_kfree;
 799         }
 800         dev->if_dvbt_6 = cfg->if_dvbt_6;
 801         dev->if_dvbt_7 = cfg->if_dvbt_7;
 802         dev->if_dvbt_8 = cfg->if_dvbt_8;
 803         dev->if_dvbc_6 = cfg->if_dvbc_6;
 804         dev->if_dvbc_8 = cfg->if_dvbc_8;
 805         dev->if_atsc = cfg->if_atsc;
 806
 807         dev->if_frequency = 0;
 808         dev->warm = false;
 809
 810         dev->regmap = devm_regmap_init_i2c(client, &tda18250_regmap_config);
 811         if (IS_ERR(dev->regmap)) {
 812                 ret = PTR_ERR(dev->regmap);
 813                 goto err_kfree;
 814         }
 815
 816         /* read the three chip ID registers */
 817         regmap_bulk_read(dev->regmap, R00_ID1, &chip_id, 3);
 818         dev_dbg(&client->dev, "chip_id=%02x:%02x:%02x",
 819                         chip_id[0], chip_id[1], chip_id[2]);
 820
 821         switch (chip_id[0]) {
 822         case 0xc7:
 823                 dev->slave = false;
 824                 break;
 825         case 0x47:
 826                 dev->slave = true;
 827                 break;
 828         default:
 829                 ret = -ENODEV;
 830                 goto err_kfree;
 831         }
 832
 833         if (chip_id[1] != 0x4a) {
 834                 ret = -ENODEV;
 835                 goto err_kfree;
 836         }
 837
 838         switch (chip_id[2]) {
 839         case 0x20:
 840                 dev_info(&client->dev,
 841                                 "NXP TDA18250AHN/%s successfully identified",
 842                                 dev->slave ? "S" : "M");
 843                 break;
 844         case 0x21:
 845                 dev_info(&client->dev,
 846                                 "NXP TDA18250BHN/%s successfully identified",
 847                                 dev->slave ? "S" : "M");
 848                 break;
 849         default:
 850                 ret = -ENODEV;
 851                 goto err_kfree;
 852         }
 853
 854         fe->tuner_priv = client;
 855         memcpy(&fe->ops.tuner_ops, &tda18250_ops,
 856                         sizeof(struct dvb_tuner_ops));
 857
 858         /* put the tuner in standby */
 859         tda18250_power_control(fe, TDA18250_POWER_STANDBY);
 860
 861         return 0;
 862 err_kfree:
 863         kfree(dev);
 864 err:
 865         dev_dbg(&client->dev, "failed=%d", ret);
 866         return ret;
 867 }
 868
 869 static int tda18250_remove(struct i2c_client *client)
 870 {
 871         struct tda18250_dev *dev = i2c_get_clientdata(client);
 872         struct dvb_frontend *fe = dev->fe;
 873
 874         dev_dbg(&client->dev, "\n");
 875
 876         memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
 877         fe->tuner_priv = NULL;
 878         kfree(dev);
 879
 880         return 0;
 881 }
 882
 883 static const struct i2c_device_id tda18250_id_table[] = {
 884         {"tda18250", 0},
 885         {}
 886 };
 887 MODULE_DEVICE_TABLE(i2c, tda18250_id_table);
 888
 889 static struct i2c_driver tda18250_driver = {
 890         .driver = {
 891                 .name   = "tda18250",
 892         },
 893         .probe          = tda18250_probe,
 894         .remove         = tda18250_remove,
 895         .id_table       = tda18250_id_table,
 896 };
 897
 898 module_i2c_driver(tda18250_driver);
 899
 900 MODULE_DESCRIPTION("NXP TDA18250 silicon tuner driver");
 901 MODULE_AUTHOR("Olli Salonen <olli.salonen@iki.fi>");
 902 MODULE_LICENSE("GPL");