drivers/media/tuners/qt1010.c

   1 /*
   2  *  Driver for Quantek QT1010 silicon tuner
   3  *
   4  *  Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
   5  *                     Aapo Tahkola <aet@rasterburn.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  */
  17 #include "qt1010.h"
  18 #include "qt1010_priv.h"
  19
  20 /* read single register */
  21 static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
  22 {
  23         struct i2c_msg msg[2] = {
  24                 { .addr = priv->cfg->i2c_address,
  25                   .flags = 0, .buf = &reg, .len = 1 },
  26                 { .addr = priv->cfg->i2c_address,
  27                   .flags = I2C_M_RD, .buf = val, .len = 1 },
  28         };
  29
  30         if (i2c_transfer(priv->i2c, msg, 2) != 2) {
  31                 dev_warn(&priv->i2c->dev, "%s: i2c rd failed reg=%02x\n",
  32                                 KBUILD_MODNAME, reg);
  33                 return -EREMOTEIO;
  34         }
  35         return 0;
  36 }
  37
  38 /* write single register */
  39 static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
  40 {
  41         u8 buf[2] = { reg, val };
  42         struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
  43                                .flags = 0, .buf = buf, .len = 2 };
  44
  45         if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
  46                 dev_warn(&priv->i2c->dev, "%s: i2c wr failed reg=%02x\n",
  47                                 KBUILD_MODNAME, reg);
  48                 return -EREMOTEIO;
  49         }
  50         return 0;
  51 }
  52
  53 static int qt1010_set_params(struct dvb_frontend *fe)
  54 {
  55         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  56         struct qt1010_priv *priv;
  57         int err;
  58         u32 freq, div, mod1, mod2;
  59         u8 i, tmpval, reg05;
  60         qt1010_i2c_oper_t rd[48] = {
  61                 { QT1010_WR, 0x01, 0x80 },
  62                 { QT1010_WR, 0x02, 0x3f },
  63                 { QT1010_WR, 0x05, 0xff }, /* 02 c write */
  64                 { QT1010_WR, 0x06, 0x44 },
  65                 { QT1010_WR, 0x07, 0xff }, /* 04 c write */
  66                 { QT1010_WR, 0x08, 0x08 },
  67                 { QT1010_WR, 0x09, 0xff }, /* 06 c write */
  68                 { QT1010_WR, 0x0a, 0xff }, /* 07 c write */
  69                 { QT1010_WR, 0x0b, 0xff }, /* 08 c write */
  70                 { QT1010_WR, 0x0c, 0xe1 },
  71                 { QT1010_WR, 0x1a, 0xff }, /* 10 c write */
  72                 { QT1010_WR, 0x1b, 0x00 },
  73                 { QT1010_WR, 0x1c, 0x89 },
  74                 { QT1010_WR, 0x11, 0xff }, /* 13 c write */
  75                 { QT1010_WR, 0x12, 0xff }, /* 14 c write */
  76                 { QT1010_WR, 0x22, 0xff }, /* 15 c write */
  77                 { QT1010_WR, 0x1e, 0x00 },
  78                 { QT1010_WR, 0x1e, 0xd0 },
  79                 { QT1010_RD, 0x22, 0xff }, /* 16 c read */
  80                 { QT1010_WR, 0x1e, 0x00 },
  81                 { QT1010_RD, 0x05, 0xff }, /* 20 c read */
  82                 { QT1010_RD, 0x22, 0xff }, /* 21 c read */
  83                 { QT1010_WR, 0x23, 0xd0 },
  84                 { QT1010_WR, 0x1e, 0x00 },
  85                 { QT1010_WR, 0x1e, 0xe0 },
  86                 { QT1010_RD, 0x23, 0xff }, /* 25 c read */
  87                 { QT1010_RD, 0x23, 0xff }, /* 26 c read */
  88                 { QT1010_WR, 0x1e, 0x00 },
  89                 { QT1010_WR, 0x24, 0xd0 },
  90                 { QT1010_WR, 0x1e, 0x00 },
  91                 { QT1010_WR, 0x1e, 0xf0 },
  92                 { QT1010_RD, 0x24, 0xff }, /* 31 c read */
  93                 { QT1010_WR, 0x1e, 0x00 },
  94                 { QT1010_WR, 0x14, 0x7f },
  95                 { QT1010_WR, 0x15, 0x7f },
  96                 { QT1010_WR, 0x05, 0xff }, /* 35 c write */
  97                 { QT1010_WR, 0x06, 0x00 },
  98                 { QT1010_WR, 0x15, 0x1f },
  99                 { QT1010_WR, 0x16, 0xff },
 100                 { QT1010_WR, 0x18, 0xff },
 101                 { QT1010_WR, 0x1f, 0xff }, /* 40 c write */
 102                 { QT1010_WR, 0x20, 0xff }, /* 41 c write */
 103                 { QT1010_WR, 0x21, 0x53 },
 104                 { QT1010_WR, 0x25, 0xff }, /* 43 c write */
 105                 { QT1010_WR, 0x26, 0x15 },
 106                 { QT1010_WR, 0x00, 0xff }, /* 45 c write */
 107                 { QT1010_WR, 0x02, 0x00 },
 108                 { QT1010_WR, 0x01, 0x00 }
 109         };
 110
 111 #define FREQ1 32000000 /* 32 MHz */
 112 #define FREQ2  4000000 /* 4 MHz Quartz oscillator in the stick? */
 113
 114         priv = fe->tuner_priv;
 115         freq = c->frequency;
 116         div = (freq + QT1010_OFFSET) / QT1010_STEP;
 117         freq = (div * QT1010_STEP) - QT1010_OFFSET;
 118         mod1 = (freq + QT1010_OFFSET) % FREQ1;
 119         mod2 = (freq + QT1010_OFFSET) % FREQ2;
 120         priv->frequency = freq;
 121
 122         if (fe->ops.i2c_gate_ctrl)
 123                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 124
 125         /* reg 05 base value */
 126         if      (freq < 290000000) reg05 = 0x14; /* 290 MHz */
 127         else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
 128         else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
 129         else                       reg05 = 0x74;
 130
 131         /* 0x5 */
 132         rd[2].val = reg05;
 133
 134         /* 07 - set frequency: 32 MHz scale */
 135         rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
 136
 137         /* 09 - changes every 8/24 MHz */
 138         if (mod1 < 8000000) rd[6].val = 0x1d;
 139         else                rd[6].val = 0x1c;
 140
 141         /* 0a - set frequency: 4 MHz scale (max 28 MHz) */
 142         if      (mod1 < 1*FREQ2) rd[7].val = 0x09; /*  +0 MHz */
 143         else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /*  +4 MHz */
 144         else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /*  +8 MHz */
 145         else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
 146         else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
 147         else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
 148         else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
 149         else                     rd[7].val = 0x0a; /* +28 MHz */
 150
 151         /* 0b - changes every 2/2 MHz */
 152         if (mod2 < 2000000) rd[8].val = 0x45;
 153         else                rd[8].val = 0x44;
 154
 155         /* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
 156         tmpval = 0x78; /* byte, overflows intentionally */
 157         rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
 158
 159         /* 11 */
 160         rd[13].val = 0xfd; /* TODO: correct value calculation */
 161
 162         /* 12 */
 163         rd[14].val = 0x91; /* TODO: correct value calculation */
 164
 165         /* 22 */
 166         if      (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
 167         else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
 168         else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
 169         else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
 170         else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
 171         else                       rd[15].val = 0xd0;
 172
 173         /* 05 */
 174         rd[35].val = (reg05 & 0xf0);
 175
 176         /* 1f */
 177         if      (mod1 <  8000000) tmpval = 0x00;
 178         else if (mod1 < 12000000) tmpval = 0x01;
 179         else if (mod1 < 16000000) tmpval = 0x02;
 180         else if (mod1 < 24000000) tmpval = 0x03;
 181         else if (mod1 < 28000000) tmpval = 0x04;
 182         else                      tmpval = 0x05;
 183         rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
 184
 185         /* 20 */
 186         if      (mod1 <  8000000) tmpval = 0x00;
 187         else if (mod1 < 12000000) tmpval = 0x01;
 188         else if (mod1 < 20000000) tmpval = 0x02;
 189         else if (mod1 < 24000000) tmpval = 0x03;
 190         else if (mod1 < 28000000) tmpval = 0x04;
 191         else                      tmpval = 0x05;
 192         rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
 193
 194         /* 25 */
 195         rd[43].val = priv->reg25_init_val;
 196
 197         /* 00 */
 198         rd[45].val = 0x92; /* TODO: correct value calculation */
 199
 200         dev_dbg(&priv->i2c->dev,
 201                         "%s: freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \
 202                         "1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \
 203                         "20:%02x 25:%02x 00:%02x\n", __func__, \
 204                         freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \
 205                         rd[8].val, rd[10].val, rd[13].val, rd[14].val, \
 206                         rd[15].val, rd[35].val, rd[40].val, rd[41].val, \
 207                         rd[43].val, rd[45].val);
 208
 209         for (i = 0; i < ARRAY_SIZE(rd); i++) {
 210                 if (rd[i].oper == QT1010_WR) {
 211                         err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
 212                 } else { /* read is required to proper locking */
 213                         err = qt1010_readreg(priv, rd[i].reg, &tmpval);
 214                 }
 215                 if (err) return err;
 216         }
 217
 218         if (fe->ops.i2c_gate_ctrl)
 219                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 220
 221         return 0;
 222 }
 223
 224 static int qt1010_init_meas1(struct qt1010_priv *priv,
 225                              u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
 226 {
 227         u8 i, val1, uninitialized_var(val2);
 228         int err;
 229
 230         qt1010_i2c_oper_t i2c_data[] = {
 231                 { QT1010_WR, reg, reg_init_val },
 232                 { QT1010_WR, 0x1e, 0x00 },
 233                 { QT1010_WR, 0x1e, oper },
 234                 { QT1010_RD, reg, 0xff }
 235         };
 236
 237         for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
 238                 if (i2c_data[i].oper == QT1010_WR) {
 239                         err = qt1010_writereg(priv, i2c_data[i].reg,
 240                                               i2c_data[i].val);
 241                 } else {
 242                         err = qt1010_readreg(priv, i2c_data[i].reg, &val2);
 243                 }
 244                 if (err) return err;
 245         }
 246
 247         do {
 248                 val1 = val2;
 249                 err = qt1010_readreg(priv, reg, &val2);
 250                 if (err) return err;
 251                 dev_dbg(&priv->i2c->dev, "%s: compare reg:%02x %02x %02x\n",
 252                                 __func__, reg, val1, val2);
 253         } while (val1 != val2);
 254         *retval = val1;
 255
 256         return qt1010_writereg(priv, 0x1e, 0x00);
 257 }
 258
 259 static int qt1010_init_meas2(struct qt1010_priv *priv,
 260                             u8 reg_init_val, u8 *retval)
 261 {
 262         u8 i, uninitialized_var(val);
 263         int err;
 264         qt1010_i2c_oper_t i2c_data[] = {
 265                 { QT1010_WR, 0x07, reg_init_val },
 266                 { QT1010_WR, 0x22, 0xd0 },
 267                 { QT1010_WR, 0x1e, 0x00 },
 268                 { QT1010_WR, 0x1e, 0xd0 },
 269                 { QT1010_RD, 0x22, 0xff },
 270                 { QT1010_WR, 0x1e, 0x00 },
 271                 { QT1010_WR, 0x22, 0xff }
 272         };
 273         for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
 274                 if (i2c_data[i].oper == QT1010_WR) {
 275                         err = qt1010_writereg(priv, i2c_data[i].reg,
 276                                               i2c_data[i].val);
 277                 } else {
 278                         err = qt1010_readreg(priv, i2c_data[i].reg, &val);
 279                 }
 280                 if (err) return err;
 281         }
 282         *retval = val;
 283         return 0;
 284 }
 285
 286 static int qt1010_init(struct dvb_frontend *fe)
 287 {
 288         struct qt1010_priv *priv = fe->tuner_priv;
 289         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 290         int err = 0;
 291         u8 i, tmpval, *valptr = NULL;
 292
 293         static const qt1010_i2c_oper_t i2c_data[] = {
 294                 { QT1010_WR, 0x01, 0x80 },
 295                 { QT1010_WR, 0x0d, 0x84 },
 296                 { QT1010_WR, 0x0e, 0xb7 },
 297                 { QT1010_WR, 0x2a, 0x23 },
 298                 { QT1010_WR, 0x2c, 0xdc },
 299                 { QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
 300                 { QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
 301                 { QT1010_WR, 0x2b, 0x70 },
 302                 { QT1010_WR, 0x2a, 0x23 },
 303                 { QT1010_M1, 0x26, 0x08 },
 304                 { QT1010_M1, 0x82, 0xff },
 305                 { QT1010_WR, 0x05, 0x14 },
 306                 { QT1010_WR, 0x06, 0x44 },
 307                 { QT1010_WR, 0x07, 0x28 },
 308                 { QT1010_WR, 0x08, 0x0b },
 309                 { QT1010_WR, 0x11, 0xfd },
 310                 { QT1010_M1, 0x22, 0x0d },
 311                 { QT1010_M1, 0xd0, 0xff },
 312                 { QT1010_WR, 0x06, 0x40 },
 313                 { QT1010_WR, 0x16, 0xf0 },
 314                 { QT1010_WR, 0x02, 0x38 },
 315                 { QT1010_WR, 0x03, 0x18 },
 316                 { QT1010_WR, 0x20, 0xe0 },
 317                 { QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
 318                 { QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
 319                 { QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
 320                 { QT1010_WR, 0x03, 0x19 },
 321                 { QT1010_WR, 0x02, 0x3f },
 322                 { QT1010_WR, 0x21, 0x53 },
 323                 { QT1010_RD, 0x21, 0xff },
 324                 { QT1010_WR, 0x11, 0xfd },
 325                 { QT1010_WR, 0x05, 0x34 },
 326                 { QT1010_WR, 0x06, 0x44 },
 327                 { QT1010_WR, 0x08, 0x08 }
 328         };
 329
 330         if (fe->ops.i2c_gate_ctrl)
 331                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 332
 333         for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
 334                 switch (i2c_data[i].oper) {
 335                 case QT1010_WR:
 336                         err = qt1010_writereg(priv, i2c_data[i].reg,
 337                                               i2c_data[i].val);
 338                         break;
 339                 case QT1010_RD:
 340                         if (i2c_data[i].val == 0x20)
 341                                 valptr = &priv->reg20_init_val;
 342                         else
 343                                 valptr = &tmpval;
 344                         err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
 345                         break;
 346                 case QT1010_M1:
 347                         if (i2c_data[i].val == 0x25)
 348                                 valptr = &priv->reg25_init_val;
 349                         else if (i2c_data[i].val == 0x1f)
 350                                 valptr = &priv->reg1f_init_val;
 351                         else
 352                                 valptr = &tmpval;
 353
 354                         BUG_ON(i >= ARRAY_SIZE(i2c_data) - 1);
 355
 356                         err = qt1010_init_meas1(priv, i2c_data[i+1].reg,
 357                                                 i2c_data[i].reg,
 358                                                 i2c_data[i].val, valptr);
 359                         i++;
 360                         break;
 361                 }
 362                 if (err)
 363                         return err;
 364         }
 365
 366         for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
 367                 if ((err = qt1010_init_meas2(priv, i, &tmpval)))
 368                         return err;
 369
 370         if (!c->frequency)
 371                 c->frequency = 545000000; /* Sigmatek DVB-110 545000000 */
 372                                       /* MSI Megasky 580 GL861 533000000 */
 373         return qt1010_set_params(fe);
 374 }
 375
 376 static void qt1010_release(struct dvb_frontend *fe)
 377 {
 378         kfree(fe->tuner_priv);
 379         fe->tuner_priv = NULL;
 380 }
 381
 382 static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 383 {
 384         struct qt1010_priv *priv = fe->tuner_priv;
 385         *frequency = priv->frequency;
 386         return 0;
 387 }
 388
 389 static int qt1010_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
 390 {
 391         *frequency = 36125000;
 392         return 0;
 393 }
 394
 395 static const struct dvb_tuner_ops qt1010_tuner_ops = {
 396         .info = {
 397                 .name              = "Quantek QT1010",
 398                 .frequency_min_hz  = QT1010_MIN_FREQ,
 399                 .frequency_max_hz  = QT1010_MAX_FREQ,
 400                 .frequency_step_hz = QT1010_STEP,
 401         },
 402
 403         .release       = qt1010_release,
 404         .init          = qt1010_init,
 405         /* TODO: implement sleep */
 406
 407         .set_params    = qt1010_set_params,
 408         .get_frequency = qt1010_get_frequency,
 409         .get_if_frequency = qt1010_get_if_frequency,
 410 };
 411
 412 struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
 413                                     struct i2c_adapter *i2c,
 414                                     struct qt1010_config *cfg)
 415 {
 416         struct qt1010_priv *priv = NULL;
 417         u8 id;
 418
 419         priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
 420         if (priv == NULL)
 421                 return NULL;
 422
 423         priv->cfg = cfg;
 424         priv->i2c = i2c;
 425
 426         if (fe->ops.i2c_gate_ctrl)
 427                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 428
 429
 430         /* Try to detect tuner chip. Probably this is not correct register. */
 431         if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
 432                 kfree(priv);
 433                 return NULL;
 434         }
 435
 436         if (fe->ops.i2c_gate_ctrl)
 437                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 438
 439         dev_info(&priv->i2c->dev,
 440                         "%s: Quantek QT1010 successfully identified\n",
 441                         KBUILD_MODNAME);
 442
 443         memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops,
 444                sizeof(struct dvb_tuner_ops));
 445
 446         fe->tuner_priv = priv;
 447         return fe;
 448 }
 449 EXPORT_SYMBOL(qt1010_attach);
 450
 451 MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
 452 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
 453 MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
 454 MODULE_VERSION("0.1");
 455 MODULE_LICENSE("GPL");