[media] media: videobuf2: Restructure vb2_buffer
[sfrench/cifs-2.6.git] / drivers / media / platform / soc_camera / mx2_camera.c
1 /*
2  * V4L2 Driver for i.MX27 camera host
3  *
4  * Copyright (C) 2008, Sascha Hauer, Pengutronix
5  * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6  * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
26 #include <linux/mm.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-dev.h>
35 #include <media/videobuf2-v4l2.h>
36 #include <media/videobuf2-dma-contig.h>
37 #include <media/soc_camera.h>
38 #include <media/soc_mediabus.h>
39
40 #include <linux/videodev2.h>
41
42 #include <linux/platform_data/camera-mx2.h>
43
44 #include <asm/dma.h>
45
46 #define MX2_CAM_DRV_NAME "mx2-camera"
47 #define MX2_CAM_VERSION "0.0.6"
48 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
49
50 /* reset values */
51 #define CSICR1_RESET_VAL        0x40000800
52 #define CSICR2_RESET_VAL        0x0
53 #define CSICR3_RESET_VAL        0x0
54
55 /* csi control reg 1 */
56 #define CSICR1_SWAP16_EN        (1 << 31)
57 #define CSICR1_EXT_VSYNC        (1 << 30)
58 #define CSICR1_EOF_INTEN        (1 << 29)
59 #define CSICR1_PRP_IF_EN        (1 << 28)
60 #define CSICR1_CCIR_MODE        (1 << 27)
61 #define CSICR1_COF_INTEN        (1 << 26)
62 #define CSICR1_SF_OR_INTEN      (1 << 25)
63 #define CSICR1_RF_OR_INTEN      (1 << 24)
64 #define CSICR1_STATFF_LEVEL     (3 << 22)
65 #define CSICR1_STATFF_INTEN     (1 << 21)
66 #define CSICR1_RXFF_LEVEL(l)    (((l) & 3) << 19)
67 #define CSICR1_RXFF_INTEN       (1 << 18)
68 #define CSICR1_SOF_POL          (1 << 17)
69 #define CSICR1_SOF_INTEN        (1 << 16)
70 #define CSICR1_MCLKDIV(d)       (((d) & 0xF) << 12)
71 #define CSICR1_HSYNC_POL        (1 << 11)
72 #define CSICR1_CCIR_EN          (1 << 10)
73 #define CSICR1_MCLKEN           (1 << 9)
74 #define CSICR1_FCC              (1 << 8)
75 #define CSICR1_PACK_DIR         (1 << 7)
76 #define CSICR1_CLR_STATFIFO     (1 << 6)
77 #define CSICR1_CLR_RXFIFO       (1 << 5)
78 #define CSICR1_GCLK_MODE        (1 << 4)
79 #define CSICR1_INV_DATA         (1 << 3)
80 #define CSICR1_INV_PCLK         (1 << 2)
81 #define CSICR1_REDGE            (1 << 1)
82 #define CSICR1_FMT_MASK         (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
83
84 #define SHIFT_STATFF_LEVEL      22
85 #define SHIFT_RXFF_LEVEL        19
86 #define SHIFT_MCLKDIV           12
87
88 #define SHIFT_FRMCNT            16
89
90 #define CSICR1                  0x00
91 #define CSICR2                  0x04
92 #define CSISR                   0x08
93 #define CSISTATFIFO             0x0c
94 #define CSIRFIFO                0x10
95 #define CSIRXCNT                0x14
96 #define CSICR3                  0x1c
97 #define CSIDMASA_STATFIFO       0x20
98 #define CSIDMATA_STATFIFO       0x24
99 #define CSIDMASA_FB1            0x28
100 #define CSIDMASA_FB2            0x2c
101 #define CSIFBUF_PARA            0x30
102 #define CSIIMAG_PARA            0x34
103
104 /* EMMA PrP */
105 #define PRP_CNTL                        0x00
106 #define PRP_INTR_CNTL                   0x04
107 #define PRP_INTRSTATUS                  0x08
108 #define PRP_SOURCE_Y_PTR                0x0c
109 #define PRP_SOURCE_CB_PTR               0x10
110 #define PRP_SOURCE_CR_PTR               0x14
111 #define PRP_DEST_RGB1_PTR               0x18
112 #define PRP_DEST_RGB2_PTR               0x1c
113 #define PRP_DEST_Y_PTR                  0x20
114 #define PRP_DEST_CB_PTR                 0x24
115 #define PRP_DEST_CR_PTR                 0x28
116 #define PRP_SRC_FRAME_SIZE              0x2c
117 #define PRP_DEST_CH1_LINE_STRIDE        0x30
118 #define PRP_SRC_PIXEL_FORMAT_CNTL       0x34
119 #define PRP_CH1_PIXEL_FORMAT_CNTL       0x38
120 #define PRP_CH1_OUT_IMAGE_SIZE          0x3c
121 #define PRP_CH2_OUT_IMAGE_SIZE          0x40
122 #define PRP_SRC_LINE_STRIDE             0x44
123 #define PRP_CSC_COEF_012                0x48
124 #define PRP_CSC_COEF_345                0x4c
125 #define PRP_CSC_COEF_678                0x50
126 #define PRP_CH1_RZ_HORI_COEF1           0x54
127 #define PRP_CH1_RZ_HORI_COEF2           0x58
128 #define PRP_CH1_RZ_HORI_VALID           0x5c
129 #define PRP_CH1_RZ_VERT_COEF1           0x60
130 #define PRP_CH1_RZ_VERT_COEF2           0x64
131 #define PRP_CH1_RZ_VERT_VALID           0x68
132 #define PRP_CH2_RZ_HORI_COEF1           0x6c
133 #define PRP_CH2_RZ_HORI_COEF2           0x70
134 #define PRP_CH2_RZ_HORI_VALID           0x74
135 #define PRP_CH2_RZ_VERT_COEF1           0x78
136 #define PRP_CH2_RZ_VERT_COEF2           0x7c
137 #define PRP_CH2_RZ_VERT_VALID           0x80
138
139 #define PRP_CNTL_CH1EN          (1 << 0)
140 #define PRP_CNTL_CH2EN          (1 << 1)
141 #define PRP_CNTL_CSIEN          (1 << 2)
142 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
143 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
144 #define PRP_CNTL_DATA_IN_RGB16  (2 << 3)
145 #define PRP_CNTL_DATA_IN_RGB32  (3 << 3)
146 #define PRP_CNTL_CH1_OUT_RGB8   (0 << 5)
147 #define PRP_CNTL_CH1_OUT_RGB16  (1 << 5)
148 #define PRP_CNTL_CH1_OUT_RGB32  (2 << 5)
149 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
150 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
151 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
152 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
153 #define PRP_CNTL_CH1_LEN        (1 << 9)
154 #define PRP_CNTL_CH2_LEN        (1 << 10)
155 #define PRP_CNTL_SKIP_FRAME     (1 << 11)
156 #define PRP_CNTL_SWRST          (1 << 12)
157 #define PRP_CNTL_CLKEN          (1 << 13)
158 #define PRP_CNTL_WEN            (1 << 14)
159 #define PRP_CNTL_CH1BYP         (1 << 15)
160 #define PRP_CNTL_IN_TSKIP(x)    ((x) << 16)
161 #define PRP_CNTL_CH1_TSKIP(x)   ((x) << 19)
162 #define PRP_CNTL_CH2_TSKIP(x)   ((x) << 22)
163 #define PRP_CNTL_INPUT_FIFO_LEVEL(x)    ((x) << 25)
164 #define PRP_CNTL_RZ_FIFO_LEVEL(x)       ((x) << 27)
165 #define PRP_CNTL_CH2B1EN        (1 << 29)
166 #define PRP_CNTL_CH2B2EN        (1 << 30)
167 #define PRP_CNTL_CH2FEN         (1 << 31)
168
169 /* IRQ Enable and status register */
170 #define PRP_INTR_RDERR          (1 << 0)
171 #define PRP_INTR_CH1WERR        (1 << 1)
172 #define PRP_INTR_CH2WERR        (1 << 2)
173 #define PRP_INTR_CH1FC          (1 << 3)
174 #define PRP_INTR_CH2FC          (1 << 5)
175 #define PRP_INTR_LBOVF          (1 << 7)
176 #define PRP_INTR_CH2OVF         (1 << 8)
177
178 /* Resizing registers */
179 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
180 #define PRP_RZ_VALID_BILINEAR   (1 << 31)
181
182 #define MAX_VIDEO_MEM   16
183
184 #define RESIZE_NUM_MIN  1
185 #define RESIZE_NUM_MAX  20
186 #define BC_COEF         3
187 #define SZ_COEF         (1 << BC_COEF)
188
189 #define RESIZE_DIR_H    0
190 #define RESIZE_DIR_V    1
191
192 #define RESIZE_ALGO_BILINEAR 0
193 #define RESIZE_ALGO_AVERAGING 1
194
195 struct mx2_prp_cfg {
196         int channel;
197         u32 in_fmt;
198         u32 out_fmt;
199         u32 src_pixel;
200         u32 ch1_pixel;
201         u32 irq_flags;
202         u32 csicr1;
203 };
204
205 /* prp resizing parameters */
206 struct emma_prp_resize {
207         int             algo; /* type of algorithm used */
208         int             len; /* number of coefficients */
209         unsigned char   s[RESIZE_NUM_MAX]; /* table of coefficients */
210 };
211
212 /* prp configuration for a client-host fmt pair */
213 struct mx2_fmt_cfg {
214         u32     in_fmt;
215         u32                             out_fmt;
216         struct mx2_prp_cfg              cfg;
217 };
218
219 struct mx2_buf_internal {
220         struct list_head        queue;
221         int                     bufnum;
222         bool                    discard;
223 };
224
225 /* buffer for one video frame */
226 struct mx2_buffer {
227         /* common v4l buffer stuff -- must be first */
228         struct vb2_v4l2_buffer vb;
229         struct mx2_buf_internal         internal;
230 };
231
232 enum mx2_camera_type {
233         IMX27_CAMERA,
234 };
235
236 struct mx2_camera_dev {
237         struct device           *dev;
238         struct soc_camera_host  soc_host;
239         struct clk              *clk_emma_ahb, *clk_emma_ipg;
240         struct clk              *clk_csi_ahb, *clk_csi_per;
241
242         void __iomem            *base_csi, *base_emma;
243
244         struct mx2_camera_platform_data *pdata;
245         unsigned long           platform_flags;
246
247         struct list_head        capture;
248         struct list_head        active_bufs;
249         struct list_head        discard;
250
251         spinlock_t              lock;
252
253         int                     dma;
254         struct mx2_buffer       *active;
255         struct mx2_buffer       *fb1_active;
256         struct mx2_buffer       *fb2_active;
257
258         u32                     csicr1;
259         enum mx2_camera_type    devtype;
260
261         struct mx2_buf_internal buf_discard[2];
262         void                    *discard_buffer;
263         dma_addr_t              discard_buffer_dma;
264         size_t                  discard_size;
265         struct mx2_fmt_cfg      *emma_prp;
266         struct emma_prp_resize  resizing[2];
267         unsigned int            s_width, s_height;
268         u32                     frame_count;
269         struct vb2_alloc_ctx    *alloc_ctx;
270 };
271
272 static struct platform_device_id mx2_camera_devtype[] = {
273         {
274                 .name = "imx27-camera",
275                 .driver_data = IMX27_CAMERA,
276         }, {
277                 /* sentinel */
278         }
279 };
280 MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
281
282 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
283 {
284         return container_of(int_buf, struct mx2_buffer, internal);
285 }
286
287 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
288         /*
289          * This is a generic configuration which is valid for most
290          * prp input-output format combinations.
291          * We set the incoming and outgoing pixelformat to a
292          * 16 Bit wide format and adjust the bytesperline
293          * accordingly. With this configuration the inputdata
294          * will not be changed by the emma and could be any type
295          * of 16 Bit Pixelformat.
296          */
297         {
298                 .in_fmt         = 0,
299                 .out_fmt        = 0,
300                 .cfg            = {
301                         .channel        = 1,
302                         .in_fmt         = PRP_CNTL_DATA_IN_RGB16,
303                         .out_fmt        = PRP_CNTL_CH1_OUT_RGB16,
304                         .src_pixel      = 0x2ca00565, /* RGB565 */
305                         .ch1_pixel      = 0x2ca00565, /* RGB565 */
306                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
307                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
308                         .csicr1         = 0,
309                 }
310         },
311         {
312                 .in_fmt         = MEDIA_BUS_FMT_UYVY8_2X8,
313                 .out_fmt        = V4L2_PIX_FMT_YUYV,
314                 .cfg            = {
315                         .channel        = 1,
316                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
317                         .out_fmt        = PRP_CNTL_CH1_OUT_YUV422,
318                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
319                         .ch1_pixel      = 0x62000888, /* YUV422 (YUYV) */
320                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
321                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
322                         .csicr1         = CSICR1_SWAP16_EN,
323                 }
324         },
325         {
326                 .in_fmt         = MEDIA_BUS_FMT_YUYV8_2X8,
327                 .out_fmt        = V4L2_PIX_FMT_YUYV,
328                 .cfg            = {
329                         .channel        = 1,
330                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
331                         .out_fmt        = PRP_CNTL_CH1_OUT_YUV422,
332                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
333                         .ch1_pixel      = 0x62000888, /* YUV422 (YUYV) */
334                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
335                                                 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
336                         .csicr1         = CSICR1_PACK_DIR,
337                 }
338         },
339         {
340                 .in_fmt         = MEDIA_BUS_FMT_YUYV8_2X8,
341                 .out_fmt        = V4L2_PIX_FMT_YUV420,
342                 .cfg            = {
343                         .channel        = 2,
344                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
345                         .out_fmt        = PRP_CNTL_CH2_OUT_YUV420,
346                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
347                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
348                                         PRP_INTR_CH2FC | PRP_INTR_LBOVF |
349                                         PRP_INTR_CH2OVF,
350                         .csicr1         = CSICR1_PACK_DIR,
351                 }
352         },
353         {
354                 .in_fmt         = MEDIA_BUS_FMT_UYVY8_2X8,
355                 .out_fmt        = V4L2_PIX_FMT_YUV420,
356                 .cfg            = {
357                         .channel        = 2,
358                         .in_fmt         = PRP_CNTL_DATA_IN_YUV422,
359                         .out_fmt        = PRP_CNTL_CH2_OUT_YUV420,
360                         .src_pixel      = 0x22000888, /* YUV422 (YUYV) */
361                         .irq_flags      = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
362                                         PRP_INTR_CH2FC | PRP_INTR_LBOVF |
363                                         PRP_INTR_CH2OVF,
364                         .csicr1         = CSICR1_SWAP16_EN,
365                 }
366         },
367 };
368
369 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(u32 in_fmt, u32 out_fmt)
370 {
371         int i;
372
373         for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
374                 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
375                                 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
376                         return &mx27_emma_prp_table[i];
377                 }
378         /* If no match return the most generic configuration */
379         return &mx27_emma_prp_table[0];
380 };
381
382 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
383                                  unsigned long phys, int bufnum)
384 {
385         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
386
387         if (prp->cfg.channel == 1) {
388                 writel(phys, pcdev->base_emma +
389                                 PRP_DEST_RGB1_PTR + 4 * bufnum);
390         } else {
391                 writel(phys, pcdev->base_emma +
392                         PRP_DEST_Y_PTR - 0x14 * bufnum);
393                 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
394                         u32 imgsize = pcdev->soc_host.icd->user_height *
395                                         pcdev->soc_host.icd->user_width;
396
397                         writel(phys + imgsize, pcdev->base_emma +
398                                 PRP_DEST_CB_PTR - 0x14 * bufnum);
399                         writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
400                                 PRP_DEST_CR_PTR - 0x14 * bufnum);
401                 }
402         }
403 }
404
405 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
406 {
407         clk_disable_unprepare(pcdev->clk_csi_ahb);
408         clk_disable_unprepare(pcdev->clk_csi_per);
409         writel(0, pcdev->base_csi + CSICR1);
410         writel(0, pcdev->base_emma + PRP_CNTL);
411 }
412
413 static int mx2_camera_add_device(struct soc_camera_device *icd)
414 {
415         dev_info(icd->parent, "Camera driver attached to camera %d\n",
416                  icd->devnum);
417
418         return 0;
419 }
420
421 static void mx2_camera_remove_device(struct soc_camera_device *icd)
422 {
423         dev_info(icd->parent, "Camera driver detached from camera %d\n",
424                  icd->devnum);
425 }
426
427 /*
428  * The following two functions absolutely depend on the fact, that
429  * there can be only one camera on mx2 camera sensor interface
430  */
431 static int mx2_camera_clock_start(struct soc_camera_host *ici)
432 {
433         struct mx2_camera_dev *pcdev = ici->priv;
434         int ret;
435         u32 csicr1;
436
437         ret = clk_prepare_enable(pcdev->clk_csi_ahb);
438         if (ret < 0)
439                 return ret;
440
441         ret = clk_prepare_enable(pcdev->clk_csi_per);
442         if (ret < 0)
443                 goto exit_csi_ahb;
444
445         csicr1 = CSICR1_MCLKEN | CSICR1_PRP_IF_EN | CSICR1_FCC |
446                 CSICR1_RXFF_LEVEL(0);
447
448         pcdev->csicr1 = csicr1;
449         writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
450
451         pcdev->frame_count = 0;
452
453         return 0;
454
455 exit_csi_ahb:
456         clk_disable_unprepare(pcdev->clk_csi_ahb);
457
458         return ret;
459 }
460
461 static void mx2_camera_clock_stop(struct soc_camera_host *ici)
462 {
463         struct mx2_camera_dev *pcdev = ici->priv;
464
465         mx2_camera_deactivate(pcdev);
466 }
467
468 /*
469  *  Videobuf operations
470  */
471 static int mx2_videobuf_setup(struct vb2_queue *vq,
472                         const struct v4l2_format *fmt,
473                         unsigned int *count, unsigned int *num_planes,
474                         unsigned int sizes[], void *alloc_ctxs[])
475 {
476         struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
477         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
478         struct mx2_camera_dev *pcdev = ici->priv;
479
480         dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
481
482         /* TODO: support for VIDIOC_CREATE_BUFS not ready */
483         if (fmt != NULL)
484                 return -ENOTTY;
485
486         alloc_ctxs[0] = pcdev->alloc_ctx;
487
488         sizes[0] = icd->sizeimage;
489
490         if (0 == *count)
491                 *count = 32;
492         if (!*num_planes &&
493             sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
494                 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
495
496         *num_planes = 1;
497
498         return 0;
499 }
500
501 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
502 {
503         struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
504         int ret = 0;
505
506         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
507                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
508
509 #ifdef DEBUG
510         /*
511          * This can be useful if you want to see if we actually fill
512          * the buffer with something
513          */
514         memset((void *)vb2_plane_vaddr(vb, 0),
515                0xaa, vb2_get_plane_payload(vb, 0));
516 #endif
517
518         vb2_set_plane_payload(vb, 0, icd->sizeimage);
519         if (vb2_plane_vaddr(vb, 0) &&
520             vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
521                 ret = -EINVAL;
522                 goto out;
523         }
524
525         return 0;
526
527 out:
528         return ret;
529 }
530
531 static void mx2_videobuf_queue(struct vb2_buffer *vb)
532 {
533         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
534         struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
535         struct soc_camera_host *ici =
536                 to_soc_camera_host(icd->parent);
537         struct mx2_camera_dev *pcdev = ici->priv;
538         struct mx2_buffer *buf = container_of(vbuf, struct mx2_buffer, vb);
539         unsigned long flags;
540
541         dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
542                 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
543
544         spin_lock_irqsave(&pcdev->lock, flags);
545
546         list_add_tail(&buf->internal.queue, &pcdev->capture);
547
548         spin_unlock_irqrestore(&pcdev->lock, flags);
549 }
550
551 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
552                 int bytesperline)
553 {
554         struct soc_camera_host *ici =
555                 to_soc_camera_host(icd->parent);
556         struct mx2_camera_dev *pcdev = ici->priv;
557         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
558
559         writel((pcdev->s_width << 16) | pcdev->s_height,
560                pcdev->base_emma + PRP_SRC_FRAME_SIZE);
561         writel(prp->cfg.src_pixel,
562                pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
563         if (prp->cfg.channel == 1) {
564                 writel((icd->user_width << 16) | icd->user_height,
565                         pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
566                 writel(bytesperline,
567                         pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
568                 writel(prp->cfg.ch1_pixel,
569                         pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
570         } else { /* channel 2 */
571                 writel((icd->user_width << 16) | icd->user_height,
572                         pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
573         }
574
575         /* Enable interrupts */
576         writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
577 }
578
579 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
580 {
581         int dir;
582
583         for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
584                 unsigned char *s = pcdev->resizing[dir].s;
585                 int len = pcdev->resizing[dir].len;
586                 unsigned int coeff[2] = {0, 0};
587                 unsigned int valid  = 0;
588                 int i;
589
590                 if (len == 0)
591                         continue;
592
593                 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
594                         int j;
595
596                         j = i > 9 ? 1 : 0;
597                         coeff[j] = (coeff[j] << BC_COEF) |
598                                         (s[i] & (SZ_COEF - 1));
599
600                         if (i == 5 || i == 15)
601                                 coeff[j] <<= 1;
602
603                         valid = (valid << 1) | (s[i] >> BC_COEF);
604                 }
605
606                 valid |= PRP_RZ_VALID_TBL_LEN(len);
607
608                 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
609                         valid |= PRP_RZ_VALID_BILINEAR;
610
611                 if (pcdev->emma_prp->cfg.channel == 1) {
612                         if (dir == RESIZE_DIR_H) {
613                                 writel(coeff[0], pcdev->base_emma +
614                                                         PRP_CH1_RZ_HORI_COEF1);
615                                 writel(coeff[1], pcdev->base_emma +
616                                                         PRP_CH1_RZ_HORI_COEF2);
617                                 writel(valid, pcdev->base_emma +
618                                                         PRP_CH1_RZ_HORI_VALID);
619                         } else {
620                                 writel(coeff[0], pcdev->base_emma +
621                                                         PRP_CH1_RZ_VERT_COEF1);
622                                 writel(coeff[1], pcdev->base_emma +
623                                                         PRP_CH1_RZ_VERT_COEF2);
624                                 writel(valid, pcdev->base_emma +
625                                                         PRP_CH1_RZ_VERT_VALID);
626                         }
627                 } else {
628                         if (dir == RESIZE_DIR_H) {
629                                 writel(coeff[0], pcdev->base_emma +
630                                                         PRP_CH2_RZ_HORI_COEF1);
631                                 writel(coeff[1], pcdev->base_emma +
632                                                         PRP_CH2_RZ_HORI_COEF2);
633                                 writel(valid, pcdev->base_emma +
634                                                         PRP_CH2_RZ_HORI_VALID);
635                         } else {
636                                 writel(coeff[0], pcdev->base_emma +
637                                                         PRP_CH2_RZ_VERT_COEF1);
638                                 writel(coeff[1], pcdev->base_emma +
639                                                         PRP_CH2_RZ_VERT_COEF2);
640                                 writel(valid, pcdev->base_emma +
641                                                         PRP_CH2_RZ_VERT_VALID);
642                         }
643                 }
644         }
645 }
646
647 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
648 {
649         struct soc_camera_device *icd = soc_camera_from_vb2q(q);
650         struct soc_camera_host *ici =
651                 to_soc_camera_host(icd->parent);
652         struct mx2_camera_dev *pcdev = ici->priv;
653         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
654         struct vb2_buffer *vb;
655         struct mx2_buffer *buf;
656         unsigned long phys;
657         int bytesperline;
658         unsigned long flags;
659
660         if (count < 2)
661                 return -ENOBUFS;
662
663         spin_lock_irqsave(&pcdev->lock, flags);
664
665         buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
666                                internal.queue);
667         buf->internal.bufnum = 0;
668         vb = &buf->vb.vb2_buf;
669
670         phys = vb2_dma_contig_plane_dma_addr(vb, 0);
671         mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
672         list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
673
674         buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
675                                internal.queue);
676         buf->internal.bufnum = 1;
677         vb = &buf->vb.vb2_buf;
678
679         phys = vb2_dma_contig_plane_dma_addr(vb, 0);
680         mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
681         list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
682
683         bytesperline = soc_mbus_bytes_per_line(icd->user_width,
684                                                icd->current_fmt->host_fmt);
685         if (bytesperline < 0) {
686                 spin_unlock_irqrestore(&pcdev->lock, flags);
687                 return bytesperline;
688         }
689
690         /*
691          * I didn't manage to properly enable/disable the prp
692          * on a per frame basis during running transfers,
693          * thus we allocate a buffer here and use it to
694          * discard frames when no buffer is available.
695          * Feel free to work on this ;)
696          */
697         pcdev->discard_size = icd->user_height * bytesperline;
698         pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
699                                         pcdev->discard_size,
700                                         &pcdev->discard_buffer_dma, GFP_ATOMIC);
701         if (!pcdev->discard_buffer) {
702                 spin_unlock_irqrestore(&pcdev->lock, flags);
703                 return -ENOMEM;
704         }
705
706         pcdev->buf_discard[0].discard = true;
707         list_add_tail(&pcdev->buf_discard[0].queue,
708                       &pcdev->discard);
709
710         pcdev->buf_discard[1].discard = true;
711         list_add_tail(&pcdev->buf_discard[1].queue,
712                       &pcdev->discard);
713
714         mx2_prp_resize_commit(pcdev);
715
716         mx27_camera_emma_buf_init(icd, bytesperline);
717
718         if (prp->cfg.channel == 1) {
719                 writel(PRP_CNTL_CH1EN |
720                        PRP_CNTL_CSIEN |
721                        prp->cfg.in_fmt |
722                        prp->cfg.out_fmt |
723                        PRP_CNTL_CH1_LEN |
724                        PRP_CNTL_CH1BYP |
725                        PRP_CNTL_CH1_TSKIP(0) |
726                        PRP_CNTL_IN_TSKIP(0),
727                        pcdev->base_emma + PRP_CNTL);
728         } else {
729                 writel(PRP_CNTL_CH2EN |
730                        PRP_CNTL_CSIEN |
731                        prp->cfg.in_fmt |
732                        prp->cfg.out_fmt |
733                        PRP_CNTL_CH2_LEN |
734                        PRP_CNTL_CH2_TSKIP(0) |
735                        PRP_CNTL_IN_TSKIP(0),
736                        pcdev->base_emma + PRP_CNTL);
737         }
738         spin_unlock_irqrestore(&pcdev->lock, flags);
739
740         return 0;
741 }
742
743 static void mx2_stop_streaming(struct vb2_queue *q)
744 {
745         struct soc_camera_device *icd = soc_camera_from_vb2q(q);
746         struct soc_camera_host *ici =
747                 to_soc_camera_host(icd->parent);
748         struct mx2_camera_dev *pcdev = ici->priv;
749         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
750         unsigned long flags;
751         void *b;
752         u32 cntl;
753
754         spin_lock_irqsave(&pcdev->lock, flags);
755
756         cntl = readl(pcdev->base_emma + PRP_CNTL);
757         if (prp->cfg.channel == 1) {
758                 writel(cntl & ~PRP_CNTL_CH1EN,
759                        pcdev->base_emma + PRP_CNTL);
760         } else {
761                 writel(cntl & ~PRP_CNTL_CH2EN,
762                        pcdev->base_emma + PRP_CNTL);
763         }
764         INIT_LIST_HEAD(&pcdev->capture);
765         INIT_LIST_HEAD(&pcdev->active_bufs);
766         INIT_LIST_HEAD(&pcdev->discard);
767
768         b = pcdev->discard_buffer;
769         pcdev->discard_buffer = NULL;
770
771         spin_unlock_irqrestore(&pcdev->lock, flags);
772
773         dma_free_coherent(ici->v4l2_dev.dev,
774                           pcdev->discard_size, b, pcdev->discard_buffer_dma);
775 }
776
777 static struct vb2_ops mx2_videobuf_ops = {
778         .queue_setup     = mx2_videobuf_setup,
779         .buf_prepare     = mx2_videobuf_prepare,
780         .buf_queue       = mx2_videobuf_queue,
781         .start_streaming = mx2_start_streaming,
782         .stop_streaming  = mx2_stop_streaming,
783 };
784
785 static int mx2_camera_init_videobuf(struct vb2_queue *q,
786                               struct soc_camera_device *icd)
787 {
788         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
789         q->io_modes = VB2_MMAP | VB2_USERPTR;
790         q->drv_priv = icd;
791         q->ops = &mx2_videobuf_ops;
792         q->mem_ops = &vb2_dma_contig_memops;
793         q->buf_struct_size = sizeof(struct mx2_buffer);
794         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
795
796         return vb2_queue_init(q);
797 }
798
799 #define MX2_BUS_FLAGS   (V4L2_MBUS_MASTER | \
800                         V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
801                         V4L2_MBUS_VSYNC_ACTIVE_LOW | \
802                         V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
803                         V4L2_MBUS_HSYNC_ACTIVE_LOW | \
804                         V4L2_MBUS_PCLK_SAMPLE_RISING | \
805                         V4L2_MBUS_PCLK_SAMPLE_FALLING | \
806                         V4L2_MBUS_DATA_ACTIVE_HIGH | \
807                         V4L2_MBUS_DATA_ACTIVE_LOW)
808
809 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
810 {
811         int count = 0;
812
813         readl(pcdev->base_emma + PRP_CNTL);
814         writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
815         while (count++ < 100) {
816                 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
817                         return 0;
818                 barrier();
819                 udelay(1);
820         }
821
822         return -ETIMEDOUT;
823 }
824
825 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
826 {
827         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
828         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
829         struct mx2_camera_dev *pcdev = ici->priv;
830         struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
831         unsigned long common_flags;
832         int ret;
833         int bytesperline;
834         u32 csicr1 = pcdev->csicr1;
835
836         ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
837         if (!ret) {
838                 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
839                 if (!common_flags) {
840                         dev_warn(icd->parent,
841                                  "Flags incompatible: camera 0x%x, host 0x%x\n",
842                                  cfg.flags, MX2_BUS_FLAGS);
843                         return -EINVAL;
844                 }
845         } else if (ret != -ENOIOCTLCMD) {
846                 return ret;
847         } else {
848                 common_flags = MX2_BUS_FLAGS;
849         }
850
851         if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
852             (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
853                 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
854                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
855                 else
856                         common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
857         }
858
859         if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
860             (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
861                 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
862                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
863                 else
864                         common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
865         }
866
867         cfg.flags = common_flags;
868         ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
869         if (ret < 0 && ret != -ENOIOCTLCMD) {
870                 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
871                         common_flags, ret);
872                 return ret;
873         }
874
875         csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
876
877         if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
878                 csicr1 |= CSICR1_REDGE;
879         if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
880                 csicr1 |= CSICR1_SOF_POL;
881         if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
882                 csicr1 |= CSICR1_HSYNC_POL;
883         if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
884                 csicr1 |= CSICR1_EXT_VSYNC;
885         if (pcdev->platform_flags & MX2_CAMERA_CCIR)
886                 csicr1 |= CSICR1_CCIR_EN;
887         if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
888                 csicr1 |= CSICR1_CCIR_MODE;
889         if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
890                 csicr1 |= CSICR1_GCLK_MODE;
891         if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
892                 csicr1 |= CSICR1_INV_DATA;
893
894         pcdev->csicr1 = csicr1;
895
896         bytesperline = soc_mbus_bytes_per_line(icd->user_width,
897                         icd->current_fmt->host_fmt);
898         if (bytesperline < 0)
899                 return bytesperline;
900
901         ret = mx27_camera_emma_prp_reset(pcdev);
902         if (ret)
903                 return ret;
904
905         writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
906
907         return 0;
908 }
909
910 static int mx2_camera_set_crop(struct soc_camera_device *icd,
911                                 const struct v4l2_crop *a)
912 {
913         struct v4l2_crop a_writable = *a;
914         struct v4l2_rect *rect = &a_writable.c;
915         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
916         struct v4l2_subdev_format fmt = {
917                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
918         };
919         struct v4l2_mbus_framefmt *mf = &fmt.format;
920         int ret;
921
922         soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
923         soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
924
925         ret = v4l2_subdev_call(sd, video, s_crop, a);
926         if (ret < 0)
927                 return ret;
928
929         /* The capture device might have changed its output  */
930         ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
931         if (ret < 0)
932                 return ret;
933
934         dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
935                 mf->width, mf->height);
936
937         icd->user_width         = mf->width;
938         icd->user_height        = mf->height;
939
940         return ret;
941 }
942
943 static int mx2_camera_get_formats(struct soc_camera_device *icd,
944                                   unsigned int idx,
945                                   struct soc_camera_format_xlate *xlate)
946 {
947         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
948         const struct soc_mbus_pixelfmt *fmt;
949         struct device *dev = icd->parent;
950         struct v4l2_subdev_mbus_code_enum code = {
951                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
952                 .index = idx,
953         };
954         int ret, formats = 0;
955
956         ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code);
957         if (ret < 0)
958                 /* no more formats */
959                 return 0;
960
961         fmt = soc_mbus_get_fmtdesc(code.code);
962         if (!fmt) {
963                 dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code);
964                 return 0;
965         }
966
967         if (code.code == MEDIA_BUS_FMT_YUYV8_2X8 ||
968             code.code == MEDIA_BUS_FMT_UYVY8_2X8) {
969                 formats++;
970                 if (xlate) {
971                         /*
972                          * CH2 can output YUV420 which is a standard format in
973                          * soc_mediabus.c
974                          */
975                         xlate->host_fmt =
976                                 soc_mbus_get_fmtdesc(MEDIA_BUS_FMT_YUYV8_1_5X8);
977                         xlate->code     = code.code;
978                         dev_dbg(dev, "Providing host format %s for sensor code %d\n",
979                                xlate->host_fmt->name, code.code);
980                         xlate++;
981                 }
982         }
983
984         if (code.code == MEDIA_BUS_FMT_UYVY8_2X8) {
985                 formats++;
986                 if (xlate) {
987                         xlate->host_fmt =
988                                 soc_mbus_get_fmtdesc(MEDIA_BUS_FMT_YUYV8_2X8);
989                         xlate->code     = code.code;
990                         dev_dbg(dev, "Providing host format %s for sensor code %d\n",
991                                 xlate->host_fmt->name, code.code);
992                         xlate++;
993                 }
994         }
995
996         /* Generic pass-trough */
997         formats++;
998         if (xlate) {
999                 xlate->host_fmt = fmt;
1000                 xlate->code     = code.code;
1001                 xlate++;
1002         }
1003         return formats;
1004 }
1005
1006 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1007                               struct v4l2_mbus_framefmt *mf_in,
1008                               struct v4l2_pix_format *pix_out, bool apply)
1009 {
1010         unsigned int num, den;
1011         unsigned long m;
1012         int i, dir;
1013
1014         for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1015                 struct emma_prp_resize tmprsz;
1016                 unsigned char *s = tmprsz.s;
1017                 int len = 0;
1018                 int in, out;
1019
1020                 if (dir == RESIZE_DIR_H) {
1021                         in = mf_in->width;
1022                         out = pix_out->width;
1023                 } else {
1024                         in = mf_in->height;
1025                         out = pix_out->height;
1026                 }
1027
1028                 if (in < out)
1029                         return -EINVAL;
1030                 else if (in == out)
1031                         continue;
1032
1033                 /* Calculate ratio */
1034                 m = gcd(in, out);
1035                 num = in / m;
1036                 den = out / m;
1037                 if (num > RESIZE_NUM_MAX)
1038                         return -EINVAL;
1039
1040                 if ((num >= 2 * den) && (den == 1) &&
1041                     (num < 9) && (!(num & 0x01))) {
1042                         int sum = 0;
1043                         int j;
1044
1045                         /* Average scaling for >= 2:1 ratios */
1046                         /* Support can be added for num >=9 and odd values */
1047
1048                         tmprsz.algo = RESIZE_ALGO_AVERAGING;
1049                         len = num;
1050
1051                         for (i = 0; i < (len / 2); i++)
1052                                 s[i] = 8;
1053
1054                         do {
1055                                 for (i = 0; i < (len / 2); i++) {
1056                                         s[i] = s[i] >> 1;
1057                                         sum = 0;
1058                                         for (j = 0; j < (len / 2); j++)
1059                                                 sum += s[j];
1060                                         if (sum == 4)
1061                                                 break;
1062                                 }
1063                         } while (sum != 4);
1064
1065                         for (i = (len / 2); i < len; i++)
1066                                 s[i] = s[len - i - 1];
1067
1068                         s[len - 1] |= SZ_COEF;
1069                 } else {
1070                         /* bilinear scaling for < 2:1 ratios */
1071                         int v; /* overflow counter */
1072                         int coeff, nxt; /* table output */
1073                         int in_pos_inc = 2 * den;
1074                         int out_pos = num;
1075                         int out_pos_inc = 2 * num;
1076                         int init_carry = num - den;
1077                         int carry = init_carry;
1078
1079                         tmprsz.algo = RESIZE_ALGO_BILINEAR;
1080                         v = den + in_pos_inc;
1081                         do {
1082                                 coeff = v - out_pos;
1083                                 out_pos += out_pos_inc;
1084                                 carry += out_pos_inc;
1085                                 for (nxt = 0; v < out_pos; nxt++) {
1086                                         v += in_pos_inc;
1087                                         carry -= in_pos_inc;
1088                                 }
1089
1090                                 if (len > RESIZE_NUM_MAX)
1091                                         return -EINVAL;
1092
1093                                 coeff = ((coeff << BC_COEF) +
1094                                         (in_pos_inc >> 1)) / in_pos_inc;
1095
1096                                 if (coeff >= (SZ_COEF - 1))
1097                                         coeff--;
1098
1099                                 coeff |= SZ_COEF;
1100                                 s[len] = (unsigned char)coeff;
1101                                 len++;
1102
1103                                 for (i = 1; i < nxt; i++) {
1104                                         if (len >= RESIZE_NUM_MAX)
1105                                                 return -EINVAL;
1106                                         s[len] = 0;
1107                                         len++;
1108                                 }
1109                         } while (carry != init_carry);
1110                 }
1111                 tmprsz.len = len;
1112                 if (dir == RESIZE_DIR_H)
1113                         mf_in->width = pix_out->width;
1114                 else
1115                         mf_in->height = pix_out->height;
1116
1117                 if (apply)
1118                         memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1119         }
1120         return 0;
1121 }
1122
1123 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1124                                struct v4l2_format *f)
1125 {
1126         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1127         struct mx2_camera_dev *pcdev = ici->priv;
1128         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1129         const struct soc_camera_format_xlate *xlate;
1130         struct v4l2_pix_format *pix = &f->fmt.pix;
1131         struct v4l2_subdev_format format = {
1132                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1133         };
1134         struct v4l2_mbus_framefmt *mf = &format.format;
1135         int ret;
1136
1137         dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1138                 __func__, pix->width, pix->height);
1139
1140         xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1141         if (!xlate) {
1142                 dev_warn(icd->parent, "Format %x not found\n",
1143                                 pix->pixelformat);
1144                 return -EINVAL;
1145         }
1146
1147         mf->width       = pix->width;
1148         mf->height      = pix->height;
1149         mf->field       = pix->field;
1150         mf->colorspace  = pix->colorspace;
1151         mf->code        = xlate->code;
1152
1153         ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format);
1154         if (ret < 0 && ret != -ENOIOCTLCMD)
1155                 return ret;
1156
1157         /* Store width and height returned by the sensor for resizing */
1158         pcdev->s_width = mf->width;
1159         pcdev->s_height = mf->height;
1160         dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1161                 __func__, pcdev->s_width, pcdev->s_height);
1162
1163         pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1164                                                    xlate->host_fmt->fourcc);
1165
1166         memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1167         if ((mf->width != pix->width || mf->height != pix->height) &&
1168                 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1169                 if (mx2_emmaprp_resize(pcdev, mf, pix, true) < 0)
1170                         dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1171         }
1172
1173         if (mf->code != xlate->code)
1174                 return -EINVAL;
1175
1176         pix->width              = mf->width;
1177         pix->height             = mf->height;
1178         pix->field              = mf->field;
1179         pix->colorspace         = mf->colorspace;
1180         icd->current_fmt        = xlate;
1181
1182         dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1183                 __func__, pix->width, pix->height);
1184
1185         return 0;
1186 }
1187
1188 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1189                                   struct v4l2_format *f)
1190 {
1191         struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1192         const struct soc_camera_format_xlate *xlate;
1193         struct v4l2_pix_format *pix = &f->fmt.pix;
1194         struct v4l2_subdev_pad_config pad_cfg;
1195         struct v4l2_subdev_format format = {
1196                 .which = V4L2_SUBDEV_FORMAT_TRY,
1197         };
1198         struct v4l2_mbus_framefmt *mf = &format.format;
1199         __u32 pixfmt = pix->pixelformat;
1200         struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1201         struct mx2_camera_dev *pcdev = ici->priv;
1202         struct mx2_fmt_cfg *emma_prp;
1203         int ret;
1204
1205         dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1206                 __func__, pix->width, pix->height);
1207
1208         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1209         if (pixfmt && !xlate) {
1210                 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1211                 return -EINVAL;
1212         }
1213
1214         /*
1215          * limit to MX27 hardware capabilities: width must be a multiple of 8 as
1216          * requested by the CSI. (Table 39-2 in the i.MX27 Reference Manual).
1217          */
1218         pix->width &= ~0x7;
1219
1220         /* limit to sensor capabilities */
1221         mf->width       = pix->width;
1222         mf->height      = pix->height;
1223         mf->field       = pix->field;
1224         mf->colorspace  = pix->colorspace;
1225         mf->code        = xlate->code;
1226
1227         ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format);
1228         if (ret < 0)
1229                 return ret;
1230
1231         dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1232                 __func__, pcdev->s_width, pcdev->s_height);
1233
1234         /* If the sensor does not support image size try PrP resizing */
1235         emma_prp = mx27_emma_prp_get_format(xlate->code,
1236                                             xlate->host_fmt->fourcc);
1237
1238         if ((mf->width != pix->width || mf->height != pix->height) &&
1239                 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1240                 if (mx2_emmaprp_resize(pcdev, mf, pix, false) < 0)
1241                         dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1242         }
1243
1244         if (mf->field == V4L2_FIELD_ANY)
1245                 mf->field = V4L2_FIELD_NONE;
1246         /*
1247          * Driver supports interlaced images provided they have
1248          * both fields so that they can be processed as if they
1249          * were progressive.
1250          */
1251         if (mf->field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf->field)) {
1252                 dev_err(icd->parent, "Field type %d unsupported.\n",
1253                                 mf->field);
1254                 return -EINVAL;
1255         }
1256
1257         pix->width      = mf->width;
1258         pix->height     = mf->height;
1259         pix->field      = mf->field;
1260         pix->colorspace = mf->colorspace;
1261
1262         dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1263                 __func__, pix->width, pix->height);
1264
1265         return 0;
1266 }
1267
1268 static int mx2_camera_querycap(struct soc_camera_host *ici,
1269                                struct v4l2_capability *cap)
1270 {
1271         /* cap->name is set by the friendly caller:-> */
1272         strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1273         cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1274         cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1275
1276         return 0;
1277 }
1278
1279 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1280 {
1281         struct soc_camera_device *icd = file->private_data;
1282
1283         return vb2_poll(&icd->vb2_vidq, file, pt);
1284 }
1285
1286 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1287         .owner          = THIS_MODULE,
1288         .add            = mx2_camera_add_device,
1289         .remove         = mx2_camera_remove_device,
1290         .clock_start    = mx2_camera_clock_start,
1291         .clock_stop     = mx2_camera_clock_stop,
1292         .set_fmt        = mx2_camera_set_fmt,
1293         .set_crop       = mx2_camera_set_crop,
1294         .get_formats    = mx2_camera_get_formats,
1295         .try_fmt        = mx2_camera_try_fmt,
1296         .init_videobuf2 = mx2_camera_init_videobuf,
1297         .poll           = mx2_camera_poll,
1298         .querycap       = mx2_camera_querycap,
1299         .set_bus_param  = mx2_camera_set_bus_param,
1300 };
1301
1302 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1303                 int bufnum, bool err)
1304 {
1305 #ifdef DEBUG
1306         struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1307 #endif
1308         struct mx2_buf_internal *ibuf;
1309         struct mx2_buffer *buf;
1310         struct vb2_buffer *vb;
1311         struct vb2_v4l2_buffer *vbuf;
1312         unsigned long phys;
1313
1314         ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1315                                queue);
1316
1317         BUG_ON(ibuf->bufnum != bufnum);
1318
1319         if (ibuf->discard) {
1320                 /*
1321                  * Discard buffer must not be returned to user space.
1322                  * Just return it to the discard queue.
1323                  */
1324                 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1325         } else {
1326                 buf = mx2_ibuf_to_buf(ibuf);
1327
1328                 vb = &buf->vb.vb2_buf;
1329                 vbuf = to_vb2_v4l2_buffer(vb);
1330 #ifdef DEBUG
1331                 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1332                 if (prp->cfg.channel == 1) {
1333                         if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1334                                 4 * bufnum) != phys) {
1335                                 dev_err(pcdev->dev, "%lx != %x\n", phys,
1336                                         readl(pcdev->base_emma +
1337                                         PRP_DEST_RGB1_PTR + 4 * bufnum));
1338                         }
1339                 } else {
1340                         if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1341                                 0x14 * bufnum) != phys) {
1342                                 dev_err(pcdev->dev, "%lx != %x\n", phys,
1343                                         readl(pcdev->base_emma +
1344                                         PRP_DEST_Y_PTR - 0x14 * bufnum));
1345                         }
1346                 }
1347 #endif
1348                 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1349                                 vb2_plane_vaddr(vb, 0),
1350                                 vb2_get_plane_payload(vb, 0));
1351
1352                 list_del_init(&buf->internal.queue);
1353                 v4l2_get_timestamp(&vbuf->timestamp);
1354                 vbuf->sequence = pcdev->frame_count;
1355                 if (err)
1356                         vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1357                 else
1358                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1359         }
1360
1361         pcdev->frame_count++;
1362
1363         if (list_empty(&pcdev->capture)) {
1364                 if (list_empty(&pcdev->discard)) {
1365                         dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1366                                  __func__);
1367                         return;
1368                 }
1369
1370                 ibuf = list_first_entry(&pcdev->discard,
1371                                         struct mx2_buf_internal, queue);
1372                 ibuf->bufnum = bufnum;
1373
1374                 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1375                 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1376                 return;
1377         }
1378
1379         buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1380                                internal.queue);
1381
1382         buf->internal.bufnum = bufnum;
1383
1384         list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1385
1386         vb = &buf->vb.vb2_buf;
1387
1388         phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1389         mx27_update_emma_buf(pcdev, phys, bufnum);
1390 }
1391
1392 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1393 {
1394         struct mx2_camera_dev *pcdev = data;
1395         unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1396         struct mx2_buf_internal *ibuf;
1397
1398         spin_lock(&pcdev->lock);
1399
1400         if (list_empty(&pcdev->active_bufs)) {
1401                 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1402                         __func__);
1403
1404                 if (!status) {
1405                         spin_unlock(&pcdev->lock);
1406                         return IRQ_NONE;
1407                 }
1408         }
1409
1410         if (status & (1 << 7)) { /* overflow */
1411                 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1412                 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1413                        pcdev->base_emma + PRP_CNTL);
1414                 writel(cntl, pcdev->base_emma + PRP_CNTL);
1415
1416                 ibuf = list_first_entry(&pcdev->active_bufs,
1417                                         struct mx2_buf_internal, queue);
1418                 mx27_camera_frame_done_emma(pcdev,
1419                                         ibuf->bufnum, true);
1420
1421                 status &= ~(1 << 7);
1422         } else if (((status & (3 << 5)) == (3 << 5)) ||
1423                 ((status & (3 << 3)) == (3 << 3))) {
1424                 /*
1425                  * Both buffers have triggered, process the one we're expecting
1426                  * to first
1427                  */
1428                 ibuf = list_first_entry(&pcdev->active_bufs,
1429                                         struct mx2_buf_internal, queue);
1430                 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1431                 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1432         } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1433                 mx27_camera_frame_done_emma(pcdev, 0, false);
1434         } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1435                 mx27_camera_frame_done_emma(pcdev, 1, false);
1436         }
1437
1438         spin_unlock(&pcdev->lock);
1439         writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1440
1441         return IRQ_HANDLED;
1442 }
1443
1444 static int mx27_camera_emma_init(struct platform_device *pdev)
1445 {
1446         struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1447         struct resource *res_emma;
1448         int irq_emma;
1449         int err = 0;
1450
1451         res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1452         irq_emma = platform_get_irq(pdev, 1);
1453         if (!res_emma || !irq_emma) {
1454                 dev_err(pcdev->dev, "no EMMA resources\n");
1455                 err = -ENODEV;
1456                 goto out;
1457         }
1458
1459         pcdev->base_emma = devm_ioremap_resource(pcdev->dev, res_emma);
1460         if (IS_ERR(pcdev->base_emma)) {
1461                 err = PTR_ERR(pcdev->base_emma);
1462                 goto out;
1463         }
1464
1465         err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1466                                MX2_CAM_DRV_NAME, pcdev);
1467         if (err) {
1468                 dev_err(pcdev->dev, "Camera EMMA interrupt register failed\n");
1469                 goto out;
1470         }
1471
1472         pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1473         if (IS_ERR(pcdev->clk_emma_ipg)) {
1474                 err = PTR_ERR(pcdev->clk_emma_ipg);
1475                 goto out;
1476         }
1477
1478         clk_prepare_enable(pcdev->clk_emma_ipg);
1479
1480         pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1481         if (IS_ERR(pcdev->clk_emma_ahb)) {
1482                 err = PTR_ERR(pcdev->clk_emma_ahb);
1483                 goto exit_clk_emma_ipg;
1484         }
1485
1486         clk_prepare_enable(pcdev->clk_emma_ahb);
1487
1488         err = mx27_camera_emma_prp_reset(pcdev);
1489         if (err)
1490                 goto exit_clk_emma_ahb;
1491
1492         return err;
1493
1494 exit_clk_emma_ahb:
1495         clk_disable_unprepare(pcdev->clk_emma_ahb);
1496 exit_clk_emma_ipg:
1497         clk_disable_unprepare(pcdev->clk_emma_ipg);
1498 out:
1499         return err;
1500 }
1501
1502 static int mx2_camera_probe(struct platform_device *pdev)
1503 {
1504         struct mx2_camera_dev *pcdev;
1505         struct resource *res_csi;
1506         int irq_csi;
1507         int err = 0;
1508
1509         dev_dbg(&pdev->dev, "initialising\n");
1510
1511         res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1512         irq_csi = platform_get_irq(pdev, 0);
1513         if (res_csi == NULL || irq_csi < 0) {
1514                 dev_err(&pdev->dev, "Missing platform resources data\n");
1515                 err = -ENODEV;
1516                 goto exit;
1517         }
1518
1519         pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1520         if (!pcdev) {
1521                 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1522                 err = -ENOMEM;
1523                 goto exit;
1524         }
1525
1526         pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1527         if (IS_ERR(pcdev->clk_csi_ahb)) {
1528                 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1529                 err = PTR_ERR(pcdev->clk_csi_ahb);
1530                 goto exit;
1531         }
1532
1533         pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1534         if (IS_ERR(pcdev->clk_csi_per)) {
1535                 dev_err(&pdev->dev, "Could not get csi per clock\n");
1536                 err = PTR_ERR(pcdev->clk_csi_per);
1537                 goto exit;
1538         }
1539
1540         pcdev->pdata = pdev->dev.platform_data;
1541         if (pcdev->pdata) {
1542                 long rate;
1543
1544                 pcdev->platform_flags = pcdev->pdata->flags;
1545
1546                 rate = clk_round_rate(pcdev->clk_csi_per,
1547                                                 pcdev->pdata->clk * 2);
1548                 if (rate <= 0) {
1549                         err = -ENODEV;
1550                         goto exit;
1551                 }
1552                 err = clk_set_rate(pcdev->clk_csi_per, rate);
1553                 if (err < 0)
1554                         goto exit;
1555         }
1556
1557         INIT_LIST_HEAD(&pcdev->capture);
1558         INIT_LIST_HEAD(&pcdev->active_bufs);
1559         INIT_LIST_HEAD(&pcdev->discard);
1560         spin_lock_init(&pcdev->lock);
1561
1562         pcdev->base_csi = devm_ioremap_resource(&pdev->dev, res_csi);
1563         if (IS_ERR(pcdev->base_csi)) {
1564                 err = PTR_ERR(pcdev->base_csi);
1565                 goto exit;
1566         }
1567
1568         pcdev->dev = &pdev->dev;
1569         platform_set_drvdata(pdev, pcdev);
1570
1571         err = mx27_camera_emma_init(pdev);
1572         if (err)
1573                 goto exit;
1574
1575         /*
1576          * We're done with drvdata here.  Clear the pointer so that
1577          * v4l2 core can start using drvdata on its purpose.
1578          */
1579         platform_set_drvdata(pdev, NULL);
1580
1581         pcdev->soc_host.drv_name        = MX2_CAM_DRV_NAME,
1582         pcdev->soc_host.ops             = &mx2_soc_camera_host_ops,
1583         pcdev->soc_host.priv            = pcdev;
1584         pcdev->soc_host.v4l2_dev.dev    = &pdev->dev;
1585         pcdev->soc_host.nr              = pdev->id;
1586
1587         pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1588         if (IS_ERR(pcdev->alloc_ctx)) {
1589                 err = PTR_ERR(pcdev->alloc_ctx);
1590                 goto eallocctx;
1591         }
1592         err = soc_camera_host_register(&pcdev->soc_host);
1593         if (err)
1594                 goto exit_free_emma;
1595
1596         dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1597                         clk_get_rate(pcdev->clk_csi_per));
1598
1599         return 0;
1600
1601 exit_free_emma:
1602         vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1603 eallocctx:
1604         clk_disable_unprepare(pcdev->clk_emma_ipg);
1605         clk_disable_unprepare(pcdev->clk_emma_ahb);
1606 exit:
1607         return err;
1608 }
1609
1610 static int mx2_camera_remove(struct platform_device *pdev)
1611 {
1612         struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1613         struct mx2_camera_dev *pcdev = container_of(soc_host,
1614                         struct mx2_camera_dev, soc_host);
1615
1616         soc_camera_host_unregister(&pcdev->soc_host);
1617
1618         vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1619
1620         clk_disable_unprepare(pcdev->clk_emma_ipg);
1621         clk_disable_unprepare(pcdev->clk_emma_ahb);
1622
1623         dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1624
1625         return 0;
1626 }
1627
1628 static struct platform_driver mx2_camera_driver = {
1629         .driver         = {
1630                 .name   = MX2_CAM_DRV_NAME,
1631         },
1632         .id_table       = mx2_camera_devtype,
1633         .remove         = mx2_camera_remove,
1634 };
1635
1636 module_platform_driver_probe(mx2_camera_driver, mx2_camera_probe);
1637
1638 MODULE_DESCRIPTION("i.MX27 SoC Camera Host driver");
1639 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1640 MODULE_LICENSE("GPL");
1641 MODULE_VERSION(MX2_CAM_VERSION);