2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
25 #include <linux/of_device.h>
26 #include <linux/of_reserved_mem.h>
27 #include <media/videobuf2-v4l2.h>
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_ctrl.h"
30 #include "s5p_mfc_debug.h"
31 #include "s5p_mfc_dec.h"
32 #include "s5p_mfc_enc.h"
33 #include "s5p_mfc_intr.h"
34 #include "s5p_mfc_iommu.h"
35 #include "s5p_mfc_opr.h"
36 #include "s5p_mfc_cmd.h"
37 #include "s5p_mfc_pm.h"
39 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
40 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
43 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
46 static char *mfc_mem_size;
47 module_param_named(mem, mfc_mem_size, charp, 0644);
48 MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
50 /* Helper functions for interrupt processing */
52 /* Remove from hw execution round robin */
53 void clear_work_bit(struct s5p_mfc_ctx *ctx)
55 struct s5p_mfc_dev *dev = ctx->dev;
57 spin_lock(&dev->condlock);
58 __clear_bit(ctx->num, &dev->ctx_work_bits);
59 spin_unlock(&dev->condlock);
62 /* Add to hw execution round robin */
63 void set_work_bit(struct s5p_mfc_ctx *ctx)
65 struct s5p_mfc_dev *dev = ctx->dev;
67 spin_lock(&dev->condlock);
68 __set_bit(ctx->num, &dev->ctx_work_bits);
69 spin_unlock(&dev->condlock);
72 /* Remove from hw execution round robin */
73 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
75 struct s5p_mfc_dev *dev = ctx->dev;
78 spin_lock_irqsave(&dev->condlock, flags);
79 __clear_bit(ctx->num, &dev->ctx_work_bits);
80 spin_unlock_irqrestore(&dev->condlock, flags);
83 /* Add to hw execution round robin */
84 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
86 struct s5p_mfc_dev *dev = ctx->dev;
89 spin_lock_irqsave(&dev->condlock, flags);
90 __set_bit(ctx->num, &dev->ctx_work_bits);
91 spin_unlock_irqrestore(&dev->condlock, flags);
94 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
99 spin_lock_irqsave(&dev->condlock, flags);
102 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
103 if (ctx == dev->curr_ctx) {
104 if (!test_bit(ctx, &dev->ctx_work_bits))
108 } while (!test_bit(ctx, &dev->ctx_work_bits));
109 spin_unlock_irqrestore(&dev->condlock, flags);
114 /* Wake up context wait_queue */
115 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
119 ctx->int_type = reason;
121 wake_up(&ctx->queue);
124 /* Wake up device wait_queue */
125 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
129 dev->int_type = reason;
131 wake_up(&dev->queue);
134 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
136 struct s5p_mfc_buf *b;
139 while (!list_empty(lh)) {
140 b = list_entry(lh->next, struct s5p_mfc_buf, list);
141 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
142 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
143 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
148 static void s5p_mfc_watchdog(struct timer_list *t)
150 struct s5p_mfc_dev *dev = from_timer(dev, t, watchdog_timer);
152 if (test_bit(0, &dev->hw_lock))
153 atomic_inc(&dev->watchdog_cnt);
154 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
155 /* This means that hw is busy and no interrupts were
156 * generated by hw for the Nth time of running this
157 * watchdog timer. This usually means a serious hw
158 * error. Now it is time to kill all instances and
160 mfc_err("Time out during waiting for HW\n");
161 schedule_work(&dev->watchdog_work);
163 dev->watchdog_timer.expires = jiffies +
164 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
165 add_timer(&dev->watchdog_timer);
168 static void s5p_mfc_watchdog_worker(struct work_struct *work)
170 struct s5p_mfc_dev *dev;
171 struct s5p_mfc_ctx *ctx;
176 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
178 mfc_err("Driver timeout error handling\n");
179 /* Lock the mutex that protects open and release.
180 * This is necessary as they may load and unload firmware. */
181 mutex_locked = mutex_trylock(&dev->mfc_mutex);
183 mfc_err("Error: some instance may be closing/opening\n");
184 spin_lock_irqsave(&dev->irqlock, flags);
188 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
192 ctx->state = MFCINST_ERROR;
193 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
194 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
196 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
198 clear_bit(0, &dev->hw_lock);
199 spin_unlock_irqrestore(&dev->irqlock, flags);
202 s5p_mfc_deinit_hw(dev);
204 /* Double check if there is at least one instance running.
205 * If no instance is in memory than no firmware should be present */
206 if (dev->num_inst > 0) {
207 ret = s5p_mfc_load_firmware(dev);
209 mfc_err("Failed to reload FW\n");
213 ret = s5p_mfc_init_hw(dev);
216 mfc_err("Failed to reinit FW\n");
220 mutex_unlock(&dev->mfc_mutex);
223 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
225 struct s5p_mfc_buf *dst_buf;
226 struct s5p_mfc_dev *dev = ctx->dev;
228 ctx->state = MFCINST_FINISHED;
230 while (!list_empty(&ctx->dst_queue)) {
231 dst_buf = list_entry(ctx->dst_queue.next,
232 struct s5p_mfc_buf, list);
233 mfc_debug(2, "Cleaning up buffer: %d\n",
234 dst_buf->b->vb2_buf.index);
235 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
236 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
237 list_del(&dst_buf->list);
238 dst_buf->flags |= MFC_BUF_FLAG_EOS;
239 ctx->dst_queue_cnt--;
240 dst_buf->b->sequence = (ctx->sequence++);
242 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
243 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
244 dst_buf->b->field = V4L2_FIELD_NONE;
246 dst_buf->b->field = V4L2_FIELD_INTERLACED;
247 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
249 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
250 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
254 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
256 struct s5p_mfc_dev *dev = ctx->dev;
257 struct s5p_mfc_buf *dst_buf, *src_buf;
259 unsigned int frame_type;
261 /* Make sure we actually have a new frame before continuing. */
262 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
263 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
265 dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
267 /* Copy timestamp / timecode from decoded src to dst and set
268 appropriate flags. */
269 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
270 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
271 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
273 if (addr == dec_y_addr) {
274 dst_buf->b->timecode = src_buf->b->timecode;
275 dst_buf->b->vb2_buf.timestamp =
276 src_buf->b->vb2_buf.timestamp;
278 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
281 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
282 switch (frame_type) {
283 case S5P_FIMV_DECODE_FRAME_I_FRAME:
285 V4L2_BUF_FLAG_KEYFRAME;
287 case S5P_FIMV_DECODE_FRAME_P_FRAME:
289 V4L2_BUF_FLAG_PFRAME;
291 case S5P_FIMV_DECODE_FRAME_B_FRAME:
293 V4L2_BUF_FLAG_BFRAME;
296 /* Don't know how to handle
297 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
298 mfc_debug(2, "Unexpected frame type: %d\n",
306 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
308 struct s5p_mfc_dev *dev = ctx->dev;
309 struct s5p_mfc_buf *dst_buf;
311 unsigned int frame_type;
313 dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
314 if (IS_MFCV6_PLUS(dev))
315 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
316 get_disp_frame_type, ctx);
318 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
319 get_dec_frame_type, dev);
321 /* If frame is same as previous then skip and do not dequeue */
322 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
323 if (!ctx->after_packed_pb)
325 ctx->after_packed_pb = 0;
329 /* The MFC returns address of the buffer, now we have to
330 * check which videobuf does it correspond to */
331 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
332 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
334 /* Check if this is the buffer we're looking for */
335 if (addr == dspl_y_addr) {
336 list_del(&dst_buf->list);
337 ctx->dst_queue_cnt--;
338 dst_buf->b->sequence = ctx->sequence;
339 if (s5p_mfc_hw_call(dev->mfc_ops,
340 get_pic_type_top, ctx) ==
341 s5p_mfc_hw_call(dev->mfc_ops,
342 get_pic_type_bot, ctx))
343 dst_buf->b->field = V4L2_FIELD_NONE;
346 V4L2_FIELD_INTERLACED;
347 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
349 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
351 clear_bit(dst_buf->b->vb2_buf.index,
354 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
355 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
362 /* Handle frame decoding interrupt */
363 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
364 unsigned int reason, unsigned int err)
366 struct s5p_mfc_dev *dev = ctx->dev;
367 unsigned int dst_frame_status;
368 unsigned int dec_frame_status;
369 struct s5p_mfc_buf *src_buf;
370 unsigned int res_change;
372 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
373 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
374 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
375 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
376 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
377 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
378 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
379 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
380 if (ctx->state == MFCINST_RES_CHANGE_INIT)
381 ctx->state = MFCINST_RES_CHANGE_FLUSH;
382 if (res_change == S5P_FIMV_RES_INCREASE ||
383 res_change == S5P_FIMV_RES_DECREASE) {
384 ctx->state = MFCINST_RES_CHANGE_INIT;
385 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
386 wake_up_ctx(ctx, reason, err);
387 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
389 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
392 if (ctx->dpb_flush_flag)
393 ctx->dpb_flush_flag = 0;
395 /* All frames remaining in the buffer have been extracted */
396 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
397 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
398 static const struct v4l2_event ev_src_ch = {
399 .type = V4L2_EVENT_SOURCE_CHANGE,
400 .u.src_change.changes =
401 V4L2_EVENT_SRC_CH_RESOLUTION,
404 s5p_mfc_handle_frame_all_extracted(ctx);
405 ctx->state = MFCINST_RES_CHANGE_END;
406 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
408 goto leave_handle_frame;
410 s5p_mfc_handle_frame_all_extracted(ctx);
414 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
415 s5p_mfc_handle_frame_copy_time(ctx);
417 /* A frame has been decoded and is in the buffer */
418 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
419 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
420 s5p_mfc_handle_frame_new(ctx, err);
422 mfc_debug(2, "No frame decode\n");
424 /* Mark source buffer as complete */
425 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
426 && !list_empty(&ctx->src_queue)) {
427 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
429 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
430 get_consumed_stream, dev);
431 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
432 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
433 ctx->consumed_stream + STUFF_BYTE <
434 src_buf->b->vb2_buf.planes[0].bytesused) {
435 /* Run MFC again on the same buffer */
436 mfc_debug(2, "Running again the same buffer\n");
437 ctx->after_packed_pb = 1;
439 mfc_debug(2, "MFC needs next buffer\n");
440 ctx->consumed_stream = 0;
441 if (src_buf->flags & MFC_BUF_FLAG_EOS)
442 ctx->state = MFCINST_FINISHING;
443 list_del(&src_buf->list);
444 ctx->src_queue_cnt--;
445 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
446 vb2_buffer_done(&src_buf->b->vb2_buf,
447 VB2_BUF_STATE_ERROR);
449 vb2_buffer_done(&src_buf->b->vb2_buf,
454 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
455 || ctx->dst_queue_cnt < ctx->pb_count)
457 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
458 wake_up_ctx(ctx, reason, err);
459 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
461 /* if suspending, wake up device and do not try_run again*/
462 if (test_bit(0, &dev->enter_suspend))
463 wake_up_dev(dev, reason, err);
465 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
468 /* Error handling for interrupt */
469 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
470 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
472 mfc_err("Interrupt Error: %08x\n", err);
475 /* Error recovery is dependent on the state of context */
476 switch (ctx->state) {
477 case MFCINST_RES_CHANGE_INIT:
478 case MFCINST_RES_CHANGE_FLUSH:
479 case MFCINST_RES_CHANGE_END:
480 case MFCINST_FINISHING:
481 case MFCINST_FINISHED:
482 case MFCINST_RUNNING:
483 /* It is highly probable that an error occurred
484 * while decoding a frame */
486 ctx->state = MFCINST_ERROR;
487 /* Mark all dst buffers as having an error */
488 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
489 /* Mark all src buffers as having an error */
490 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
491 wake_up_ctx(ctx, reason, err);
495 ctx->state = MFCINST_ERROR;
496 wake_up_ctx(ctx, reason, err);
500 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
501 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
503 wake_up_dev(dev, reason, err);
506 /* Header parsing interrupt handling */
507 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
508 unsigned int reason, unsigned int err)
510 struct s5p_mfc_dev *dev;
515 if (ctx->c_ops->post_seq_start) {
516 if (ctx->c_ops->post_seq_start(ctx))
517 mfc_err("post_seq_start() failed\n");
519 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
521 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
524 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
526 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
528 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
530 ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
531 get_min_scratch_buf_size, dev);
532 if (ctx->img_width == 0 || ctx->img_height == 0)
533 ctx->state = MFCINST_ERROR;
535 ctx->state = MFCINST_HEAD_PARSED;
537 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
538 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
539 !list_empty(&ctx->src_queue)) {
540 struct s5p_mfc_buf *src_buf;
541 src_buf = list_entry(ctx->src_queue.next,
542 struct s5p_mfc_buf, list);
543 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
545 src_buf->b->vb2_buf.planes[0].bytesused)
546 ctx->head_processed = 0;
548 ctx->head_processed = 1;
550 ctx->head_processed = 1;
553 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
555 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
557 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
558 wake_up_ctx(ctx, reason, err);
561 /* Header parsing interrupt handling */
562 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
563 unsigned int reason, unsigned int err)
565 struct s5p_mfc_buf *src_buf;
566 struct s5p_mfc_dev *dev;
571 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
572 ctx->int_type = reason;
577 ctx->state = MFCINST_RUNNING;
578 if (!ctx->dpb_flush_flag && ctx->head_processed) {
579 if (!list_empty(&ctx->src_queue)) {
580 src_buf = list_entry(ctx->src_queue.next,
581 struct s5p_mfc_buf, list);
582 list_del(&src_buf->list);
583 ctx->src_queue_cnt--;
584 vb2_buffer_done(&src_buf->b->vb2_buf,
588 ctx->dpb_flush_flag = 0;
590 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
594 wake_up(&ctx->queue);
595 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
597 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
601 wake_up(&ctx->queue);
605 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
607 struct s5p_mfc_dev *dev = ctx->dev;
608 struct s5p_mfc_buf *mb_entry;
610 mfc_debug(2, "Stream completed\n");
612 ctx->state = MFCINST_FINISHED;
614 if (!list_empty(&ctx->dst_queue)) {
615 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
617 list_del(&mb_entry->list);
618 ctx->dst_queue_cnt--;
619 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
620 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
625 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
628 wake_up(&ctx->queue);
629 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
632 /* Interrupt processing */
633 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
635 struct s5p_mfc_dev *dev = priv;
636 struct s5p_mfc_ctx *ctx;
641 /* Reset the timeout watchdog */
642 atomic_set(&dev->watchdog_cnt, 0);
643 spin_lock(&dev->irqlock);
644 ctx = dev->ctx[dev->curr_ctx];
645 /* Get the reason of interrupt and the error code */
646 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
647 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
648 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
650 case S5P_MFC_R2H_CMD_ERR_RET:
651 /* An error has occurred */
652 if (ctx->state == MFCINST_RUNNING &&
653 (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
655 err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
656 err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
657 err == S5P_FIMV_ERR_TIMEOUT))
658 s5p_mfc_handle_frame(ctx, reason, err);
660 s5p_mfc_handle_error(dev, ctx, reason, err);
661 clear_bit(0, &dev->enter_suspend);
664 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
665 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
666 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
667 if (ctx->c_ops->post_frame_start) {
668 if (ctx->c_ops->post_frame_start(ctx))
669 mfc_err("post_frame_start() failed\n");
671 if (ctx->state == MFCINST_FINISHING &&
672 list_empty(&ctx->ref_queue)) {
673 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
674 s5p_mfc_handle_stream_complete(ctx);
677 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
678 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
680 wake_up_ctx(ctx, reason, err);
681 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
683 s5p_mfc_handle_frame(ctx, reason, err);
687 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
688 s5p_mfc_handle_seq_done(ctx, reason, err);
691 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
692 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
693 ctx->state = MFCINST_GOT_INST;
696 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
697 ctx->inst_no = MFC_NO_INSTANCE_SET;
698 ctx->state = MFCINST_FREE;
701 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
702 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
703 case S5P_MFC_R2H_CMD_SLEEP_RET:
704 case S5P_MFC_R2H_CMD_WAKEUP_RET:
707 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
708 clear_bit(0, &dev->hw_lock);
709 clear_bit(0, &dev->enter_suspend);
710 wake_up_dev(dev, reason, err);
713 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
714 s5p_mfc_handle_init_buffers(ctx, reason, err);
717 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
718 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
719 ctx->int_type = reason;
721 s5p_mfc_handle_stream_complete(ctx);
724 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
725 ctx->state = MFCINST_RUNNING;
729 mfc_debug(2, "Unknown int reason\n");
730 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
732 spin_unlock(&dev->irqlock);
736 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
737 ctx->int_type = reason;
740 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
741 mfc_err("Failed to unlock hw\n");
745 wake_up(&ctx->queue);
747 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
748 spin_unlock(&dev->irqlock);
749 mfc_debug(2, "Exit via irq_cleanup_hw\n");
753 /* Open an MFC node */
754 static int s5p_mfc_open(struct file *file)
756 struct video_device *vdev = video_devdata(file);
757 struct s5p_mfc_dev *dev = video_drvdata(file);
758 struct s5p_mfc_ctx *ctx = NULL;
763 if (mutex_lock_interruptible(&dev->mfc_mutex))
765 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
766 /* Allocate memory for context */
767 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
772 init_waitqueue_head(&ctx->queue);
773 v4l2_fh_init(&ctx->fh, vdev);
774 file->private_data = &ctx->fh;
775 v4l2_fh_add(&ctx->fh);
777 INIT_LIST_HEAD(&ctx->src_queue);
778 INIT_LIST_HEAD(&ctx->dst_queue);
779 ctx->src_queue_cnt = 0;
780 ctx->dst_queue_cnt = 0;
781 /* Get context number */
783 while (dev->ctx[ctx->num]) {
785 if (ctx->num >= MFC_NUM_CONTEXTS) {
786 mfc_debug(2, "Too many open contexts\n");
791 /* Mark context as idle */
792 clear_work_bit_irqsave(ctx);
793 dev->ctx[ctx->num] = ctx;
794 if (vdev == dev->vfd_dec) {
795 ctx->type = MFCINST_DECODER;
796 ctx->c_ops = get_dec_codec_ops();
797 s5p_mfc_dec_init(ctx);
798 /* Setup ctrl handler */
799 ret = s5p_mfc_dec_ctrls_setup(ctx);
801 mfc_err("Failed to setup mfc controls\n");
802 goto err_ctrls_setup;
804 } else if (vdev == dev->vfd_enc) {
805 ctx->type = MFCINST_ENCODER;
806 ctx->c_ops = get_enc_codec_ops();
807 /* only for encoder */
808 INIT_LIST_HEAD(&ctx->ref_queue);
809 ctx->ref_queue_cnt = 0;
810 s5p_mfc_enc_init(ctx);
811 /* Setup ctrl handler */
812 ret = s5p_mfc_enc_ctrls_setup(ctx);
814 mfc_err("Failed to setup mfc controls\n");
815 goto err_ctrls_setup;
821 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
822 ctx->inst_no = MFC_NO_INSTANCE_SET;
823 /* Load firmware if this is the first instance */
824 if (dev->num_inst == 1) {
825 dev->watchdog_timer.expires = jiffies +
826 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
827 add_timer(&dev->watchdog_timer);
828 ret = s5p_mfc_power_on();
830 mfc_err("power on failed\n");
834 ret = s5p_mfc_load_firmware(dev);
840 ret = s5p_mfc_init_hw(dev);
845 /* Init videobuf2 queue for CAPTURE */
847 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
848 q->drv_priv = &ctx->fh;
849 q->lock = &dev->mfc_mutex;
850 if (vdev == dev->vfd_dec) {
851 q->io_modes = VB2_MMAP;
852 q->ops = get_dec_queue_ops();
853 } else if (vdev == dev->vfd_enc) {
854 q->io_modes = VB2_MMAP | VB2_USERPTR;
855 q->ops = get_enc_queue_ops();
861 * We'll do mostly sequential access, so sacrifice TLB efficiency for
864 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
865 q->mem_ops = &vb2_dma_contig_memops;
866 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
867 ret = vb2_queue_init(q);
869 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
872 /* Init videobuf2 queue for OUTPUT */
874 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
875 q->drv_priv = &ctx->fh;
876 q->lock = &dev->mfc_mutex;
877 if (vdev == dev->vfd_dec) {
878 q->io_modes = VB2_MMAP;
879 q->ops = get_dec_queue_ops();
880 } else if (vdev == dev->vfd_enc) {
881 q->io_modes = VB2_MMAP | VB2_USERPTR;
882 q->ops = get_enc_queue_ops();
887 /* One way to indicate end-of-stream for MFC is to set the
888 * bytesused == 0. However by default videobuf2 handles bytesused
889 * equal to 0 as a special case and changes its value to the size
890 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
891 * will keep the value of bytesused intact.
893 q->allow_zero_bytesused = 1;
896 * We'll do mostly sequential access, so sacrifice TLB efficiency for
899 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
900 q->mem_ops = &vb2_dma_contig_memops;
901 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
902 ret = vb2_queue_init(q);
904 mfc_err("Failed to initialize videobuf2 queue(output)\n");
907 mutex_unlock(&dev->mfc_mutex);
910 /* Deinit when failure occurred */
912 if (dev->num_inst == 1)
913 s5p_mfc_deinit_hw(dev);
917 if (dev->num_inst == 1) {
918 if (s5p_mfc_power_off() < 0)
919 mfc_err("power off failed\n");
920 del_timer_sync(&dev->watchdog_timer);
923 s5p_mfc_dec_ctrls_delete(ctx);
925 dev->ctx[ctx->num] = NULL;
927 v4l2_fh_del(&ctx->fh);
928 v4l2_fh_exit(&ctx->fh);
932 mutex_unlock(&dev->mfc_mutex);
937 /* Release MFC context */
938 static int s5p_mfc_release(struct file *file)
940 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
941 struct s5p_mfc_dev *dev = ctx->dev;
943 /* if dev is null, do cleanup that doesn't need dev */
946 mutex_lock(&dev->mfc_mutex);
947 vb2_queue_release(&ctx->vq_src);
948 vb2_queue_release(&ctx->vq_dst);
952 /* Mark context as idle */
953 clear_work_bit_irqsave(ctx);
955 * If instance was initialised and not yet freed,
956 * return instance and free resources
958 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
959 mfc_debug(2, "Has to free instance\n");
960 s5p_mfc_close_mfc_inst(dev, ctx);
962 /* hardware locking scheme */
963 if (dev->curr_ctx == ctx->num)
964 clear_bit(0, &dev->hw_lock);
966 if (dev->num_inst == 0) {
967 mfc_debug(2, "Last instance\n");
968 s5p_mfc_deinit_hw(dev);
969 del_timer_sync(&dev->watchdog_timer);
971 if (s5p_mfc_power_off() < 0)
972 mfc_err("Power off failed\n");
974 mfc_debug(2, "Shutting down clock\n");
979 dev->ctx[ctx->num] = NULL;
980 s5p_mfc_dec_ctrls_delete(ctx);
981 v4l2_fh_del(&ctx->fh);
982 /* vdev is gone if dev is null */
984 v4l2_fh_exit(&ctx->fh);
988 mutex_unlock(&dev->mfc_mutex);
994 static __poll_t s5p_mfc_poll(struct file *file,
995 struct poll_table_struct *wait)
997 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
998 struct s5p_mfc_dev *dev = ctx->dev;
999 struct vb2_queue *src_q, *dst_q;
1000 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
1002 unsigned long flags;
1004 mutex_lock(&dev->mfc_mutex);
1005 src_q = &ctx->vq_src;
1006 dst_q = &ctx->vq_dst;
1008 * There has to be at least one buffer queued on each queued_list, which
1009 * means either in driver already or waiting for driver to claim it
1010 * and start processing.
1012 if ((!src_q->streaming || list_empty(&src_q->queued_list))
1013 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
1017 mutex_unlock(&dev->mfc_mutex);
1018 poll_wait(file, &ctx->fh.wait, wait);
1019 poll_wait(file, &src_q->done_wq, wait);
1020 poll_wait(file, &dst_q->done_wq, wait);
1021 mutex_lock(&dev->mfc_mutex);
1022 if (v4l2_event_pending(&ctx->fh))
1024 spin_lock_irqsave(&src_q->done_lock, flags);
1025 if (!list_empty(&src_q->done_list))
1026 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1028 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1029 || src_vb->state == VB2_BUF_STATE_ERROR))
1030 rc |= EPOLLOUT | EPOLLWRNORM;
1031 spin_unlock_irqrestore(&src_q->done_lock, flags);
1032 spin_lock_irqsave(&dst_q->done_lock, flags);
1033 if (!list_empty(&dst_q->done_list))
1034 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1036 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1037 || dst_vb->state == VB2_BUF_STATE_ERROR))
1038 rc |= EPOLLIN | EPOLLRDNORM;
1039 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1041 mutex_unlock(&dev->mfc_mutex);
1046 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1048 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1049 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1052 if (offset < DST_QUEUE_OFF_BASE) {
1053 mfc_debug(2, "mmaping source\n");
1054 ret = vb2_mmap(&ctx->vq_src, vma);
1055 } else { /* capture */
1056 mfc_debug(2, "mmaping destination\n");
1057 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1058 ret = vb2_mmap(&ctx->vq_dst, vma);
1064 static const struct v4l2_file_operations s5p_mfc_fops = {
1065 .owner = THIS_MODULE,
1066 .open = s5p_mfc_open,
1067 .release = s5p_mfc_release,
1068 .poll = s5p_mfc_poll,
1069 .unlocked_ioctl = video_ioctl2,
1070 .mmap = s5p_mfc_mmap,
1073 /* DMA memory related helper functions */
1074 static void s5p_mfc_memdev_release(struct device *dev)
1076 of_reserved_mem_device_release(dev);
1079 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1080 const char *name, unsigned int idx)
1082 struct device *child;
1085 child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL);
1089 device_initialize(child);
1090 dev_set_name(child, "%s:%s", dev_name(dev), name);
1091 child->parent = dev;
1092 child->bus = dev->bus;
1093 child->coherent_dma_mask = dev->coherent_dma_mask;
1094 child->dma_mask = dev->dma_mask;
1095 child->release = s5p_mfc_memdev_release;
1098 * The memdevs are not proper OF platform devices, so in order for them
1099 * to be treated as valid DMA masters we need a bit of a hack to force
1100 * them to inherit the MFC node's DMA configuration.
1102 of_dma_configure(child, dev->of_node, true);
1104 if (device_add(child) == 0) {
1105 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1116 static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1118 struct device *dev = &mfc_dev->plat_dev->dev;
1120 dma_addr_t bank2_dma_addr;
1121 unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1125 * Create and initialize virtual devices for accessing
1126 * reserved memory regions.
1128 mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1130 if (!mfc_dev->mem_dev[BANK_L_CTX])
1132 mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1134 if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1135 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1139 /* Allocate memory for firmware and initialize both banks addresses */
1140 ret = s5p_mfc_alloc_firmware(mfc_dev);
1142 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1143 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1147 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1149 bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1150 align_size, &bank2_dma_addr, GFP_KERNEL);
1152 mfc_err("Allocating bank2 base failed\n");
1153 s5p_mfc_release_firmware(mfc_dev);
1154 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1155 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1159 /* Valid buffers passed to MFC encoder with LAST_FRAME command
1160 * should not have address of bank2 - MFC will treat it as a null frame.
1161 * To avoid such situation we set bank2 address below the pool address.
1163 mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1165 dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1168 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1170 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1176 static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1178 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1179 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1180 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1181 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1184 static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1186 struct device *dev = &mfc_dev->plat_dev->dev;
1187 unsigned long mem_size = SZ_4M;
1188 unsigned int bitmap_size;
1190 if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1194 mem_size = memparse(mfc_mem_size, NULL);
1196 bitmap_size = BITS_TO_LONGS(mem_size >> PAGE_SHIFT) * sizeof(long);
1198 mfc_dev->mem_bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1199 if (!mfc_dev->mem_bitmap)
1202 mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1203 &mfc_dev->mem_base, GFP_KERNEL);
1204 if (!mfc_dev->mem_virt) {
1205 kfree(mfc_dev->mem_bitmap);
1206 dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1207 (mem_size / SZ_1M));
1210 mfc_dev->mem_size = mem_size;
1211 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1212 mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1215 * MFC hardware cannot handle 0 as a base address, so mark first 128K
1216 * as used (to keep required base alignment) and adjust base address
1218 if (mfc_dev->mem_base == (dma_addr_t)0) {
1219 unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1221 bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1222 mfc_dev->dma_base[BANK_L_CTX] += offset;
1223 mfc_dev->dma_base[BANK_R_CTX] += offset;
1226 /* Firmware allocation cannot fail in this case */
1227 s5p_mfc_alloc_firmware(mfc_dev);
1229 mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1230 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1232 dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1233 (mem_size / SZ_1M));
1238 static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1240 struct device *dev = &mfc_dev->plat_dev->dev;
1242 dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1244 kfree(mfc_dev->mem_bitmap);
1245 vb2_dma_contig_clear_max_seg_size(dev);
1248 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1250 struct device *dev = &mfc_dev->plat_dev->dev;
1252 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1253 return s5p_mfc_configure_common_memory(mfc_dev);
1255 return s5p_mfc_configure_2port_memory(mfc_dev);
1258 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1260 struct device *dev = &mfc_dev->plat_dev->dev;
1262 s5p_mfc_release_firmware(mfc_dev);
1263 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1264 s5p_mfc_unconfigure_common_memory(mfc_dev);
1266 s5p_mfc_unconfigure_2port_memory(mfc_dev);
1269 /* MFC probe function */
1270 static int s5p_mfc_probe(struct platform_device *pdev)
1272 struct s5p_mfc_dev *dev;
1273 struct video_device *vfd;
1274 struct resource *res;
1277 pr_debug("%s++\n", __func__);
1278 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1282 spin_lock_init(&dev->irqlock);
1283 spin_lock_init(&dev->condlock);
1284 dev->plat_dev = pdev;
1285 if (!dev->plat_dev) {
1286 dev_err(&pdev->dev, "No platform data specified\n");
1290 dev->variant = of_device_get_match_data(&pdev->dev);
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1294 if (IS_ERR(dev->regs_base))
1295 return PTR_ERR(dev->regs_base);
1297 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1299 dev_err(&pdev->dev, "failed to get irq resource\n");
1302 dev->irq = res->start;
1303 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1304 0, pdev->name, dev);
1306 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1310 ret = s5p_mfc_configure_dma_memory(dev);
1312 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1316 ret = s5p_mfc_init_pm(dev);
1318 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1323 * Load fails if fs isn't mounted. Try loading anyway.
1324 * _open() will load it, it it fails now. Ignore failure.
1326 s5p_mfc_load_firmware(dev);
1328 mutex_init(&dev->mfc_mutex);
1329 init_waitqueue_head(&dev->queue);
1331 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1332 atomic_set(&dev->watchdog_cnt, 0);
1333 timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0);
1335 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1337 goto err_v4l2_dev_reg;
1340 vfd = video_device_alloc();
1342 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1346 vfd->fops = &s5p_mfc_fops;
1347 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1348 vfd->release = video_device_release;
1349 vfd->lock = &dev->mfc_mutex;
1350 vfd->v4l2_dev = &dev->v4l2_dev;
1351 vfd->vfl_dir = VFL_DIR_M2M;
1352 set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags);
1353 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1355 video_set_drvdata(vfd, dev);
1358 vfd = video_device_alloc();
1360 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1364 vfd->fops = &s5p_mfc_fops;
1365 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1366 vfd->release = video_device_release;
1367 vfd->lock = &dev->mfc_mutex;
1368 vfd->v4l2_dev = &dev->v4l2_dev;
1369 vfd->vfl_dir = VFL_DIR_M2M;
1370 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1372 video_set_drvdata(vfd, dev);
1373 platform_set_drvdata(pdev, dev);
1375 /* Initialize HW ops and commands based on MFC version */
1376 s5p_mfc_init_hw_ops(dev);
1377 s5p_mfc_init_hw_cmds(dev);
1378 s5p_mfc_init_regs(dev);
1380 /* Register decoder and encoder */
1381 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1383 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1386 v4l2_info(&dev->v4l2_dev,
1387 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1389 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1391 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1394 v4l2_info(&dev->v4l2_dev,
1395 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1397 pr_debug("%s--\n", __func__);
1400 /* Deinit MFC if probe had failed */
1402 video_unregister_device(dev->vfd_dec);
1404 video_device_release(dev->vfd_enc);
1406 video_device_release(dev->vfd_dec);
1408 v4l2_device_unregister(&dev->v4l2_dev);
1410 s5p_mfc_final_pm(dev);
1412 s5p_mfc_unconfigure_dma_memory(dev);
1414 pr_debug("%s-- with error\n", __func__);
1419 /* Remove the driver */
1420 static int s5p_mfc_remove(struct platform_device *pdev)
1422 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1423 struct s5p_mfc_ctx *ctx;
1426 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1429 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1430 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1431 * after s5p_mfc_remove() is run during unbind.
1433 mutex_lock(&dev->mfc_mutex);
1434 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1438 /* clear ctx->dev */
1441 mutex_unlock(&dev->mfc_mutex);
1443 del_timer_sync(&dev->watchdog_timer);
1444 flush_work(&dev->watchdog_work);
1446 video_unregister_device(dev->vfd_enc);
1447 video_unregister_device(dev->vfd_dec);
1448 video_device_release(dev->vfd_enc);
1449 video_device_release(dev->vfd_dec);
1450 v4l2_device_unregister(&dev->v4l2_dev);
1451 s5p_mfc_unconfigure_dma_memory(dev);
1453 s5p_mfc_final_pm(dev);
1457 #ifdef CONFIG_PM_SLEEP
1459 static int s5p_mfc_suspend(struct device *dev)
1461 struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1464 if (m_dev->num_inst == 0)
1467 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1468 mfc_err("Error: going to suspend for a second time\n");
1472 /* Check if we're processing then wait if it necessary. */
1473 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1474 /* Try and lock the HW */
1475 /* Wait on the interrupt waitqueue */
1476 ret = wait_event_interruptible_timeout(m_dev->queue,
1477 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1479 mfc_err("Waiting for hardware to finish timed out\n");
1480 clear_bit(0, &m_dev->enter_suspend);
1485 ret = s5p_mfc_sleep(m_dev);
1487 clear_bit(0, &m_dev->enter_suspend);
1488 clear_bit(0, &m_dev->hw_lock);
1493 static int s5p_mfc_resume(struct device *dev)
1495 struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1497 if (m_dev->num_inst == 0)
1499 return s5p_mfc_wakeup(m_dev);
1503 /* Power management */
1504 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1505 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1508 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1509 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1510 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1511 .dsc = DESC_BUF_SIZE,
1512 .shm = SHARED_BUF_SIZE,
1515 static struct s5p_mfc_buf_size buf_size_v5 = {
1517 .cpb = MAX_CPB_SIZE,
1518 .priv = &mfc_buf_size_v5,
1521 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1522 .version = MFC_VERSION,
1523 .version_bit = MFC_V5_BIT,
1524 .port_num = MFC_NUM_PORTS,
1525 .buf_size = &buf_size_v5,
1526 .fw_name[0] = "s5p-mfc.fw",
1527 .clk_names = {"mfc", "sclk_mfc"},
1529 .use_clock_gating = true,
1532 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1533 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1534 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1535 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1536 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1537 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1540 static struct s5p_mfc_buf_size buf_size_v6 = {
1541 .fw = MAX_FW_SIZE_V6,
1542 .cpb = MAX_CPB_SIZE_V6,
1543 .priv = &mfc_buf_size_v6,
1546 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1547 .version = MFC_VERSION_V6,
1548 .version_bit = MFC_V6_BIT,
1549 .port_num = MFC_NUM_PORTS_V6,
1550 .buf_size = &buf_size_v6,
1551 .fw_name[0] = "s5p-mfc-v6.fw",
1553 * v6-v2 firmware contains bug fixes and interface change
1554 * for init buffer command
1556 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1557 .clk_names = {"mfc"},
1561 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1562 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1563 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1564 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1565 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1566 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1569 static struct s5p_mfc_buf_size buf_size_v7 = {
1570 .fw = MAX_FW_SIZE_V7,
1571 .cpb = MAX_CPB_SIZE_V7,
1572 .priv = &mfc_buf_size_v7,
1575 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1576 .version = MFC_VERSION_V7,
1577 .version_bit = MFC_V7_BIT,
1578 .port_num = MFC_NUM_PORTS_V7,
1579 .buf_size = &buf_size_v7,
1580 .fw_name[0] = "s5p-mfc-v7.fw",
1581 .clk_names = {"mfc", "sclk_mfc"},
1585 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1586 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1587 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1588 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1589 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1590 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1593 static struct s5p_mfc_buf_size buf_size_v8 = {
1594 .fw = MAX_FW_SIZE_V8,
1595 .cpb = MAX_CPB_SIZE_V8,
1596 .priv = &mfc_buf_size_v8,
1599 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1600 .version = MFC_VERSION_V8,
1601 .version_bit = MFC_V8_BIT,
1602 .port_num = MFC_NUM_PORTS_V8,
1603 .buf_size = &buf_size_v8,
1604 .fw_name[0] = "s5p-mfc-v8.fw",
1605 .clk_names = {"mfc"},
1609 static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1610 .version = MFC_VERSION_V8,
1611 .version_bit = MFC_V8_BIT,
1612 .port_num = MFC_NUM_PORTS_V8,
1613 .buf_size = &buf_size_v8,
1614 .fw_name[0] = "s5p-mfc-v8.fw",
1615 .clk_names = {"pclk", "aclk", "aclk_xiu"},
1619 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
1620 .dev_ctx = MFC_CTX_BUF_SIZE_V10,
1621 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V10,
1622 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
1623 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V10,
1624 .hevc_enc_ctx = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
1625 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
1628 static struct s5p_mfc_buf_size buf_size_v10 = {
1629 .fw = MAX_FW_SIZE_V10,
1630 .cpb = MAX_CPB_SIZE_V10,
1631 .priv = &mfc_buf_size_v10,
1634 static struct s5p_mfc_variant mfc_drvdata_v10 = {
1635 .version = MFC_VERSION_V10,
1636 .version_bit = MFC_V10_BIT,
1637 .port_num = MFC_NUM_PORTS_V10,
1638 .buf_size = &buf_size_v10,
1639 .fw_name[0] = "s5p-mfc-v10.fw",
1642 static const struct of_device_id exynos_mfc_match[] = {
1644 .compatible = "samsung,mfc-v5",
1645 .data = &mfc_drvdata_v5,
1647 .compatible = "samsung,mfc-v6",
1648 .data = &mfc_drvdata_v6,
1650 .compatible = "samsung,mfc-v7",
1651 .data = &mfc_drvdata_v7,
1653 .compatible = "samsung,mfc-v8",
1654 .data = &mfc_drvdata_v8,
1656 .compatible = "samsung,exynos5433-mfc",
1657 .data = &mfc_drvdata_v8_5433,
1659 .compatible = "samsung,mfc-v10",
1660 .data = &mfc_drvdata_v10,
1664 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1666 static struct platform_driver s5p_mfc_driver = {
1667 .probe = s5p_mfc_probe,
1668 .remove = s5p_mfc_remove,
1670 .name = S5P_MFC_NAME,
1671 .pm = &s5p_mfc_pm_ops,
1672 .of_match_table = exynos_mfc_match,
1676 module_platform_driver(s5p_mfc_driver);
1678 MODULE_LICENSE("GPL");
1679 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1680 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");