drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * camss-csiphy-2ph-1-0.c
   4  *
   5  * Qualcomm MSM Camera Subsystem - CSIPHY Module 2phase v1.0
   6  *
   7  * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
   8  * Copyright (C) 2016-2018 Linaro Ltd.
   9  */
  10
  11 #include "camss-csiphy.h"
  12
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16
  17 #define CAMSS_CSI_PHY_LNn_CFG2(n)               (0x004 + 0x40 * (n))
  18 #define CAMSS_CSI_PHY_LNn_CFG3(n)               (0x008 + 0x40 * (n))
  19 #define CAMSS_CSI_PHY_GLBL_RESET                0x140
  20 #define CAMSS_CSI_PHY_GLBL_PWR_CFG              0x144
  21 #define CAMSS_CSI_PHY_GLBL_IRQ_CMD              0x164
  22 #define CAMSS_CSI_PHY_HW_VERSION                0x188
  23 #define CAMSS_CSI_PHY_INTERRUPT_STATUSn(n)      (0x18c + 0x4 * (n))
  24 #define CAMSS_CSI_PHY_INTERRUPT_MASKn(n)        (0x1ac + 0x4 * (n))
  25 #define CAMSS_CSI_PHY_INTERRUPT_CLEARn(n)       (0x1cc + 0x4 * (n))
  26 #define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0          0x1ec
  27 #define CAMSS_CSI_PHY_T_WAKEUP_CFG0             0x1f4
  28
  29 static void csiphy_hw_version_read(struct csiphy_device *csiphy,
  30                                    struct device *dev)
  31 {
  32         u8 hw_version = readl_relaxed(csiphy->base +
  33                                       CAMSS_CSI_PHY_HW_VERSION);
  34
  35         dev_dbg(dev, "CSIPHY HW Version = 0x%02x\n", hw_version);
  36 }
  37
  38 /*
  39  * csiphy_reset - Perform software reset on CSIPHY module
  40  * @csiphy: CSIPHY device
  41  */
  42 static void csiphy_reset(struct csiphy_device *csiphy)
  43 {
  44         writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
  45         usleep_range(5000, 8000);
  46         writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
  47 }
  48
  49 /*
  50  * csiphy_settle_cnt_calc - Calculate settle count value
  51  *
  52  * Helper function to calculate settle count value. This is
  53  * based on the CSI2 T_hs_settle parameter which in turn
  54  * is calculated based on the CSI2 transmitter pixel clock
  55  * frequency.
  56  *
  57  * Return settle count value or 0 if the CSI2 pixel clock
  58  * frequency is not available
  59  */
  60 static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes,
  61                                  u32 timer_clk_rate)
  62 {
  63         u32 mipi_clock; /* Hz */
  64         u32 ui; /* ps */
  65         u32 timer_period; /* ps */
  66         u32 t_hs_prepare_max; /* ps */
  67         u32 t_hs_prepare_zero_min; /* ps */
  68         u32 t_hs_settle; /* ps */
  69         u8 settle_cnt;
  70
  71         mipi_clock = pixel_clock * bpp / (2 * num_lanes);
  72         ui = div_u64(1000000000000LL, mipi_clock);
  73         ui /= 2;
  74         t_hs_prepare_max = 85000 + 6 * ui;
  75         t_hs_prepare_zero_min = 145000 + 10 * ui;
  76         t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2;
  77
  78         timer_period = div_u64(1000000000000LL, timer_clk_rate);
  79         settle_cnt = t_hs_settle / timer_period - 1;
  80
  81         return settle_cnt;
  82 }
  83
  84 static void csiphy_lanes_enable(struct csiphy_device *csiphy,
  85                                 struct csiphy_config *cfg,
  86                                 u32 pixel_clock, u8 bpp, u8 lane_mask)
  87 {
  88         struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
  89         u8 settle_cnt;
  90         u8 val, l = 0;
  91         int i = 0;
  92
  93         settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data,
  94                                             csiphy->timer_clk_rate);
  95
  96         writel_relaxed(0x1, csiphy->base +
  97                        CAMSS_CSI_PHY_GLBL_T_INIT_CFG0);
  98         writel_relaxed(0x1, csiphy->base +
  99                        CAMSS_CSI_PHY_T_WAKEUP_CFG0);
 100
 101         val = 0x1;
 102         val |= lane_mask << 1;
 103         writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
 104
 105         val = cfg->combo_mode << 4;
 106         writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
 107
 108         for (i = 0; i <= c->num_data; i++) {
 109                 if (i == c->num_data)
 110                         l = c->clk.pos;
 111                 else
 112                         l = c->data[i].pos;
 113
 114                 writel_relaxed(0x10, csiphy->base +
 115                                CAMSS_CSI_PHY_LNn_CFG2(l));
 116                 writel_relaxed(settle_cnt, csiphy->base +
 117                                CAMSS_CSI_PHY_LNn_CFG3(l));
 118                 writel_relaxed(0x3f, csiphy->base +
 119                                CAMSS_CSI_PHY_INTERRUPT_MASKn(l));
 120                 writel_relaxed(0x3f, csiphy->base +
 121                                CAMSS_CSI_PHY_INTERRUPT_CLEARn(l));
 122         }
 123 }
 124
 125 static void csiphy_lanes_disable(struct csiphy_device *csiphy,
 126                                  struct csiphy_config *cfg)
 127 {
 128         struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
 129         u8 l = 0;
 130         int i = 0;
 131
 132         for (i = 0; i <= c->num_data; i++) {
 133                 if (i == c->num_data)
 134                         l = c->clk.pos;
 135                 else
 136                         l = c->data[i].pos;
 137
 138                 writel_relaxed(0x0, csiphy->base +
 139                                CAMSS_CSI_PHY_LNn_CFG2(l));
 140         }
 141
 142         writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
 143 }
 144
 145 /*
 146  * csiphy_isr - CSIPHY module interrupt handler
 147  * @irq: Interrupt line
 148  * @dev: CSIPHY device
 149  *
 150  * Return IRQ_HANDLED on success
 151  */
 152 static irqreturn_t csiphy_isr(int irq, void *dev)
 153 {
 154         struct csiphy_device *csiphy = dev;
 155         u8 i;
 156
 157         for (i = 0; i < 8; i++) {
 158                 u8 val = readl_relaxed(csiphy->base +
 159                                        CAMSS_CSI_PHY_INTERRUPT_STATUSn(i));
 160                 writel_relaxed(val, csiphy->base +
 161                                CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
 162                 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
 163                 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
 164                 writel_relaxed(0x0, csiphy->base +
 165                                CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
 166         }
 167
 168         return IRQ_HANDLED;
 169 }
 170
 171 const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = {
 172         .hw_version_read = csiphy_hw_version_read,
 173         .reset = csiphy_reset,
 174         .lanes_enable = csiphy_lanes_enable,
 175         .lanes_disable = csiphy_lanes_disable,
 176         .isr = csiphy_isr,
 177 };