[media] omap3isp: Remove boilerplate disclaimer and FSF address
[sfrench/cifs-2.6.git] / drivers / media / platform / omap3isp / ispreg.h
1 /*
2  * ispreg.h
3  *
4  * TI OMAP3 ISP - Registers definitions
5  *
6  * Copyright (C) 2010 Nokia Corporation
7  * Copyright (C) 2009 Texas Instruments, Inc
8  *
9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10  *           Sakari Ailus <sakari.ailus@iki.fi>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16
17 #ifndef OMAP3_ISP_REG_H
18 #define OMAP3_ISP_REG_H
19
20 #define CM_CAM_MCLK_HZ                  172800000       /* Hz */
21
22 /* ISP module register offset */
23
24 #define ISP_REVISION                    (0x000)
25 #define ISP_SYSCONFIG                   (0x004)
26 #define ISP_SYSSTATUS                   (0x008)
27 #define ISP_IRQ0ENABLE                  (0x00C)
28 #define ISP_IRQ0STATUS                  (0x010)
29 #define ISP_IRQ1ENABLE                  (0x014)
30 #define ISP_IRQ1STATUS                  (0x018)
31 #define ISP_TCTRL_GRESET_LENGTH         (0x030)
32 #define ISP_TCTRL_PSTRB_REPLAY          (0x034)
33 #define ISP_CTRL                        (0x040)
34 #define ISP_SECURE                      (0x044)
35 #define ISP_TCTRL_CTRL                  (0x050)
36 #define ISP_TCTRL_FRAME                 (0x054)
37 #define ISP_TCTRL_PSTRB_DELAY           (0x058)
38 #define ISP_TCTRL_STRB_DELAY            (0x05C)
39 #define ISP_TCTRL_SHUT_DELAY            (0x060)
40 #define ISP_TCTRL_PSTRB_LENGTH          (0x064)
41 #define ISP_TCTRL_STRB_LENGTH           (0x068)
42 #define ISP_TCTRL_SHUT_LENGTH           (0x06C)
43 #define ISP_PING_PONG_ADDR              (0x070)
44 #define ISP_PING_PONG_MEM_RANGE         (0x074)
45 #define ISP_PING_PONG_BUF_SIZE          (0x078)
46
47 /* CCP2 receiver registers */
48
49 #define ISPCCP2_REVISION                (0x000)
50 #define ISPCCP2_SYSCONFIG               (0x004)
51 #define ISPCCP2_SYSCONFIG_SOFT_RESET    (1 << 1)
52 #define ISPCCP2_SYSCONFIG_AUTO_IDLE             0x1
53 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT   12
54 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE   \
55         (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
56 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO      \
57         (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
58 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART   \
59         (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
60 #define ISPCCP2_SYSSTATUS               (0x008)
61 #define ISPCCP2_SYSSTATUS_RESET_DONE    (1 << 0)
62 #define ISPCCP2_LC01_IRQENABLE          (0x00C)
63 #define ISPCCP2_LC01_IRQSTATUS          (0x010)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ       (1 << 11)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ       (1 << 10)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ       (1 << 9)
67 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ       (1 << 8)
68 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ    (1 << 7)
69 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5)
70 #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ      (1 << 4)
71 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ      (1 << 3)
72 #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ       (1 << 2)
73 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ      (1 << 1)
74 #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ      (1 << 0)
75
76 #define ISPCCP2_LC23_IRQENABLE          (0x014)
77 #define ISPCCP2_LC23_IRQSTATUS          (0x018)
78 #define ISPCCP2_LCM_IRQENABLE           (0x02C)
79 #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ           (1 << 0)
80 #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ      (1 << 1)
81 #define ISPCCP2_LCM_IRQSTATUS           (0x030)
82 #define ISPCCP2_CTRL                    (0x040)
83 #define ISPCCP2_CTRL_IF_EN              (1 << 0)
84 #define ISPCCP2_CTRL_PHY_SEL            (1 << 1)
85 #define ISPCCP2_CTRL_PHY_SEL_CLOCK      (0 << 1)
86 #define ISPCCP2_CTRL_PHY_SEL_STROBE     (1 << 1)
87 #define ISPCCP2_CTRL_PHY_SEL_MASK       0x1
88 #define ISPCCP2_CTRL_PHY_SEL_SHIFT      1
89 #define ISPCCP2_CTRL_IO_OUT_SEL         (1 << 2)
90 #define ISPCCP2_CTRL_MODE               (1 << 4)
91 #define ISPCCP2_CTRL_VP_CLK_FORCE_ON    (1 << 9)
92 #define ISPCCP2_CTRL_INV                (1 << 10)
93 #define ISPCCP2_CTRL_INV_MASK           0x1
94 #define ISPCCP2_CTRL_INV_SHIFT          10
95 #define ISPCCP2_CTRL_VP_ONLY_EN         (1 << 11)
96 #define ISPCCP2_CTRL_VP_CLK_POL         (1 << 12)
97 #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT    15
98 #define ISPCCP2_CTRL_VPCLK_DIV_MASK     0x1ffff /* [31:15] */
99 #define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT  8 /* 3430 bits */
100 #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK   0x3 /* 3430 bits */
101 #define ISPCCP2_DBG                     (0x044)
102 #define ISPCCP2_GNQ                     (0x048)
103 #define ISPCCP2_LCx_CTRL(x)                     ((0x050)+0x30*(x))
104 #define ISPCCP2_LCx_CTRL_CHAN_EN                (1 << 0)
105 #define ISPCCP2_LCx_CTRL_CRC_EN                 (1 << 19)
106 #define ISPCCP2_LCx_CTRL_CRC_MASK               0x1
107 #define ISPCCP2_LCx_CTRL_CRC_SHIFT              2
108 #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0         19
109 #define ISPCCP2_LCx_CTRL_REGION_EN              (1 << 1)
110 #define ISPCCP2_LCx_CTRL_REGION_MASK            0x1
111 #define ISPCCP2_LCx_CTRL_REGION_SHIFT           1
112 #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0       0x3f
113 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0      0x2
114 #define ISPCCP2_LCx_CTRL_FORMAT_MASK            0x1f
115 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT           0x3
116 #define ISPCCP2_LCx_CODE(x)             ((0x054)+0x30*(x))
117 #define ISPCCP2_LCx_STAT_START(x)       ((0x058)+0x30*(x))
118 #define ISPCCP2_LCx_STAT_SIZE(x)        ((0x05C)+0x30*(x))
119 #define ISPCCP2_LCx_SOF_ADDR(x)         ((0x060)+0x30*(x))
120 #define ISPCCP2_LCx_EOF_ADDR(x)         ((0x064)+0x30*(x))
121 #define ISPCCP2_LCx_DAT_START(x)        ((0x068)+0x30*(x))
122 #define ISPCCP2_LCx_DAT_SIZE(x)         ((0x06C)+0x30*(x))
123 #define ISPCCP2_LCx_DAT_MASK            0xFFF
124 #define ISPCCP2_LCx_DAT_SHIFT           16
125 #define ISPCCP2_LCx_DAT_PING_ADDR(x)    ((0x070)+0x30*(x))
126 #define ISPCCP2_LCx_DAT_PONG_ADDR(x)    ((0x074)+0x30*(x))
127 #define ISPCCP2_LCx_DAT_OFST(x)         ((0x078)+0x30*(x))
128 #define ISPCCP2_LCM_CTRL                (0x1D0)
129 #define ISPCCP2_LCM_CTRL_CHAN_EN               (1 << 0)
130 #define ISPCCP2_LCM_CTRL_DST_PORT              (1 << 2)
131 #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT         2
132 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT    3
133 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK     0x11
134 #define ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT       5
135 #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK        0x7
136 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT       16
137 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK        0x7
138 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT      20
139 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK       0x3
140 #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED          (1 << 22)
141 #define ISPCCP2_LCM_CTRL_SRC_PACK               (1 << 23)
142 #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT       24
143 #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK        0x7
144 #define ISPCCP2_LCM_VSIZE               (0x1D4)
145 #define ISPCCP2_LCM_VSIZE_SHIFT         16
146 #define ISPCCP2_LCM_HSIZE               (0x1D8)
147 #define ISPCCP2_LCM_HSIZE_SHIFT         16
148 #define ISPCCP2_LCM_PREFETCH            (0x1DC)
149 #define ISPCCP2_LCM_PREFETCH_SHIFT      3
150 #define ISPCCP2_LCM_SRC_ADDR            (0x1E0)
151 #define ISPCCP2_LCM_SRC_OFST            (0x1E4)
152 #define ISPCCP2_LCM_DST_ADDR            (0x1E8)
153 #define ISPCCP2_LCM_DST_OFST            (0x1EC)
154
155 /* CCDC module register offset */
156
157 #define ISPCCDC_PID                     (0x000)
158 #define ISPCCDC_PCR                     (0x004)
159 #define ISPCCDC_SYN_MODE                (0x008)
160 #define ISPCCDC_HD_VD_WID               (0x00C)
161 #define ISPCCDC_PIX_LINES               (0x010)
162 #define ISPCCDC_HORZ_INFO               (0x014)
163 #define ISPCCDC_VERT_START              (0x018)
164 #define ISPCCDC_VERT_LINES              (0x01C)
165 #define ISPCCDC_CULLING                 (0x020)
166 #define ISPCCDC_HSIZE_OFF               (0x024)
167 #define ISPCCDC_SDOFST                  (0x028)
168 #define ISPCCDC_SDR_ADDR                (0x02C)
169 #define ISPCCDC_CLAMP                   (0x030)
170 #define ISPCCDC_DCSUB                   (0x034)
171 #define ISPCCDC_COLPTN                  (0x038)
172 #define ISPCCDC_BLKCMP                  (0x03C)
173 #define ISPCCDC_FPC                     (0x040)
174 #define ISPCCDC_FPC_ADDR                (0x044)
175 #define ISPCCDC_VDINT                   (0x048)
176 #define ISPCCDC_ALAW                    (0x04C)
177 #define ISPCCDC_REC656IF                (0x050)
178 #define ISPCCDC_CFG                     (0x054)
179 #define ISPCCDC_FMTCFG                  (0x058)
180 #define ISPCCDC_FMT_HORZ                (0x05C)
181 #define ISPCCDC_FMT_VERT                (0x060)
182 #define ISPCCDC_FMT_ADDR0               (0x064)
183 #define ISPCCDC_FMT_ADDR1               (0x068)
184 #define ISPCCDC_FMT_ADDR2               (0x06C)
185 #define ISPCCDC_FMT_ADDR3               (0x070)
186 #define ISPCCDC_FMT_ADDR4               (0x074)
187 #define ISPCCDC_FMT_ADDR5               (0x078)
188 #define ISPCCDC_FMT_ADDR6               (0x07C)
189 #define ISPCCDC_FMT_ADDR7               (0x080)
190 #define ISPCCDC_PRGEVEN0                (0x084)
191 #define ISPCCDC_PRGEVEN1                (0x088)
192 #define ISPCCDC_PRGODD0                 (0x08C)
193 #define ISPCCDC_PRGODD1                 (0x090)
194 #define ISPCCDC_VP_OUT                  (0x094)
195
196 #define ISPCCDC_LSC_CONFIG              (0x098)
197 #define ISPCCDC_LSC_INITIAL             (0x09C)
198 #define ISPCCDC_LSC_TABLE_BASE          (0x0A0)
199 #define ISPCCDC_LSC_TABLE_OFFSET        (0x0A4)
200
201 /* SBL */
202 #define ISPSBL_PCR                      0x4
203 #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF    (1 << 16)
204 #define ISPSBL_PCR_H3A_AF_WBL_OVF       (1 << 17)
205 #define ISPSBL_PCR_RSZ4_WBL_OVF         (1 << 18)
206 #define ISPSBL_PCR_RSZ3_WBL_OVF         (1 << 19)
207 #define ISPSBL_PCR_RSZ2_WBL_OVF         (1 << 20)
208 #define ISPSBL_PCR_RSZ1_WBL_OVF         (1 << 21)
209 #define ISPSBL_PCR_PRV_WBL_OVF          (1 << 22)
210 #define ISPSBL_PCR_CCDC_WBL_OVF         (1 << 23)
211 #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF    (1 << 24)
212 #define ISPSBL_PCR_CSIA_WBL_OVF         (1 << 25)
213 #define ISPSBL_PCR_CSIB_WBL_OVF         (1 << 26)
214 #define ISPSBL_CCDC_WR_0                (0x028)
215 #define ISPSBL_CCDC_WR_0_DATA_READY     (1 << 21)
216 #define ISPSBL_CCDC_WR_1                (0x02C)
217 #define ISPSBL_CCDC_WR_2                (0x030)
218 #define ISPSBL_CCDC_WR_3                (0x034)
219
220 #define ISPSBL_SDR_REQ_EXP              0xF8
221 #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT   0
222 #define ISPSBL_SDR_REQ_HIST_EXP_MASK    (0x3FF)
223 #define ISPSBL_SDR_REQ_RSZ_EXP_SHIFT    10
224 #define ISPSBL_SDR_REQ_RSZ_EXP_MASK     (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT)
225 #define ISPSBL_SDR_REQ_PRV_EXP_SHIFT    20
226 #define ISPSBL_SDR_REQ_PRV_EXP_MASK     (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT)
227
228 /* Histogram registers */
229 #define ISPHIST_PID                     (0x000)
230 #define ISPHIST_PCR                     (0x004)
231 #define ISPHIST_CNT                     (0x008)
232 #define ISPHIST_WB_GAIN                 (0x00C)
233 #define ISPHIST_R0_HORZ                 (0x010)
234 #define ISPHIST_R0_VERT                 (0x014)
235 #define ISPHIST_R1_HORZ                 (0x018)
236 #define ISPHIST_R1_VERT                 (0x01C)
237 #define ISPHIST_R2_HORZ                 (0x020)
238 #define ISPHIST_R2_VERT                 (0x024)
239 #define ISPHIST_R3_HORZ                 (0x028)
240 #define ISPHIST_R3_VERT                 (0x02C)
241 #define ISPHIST_ADDR                    (0x030)
242 #define ISPHIST_DATA                    (0x034)
243 #define ISPHIST_RADD                    (0x038)
244 #define ISPHIST_RADD_OFF                (0x03C)
245 #define ISPHIST_H_V_INFO                (0x040)
246
247 /* H3A module registers */
248 #define ISPH3A_PID                      (0x000)
249 #define ISPH3A_PCR                      (0x004)
250 #define ISPH3A_AEWWIN1                  (0x04C)
251 #define ISPH3A_AEWINSTART               (0x050)
252 #define ISPH3A_AEWINBLK                 (0x054)
253 #define ISPH3A_AEWSUBWIN                (0x058)
254 #define ISPH3A_AEWBUFST                 (0x05C)
255 #define ISPH3A_AFPAX1                   (0x008)
256 #define ISPH3A_AFPAX2                   (0x00C)
257 #define ISPH3A_AFPAXSTART               (0x010)
258 #define ISPH3A_AFIIRSH                  (0x014)
259 #define ISPH3A_AFBUFST                  (0x018)
260 #define ISPH3A_AFCOEF010                (0x01C)
261 #define ISPH3A_AFCOEF032                (0x020)
262 #define ISPH3A_AFCOEF054                (0x024)
263 #define ISPH3A_AFCOEF076                (0x028)
264 #define ISPH3A_AFCOEF098                (0x02C)
265 #define ISPH3A_AFCOEF0010               (0x030)
266 #define ISPH3A_AFCOEF110                (0x034)
267 #define ISPH3A_AFCOEF132                (0x038)
268 #define ISPH3A_AFCOEF154                (0x03C)
269 #define ISPH3A_AFCOEF176                (0x040)
270 #define ISPH3A_AFCOEF198                (0x044)
271 #define ISPH3A_AFCOEF1010               (0x048)
272
273 #define ISPPRV_PCR                      (0x004)
274 #define ISPPRV_HORZ_INFO                (0x008)
275 #define ISPPRV_VERT_INFO                (0x00C)
276 #define ISPPRV_RSDR_ADDR                (0x010)
277 #define ISPPRV_RADR_OFFSET              (0x014)
278 #define ISPPRV_DSDR_ADDR                (0x018)
279 #define ISPPRV_DRKF_OFFSET              (0x01C)
280 #define ISPPRV_WSDR_ADDR                (0x020)
281 #define ISPPRV_WADD_OFFSET              (0x024)
282 #define ISPPRV_AVE                      (0x028)
283 #define ISPPRV_HMED                     (0x02C)
284 #define ISPPRV_NF                       (0x030)
285 #define ISPPRV_WB_DGAIN                 (0x034)
286 #define ISPPRV_WBGAIN                   (0x038)
287 #define ISPPRV_WBSEL                    (0x03C)
288 #define ISPPRV_CFA                      (0x040)
289 #define ISPPRV_BLKADJOFF                (0x044)
290 #define ISPPRV_RGB_MAT1                 (0x048)
291 #define ISPPRV_RGB_MAT2                 (0x04C)
292 #define ISPPRV_RGB_MAT3                 (0x050)
293 #define ISPPRV_RGB_MAT4                 (0x054)
294 #define ISPPRV_RGB_MAT5                 (0x058)
295 #define ISPPRV_RGB_OFF1                 (0x05C)
296 #define ISPPRV_RGB_OFF2                 (0x060)
297 #define ISPPRV_CSC0                     (0x064)
298 #define ISPPRV_CSC1                     (0x068)
299 #define ISPPRV_CSC2                     (0x06C)
300 #define ISPPRV_CSC_OFFSET               (0x070)
301 #define ISPPRV_CNT_BRT                  (0x074)
302 #define ISPPRV_CSUP                     (0x078)
303 #define ISPPRV_SETUP_YC                 (0x07C)
304 #define ISPPRV_SET_TBL_ADDR             (0x080)
305 #define ISPPRV_SET_TBL_DATA             (0x084)
306 #define ISPPRV_CDC_THR0                 (0x090)
307 #define ISPPRV_CDC_THR1                 (ISPPRV_CDC_THR0 + (0x4))
308 #define ISPPRV_CDC_THR2                 (ISPPRV_CDC_THR0 + (0x4) * 2)
309 #define ISPPRV_CDC_THR3                 (ISPPRV_CDC_THR0 + (0x4) * 3)
310
311 #define ISPPRV_REDGAMMA_TABLE_ADDR      0x0000
312 #define ISPPRV_GREENGAMMA_TABLE_ADDR    0x0400
313 #define ISPPRV_BLUEGAMMA_TABLE_ADDR     0x0800
314 #define ISPPRV_NF_TABLE_ADDR            0x0C00
315 #define ISPPRV_YENH_TABLE_ADDR          0x1000
316 #define ISPPRV_CFA_TABLE_ADDR           0x1400
317
318 #define ISPRSZ_MIN_OUTPUT               64
319 #define ISPRSZ_MAX_OUTPUT               3312
320
321 /* Resizer module register offset */
322 #define ISPRSZ_PID                      (0x000)
323 #define ISPRSZ_PCR                      (0x004)
324 #define ISPRSZ_CNT                      (0x008)
325 #define ISPRSZ_OUT_SIZE                 (0x00C)
326 #define ISPRSZ_IN_START                 (0x010)
327 #define ISPRSZ_IN_SIZE                  (0x014)
328 #define ISPRSZ_SDR_INADD                (0x018)
329 #define ISPRSZ_SDR_INOFF                (0x01C)
330 #define ISPRSZ_SDR_OUTADD               (0x020)
331 #define ISPRSZ_SDR_OUTOFF               (0x024)
332 #define ISPRSZ_HFILT10                  (0x028)
333 #define ISPRSZ_HFILT32                  (0x02C)
334 #define ISPRSZ_HFILT54                  (0x030)
335 #define ISPRSZ_HFILT76                  (0x034)
336 #define ISPRSZ_HFILT98                  (0x038)
337 #define ISPRSZ_HFILT1110                (0x03C)
338 #define ISPRSZ_HFILT1312                (0x040)
339 #define ISPRSZ_HFILT1514                (0x044)
340 #define ISPRSZ_HFILT1716                (0x048)
341 #define ISPRSZ_HFILT1918                (0x04C)
342 #define ISPRSZ_HFILT2120                (0x050)
343 #define ISPRSZ_HFILT2322                (0x054)
344 #define ISPRSZ_HFILT2524                (0x058)
345 #define ISPRSZ_HFILT2726                (0x05C)
346 #define ISPRSZ_HFILT2928                (0x060)
347 #define ISPRSZ_HFILT3130                (0x064)
348 #define ISPRSZ_VFILT10                  (0x068)
349 #define ISPRSZ_VFILT32                  (0x06C)
350 #define ISPRSZ_VFILT54                  (0x070)
351 #define ISPRSZ_VFILT76                  (0x074)
352 #define ISPRSZ_VFILT98                  (0x078)
353 #define ISPRSZ_VFILT1110                (0x07C)
354 #define ISPRSZ_VFILT1312                (0x080)
355 #define ISPRSZ_VFILT1514                (0x084)
356 #define ISPRSZ_VFILT1716                (0x088)
357 #define ISPRSZ_VFILT1918                (0x08C)
358 #define ISPRSZ_VFILT2120                (0x090)
359 #define ISPRSZ_VFILT2322                (0x094)
360 #define ISPRSZ_VFILT2524                (0x098)
361 #define ISPRSZ_VFILT2726                (0x09C)
362 #define ISPRSZ_VFILT2928                (0x0A0)
363 #define ISPRSZ_VFILT3130                (0x0A4)
364 #define ISPRSZ_YENH                     (0x0A8)
365
366 #define ISP_INT_CLR                     0xFF113F11
367 #define ISPPRV_PCR_EN                   1
368 #define ISPPRV_PCR_BUSY                 (1 << 1)
369 #define ISPPRV_PCR_SOURCE               (1 << 2)
370 #define ISPPRV_PCR_ONESHOT              (1 << 3)
371 #define ISPPRV_PCR_WIDTH                (1 << 4)
372 #define ISPPRV_PCR_INVALAW              (1 << 5)
373 #define ISPPRV_PCR_DRKFEN               (1 << 6)
374 #define ISPPRV_PCR_DRKFCAP              (1 << 7)
375 #define ISPPRV_PCR_HMEDEN               (1 << 8)
376 #define ISPPRV_PCR_NFEN                 (1 << 9)
377 #define ISPPRV_PCR_CFAEN                (1 << 10)
378 #define ISPPRV_PCR_CFAFMT_SHIFT         11
379 #define ISPPRV_PCR_CFAFMT_MASK          0x7800
380 #define ISPPRV_PCR_CFAFMT_BAYER         (0 << 11)
381 #define ISPPRV_PCR_CFAFMT_SONYVGA       (1 << 11)
382 #define ISPPRV_PCR_CFAFMT_RGBFOVEON     (2 << 11)
383 #define ISPPRV_PCR_CFAFMT_DNSPL         (3 << 11)
384 #define ISPPRV_PCR_CFAFMT_HONEYCOMB     (4 << 11)
385 #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON  (5 << 11)
386 #define ISPPRV_PCR_YNENHEN              (1 << 15)
387 #define ISPPRV_PCR_SUPEN                (1 << 16)
388 #define ISPPRV_PCR_YCPOS_SHIFT          17
389 #define ISPPRV_PCR_YCPOS_YCrYCb         (0 << 17)
390 #define ISPPRV_PCR_YCPOS_YCbYCr         (1 << 17)
391 #define ISPPRV_PCR_YCPOS_CbYCrY         (2 << 17)
392 #define ISPPRV_PCR_YCPOS_CrYCbY         (3 << 17)
393 #define ISPPRV_PCR_RSZPORT              (1 << 19)
394 #define ISPPRV_PCR_SDRPORT              (1 << 20)
395 #define ISPPRV_PCR_SCOMP_EN             (1 << 21)
396 #define ISPPRV_PCR_SCOMP_SFT_SHIFT      (22)
397 #define ISPPRV_PCR_SCOMP_SFT_MASK       (7 << 22)
398 #define ISPPRV_PCR_GAMMA_BYPASS         (1 << 26)
399 #define ISPPRV_PCR_DCOREN               (1 << 27)
400 #define ISPPRV_PCR_DCCOUP               (1 << 28)
401 #define ISPPRV_PCR_DRK_FAIL             (1 << 31)
402
403 #define ISPPRV_HORZ_INFO_EPH_SHIFT      0
404 #define ISPPRV_HORZ_INFO_EPH_MASK       0x3fff
405 #define ISPPRV_HORZ_INFO_SPH_SHIFT      16
406 #define ISPPRV_HORZ_INFO_SPH_MASK       0x3fff0
407
408 #define ISPPRV_VERT_INFO_ELV_SHIFT      0
409 #define ISPPRV_VERT_INFO_ELV_MASK       0x3fff
410 #define ISPPRV_VERT_INFO_SLV_SHIFT      16
411 #define ISPPRV_VERT_INFO_SLV_MASK       0x3fff0
412
413 #define ISPPRV_AVE_EVENDIST_SHIFT       2
414 #define ISPPRV_AVE_EVENDIST_1           0x0
415 #define ISPPRV_AVE_EVENDIST_2           0x1
416 #define ISPPRV_AVE_EVENDIST_3           0x2
417 #define ISPPRV_AVE_EVENDIST_4           0x3
418 #define ISPPRV_AVE_ODDDIST_SHIFT        4
419 #define ISPPRV_AVE_ODDDIST_1            0x0
420 #define ISPPRV_AVE_ODDDIST_2            0x1
421 #define ISPPRV_AVE_ODDDIST_3            0x2
422 #define ISPPRV_AVE_ODDDIST_4            0x3
423
424 #define ISPPRV_HMED_THRESHOLD_SHIFT     0
425 #define ISPPRV_HMED_EVENDIST            (1 << 8)
426 #define ISPPRV_HMED_ODDDIST             (1 << 9)
427
428 #define ISPPRV_WBGAIN_COEF0_SHIFT       0
429 #define ISPPRV_WBGAIN_COEF1_SHIFT       8
430 #define ISPPRV_WBGAIN_COEF2_SHIFT       16
431 #define ISPPRV_WBGAIN_COEF3_SHIFT       24
432
433 #define ISPPRV_WBSEL_COEF0              0x0
434 #define ISPPRV_WBSEL_COEF1              0x1
435 #define ISPPRV_WBSEL_COEF2              0x2
436 #define ISPPRV_WBSEL_COEF3              0x3
437
438 #define ISPPRV_WBSEL_N0_0_SHIFT         0
439 #define ISPPRV_WBSEL_N0_1_SHIFT         2
440 #define ISPPRV_WBSEL_N0_2_SHIFT         4
441 #define ISPPRV_WBSEL_N0_3_SHIFT         6
442 #define ISPPRV_WBSEL_N1_0_SHIFT         8
443 #define ISPPRV_WBSEL_N1_1_SHIFT         10
444 #define ISPPRV_WBSEL_N1_2_SHIFT         12
445 #define ISPPRV_WBSEL_N1_3_SHIFT         14
446 #define ISPPRV_WBSEL_N2_0_SHIFT         16
447 #define ISPPRV_WBSEL_N2_1_SHIFT         18
448 #define ISPPRV_WBSEL_N2_2_SHIFT         20
449 #define ISPPRV_WBSEL_N2_3_SHIFT         22
450 #define ISPPRV_WBSEL_N3_0_SHIFT         24
451 #define ISPPRV_WBSEL_N3_1_SHIFT         26
452 #define ISPPRV_WBSEL_N3_2_SHIFT         28
453 #define ISPPRV_WBSEL_N3_3_SHIFT         30
454
455 #define ISPPRV_CFA_GRADTH_HOR_SHIFT     0
456 #define ISPPRV_CFA_GRADTH_VER_SHIFT     8
457
458 #define ISPPRV_BLKADJOFF_B_SHIFT        0
459 #define ISPPRV_BLKADJOFF_G_SHIFT        8
460 #define ISPPRV_BLKADJOFF_R_SHIFT        16
461
462 #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT    0
463 #define ISPPRV_RGB_MAT1_MTX_GR_SHIFT    16
464
465 #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT    0
466 #define ISPPRV_RGB_MAT2_MTX_RG_SHIFT    16
467
468 #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT    0
469 #define ISPPRV_RGB_MAT3_MTX_BG_SHIFT    16
470
471 #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT    0
472 #define ISPPRV_RGB_MAT4_MTX_GB_SHIFT    16
473
474 #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT    0
475
476 #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT  0
477 #define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT  16
478
479 #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT  0
480
481 #define ISPPRV_CSC0_RY_SHIFT            0
482 #define ISPPRV_CSC0_GY_SHIFT            10
483 #define ISPPRV_CSC0_BY_SHIFT            20
484
485 #define ISPPRV_CSC1_RCB_SHIFT           0
486 #define ISPPRV_CSC1_GCB_SHIFT           10
487 #define ISPPRV_CSC1_BCB_SHIFT           20
488
489 #define ISPPRV_CSC2_RCR_SHIFT           0
490 #define ISPPRV_CSC2_GCR_SHIFT           10
491 #define ISPPRV_CSC2_BCR_SHIFT           20
492
493 #define ISPPRV_CSC_OFFSET_CR_SHIFT      0
494 #define ISPPRV_CSC_OFFSET_CB_SHIFT      8
495 #define ISPPRV_CSC_OFFSET_Y_SHIFT       16
496
497 #define ISPPRV_CNT_BRT_BRT_SHIFT        0
498 #define ISPPRV_CNT_BRT_CNT_SHIFT        8
499
500 #define ISPPRV_CONTRAST_MAX             0x10
501 #define ISPPRV_CONTRAST_MIN             0xFF
502 #define ISPPRV_BRIGHT_MIN               0x00
503 #define ISPPRV_BRIGHT_MAX               0xFF
504
505 #define ISPPRV_CSUP_CSUPG_SHIFT         0
506 #define ISPPRV_CSUP_THRES_SHIFT         8
507 #define ISPPRV_CSUP_HPYF_SHIFT          16
508
509 #define ISPPRV_SETUP_YC_MINC_SHIFT      0
510 #define ISPPRV_SETUP_YC_MAXC_SHIFT      8
511 #define ISPPRV_SETUP_YC_MINY_SHIFT      16
512 #define ISPPRV_SETUP_YC_MAXY_SHIFT      24
513 #define ISPPRV_YC_MAX                   0xFF
514 #define ISPPRV_YC_MIN                   0x0
515
516 /* Define bit fields within selected registers */
517 #define ISP_REVISION_SHIFT                      0
518
519 #define ISP_SYSCONFIG_AUTOIDLE                  (1 << 0)
520 #define ISP_SYSCONFIG_SOFTRESET                 (1 << 1)
521 #define ISP_SYSCONFIG_MIDLEMODE_SHIFT           12
522 #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY    0x0
523 #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY        0x1
524 #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY    0x2
525
526 #define ISP_SYSSTATUS_RESETDONE                 0
527
528 #define IRQ0ENABLE_CSIA_IRQ                     (1 << 0)
529 #define IRQ0ENABLE_CSIC_IRQ                     (1 << 1)
530 #define IRQ0ENABLE_CCP2_LCM_IRQ                 (1 << 3)
531 #define IRQ0ENABLE_CCP2_LC0_IRQ                 (1 << 4)
532 #define IRQ0ENABLE_CCP2_LC1_IRQ                 (1 << 5)
533 #define IRQ0ENABLE_CCP2_LC2_IRQ                 (1 << 6)
534 #define IRQ0ENABLE_CCP2_LC3_IRQ                 (1 << 7)
535 #define IRQ0ENABLE_CSIB_IRQ                     (IRQ0ENABLE_CCP2_LCM_IRQ | \
536                                                 IRQ0ENABLE_CCP2_LC0_IRQ | \
537                                                 IRQ0ENABLE_CCP2_LC1_IRQ | \
538                                                 IRQ0ENABLE_CCP2_LC2_IRQ | \
539                                                 IRQ0ENABLE_CCP2_LC3_IRQ)
540
541 #define IRQ0ENABLE_CCDC_VD0_IRQ                 (1 << 8)
542 #define IRQ0ENABLE_CCDC_VD1_IRQ                 (1 << 9)
543 #define IRQ0ENABLE_CCDC_VD2_IRQ                 (1 << 10)
544 #define IRQ0ENABLE_CCDC_ERR_IRQ                 (1 << 11)
545 #define IRQ0ENABLE_H3A_AF_DONE_IRQ              (1 << 12)
546 #define IRQ0ENABLE_H3A_AWB_DONE_IRQ             (1 << 13)
547 #define IRQ0ENABLE_HIST_DONE_IRQ                (1 << 16)
548 #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ            (1 << 17)
549 #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ       (1 << 18)
550 #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ        (1 << 19)
551 #define IRQ0ENABLE_PRV_DONE_IRQ                 (1 << 20)
552 #define IRQ0ENABLE_RSZ_DONE_IRQ                 (1 << 24)
553 #define IRQ0ENABLE_OVF_IRQ                      (1 << 25)
554 #define IRQ0ENABLE_PING_IRQ                     (1 << 26)
555 #define IRQ0ENABLE_PONG_IRQ                     (1 << 27)
556 #define IRQ0ENABLE_MMU_ERR_IRQ                  (1 << 28)
557 #define IRQ0ENABLE_OCP_ERR_IRQ                  (1 << 29)
558 #define IRQ0ENABLE_SEC_ERR_IRQ                  (1 << 30)
559 #define IRQ0ENABLE_HS_VS_IRQ                    (1 << 31)
560
561 #define IRQ0STATUS_CSIA_IRQ                     (1 << 0)
562 #define IRQ0STATUS_CSI2C_IRQ                    (1 << 1)
563 #define IRQ0STATUS_CCP2_LCM_IRQ                 (1 << 3)
564 #define IRQ0STATUS_CCP2_LC0_IRQ                 (1 << 4)
565 #define IRQ0STATUS_CSIB_IRQ                     (IRQ0STATUS_CCP2_LCM_IRQ | \
566                                                 IRQ0STATUS_CCP2_LC0_IRQ)
567
568 #define IRQ0STATUS_CSIB_LC1_IRQ                 (1 << 5)
569 #define IRQ0STATUS_CSIB_LC2_IRQ                 (1 << 6)
570 #define IRQ0STATUS_CSIB_LC3_IRQ                 (1 << 7)
571 #define IRQ0STATUS_CCDC_VD0_IRQ                 (1 << 8)
572 #define IRQ0STATUS_CCDC_VD1_IRQ                 (1 << 9)
573 #define IRQ0STATUS_CCDC_VD2_IRQ                 (1 << 10)
574 #define IRQ0STATUS_CCDC_ERR_IRQ                 (1 << 11)
575 #define IRQ0STATUS_H3A_AF_DONE_IRQ              (1 << 12)
576 #define IRQ0STATUS_H3A_AWB_DONE_IRQ             (1 << 13)
577 #define IRQ0STATUS_HIST_DONE_IRQ                (1 << 16)
578 #define IRQ0STATUS_CCDC_LSC_DONE_IRQ            (1 << 17)
579 #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ       (1 << 18)
580 #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ        (1 << 19)
581 #define IRQ0STATUS_PRV_DONE_IRQ                 (1 << 20)
582 #define IRQ0STATUS_RSZ_DONE_IRQ                 (1 << 24)
583 #define IRQ0STATUS_OVF_IRQ                      (1 << 25)
584 #define IRQ0STATUS_PING_IRQ                     (1 << 26)
585 #define IRQ0STATUS_PONG_IRQ                     (1 << 27)
586 #define IRQ0STATUS_MMU_ERR_IRQ                  (1 << 28)
587 #define IRQ0STATUS_OCP_ERR_IRQ                  (1 << 29)
588 #define IRQ0STATUS_SEC_ERR_IRQ                  (1 << 30)
589 #define IRQ0STATUS_HS_VS_IRQ                    (1 << 31)
590
591 #define TCTRL_GRESET_LEN                        0
592
593 #define TCTRL_PSTRB_REPLAY_DELAY                0
594 #define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT        25
595
596 #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL        0x0
597 #define ISPCTRL_PAR_SER_CLK_SEL_CSIA            0x1
598 #define ISPCTRL_PAR_SER_CLK_SEL_CSIB            0x2
599 #define ISPCTRL_PAR_SER_CLK_SEL_CSIC            0x3
600 #define ISPCTRL_PAR_SER_CLK_SEL_MASK            0x3
601
602 #define ISPCTRL_PAR_BRIDGE_SHIFT                2
603 #define ISPCTRL_PAR_BRIDGE_DISABLE              (0x0 << 2)
604 #define ISPCTRL_PAR_BRIDGE_LENDIAN              (0x2 << 2)
605 #define ISPCTRL_PAR_BRIDGE_BENDIAN              (0x3 << 2)
606 #define ISPCTRL_PAR_BRIDGE_MASK                 (0x3 << 2)
607
608 #define ISPCTRL_PAR_CLK_POL_SHIFT               4
609 #define ISPCTRL_PAR_CLK_POL_INV                 (1 << 4)
610 #define ISPCTRL_PING_PONG_EN                    (1 << 5)
611 #define ISPCTRL_SHIFT_SHIFT                     6
612 #define ISPCTRL_SHIFT_0                         (0x0 << 6)
613 #define ISPCTRL_SHIFT_2                         (0x1 << 6)
614 #define ISPCTRL_SHIFT_4                         (0x2 << 6)
615 #define ISPCTRL_SHIFT_MASK                      (0x3 << 6)
616
617 #define ISPCTRL_CCDC_CLK_EN                     (1 << 8)
618 #define ISPCTRL_SCMP_CLK_EN                     (1 << 9)
619 #define ISPCTRL_H3A_CLK_EN                      (1 << 10)
620 #define ISPCTRL_HIST_CLK_EN                     (1 << 11)
621 #define ISPCTRL_PREV_CLK_EN                     (1 << 12)
622 #define ISPCTRL_RSZ_CLK_EN                      (1 << 13)
623 #define ISPCTRL_SYNC_DETECT_SHIFT               14
624 #define ISPCTRL_SYNC_DETECT_HSFALL      (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
625 #define ISPCTRL_SYNC_DETECT_HSRISE      (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
626 #define ISPCTRL_SYNC_DETECT_VSFALL      (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
627 #define ISPCTRL_SYNC_DETECT_VSRISE      (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
628 #define ISPCTRL_SYNC_DETECT_MASK        (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
629
630 #define ISPCTRL_CCDC_RAM_EN             (1 << 16)
631 #define ISPCTRL_PREV_RAM_EN             (1 << 17)
632 #define ISPCTRL_SBL_RD_RAM_EN           (1 << 18)
633 #define ISPCTRL_SBL_WR1_RAM_EN          (1 << 19)
634 #define ISPCTRL_SBL_WR0_RAM_EN          (1 << 20)
635 #define ISPCTRL_SBL_AUTOIDLE            (1 << 21)
636 #define ISPCTRL_SBL_SHARED_WPORTC       (1 << 26)
637 #define ISPCTRL_SBL_SHARED_RPORTA       (1 << 27)
638 #define ISPCTRL_SBL_SHARED_RPORTB       (1 << 28)
639 #define ISPCTRL_JPEG_FLUSH              (1 << 30)
640 #define ISPCTRL_CCDC_FLUSH              (1 << 31)
641
642 #define ISPSECURE_SECUREMODE            0
643
644 #define ISPTCTRL_CTRL_DIV_LOW           0x0
645 #define ISPTCTRL_CTRL_DIV_HIGH          0x1
646 #define ISPTCTRL_CTRL_DIV_BYPASS        0x1F
647
648 #define ISPTCTRL_CTRL_DIVA_SHIFT        0
649 #define ISPTCTRL_CTRL_DIVA_MASK         (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
650
651 #define ISPTCTRL_CTRL_DIVB_SHIFT        5
652 #define ISPTCTRL_CTRL_DIVB_MASK         (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
653
654 #define ISPTCTRL_CTRL_DIVC_SHIFT        10
655 #define ISPTCTRL_CTRL_DIVC_NOCLOCK      (0x0 << 10)
656
657 #define ISPTCTRL_CTRL_SHUTEN            (1 << 21)
658 #define ISPTCTRL_CTRL_PSTRBEN           (1 << 22)
659 #define ISPTCTRL_CTRL_STRBEN            (1 << 23)
660 #define ISPTCTRL_CTRL_SHUTPOL           (1 << 24)
661 #define ISPTCTRL_CTRL_STRBPSTRBPOL      (1 << 26)
662
663 #define ISPTCTRL_CTRL_INSEL_SHIFT       27
664 #define ISPTCTRL_CTRL_INSEL_PARALLEL    (0x0 << 27)
665 #define ISPTCTRL_CTRL_INSEL_CSIA        (0x1 << 27)
666 #define ISPTCTRL_CTRL_INSEL_CSIB        (0x2 << 27)
667
668 #define ISPTCTRL_CTRL_GRESETEn          (1 << 29)
669 #define ISPTCTRL_CTRL_GRESETPOL         (1 << 30)
670 #define ISPTCTRL_CTRL_GRESETDIR         (1 << 31)
671
672 #define ISPTCTRL_FRAME_SHUT_SHIFT               0
673 #define ISPTCTRL_FRAME_PSTRB_SHIFT              6
674 #define ISPTCTRL_FRAME_STRB_SHIFT               12
675
676 #define ISPCCDC_PID_PREV_SHIFT                  0
677 #define ISPCCDC_PID_CID_SHIFT                   8
678 #define ISPCCDC_PID_TID_SHIFT                   16
679
680 #define ISPCCDC_PCR_EN                          1
681 #define ISPCCDC_PCR_BUSY                        (1 << 1)
682
683 #define ISPCCDC_SYN_MODE_VDHDOUT                0x1
684 #define ISPCCDC_SYN_MODE_FLDOUT                 (1 << 1)
685 #define ISPCCDC_SYN_MODE_VDPOL                  (1 << 2)
686 #define ISPCCDC_SYN_MODE_HDPOL                  (1 << 3)
687 #define ISPCCDC_SYN_MODE_FLDPOL                 (1 << 4)
688 #define ISPCCDC_SYN_MODE_EXWEN                  (1 << 5)
689 #define ISPCCDC_SYN_MODE_DATAPOL                (1 << 6)
690 #define ISPCCDC_SYN_MODE_FLDMODE                (1 << 7)
691 #define ISPCCDC_SYN_MODE_DATSIZ_MASK            (0x7 << 8)
692 #define ISPCCDC_SYN_MODE_DATSIZ_8_16            (0x0 << 8)
693 #define ISPCCDC_SYN_MODE_DATSIZ_12              (0x4 << 8)
694 #define ISPCCDC_SYN_MODE_DATSIZ_11              (0x5 << 8)
695 #define ISPCCDC_SYN_MODE_DATSIZ_10              (0x6 << 8)
696 #define ISPCCDC_SYN_MODE_DATSIZ_8               (0x7 << 8)
697 #define ISPCCDC_SYN_MODE_PACK8                  (1 << 11)
698 #define ISPCCDC_SYN_MODE_INPMOD_MASK            (3 << 12)
699 #define ISPCCDC_SYN_MODE_INPMOD_RAW             (0 << 12)
700 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16         (1 << 12)
701 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8          (2 << 12)
702 #define ISPCCDC_SYN_MODE_LPF                    (1 << 14)
703 #define ISPCCDC_SYN_MODE_FLDSTAT                (1 << 15)
704 #define ISPCCDC_SYN_MODE_VDHDEN                 (1 << 16)
705 #define ISPCCDC_SYN_MODE_WEN                    (1 << 17)
706 #define ISPCCDC_SYN_MODE_VP2SDR                 (1 << 18)
707 #define ISPCCDC_SYN_MODE_SDR2RSZ                (1 << 19)
708
709 #define ISPCCDC_HD_VD_WID_VDW_SHIFT             0
710 #define ISPCCDC_HD_VD_WID_HDW_SHIFT             16
711
712 #define ISPCCDC_PIX_LINES_HLPRF_SHIFT           0
713 #define ISPCCDC_PIX_LINES_PPLN_SHIFT            16
714
715 #define ISPCCDC_HORZ_INFO_NPH_SHIFT             0
716 #define ISPCCDC_HORZ_INFO_NPH_MASK              0x00007fff
717 #define ISPCCDC_HORZ_INFO_SPH_SHIFT             16
718 #define ISPCCDC_HORZ_INFO_SPH_MASK              0x7fff0000
719
720 #define ISPCCDC_VERT_START_SLV1_SHIFT           0
721 #define ISPCCDC_VERT_START_SLV0_SHIFT           16
722 #define ISPCCDC_VERT_START_SLV0_MASK            0x7fff0000
723
724 #define ISPCCDC_VERT_LINES_NLV_SHIFT            0
725 #define ISPCCDC_VERT_LINES_NLV_MASK             0x00007fff
726
727 #define ISPCCDC_CULLING_CULV_SHIFT              0
728 #define ISPCCDC_CULLING_CULHODD_SHIFT           16
729 #define ISPCCDC_CULLING_CULHEVN_SHIFT           24
730
731 #define ISPCCDC_HSIZE_OFF_SHIFT                 0
732
733 #define ISPCCDC_SDOFST_FINV                     (1 << 14)
734 #define ISPCCDC_SDOFST_FOFST_1L                 0
735 #define ISPCCDC_SDOFST_FOFST_4L                 (3 << 12)
736 #define ISPCCDC_SDOFST_LOFST3_SHIFT             0
737 #define ISPCCDC_SDOFST_LOFST2_SHIFT             3
738 #define ISPCCDC_SDOFST_LOFST1_SHIFT             6
739 #define ISPCCDC_SDOFST_LOFST0_SHIFT             9
740 #define EVENEVEN                                1
741 #define ODDEVEN                                 2
742 #define EVENODD                                 3
743 #define ODDODD                                  4
744
745 #define ISPCCDC_CLAMP_OBGAIN_SHIFT              0
746 #define ISPCCDC_CLAMP_OBST_SHIFT                10
747 #define ISPCCDC_CLAMP_OBSLN_SHIFT               25
748 #define ISPCCDC_CLAMP_OBSLEN_SHIFT              28
749 #define ISPCCDC_CLAMP_CLAMPEN                   (1 << 31)
750
751 #define ISPCCDC_COLPTN_R_Ye                     0x0
752 #define ISPCCDC_COLPTN_Gr_Cy                    0x1
753 #define ISPCCDC_COLPTN_Gb_G                     0x2
754 #define ISPCCDC_COLPTN_B_Mg                     0x3
755 #define ISPCCDC_COLPTN_CP0PLC0_SHIFT            0
756 #define ISPCCDC_COLPTN_CP0PLC1_SHIFT            2
757 #define ISPCCDC_COLPTN_CP0PLC2_SHIFT            4
758 #define ISPCCDC_COLPTN_CP0PLC3_SHIFT            6
759 #define ISPCCDC_COLPTN_CP1PLC0_SHIFT            8
760 #define ISPCCDC_COLPTN_CP1PLC1_SHIFT            10
761 #define ISPCCDC_COLPTN_CP1PLC2_SHIFT            12
762 #define ISPCCDC_COLPTN_CP1PLC3_SHIFT            14
763 #define ISPCCDC_COLPTN_CP2PLC0_SHIFT            16
764 #define ISPCCDC_COLPTN_CP2PLC1_SHIFT            18
765 #define ISPCCDC_COLPTN_CP2PLC2_SHIFT            20
766 #define ISPCCDC_COLPTN_CP2PLC3_SHIFT            22
767 #define ISPCCDC_COLPTN_CP3PLC0_SHIFT            24
768 #define ISPCCDC_COLPTN_CP3PLC1_SHIFT            26
769 #define ISPCCDC_COLPTN_CP3PLC2_SHIFT            28
770 #define ISPCCDC_COLPTN_CP3PLC3_SHIFT            30
771
772 #define ISPCCDC_BLKCMP_B_MG_SHIFT               0
773 #define ISPCCDC_BLKCMP_GB_G_SHIFT               8
774 #define ISPCCDC_BLKCMP_GR_CY_SHIFT              16
775 #define ISPCCDC_BLKCMP_R_YE_SHIFT               24
776
777 #define ISPCCDC_FPC_FPNUM_SHIFT                 0
778 #define ISPCCDC_FPC_FPCEN                       (1 << 15)
779 #define ISPCCDC_FPC_FPERR                       (1 << 16)
780
781 #define ISPCCDC_VDINT_1_SHIFT                   0
782 #define ISPCCDC_VDINT_1_MASK                    0x00007fff
783 #define ISPCCDC_VDINT_0_SHIFT                   16
784 #define ISPCCDC_VDINT_0_MASK                    0x7fff0000
785
786 #define ISPCCDC_ALAW_GWDI_12_3                  (0x3 << 0)
787 #define ISPCCDC_ALAW_GWDI_11_2                  (0x4 << 0)
788 #define ISPCCDC_ALAW_GWDI_10_1                  (0x5 << 0)
789 #define ISPCCDC_ALAW_GWDI_9_0                   (0x6 << 0)
790 #define ISPCCDC_ALAW_CCDTBL                     (1 << 3)
791
792 #define ISPCCDC_REC656IF_R656ON                 1
793 #define ISPCCDC_REC656IF_ECCFVH                 (1 << 1)
794
795 #define ISPCCDC_CFG_BW656                       (1 << 5)
796 #define ISPCCDC_CFG_FIDMD_SHIFT                 6
797 #define ISPCCDC_CFG_WENLOG                      (1 << 8)
798 #define ISPCCDC_CFG_WENLOG_AND                  (0 << 8)
799 #define ISPCCDC_CFG_WENLOG_OR                   (1 << 8)
800 #define ISPCCDC_CFG_Y8POS                       (1 << 11)
801 #define ISPCCDC_CFG_BSWD                        (1 << 12)
802 #define ISPCCDC_CFG_MSBINVI                     (1 << 13)
803 #define ISPCCDC_CFG_VDLC                        (1 << 15)
804
805 #define ISPCCDC_FMTCFG_FMTEN                    0x1
806 #define ISPCCDC_FMTCFG_LNALT                    (1 << 1)
807 #define ISPCCDC_FMTCFG_LNUM_SHIFT               2
808 #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT           4
809 #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT          8
810 #define ISPCCDC_FMTCFG_VPIN_MASK                0x00007000
811 #define ISPCCDC_FMTCFG_VPIN_12_3                (0x3 << 12)
812 #define ISPCCDC_FMTCFG_VPIN_11_2                (0x4 << 12)
813 #define ISPCCDC_FMTCFG_VPIN_10_1                (0x5 << 12)
814 #define ISPCCDC_FMTCFG_VPIN_9_0                 (0x6 << 12)
815 #define ISPCCDC_FMTCFG_VPEN                     (1 << 15)
816
817 #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK            0x003f0000
818 #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT           16
819 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2             (0x0 << 16)
820 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3             (0x1 << 16)
821 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4             (0x2 << 16)
822 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5             (0x3 << 16)
823 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6             (0x4 << 16)
824
825 #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT           0
826 #define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT           16
827
828 #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT           0
829 #define ISPCCDC_FMT_VERT_FMTSLV_SHIFT           16
830
831 #define ISPCCDC_FMT_HORZ_FMTSPH_MASK            0x1fff0000
832 #define ISPCCDC_FMT_HORZ_FMTLNH_MASK            0x00001fff
833
834 #define ISPCCDC_FMT_VERT_FMTSLV_MASK            0x1fff0000
835 #define ISPCCDC_FMT_VERT_FMTLNV_MASK            0x00001fff
836
837 #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT            0
838 #define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT           4
839 #define ISPCCDC_VP_OUT_VERT_NUM_SHIFT           17
840
841 #define ISPRSZ_PID_PREV_SHIFT                   0
842 #define ISPRSZ_PID_CID_SHIFT                    8
843 #define ISPRSZ_PID_TID_SHIFT                    16
844
845 #define ISPRSZ_PCR_ENABLE                       (1 << 0)
846 #define ISPRSZ_PCR_BUSY                         (1 << 1)
847 #define ISPRSZ_PCR_ONESHOT                      (1 << 2)
848
849 #define ISPRSZ_CNT_HRSZ_SHIFT                   0
850 #define ISPRSZ_CNT_HRSZ_MASK                    \
851         (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT)
852 #define ISPRSZ_CNT_VRSZ_SHIFT                   10
853 #define ISPRSZ_CNT_VRSZ_MASK                    \
854         (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT)
855 #define ISPRSZ_CNT_HSTPH_SHIFT                  20
856 #define ISPRSZ_CNT_HSTPH_MASK                   (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
857 #define ISPRSZ_CNT_VSTPH_SHIFT                  23
858 #define ISPRSZ_CNT_VSTPH_MASK                   (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
859 #define ISPRSZ_CNT_YCPOS                        (1 << 26)
860 #define ISPRSZ_CNT_INPTYP                       (1 << 27)
861 #define ISPRSZ_CNT_INPSRC                       (1 << 28)
862 #define ISPRSZ_CNT_CBILIN                       (1 << 29)
863
864 #define ISPRSZ_OUT_SIZE_HORZ_SHIFT              0
865 #define ISPRSZ_OUT_SIZE_HORZ_MASK               \
866         (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT)
867 #define ISPRSZ_OUT_SIZE_VERT_SHIFT              16
868 #define ISPRSZ_OUT_SIZE_VERT_MASK               \
869         (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT)
870
871 #define ISPRSZ_IN_START_HORZ_ST_SHIFT           0
872 #define ISPRSZ_IN_START_HORZ_ST_MASK            \
873         (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT)
874 #define ISPRSZ_IN_START_VERT_ST_SHIFT           16
875 #define ISPRSZ_IN_START_VERT_ST_MASK            \
876         (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT)
877
878 #define ISPRSZ_IN_SIZE_HORZ_SHIFT               0
879 #define ISPRSZ_IN_SIZE_HORZ_MASK                \
880         (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT)
881 #define ISPRSZ_IN_SIZE_VERT_SHIFT               16
882 #define ISPRSZ_IN_SIZE_VERT_MASK                \
883         (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT)
884
885 #define ISPRSZ_SDR_INADD_ADDR_SHIFT             0
886 #define ISPRSZ_SDR_INADD_ADDR_MASK              0xFFFFFFFF
887
888 #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT           0
889 #define ISPRSZ_SDR_INOFF_OFFSET_MASK            \
890         (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT)
891
892 #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT            0
893 #define ISPRSZ_SDR_OUTADD_ADDR_MASK             0xFFFFFFFF
894
895
896 #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT          0
897 #define ISPRSZ_SDR_OUTOFF_OFFSET_MASK           \
898         (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT)
899
900 #define ISPRSZ_HFILT_COEF0_SHIFT                0
901 #define ISPRSZ_HFILT_COEF0_MASK                 \
902         (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT)
903 #define ISPRSZ_HFILT_COEF1_SHIFT                16
904 #define ISPRSZ_HFILT_COEF1_MASK                 \
905         (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT)
906
907 #define ISPRSZ_HFILT32_COEF2_SHIFT              0
908 #define ISPRSZ_HFILT32_COEF2_MASK               0x3FF
909 #define ISPRSZ_HFILT32_COEF3_SHIFT              16
910 #define ISPRSZ_HFILT32_COEF3_MASK               0x3FF0000
911
912 #define ISPRSZ_HFILT54_COEF4_SHIFT              0
913 #define ISPRSZ_HFILT54_COEF4_MASK               0x3FF
914 #define ISPRSZ_HFILT54_COEF5_SHIFT              16
915 #define ISPRSZ_HFILT54_COEF5_MASK               0x3FF0000
916
917 #define ISPRSZ_HFILT76_COEFF6_SHIFT             0
918 #define ISPRSZ_HFILT76_COEFF6_MASK              0x3FF
919 #define ISPRSZ_HFILT76_COEFF7_SHIFT             16
920 #define ISPRSZ_HFILT76_COEFF7_MASK              0x3FF0000
921
922 #define ISPRSZ_HFILT98_COEFF8_SHIFT             0
923 #define ISPRSZ_HFILT98_COEFF8_MASK              0x3FF
924 #define ISPRSZ_HFILT98_COEFF9_SHIFT             16
925 #define ISPRSZ_HFILT98_COEFF9_MASK              0x3FF0000
926
927 #define ISPRSZ_HFILT1110_COEF10_SHIFT           0
928 #define ISPRSZ_HFILT1110_COEF10_MASK            0x3FF
929 #define ISPRSZ_HFILT1110_COEF11_SHIFT           16
930 #define ISPRSZ_HFILT1110_COEF11_MASK            0x3FF0000
931
932 #define ISPRSZ_HFILT1312_COEFF12_SHIFT          0
933 #define ISPRSZ_HFILT1312_COEFF12_MASK           0x3FF
934 #define ISPRSZ_HFILT1312_COEFF13_SHIFT          16
935 #define ISPRSZ_HFILT1312_COEFF13_MASK           0x3FF0000
936
937 #define ISPRSZ_HFILT1514_COEFF14_SHIFT          0
938 #define ISPRSZ_HFILT1514_COEFF14_MASK           0x3FF
939 #define ISPRSZ_HFILT1514_COEFF15_SHIFT          16
940 #define ISPRSZ_HFILT1514_COEFF15_MASK           0x3FF0000
941
942 #define ISPRSZ_HFILT1716_COEF16_SHIFT           0
943 #define ISPRSZ_HFILT1716_COEF16_MASK            0x3FF
944 #define ISPRSZ_HFILT1716_COEF17_SHIFT           16
945 #define ISPRSZ_HFILT1716_COEF17_MASK            0x3FF0000
946
947 #define ISPRSZ_HFILT1918_COEF18_SHIFT           0
948 #define ISPRSZ_HFILT1918_COEF18_MASK            0x3FF
949 #define ISPRSZ_HFILT1918_COEF19_SHIFT           16
950 #define ISPRSZ_HFILT1918_COEF19_MASK            0x3FF0000
951
952 #define ISPRSZ_HFILT2120_COEF20_SHIFT           0
953 #define ISPRSZ_HFILT2120_COEF20_MASK            0x3FF
954 #define ISPRSZ_HFILT2120_COEF21_SHIFT           16
955 #define ISPRSZ_HFILT2120_COEF21_MASK            0x3FF0000
956
957 #define ISPRSZ_HFILT2322_COEF22_SHIFT           0
958 #define ISPRSZ_HFILT2322_COEF22_MASK            0x3FF
959 #define ISPRSZ_HFILT2322_COEF23_SHIFT           16
960 #define ISPRSZ_HFILT2322_COEF23_MASK            0x3FF0000
961
962 #define ISPRSZ_HFILT2524_COEF24_SHIFT           0
963 #define ISPRSZ_HFILT2524_COEF24_MASK            0x3FF
964 #define ISPRSZ_HFILT2524_COEF25_SHIFT           16
965 #define ISPRSZ_HFILT2524_COEF25_MASK            0x3FF0000
966
967 #define ISPRSZ_HFILT2726_COEF26_SHIFT           0
968 #define ISPRSZ_HFILT2726_COEF26_MASK            0x3FF
969 #define ISPRSZ_HFILT2726_COEF27_SHIFT           16
970 #define ISPRSZ_HFILT2726_COEF27_MASK            0x3FF0000
971
972 #define ISPRSZ_HFILT2928_COEF28_SHIFT           0
973 #define ISPRSZ_HFILT2928_COEF28_MASK            0x3FF
974 #define ISPRSZ_HFILT2928_COEF29_SHIFT           16
975 #define ISPRSZ_HFILT2928_COEF29_MASK            0x3FF0000
976
977 #define ISPRSZ_HFILT3130_COEF30_SHIFT           0
978 #define ISPRSZ_HFILT3130_COEF30_MASK            0x3FF
979 #define ISPRSZ_HFILT3130_COEF31_SHIFT           16
980 #define ISPRSZ_HFILT3130_COEF31_MASK            0x3FF0000
981
982 #define ISPRSZ_VFILT_COEF0_SHIFT                0
983 #define ISPRSZ_VFILT_COEF0_MASK                 \
984         (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT)
985 #define ISPRSZ_VFILT_COEF1_SHIFT                16
986 #define ISPRSZ_VFILT_COEF1_MASK                 \
987         (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT)
988
989 #define ISPRSZ_VFILT10_COEF0_SHIFT              0
990 #define ISPRSZ_VFILT10_COEF0_MASK               0x3FF
991 #define ISPRSZ_VFILT10_COEF1_SHIFT              16
992 #define ISPRSZ_VFILT10_COEF1_MASK               0x3FF0000
993
994 #define ISPRSZ_VFILT32_COEF2_SHIFT              0
995 #define ISPRSZ_VFILT32_COEF2_MASK               0x3FF
996 #define ISPRSZ_VFILT32_COEF3_SHIFT              16
997 #define ISPRSZ_VFILT32_COEF3_MASK               0x3FF0000
998
999 #define ISPRSZ_VFILT54_COEF4_SHIFT              0
1000 #define ISPRSZ_VFILT54_COEF4_MASK               0x3FF
1001 #define ISPRSZ_VFILT54_COEF5_SHIFT              16
1002 #define ISPRSZ_VFILT54_COEF5_MASK               0x3FF0000
1003
1004 #define ISPRSZ_VFILT76_COEFF6_SHIFT             0
1005 #define ISPRSZ_VFILT76_COEFF6_MASK              0x3FF
1006 #define ISPRSZ_VFILT76_COEFF7_SHIFT             16
1007 #define ISPRSZ_VFILT76_COEFF7_MASK              0x3FF0000
1008
1009 #define ISPRSZ_VFILT98_COEFF8_SHIFT             0
1010 #define ISPRSZ_VFILT98_COEFF8_MASK              0x3FF
1011 #define ISPRSZ_VFILT98_COEFF9_SHIFT             16
1012 #define ISPRSZ_VFILT98_COEFF9_MASK              0x3FF0000
1013
1014 #define ISPRSZ_VFILT1110_COEF10_SHIFT           0
1015 #define ISPRSZ_VFILT1110_COEF10_MASK            0x3FF
1016 #define ISPRSZ_VFILT1110_COEF11_SHIFT           16
1017 #define ISPRSZ_VFILT1110_COEF11_MASK            0x3FF0000
1018
1019 #define ISPRSZ_VFILT1312_COEFF12_SHIFT          0
1020 #define ISPRSZ_VFILT1312_COEFF12_MASK           0x3FF
1021 #define ISPRSZ_VFILT1312_COEFF13_SHIFT          16
1022 #define ISPRSZ_VFILT1312_COEFF13_MASK           0x3FF0000
1023
1024 #define ISPRSZ_VFILT1514_COEFF14_SHIFT          0
1025 #define ISPRSZ_VFILT1514_COEFF14_MASK           0x3FF
1026 #define ISPRSZ_VFILT1514_COEFF15_SHIFT          16
1027 #define ISPRSZ_VFILT1514_COEFF15_MASK           0x3FF0000
1028
1029 #define ISPRSZ_VFILT1716_COEF16_SHIFT           0
1030 #define ISPRSZ_VFILT1716_COEF16_MASK            0x3FF
1031 #define ISPRSZ_VFILT1716_COEF17_SHIFT           16
1032 #define ISPRSZ_VFILT1716_COEF17_MASK            0x3FF0000
1033
1034 #define ISPRSZ_VFILT1918_COEF18_SHIFT           0
1035 #define ISPRSZ_VFILT1918_COEF18_MASK            0x3FF
1036 #define ISPRSZ_VFILT1918_COEF19_SHIFT           16
1037 #define ISPRSZ_VFILT1918_COEF19_MASK            0x3FF0000
1038
1039 #define ISPRSZ_VFILT2120_COEF20_SHIFT           0
1040 #define ISPRSZ_VFILT2120_COEF20_MASK            0x3FF
1041 #define ISPRSZ_VFILT2120_COEF21_SHIFT           16
1042 #define ISPRSZ_VFILT2120_COEF21_MASK            0x3FF0000
1043
1044 #define ISPRSZ_VFILT2322_COEF22_SHIFT           0
1045 #define ISPRSZ_VFILT2322_COEF22_MASK            0x3FF
1046 #define ISPRSZ_VFILT2322_COEF23_SHIFT           16
1047 #define ISPRSZ_VFILT2322_COEF23_MASK            0x3FF0000
1048
1049 #define ISPRSZ_VFILT2524_COEF24_SHIFT           0
1050 #define ISPRSZ_VFILT2524_COEF24_MASK            0x3FF
1051 #define ISPRSZ_VFILT2524_COEF25_SHIFT           16
1052 #define ISPRSZ_VFILT2524_COEF25_MASK            0x3FF0000
1053
1054 #define ISPRSZ_VFILT2726_COEF26_SHIFT           0
1055 #define ISPRSZ_VFILT2726_COEF26_MASK            0x3FF
1056 #define ISPRSZ_VFILT2726_COEF27_SHIFT           16
1057 #define ISPRSZ_VFILT2726_COEF27_MASK            0x3FF0000
1058
1059 #define ISPRSZ_VFILT2928_COEF28_SHIFT           0
1060 #define ISPRSZ_VFILT2928_COEF28_MASK            0x3FF
1061 #define ISPRSZ_VFILT2928_COEF29_SHIFT           16
1062 #define ISPRSZ_VFILT2928_COEF29_MASK            0x3FF0000
1063
1064 #define ISPRSZ_VFILT3130_COEF30_SHIFT           0
1065 #define ISPRSZ_VFILT3130_COEF30_MASK            0x3FF
1066 #define ISPRSZ_VFILT3130_COEF31_SHIFT           16
1067 #define ISPRSZ_VFILT3130_COEF31_MASK            0x3FF0000
1068
1069 #define ISPRSZ_YENH_CORE_SHIFT                  0
1070 #define ISPRSZ_YENH_CORE_MASK                   \
1071         (0xFF << ISPRSZ_YENH_CORE_SHIFT)
1072 #define ISPRSZ_YENH_SLOP_SHIFT                  8
1073 #define ISPRSZ_YENH_SLOP_MASK                   \
1074         (0xF << ISPRSZ_YENH_SLOP_SHIFT)
1075 #define ISPRSZ_YENH_GAIN_SHIFT                  12
1076 #define ISPRSZ_YENH_GAIN_MASK                   \
1077         (0xF << ISPRSZ_YENH_GAIN_SHIFT)
1078 #define ISPRSZ_YENH_ALGO_SHIFT                  16
1079 #define ISPRSZ_YENH_ALGO_MASK                   \
1080         (0x3 << ISPRSZ_YENH_ALGO_SHIFT)
1081
1082 #define ISPH3A_PCR_AEW_ALAW_EN_SHIFT            1
1083 #define ISPH3A_PCR_AF_MED_TH_SHIFT              3
1084 #define ISPH3A_PCR_AF_RGBPOS_SHIFT              11
1085 #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT            22
1086 #define ISPH3A_PCR_AEW_AVE2LMT_MASK             0xFFC00000
1087 #define ISPH3A_PCR_BUSYAF                       (1 << 15)
1088 #define ISPH3A_PCR_BUSYAEAWB                    (1 << 18)
1089
1090 #define ISPH3A_AEWWIN1_WINHC_SHIFT              0
1091 #define ISPH3A_AEWWIN1_WINHC_MASK               0x3F
1092 #define ISPH3A_AEWWIN1_WINVC_SHIFT              6
1093 #define ISPH3A_AEWWIN1_WINVC_MASK               0x1FC0
1094 #define ISPH3A_AEWWIN1_WINW_SHIFT               13
1095 #define ISPH3A_AEWWIN1_WINW_MASK                0xFE000
1096 #define ISPH3A_AEWWIN1_WINH_SHIFT               24
1097 #define ISPH3A_AEWWIN1_WINH_MASK                0x7F000000
1098
1099 #define ISPH3A_AEWINSTART_WINSH_SHIFT           0
1100 #define ISPH3A_AEWINSTART_WINSH_MASK            0x0FFF
1101 #define ISPH3A_AEWINSTART_WINSV_SHIFT           16
1102 #define ISPH3A_AEWINSTART_WINSV_MASK            0x0FFF0000
1103
1104 #define ISPH3A_AEWINBLK_WINH_SHIFT              0
1105 #define ISPH3A_AEWINBLK_WINH_MASK               0x7F
1106 #define ISPH3A_AEWINBLK_WINSV_SHIFT             16
1107 #define ISPH3A_AEWINBLK_WINSV_MASK              0x0FFF0000
1108
1109 #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT          0
1110 #define ISPH3A_AEWSUBWIN_AEWINCH_MASK           0x0F
1111 #define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT          8
1112 #define ISPH3A_AEWSUBWIN_AEWINCV_MASK           0x0F00
1113
1114 #define ISPHIST_PCR_ENABLE_SHIFT        0
1115 #define ISPHIST_PCR_ENABLE_MASK         0x01
1116 #define ISPHIST_PCR_ENABLE              (1 << ISPHIST_PCR_ENABLE_SHIFT)
1117 #define ISPHIST_PCR_BUSY                0x02
1118
1119 #define ISPHIST_CNT_DATASIZE_SHIFT      8
1120 #define ISPHIST_CNT_DATASIZE_MASK       0x0100
1121 #define ISPHIST_CNT_CLEAR_SHIFT         7
1122 #define ISPHIST_CNT_CLEAR_MASK          0x080
1123 #define ISPHIST_CNT_CLEAR               (1 << ISPHIST_CNT_CLEAR_SHIFT)
1124 #define ISPHIST_CNT_CFA_SHIFT           6
1125 #define ISPHIST_CNT_CFA_MASK            0x040
1126 #define ISPHIST_CNT_BINS_SHIFT          4
1127 #define ISPHIST_CNT_BINS_MASK           0x030
1128 #define ISPHIST_CNT_SOURCE_SHIFT        3
1129 #define ISPHIST_CNT_SOURCE_MASK         0x08
1130 #define ISPHIST_CNT_SHIFT_SHIFT         0
1131 #define ISPHIST_CNT_SHIFT_MASK          0x07
1132
1133 #define ISPHIST_WB_GAIN_WG00_SHIFT      24
1134 #define ISPHIST_WB_GAIN_WG00_MASK       0xFF000000
1135 #define ISPHIST_WB_GAIN_WG01_SHIFT      16
1136 #define ISPHIST_WB_GAIN_WG01_MASK       0xFF0000
1137 #define ISPHIST_WB_GAIN_WG02_SHIFT      8
1138 #define ISPHIST_WB_GAIN_WG02_MASK       0xFF00
1139 #define ISPHIST_WB_GAIN_WG03_SHIFT      0
1140 #define ISPHIST_WB_GAIN_WG03_MASK       0xFF
1141
1142 #define ISPHIST_REG_START_END_MASK              0x3FFF
1143 #define ISPHIST_REG_START_SHIFT                 16
1144 #define ISPHIST_REG_END_SHIFT                   0
1145 #define ISPHIST_REG_START_MASK                  (ISPHIST_REG_START_END_MASK << \
1146                                                  ISPHIST_REG_START_SHIFT)
1147 #define ISPHIST_REG_END_MASK                    (ISPHIST_REG_START_END_MASK << \
1148                                                  ISPHIST_REG_END_SHIFT)
1149
1150 #define ISPHIST_REG_MASK                        (ISPHIST_REG_START_MASK | \
1151                                                  ISPHIST_REG_END_MASK)
1152
1153 #define ISPHIST_ADDR_SHIFT                      0
1154 #define ISPHIST_ADDR_MASK                       0x3FF
1155
1156 #define ISPHIST_DATA_SHIFT                      0
1157 #define ISPHIST_DATA_MASK                       0xFFFFF
1158
1159 #define ISPHIST_RADD_SHIFT                      0
1160 #define ISPHIST_RADD_MASK                       0xFFFFFFFF
1161
1162 #define ISPHIST_RADD_OFF_SHIFT                  0
1163 #define ISPHIST_RADD_OFF_MASK                   0xFFFF
1164
1165 #define ISPHIST_HV_INFO_HSIZE_SHIFT             16
1166 #define ISPHIST_HV_INFO_HSIZE_MASK              0x3FFF0000
1167 #define ISPHIST_HV_INFO_VSIZE_SHIFT             0
1168 #define ISPHIST_HV_INFO_VSIZE_MASK              0x3FFF
1169
1170 #define ISPHIST_HV_INFO_MASK                    0x3FFF3FFF
1171
1172 #define ISPCCDC_LSC_ENABLE                      1
1173 #define ISPCCDC_LSC_BUSY                        (1 << 7)
1174 #define ISPCCDC_LSC_GAIN_MODE_N_MASK            0x700
1175 #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT           8
1176 #define ISPCCDC_LSC_GAIN_MODE_M_MASK            0x3800
1177 #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT           12
1178 #define ISPCCDC_LSC_GAIN_FORMAT_MASK            0xE
1179 #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT           1
1180 #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK      (1<<6)
1181
1182 #define ISPCCDC_LSC_INITIAL_X_MASK              0x3F
1183 #define ISPCCDC_LSC_INITIAL_X_SHIFT             0
1184 #define ISPCCDC_LSC_INITIAL_Y_MASK              0x3F0000
1185 #define ISPCCDC_LSC_INITIAL_Y_SHIFT             16
1186
1187 /* -----------------------------------------------------------------------------
1188  * CSI2 receiver registers (ES2.0)
1189  */
1190
1191 #define ISPCSI2_REVISION                        (0x000)
1192 #define ISPCSI2_SYSCONFIG                       (0x010)
1193 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT   12
1194 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK    \
1195         (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1196 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE   \
1197         (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1198 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO      \
1199         (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1200 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART   \
1201         (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1202 #define ISPCSI2_SYSCONFIG_SOFT_RESET            (1 << 1)
1203 #define ISPCSI2_SYSCONFIG_AUTO_IDLE             (1 << 0)
1204
1205 #define ISPCSI2_SYSSTATUS                       (0x014)
1206 #define ISPCSI2_SYSSTATUS_RESET_DONE            (1 << 0)
1207
1208 #define ISPCSI2_IRQSTATUS                       (0x018)
1209 #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ           (1 << 14)
1210 #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ      (1 << 13)
1211 #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ    (1 << 12)
1212 #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11)
1213 #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ    (1 << 10)
1214 #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ    (1 << 9)
1215 #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ          (1 << 8)
1216 #define ISPCSI2_IRQSTATUS_CONTEXT(n)            (1 << (n))
1217
1218 #define ISPCSI2_IRQENABLE                       (0x01c)
1219 #define ISPCSI2_CTRL                            (0x040)
1220 #define ISPCSI2_CTRL_VP_CLK_EN                  (1 << 15)
1221 #define ISPCSI2_CTRL_VP_ONLY_EN                 (1 << 11)
1222 #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT          8
1223 #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK           \
1224         (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
1225 #define ISPCSI2_CTRL_DBG_EN                     (1 << 7)
1226 #define ISPCSI2_CTRL_BURST_SIZE_SHIFT           5
1227 #define ISPCSI2_CTRL_BURST_SIZE_MASK            \
1228         (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT)
1229 #define ISPCSI2_CTRL_FRAME                      (1 << 3)
1230 #define ISPCSI2_CTRL_ECC_EN                     (1 << 2)
1231 #define ISPCSI2_CTRL_SECURE                     (1 << 1)
1232 #define ISPCSI2_CTRL_IF_EN                      (1 << 0)
1233
1234 #define ISPCSI2_DBG_H                           (0x044)
1235 #define ISPCSI2_GNQ                             (0x048)
1236 #define ISPCSI2_PHY_CFG                         (0x050)
1237 #define ISPCSI2_PHY_CFG_RESET_CTRL              (1 << 30)
1238 #define ISPCSI2_PHY_CFG_RESET_DONE              (1 << 29)
1239 #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT           27
1240 #define ISPCSI2_PHY_CFG_PWR_CMD_MASK            \
1241         (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1242 #define ISPCSI2_PHY_CFG_PWR_CMD_OFF             \
1243         (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1244 #define ISPCSI2_PHY_CFG_PWR_CMD_ON              \
1245         (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1246 #define ISPCSI2_PHY_CFG_PWR_CMD_ULPW            \
1247         (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1248 #define ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT        25
1249 #define ISPCSI2_PHY_CFG_PWR_STATUS_MASK         \
1250         (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1251 #define ISPCSI2_PHY_CFG_PWR_STATUS_OFF          \
1252         (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1253 #define ISPCSI2_PHY_CFG_PWR_STATUS_ON           \
1254         (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1255 #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW         \
1256         (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1257 #define ISPCSI2_PHY_CFG_PWR_AUTO                (1 << 24)
1258
1259 #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)       (3 + ((n) * 4))
1260 #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n)        \
1261         (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1262 #define ISPCSI2_PHY_CFG_DATA_POL_PN(n)          \
1263         (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1264 #define ISPCSI2_PHY_CFG_DATA_POL_NP(n)          \
1265         (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1266
1267 #define ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)  ((n) * 4)
1268 #define ISPCSI2_PHY_CFG_DATA_POSITION_MASK(n)   \
1269         (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1270 #define ISPCSI2_PHY_CFG_DATA_POSITION_NC(n)     \
1271         (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1272 #define ISPCSI2_PHY_CFG_DATA_POSITION_1(n)      \
1273         (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1274 #define ISPCSI2_PHY_CFG_DATA_POSITION_2(n)      \
1275         (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1276 #define ISPCSI2_PHY_CFG_DATA_POSITION_3(n)      \
1277         (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1278 #define ISPCSI2_PHY_CFG_DATA_POSITION_4(n)      \
1279         (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1280 #define ISPCSI2_PHY_CFG_DATA_POSITION_5(n)      \
1281         (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1282
1283 #define ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT         3
1284 #define ISPCSI2_PHY_CFG_CLOCK_POL_MASK          \
1285         (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1286 #define ISPCSI2_PHY_CFG_CLOCK_POL_PN            \
1287         (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1288 #define ISPCSI2_PHY_CFG_CLOCK_POL_NP            \
1289         (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1290
1291 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT    0
1292 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK     \
1293         (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1294 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_1        \
1295         (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1296 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_2        \
1297         (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1298 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_3        \
1299         (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1300 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_4        \
1301         (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1302 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_5        \
1303         (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1304
1305 #define ISPCSI2_PHY_IRQSTATUS                   (0x054)
1306 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT  (1 << 26)
1307 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25)
1308 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5        (1 << 24)
1309 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4        (1 << 23)
1310 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3        (1 << 22)
1311 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2        (1 << 21)
1312 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1        (1 << 20)
1313 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5       (1 << 19)
1314 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4       (1 << 18)
1315 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3       (1 << 17)
1316 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2       (1 << 16)
1317 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1       (1 << 15)
1318 #define ISPCSI2_PHY_IRQSTATUS_ERRESC5           (1 << 14)
1319 #define ISPCSI2_PHY_IRQSTATUS_ERRESC4           (1 << 13)
1320 #define ISPCSI2_PHY_IRQSTATUS_ERRESC3           (1 << 12)
1321 #define ISPCSI2_PHY_IRQSTATUS_ERRESC2           (1 << 11)
1322 #define ISPCSI2_PHY_IRQSTATUS_ERRESC1           (1 << 10)
1323 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5     (1 << 9)
1324 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4     (1 << 8)
1325 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3     (1 << 7)
1326 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2     (1 << 6)
1327 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1     (1 << 5)
1328 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5         (1 << 4)
1329 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4         (1 << 3)
1330 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3         (1 << 2)
1331 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2         (1 << 1)
1332 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1         1
1333
1334 #define ISPCSI2_SHORT_PACKET                    (0x05c)
1335 #define ISPCSI2_PHY_IRQENABLE                   (0x060)
1336 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT  (1 << 26)
1337 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25)
1338 #define ISPCSI2_PHY_IRQENABLE_STATEULPM5        (1 << 24)
1339 #define ISPCSI2_PHY_IRQENABLE_STATEULPM4        (1 << 23)
1340 #define ISPCSI2_PHY_IRQENABLE_STATEULPM3        (1 << 22)
1341 #define ISPCSI2_PHY_IRQENABLE_STATEULPM2        (1 << 21)
1342 #define ISPCSI2_PHY_IRQENABLE_STATEULPM1        (1 << 20)
1343 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5       (1 << 19)
1344 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4       (1 << 18)
1345 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3       (1 << 17)
1346 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2       (1 << 16)
1347 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1       (1 << 15)
1348 #define ISPCSI2_PHY_IRQENABLE_ERRESC5           (1 << 14)
1349 #define ISPCSI2_PHY_IRQENABLE_ERRESC4           (1 << 13)
1350 #define ISPCSI2_PHY_IRQENABLE_ERRESC3           (1 << 12)
1351 #define ISPCSI2_PHY_IRQENABLE_ERRESC2           (1 << 11)
1352 #define ISPCSI2_PHY_IRQENABLE_ERRESC1           (1 << 10)
1353 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5     (1 << 9)
1354 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4     (1 << 8)
1355 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3     (1 << 7)
1356 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2     (1 << 6)
1357 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1     (1 << 5)
1358 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5         (1 << 4)
1359 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4         (1 << 3)
1360 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3         (1 << 2)
1361 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2         (1 << 1)
1362 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1         (1 << 0)
1363
1364 #define ISPCSI2_DBG_P                           (0x068)
1365 #define ISPCSI2_TIMING                          (0x06c)
1366 #define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n)      (1 << ((16 * ((n) - 1)) + 15))
1367 #define ISPCSI2_TIMING_STOP_STATE_X16_IO(n)     (1 << ((16 * ((n) - 1)) + 14))
1368 #define ISPCSI2_TIMING_STOP_STATE_X4_IO(n)      (1 << ((16 * ((n) - 1)) + 13))
1369 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n)   (16 * ((n) - 1))
1370 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n)    \
1371         (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
1372
1373 #define ISPCSI2_CTX_CTRL1(n)                    ((0x070) + 0x20 * (n))
1374 #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT           8
1375 #define ISPCSI2_CTX_CTRL1_COUNT_MASK            \
1376         (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
1377 #define ISPCSI2_CTX_CTRL1_EOF_EN                (1 << 7)
1378 #define ISPCSI2_CTX_CTRL1_EOL_EN                (1 << 6)
1379 #define ISPCSI2_CTX_CTRL1_CS_EN                 (1 << 5)
1380 #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK          (1 << 4)
1381 #define ISPCSI2_CTX_CTRL1_PING_PONG             (1 << 3)
1382 #define ISPCSI2_CTX_CTRL1_CTX_EN                (1 << 0)
1383
1384 #define ISPCSI2_CTX_CTRL2(n)                    ((0x074) + 0x20 * (n))
1385 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT    13
1386 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK     \
1387         (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
1388 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT      11
1389 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK       \
1390         (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
1391 #define ISPCSI2_CTX_CTRL2_DPCM_PRED             (1 << 10)
1392 #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT          0
1393 #define ISPCSI2_CTX_CTRL2_FORMAT_MASK           \
1394         (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
1395 #define ISPCSI2_CTX_CTRL2_FRAME_SHIFT           16
1396 #define ISPCSI2_CTX_CTRL2_FRAME_MASK            \
1397         (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT)
1398
1399 #define ISPCSI2_CTX_DAT_OFST(n)                 ((0x078) + 0x20 * (n))
1400 #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT         0
1401 #define ISPCSI2_CTX_DAT_OFST_OFST_MASK          \
1402         (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
1403
1404 #define ISPCSI2_CTX_DAT_PING_ADDR(n)            ((0x07c) + 0x20 * (n))
1405 #define ISPCSI2_CTX_DAT_PONG_ADDR(n)            ((0x080) + 0x20 * (n))
1406 #define ISPCSI2_CTX_IRQENABLE(n)                ((0x084) + 0x20 * (n))
1407 #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ        (1 << 8)
1408 #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ   (1 << 7)
1409 #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ  (1 << 6)
1410 #define ISPCSI2_CTX_IRQENABLE_CS_IRQ            (1 << 5)
1411 #define ISPCSI2_CTX_IRQENABLE_LE_IRQ            (1 << 3)
1412 #define ISPCSI2_CTX_IRQENABLE_LS_IRQ            (1 << 2)
1413 #define ISPCSI2_CTX_IRQENABLE_FE_IRQ            (1 << 1)
1414 #define ISPCSI2_CTX_IRQENABLE_FS_IRQ            (1 << 0)
1415
1416 #define ISPCSI2_CTX_IRQSTATUS(n)                ((0x088) + 0x20 * (n))
1417 #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ        (1 << 8)
1418 #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ   (1 << 7)
1419 #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ  (1 << 6)
1420 #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ            (1 << 5)
1421 #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ            (1 << 3)
1422 #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ            (1 << 2)
1423 #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ            (1 << 1)
1424 #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ            (1 << 0)
1425
1426 #define ISPCSI2_CTX_CTRL3(n)                    ((0x08c) + 0x20 * (n))
1427 #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT           5
1428 #define ISPCSI2_CTX_CTRL3_ALPHA_MASK            \
1429         (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
1430
1431 /* This instance is for OMAP3630 only */
1432 #define ISPCSI2_CTX_TRANSCODEH(n)               (0x000 + 0x8 * (n))
1433 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT     16
1434 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK      \
1435         (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1436 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT      0
1437 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK       \
1438         (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1439 #define ISPCSI2_CTX_TRANSCODEV(n)               (0x004 + 0x8 * (n))
1440 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT     16
1441 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK      \
1442         (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1443 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT      0
1444 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK       \
1445         (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1446
1447 /* -----------------------------------------------------------------------------
1448  * CSI PHY registers
1449  */
1450
1451 #define ISPCSIPHY_REG0                          (0x000)
1452 #define ISPCSIPHY_REG0_THS_TERM_SHIFT           8
1453 #define ISPCSIPHY_REG0_THS_TERM_MASK            \
1454         (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT)
1455 #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT         0
1456 #define ISPCSIPHY_REG0_THS_SETTLE_MASK          \
1457         (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
1458
1459 #define ISPCSIPHY_REG1                                  (0x004)
1460 #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK               (1 << 29)
1461 /* This field is for OMAP3630 only */
1462 #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS       (1 << 25)
1463 #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT                  18
1464 #define ISPCSIPHY_REG1_TCLK_TERM_MASK                   \
1465         (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
1466 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT       10
1467 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK        \
1468         (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN)
1469 /* This field is for OMAP3430 only */
1470 #define ISPCSIPHY_REG1_TCLK_MISS_SHIFT                  8
1471 #define ISPCSIPHY_REG1_TCLK_MISS_MASK                   \
1472         (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT)
1473 /* This field is for OMAP3630 only */
1474 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT         8
1475 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK          \
1476         (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT)
1477 #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT                0
1478 #define ISPCSIPHY_REG1_TCLK_SETTLE_MASK                 \
1479         (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT)
1480
1481 /* This register is for OMAP3630 only */
1482 #define ISPCSIPHY_REG2                                  (0x008)
1483 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT     30
1484 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK      \
1485         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT)
1486 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT     28
1487 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK      \
1488         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT)
1489 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT     26
1490 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK      \
1491         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT)
1492 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT     24
1493 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK      \
1494         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT)
1495 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT          0
1496 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK           \
1497         (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT)
1498
1499 /* -----------------------------------------------------------------------------
1500  * CONTROL registers for CSI-2 phy routing
1501  */
1502
1503 /* OMAP343X_CONTROL_CSIRXFE */
1504 #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV       (1 << 7)
1505 #define OMAP343X_CONTROL_CSIRXFE_RESENABLE      (1 << 8)
1506 #define OMAP343X_CONTROL_CSIRXFE_SELFORM        (1 << 10)
1507 #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ         (1 << 12)
1508 #define OMAP343X_CONTROL_CSIRXFE_RESET          (1 << 13)
1509
1510 /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */
1511 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT     2
1512 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT     0
1513 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY           0x0
1514 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE 0x1
1515 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK 0x2
1516 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI            0x3
1517 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK           0x3
1518 /* CCP2B: set to receive data from PHY2 instead of PHY1 */
1519 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2       (1 << 4)
1520
1521 #endif  /* OMAP3_ISP_REG_H */