drivers/media/platform/omap3isp/ispccp2.c

   1 /*
   2  * ispccp2.c
   3  *
   4  * TI OMAP3 ISP - CCP2 module
   5  *
   6  * Copyright (C) 2010 Nokia Corporation
   7  * Copyright (C) 2010 Texas Instruments, Inc.
   8  *
   9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  *           Sakari Ailus <sakari.ailus@iki.fi>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  24  * 02110-1301 USA
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/device.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mutex.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 #include "isp.h"
  36 #include "ispreg.h"
  37 #include "ispccp2.h"
  38
  39 /* Number of LCX channels */
  40 #define CCP2_LCx_CHANS_NUM                      3
  41 /* Max/Min size for CCP2 video port */
  42 #define ISPCCP2_DAT_START_MIN                   0
  43 #define ISPCCP2_DAT_START_MAX                   4095
  44 #define ISPCCP2_DAT_SIZE_MIN                    0
  45 #define ISPCCP2_DAT_SIZE_MAX                    4095
  46 #define ISPCCP2_VPCLK_FRACDIV                   65536
  47 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP  0x12
  48 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP        0x16
  49 /* Max/Min size for CCP2 memory channel */
  50 #define ISPCCP2_LCM_HSIZE_COUNT_MIN             16
  51 #define ISPCCP2_LCM_HSIZE_COUNT_MAX             8191
  52 #define ISPCCP2_LCM_HSIZE_SKIP_MIN              0
  53 #define ISPCCP2_LCM_HSIZE_SKIP_MAX              8191
  54 #define ISPCCP2_LCM_VSIZE_MIN                   1
  55 #define ISPCCP2_LCM_VSIZE_MAX                   8191
  56 #define ISPCCP2_LCM_HWORDS_MIN                  1
  57 #define ISPCCP2_LCM_HWORDS_MAX                  4095
  58 #define ISPCCP2_LCM_CTRL_BURST_SIZE_32X         5
  59 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL     0
  60 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10     2
  61 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8        2
  62 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10       3
  63 #define ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10       3
  64 #define ISPCCP2_LCM_CTRL_DST_PORT_VP            0
  65 #define ISPCCP2_LCM_CTRL_DST_PORT_MEM           1
  66
  67 /* Set only the required bits */
  68 #define BIT_SET(var, shift, mask, val)                  \
  69         do {                                            \
  70                 var = ((var) & ~((mask) << (shift)))    \
  71                         | ((val) << (shift));           \
  72         } while (0)
  73
  74 /*
  75  * ccp2_print_status - Print current CCP2 module register values.
  76  */
  77 #define CCP2_PRINT_REGISTER(isp, name)\
  78         dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
  79                 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_##name))
  80
  81 static void ccp2_print_status(struct isp_ccp2_device *ccp2)
  82 {
  83         struct isp_device *isp = to_isp_device(ccp2);
  84
  85         dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n");
  86
  87         CCP2_PRINT_REGISTER(isp, SYSCONFIG);
  88         CCP2_PRINT_REGISTER(isp, SYSSTATUS);
  89         CCP2_PRINT_REGISTER(isp, LC01_IRQENABLE);
  90         CCP2_PRINT_REGISTER(isp, LC01_IRQSTATUS);
  91         CCP2_PRINT_REGISTER(isp, LC23_IRQENABLE);
  92         CCP2_PRINT_REGISTER(isp, LC23_IRQSTATUS);
  93         CCP2_PRINT_REGISTER(isp, LCM_IRQENABLE);
  94         CCP2_PRINT_REGISTER(isp, LCM_IRQSTATUS);
  95         CCP2_PRINT_REGISTER(isp, CTRL);
  96         CCP2_PRINT_REGISTER(isp, LCx_CTRL(0));
  97         CCP2_PRINT_REGISTER(isp, LCx_CODE(0));
  98         CCP2_PRINT_REGISTER(isp, LCx_STAT_START(0));
  99         CCP2_PRINT_REGISTER(isp, LCx_STAT_SIZE(0));
 100         CCP2_PRINT_REGISTER(isp, LCx_SOF_ADDR(0));
 101         CCP2_PRINT_REGISTER(isp, LCx_EOF_ADDR(0));
 102         CCP2_PRINT_REGISTER(isp, LCx_DAT_START(0));
 103         CCP2_PRINT_REGISTER(isp, LCx_DAT_SIZE(0));
 104         CCP2_PRINT_REGISTER(isp, LCx_DAT_PING_ADDR(0));
 105         CCP2_PRINT_REGISTER(isp, LCx_DAT_PONG_ADDR(0));
 106         CCP2_PRINT_REGISTER(isp, LCx_DAT_OFST(0));
 107         CCP2_PRINT_REGISTER(isp, LCM_CTRL);
 108         CCP2_PRINT_REGISTER(isp, LCM_VSIZE);
 109         CCP2_PRINT_REGISTER(isp, LCM_HSIZE);
 110         CCP2_PRINT_REGISTER(isp, LCM_PREFETCH);
 111         CCP2_PRINT_REGISTER(isp, LCM_SRC_ADDR);
 112         CCP2_PRINT_REGISTER(isp, LCM_SRC_OFST);
 113         CCP2_PRINT_REGISTER(isp, LCM_DST_ADDR);
 114         CCP2_PRINT_REGISTER(isp, LCM_DST_OFST);
 115
 116         dev_dbg(isp->dev, "--------------------------------------------\n");
 117 }
 118
 119 /*
 120  * ccp2_reset - Reset the CCP2
 121  * @ccp2: pointer to ISP CCP2 device
 122  */
 123 static void ccp2_reset(struct isp_ccp2_device *ccp2)
 124 {
 125         struct isp_device *isp = to_isp_device(ccp2);
 126         int i = 0;
 127
 128         /* Reset the CSI1/CCP2B and wait for reset to complete */
 129         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG,
 130                     ISPCCP2_SYSCONFIG_SOFT_RESET);
 131         while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSSTATUS) &
 132                  ISPCCP2_SYSSTATUS_RESET_DONE)) {
 133                 udelay(10);
 134                 if (i++ > 10) {  /* try read 10 times */
 135                         dev_warn(isp->dev,
 136                                 "omap3_isp: timeout waiting for ccp2 reset\n");
 137                         break;
 138                 }
 139         }
 140 }
 141
 142 /*
 143  * ccp2_pwr_cfg - Configure the power mode settings
 144  * @ccp2: pointer to ISP CCP2 device
 145  */
 146 static void ccp2_pwr_cfg(struct isp_ccp2_device *ccp2)
 147 {
 148         struct isp_device *isp = to_isp_device(ccp2);
 149
 150         isp_reg_writel(isp, ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART |
 151                         ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ?
 152                           ISPCCP2_SYSCONFIG_AUTO_IDLE : 0),
 153                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG);
 154 }
 155
 156 /*
 157  * ccp2_if_enable - Enable CCP2 interface.
 158  * @ccp2: pointer to ISP CCP2 device
 159  * @enable: enable/disable flag
 160  */
 161 static void ccp2_if_enable(struct isp_ccp2_device *ccp2, u8 enable)
 162 {
 163         struct isp_device *isp = to_isp_device(ccp2);
 164         int i;
 165
 166         if (enable && ccp2->vdds_csib)
 167                 regulator_enable(ccp2->vdds_csib);
 168
 169         /* Enable/Disable all the LCx channels */
 170         for (i = 0; i < CCP2_LCx_CHANS_NUM; i++)
 171                 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
 172                                 ISPCCP2_LCx_CTRL_CHAN_EN,
 173                                 enable ? ISPCCP2_LCx_CTRL_CHAN_EN : 0);
 174
 175         /* Enable/Disable ccp2 interface in ccp2 mode */
 176         isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
 177                         ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN,
 178                         enable ? (ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN) : 0);
 179
 180         if (!enable && ccp2->vdds_csib)
 181                 regulator_disable(ccp2->vdds_csib);
 182 }
 183
 184 /*
 185  * ccp2_mem_enable - Enable CCP2 memory interface.
 186  * @ccp2: pointer to ISP CCP2 device
 187  * @enable: enable/disable flag
 188  */
 189 static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable)
 190 {
 191         struct isp_device *isp = to_isp_device(ccp2);
 192
 193         if (enable)
 194                 ccp2_if_enable(ccp2, 0);
 195
 196         /* Enable/Disable ccp2 interface in ccp2 mode */
 197         isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
 198                         ISPCCP2_CTRL_MODE, enable ? ISPCCP2_CTRL_MODE : 0);
 199
 200         isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL,
 201                         ISPCCP2_LCM_CTRL_CHAN_EN,
 202                         enable ? ISPCCP2_LCM_CTRL_CHAN_EN : 0);
 203 }
 204
 205 /*
 206  * ccp2_phyif_config - Initialize CCP2 phy interface config
 207  * @ccp2: Pointer to ISP CCP2 device
 208  * @config: CCP2 platform data
 209  *
 210  * Configure the CCP2 physical interface module from platform data.
 211  *
 212  * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
 213  */
 214 static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
 215                              const struct isp_ccp2_platform_data *pdata)
 216 {
 217         struct isp_device *isp = to_isp_device(ccp2);
 218         u32 val;
 219
 220         /* CCP2B mode */
 221         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
 222                             ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE;
 223         /* Data/strobe physical layer */
 224         BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
 225                 pdata->phy_layer);
 226         BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
 227                 pdata->strobe_clk_pol);
 228         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 229
 230         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 231         if (!(val & ISPCCP2_CTRL_MODE)) {
 232                 if (pdata->ccp2_mode == ISP_CCP2_MODE_CCP2)
 233                         dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n");
 234                 if (pdata->phy_layer == ISP_CCP2_PHY_DATA_STROBE)
 235                         /* Strobe mode requires CCP2 */
 236                         return -EIO;
 237         }
 238
 239         return 0;
 240 }
 241
 242 /*
 243  * ccp2_vp_config - Initialize CCP2 video port interface.
 244  * @ccp2: Pointer to ISP CCP2 device
 245  * @vpclk_div: Video port divisor
 246  *
 247  * Configure the CCP2 video port with the given clock divisor. The valid divisor
 248  * values depend on the ISP revision:
 249  *
 250  * - revision 1.0 and 2.0       1 to 4
 251  * - revision 15.0              1 to 65536
 252  *
 253  * The exact divisor value used might differ from the requested value, as ISP
 254  * revision 15.0 represent the divisor by 65536 divided by an integer.
 255  */
 256 static void ccp2_vp_config(struct isp_ccp2_device *ccp2,
 257                            unsigned int vpclk_div)
 258 {
 259         struct isp_device *isp = to_isp_device(ccp2);
 260         u32 val;
 261
 262         /* ISPCCP2_CTRL Video port */
 263         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 264         val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */
 265
 266         if (isp->revision == ISP_REVISION_15_0) {
 267                 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 65536);
 268                 vpclk_div = min(ISPCCP2_VPCLK_FRACDIV / vpclk_div, 65535U);
 269                 BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT,
 270                         ISPCCP2_CTRL_VPCLK_DIV_MASK, vpclk_div);
 271         } else {
 272                 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 4);
 273                 BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT,
 274                         ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1);
 275         }
 276
 277         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 278 }
 279
 280 /*
 281  * ccp2_lcx_config - Initialize CCP2 logical channel interface.
 282  * @ccp2: Pointer to ISP CCP2 device
 283  * @config: Pointer to ISP LCx config structure.
 284  *
 285  * This will analyze the parameters passed by the interface config
 286  * and configure CSI1/CCP2 logical channel
 287  *
 288  */
 289 static void ccp2_lcx_config(struct isp_ccp2_device *ccp2,
 290                             struct isp_interface_lcx_config *config)
 291 {
 292         struct isp_device *isp = to_isp_device(ccp2);
 293         u32 val, format;
 294
 295         switch (config->format) {
 296         case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
 297                 format = ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP;
 298                 break;
 299         case V4L2_MBUS_FMT_SGRBG10_1X10:
 300         default:
 301                 format = ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP;      /* RAW10+VP */
 302                 break;
 303         }
 304         /* ISPCCP2_LCx_CTRL logical channel #0 */
 305         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0))
 306                             | (ISPCCP2_LCx_CTRL_REGION_EN); /* Region */
 307
 308         if (isp->revision == ISP_REVISION_15_0) {
 309                 /* CRC */
 310                 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0,
 311                         ISPCCP2_LCx_CTRL_CRC_MASK,
 312                         config->crc);
 313                 /* Format = RAW10+VP or RAW8+DPCM10+VP*/
 314                 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0,
 315                         ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0, format);
 316         } else {
 317                 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT,
 318                         ISPCCP2_LCx_CTRL_CRC_MASK,
 319                         config->crc);
 320
 321                 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT,
 322                         ISPCCP2_LCx_CTRL_FORMAT_MASK, format);
 323         }
 324         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0));
 325
 326         /* ISPCCP2_DAT_START for logical channel #0 */
 327         isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT,
 328                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_START(0));
 329
 330         /* ISPCCP2_DAT_SIZE for logical channel #0 */
 331         isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT,
 332                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_SIZE(0));
 333
 334         /* Enable error IRQs for logical channel #0 */
 335         val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
 336               ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
 337               ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
 338               ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
 339               ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
 340               ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
 341
 342         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS);
 343         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val);
 344 }
 345
 346 /*
 347  * ccp2_if_configure - Configure ccp2 with data from sensor
 348  * @ccp2: Pointer to ISP CCP2 device
 349  *
 350  * Return 0 on success or a negative error code
 351  */
 352 static int ccp2_if_configure(struct isp_ccp2_device *ccp2)
 353 {
 354         const struct isp_v4l2_subdevs_group *pdata;
 355         struct v4l2_mbus_framefmt *format;
 356         struct media_pad *pad;
 357         struct v4l2_subdev *sensor;
 358         u32 lines = 0;
 359         int ret;
 360
 361         ccp2_pwr_cfg(ccp2);
 362
 363         pad = media_entity_remote_source(&ccp2->pads[CCP2_PAD_SINK]);
 364         sensor = media_entity_to_v4l2_subdev(pad->entity);
 365         pdata = sensor->host_priv;
 366
 367         ret = ccp2_phyif_config(ccp2, &pdata->bus.ccp2);
 368         if (ret < 0)
 369                 return ret;
 370
 371         ccp2_vp_config(ccp2, pdata->bus.ccp2.vpclk_div + 1);
 372
 373         v4l2_subdev_call(sensor, sensor, g_skip_top_lines, &lines);
 374
 375         format = &ccp2->formats[CCP2_PAD_SINK];
 376
 377         ccp2->if_cfg.data_start = lines;
 378         ccp2->if_cfg.crc = pdata->bus.ccp2.crc;
 379         ccp2->if_cfg.format = format->code;
 380         ccp2->if_cfg.data_size = format->height;
 381
 382         ccp2_lcx_config(ccp2, &ccp2->if_cfg);
 383
 384         return 0;
 385 }
 386
 387 static int ccp2_adjust_bandwidth(struct isp_ccp2_device *ccp2)
 388 {
 389         struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
 390         struct isp_device *isp = to_isp_device(ccp2);
 391         const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE];
 392         unsigned long l3_ick = pipe->l3_ick;
 393         struct v4l2_fract *timeperframe;
 394         unsigned int vpclk_div = 2;
 395         unsigned int value;
 396         u64 bound;
 397         u64 area;
 398
 399         /* Compute the minimum clock divisor, based on the pipeline maximum
 400          * data rate. This is an absolute lower bound if we don't want SBL
 401          * overflows, so round the value up.
 402          */
 403         vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate),
 404                           vpclk_div);
 405
 406         /* Compute the maximum clock divisor, based on the requested frame rate.
 407          * This is a soft lower bound to achieve a frame rate equal or higher
 408          * than the requested value, so round the value down.
 409          */
 410         timeperframe = &pipe->max_timeperframe;
 411
 412         if (timeperframe->numerator) {
 413                 area = ofmt->width * ofmt->height;
 414                 bound = div_u64(area * timeperframe->denominator,
 415                                 timeperframe->numerator);
 416                 value = min_t(u64, bound, l3_ick);
 417                 vpclk_div = max_t(unsigned int, l3_ick / value, vpclk_div);
 418         }
 419
 420         dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__,
 421                 vpclk_div);
 422
 423         return vpclk_div;
 424 }
 425
 426 /*
 427  * ccp2_mem_configure - Initialize CCP2 memory input/output interface
 428  * @ccp2: Pointer to ISP CCP2 device
 429  * @config: Pointer to ISP mem interface config structure
 430  *
 431  * This will analyze the parameters passed by the interface config
 432  * structure, and configure the respective registers for proper
 433  * CSI1/CCP2 memory input.
 434  */
 435 static void ccp2_mem_configure(struct isp_ccp2_device *ccp2,
 436                                struct isp_interface_mem_config *config)
 437 {
 438         struct isp_device *isp = to_isp_device(ccp2);
 439         u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code;
 440         u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code;
 441         unsigned int dpcm_decompress = 0;
 442         u32 val, hwords;
 443
 444         if (sink_pixcode != source_pixcode &&
 445             sink_pixcode == V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
 446                 dpcm_decompress = 1;
 447
 448         ccp2_pwr_cfg(ccp2);
 449
 450         /* Hsize, Skip */
 451         isp_reg_writel(isp, ISPCCP2_LCM_HSIZE_SKIP_MIN |
 452                        (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT),
 453                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_HSIZE);
 454
 455         /* Vsize, no. of lines */
 456         isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT,
 457                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_VSIZE);
 458
 459         if (ccp2->video_in.bpl_padding == 0)
 460                 config->src_ofst = 0;
 461         else
 462                 config->src_ofst = ccp2->video_in.bpl_value;
 463
 464         isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2,
 465                        ISPCCP2_LCM_SRC_OFST);
 466
 467         /* Source and Destination formats */
 468         val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 <<
 469               ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT;
 470
 471         if (dpcm_decompress) {
 472                 /* source format is RAW8 */
 473                 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 <<
 474                        ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
 475
 476                 /* RAW8 + DPCM10 - simple predictor */
 477                 val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED;
 478
 479                 /* enable source DPCM decompression */
 480                 val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 <<
 481                        ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT;
 482         } else {
 483                 /* source format is RAW10 */
 484                 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 <<
 485                        ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
 486         }
 487
 488         /* Burst size to 32x64 */
 489         val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X <<
 490                ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT;
 491
 492         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL);
 493
 494         /* Prefetch setup */
 495         if (dpcm_decompress)
 496                 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
 497                           config->hsize_count) >> 3;
 498         else
 499                 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
 500                           config->hsize_count) >> 2;
 501
 502         isp_reg_writel(isp, hwords << ISPCCP2_LCM_PREFETCH_SHIFT,
 503                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_PREFETCH);
 504
 505         /* Video port */
 506         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
 507                     ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE);
 508         ccp2_vp_config(ccp2, ccp2_adjust_bandwidth(ccp2));
 509
 510         /* Clear LCM interrupts */
 511         isp_reg_writel(isp, ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ |
 512                        ISPCCP2_LCM_IRQSTATUS_EOF_IRQ,
 513                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS);
 514
 515         /* Enable LCM interupts */
 516         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE,
 517                     ISPCCP2_LCM_IRQSTATUS_EOF_IRQ |
 518                     ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ);
 519 }
 520
 521 /*
 522  * ccp2_set_inaddr - Sets memory address of input frame.
 523  * @ccp2: Pointer to ISP CCP2 device
 524  * @addr: 32bit memory address aligned on 32byte boundary.
 525  *
 526  * Configures the memory address from which the input frame is to be read.
 527  */
 528 static void ccp2_set_inaddr(struct isp_ccp2_device *ccp2, u32 addr)
 529 {
 530         struct isp_device *isp = to_isp_device(ccp2);
 531
 532         isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_SRC_ADDR);
 533 }
 534
 535 /* -----------------------------------------------------------------------------
 536  * Interrupt handling
 537  */
 538
 539 static void ccp2_isr_buffer(struct isp_ccp2_device *ccp2)
 540 {
 541         struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
 542         struct isp_buffer *buffer;
 543
 544         buffer = omap3isp_video_buffer_next(&ccp2->video_in);
 545         if (buffer != NULL)
 546                 ccp2_set_inaddr(ccp2, buffer->isp_addr);
 547
 548         pipe->state |= ISP_PIPELINE_IDLE_INPUT;
 549
 550         if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) {
 551                 if (isp_pipeline_ready(pipe))
 552                         omap3isp_pipeline_set_stream(pipe,
 553                                                 ISP_PIPELINE_STREAM_SINGLESHOT);
 554         }
 555 }
 556
 557 /*
 558  * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
 559  * @ccp2: Pointer to ISP CCP2 device
 560  *
 561  * This will handle the CCP2 interrupts
 562  */
 563 void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2)
 564 {
 565         struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
 566         struct isp_device *isp = to_isp_device(ccp2);
 567         static const u32 ISPCCP2_LC01_ERROR =
 568                 ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
 569                 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
 570                 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
 571                 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
 572                 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
 573                 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
 574         u32 lcx_irqstatus, lcm_irqstatus;
 575
 576         /* First clear the interrupts */
 577         lcx_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
 578                                       ISPCCP2_LC01_IRQSTATUS);
 579         isp_reg_writel(isp, lcx_irqstatus, OMAP3_ISP_IOMEM_CCP2,
 580                        ISPCCP2_LC01_IRQSTATUS);
 581
 582         lcm_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
 583                                       ISPCCP2_LCM_IRQSTATUS);
 584         isp_reg_writel(isp, lcm_irqstatus, OMAP3_ISP_IOMEM_CCP2,
 585                        ISPCCP2_LCM_IRQSTATUS);
 586         /* Errors */
 587         if (lcx_irqstatus & ISPCCP2_LC01_ERROR) {
 588                 pipe->error = true;
 589                 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus);
 590                 return;
 591         }
 592
 593         if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ) {
 594                 pipe->error = true;
 595                 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus);
 596         }
 597
 598         if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping))
 599                 return;
 600
 601         /* Handle queued buffers on frame end interrupts */
 602         if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_EOF_IRQ)
 603                 ccp2_isr_buffer(ccp2);
 604 }
 605
 606 /* -----------------------------------------------------------------------------
 607  * V4L2 subdev operations
 608  */
 609
 610 static const unsigned int ccp2_fmts[] = {
 611         V4L2_MBUS_FMT_SGRBG10_1X10,
 612         V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
 613 };
 614
 615 /*
 616  * __ccp2_get_format - helper function for getting ccp2 format
 617  * @ccp2  : Pointer to ISP CCP2 device
 618  * @fh    : V4L2 subdev file handle
 619  * @pad   : pad number
 620  * @which : wanted subdev format
 621  * return format structure or NULL on error
 622  */
 623 static struct v4l2_mbus_framefmt *
 624 __ccp2_get_format(struct isp_ccp2_device *ccp2, struct v4l2_subdev_fh *fh,
 625                      unsigned int pad, enum v4l2_subdev_format_whence which)
 626 {
 627         if (which == V4L2_SUBDEV_FORMAT_TRY)
 628                 return v4l2_subdev_get_try_format(fh, pad);
 629         else
 630                 return &ccp2->formats[pad];
 631 }
 632
 633 /*
 634  * ccp2_try_format - Handle try format by pad subdev method
 635  * @ccp2  : Pointer to ISP CCP2 device
 636  * @fh    : V4L2 subdev file handle
 637  * @pad   : pad num
 638  * @fmt   : pointer to v4l2 mbus format structure
 639  * @which : wanted subdev format
 640  */
 641 static void ccp2_try_format(struct isp_ccp2_device *ccp2,
 642                                struct v4l2_subdev_fh *fh, unsigned int pad,
 643                                struct v4l2_mbus_framefmt *fmt,
 644                                enum v4l2_subdev_format_whence which)
 645 {
 646         struct v4l2_mbus_framefmt *format;
 647
 648         switch (pad) {
 649         case CCP2_PAD_SINK:
 650                 if (fmt->code != V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
 651                         fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
 652
 653                 if (ccp2->input == CCP2_INPUT_SENSOR) {
 654                         fmt->width = clamp_t(u32, fmt->width,
 655                                              ISPCCP2_DAT_START_MIN,
 656                                              ISPCCP2_DAT_START_MAX);
 657                         fmt->height = clamp_t(u32, fmt->height,
 658                                               ISPCCP2_DAT_SIZE_MIN,
 659                                               ISPCCP2_DAT_SIZE_MAX);
 660                 } else if (ccp2->input == CCP2_INPUT_MEMORY) {
 661                         fmt->width = clamp_t(u32, fmt->width,
 662                                              ISPCCP2_LCM_HSIZE_COUNT_MIN,
 663                                              ISPCCP2_LCM_HSIZE_COUNT_MAX);
 664                         fmt->height = clamp_t(u32, fmt->height,
 665                                               ISPCCP2_LCM_VSIZE_MIN,
 666                                               ISPCCP2_LCM_VSIZE_MAX);
 667                 }
 668                 break;
 669
 670         case CCP2_PAD_SOURCE:
 671                 /* Source format - copy sink format and change pixel code
 672                  * to SGRBG10_1X10 as we don't support CCP2 write to memory.
 673                  * When CCP2 write to memory feature will be added this
 674                  * should be changed properly.
 675                  */
 676                 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK, which);
 677                 memcpy(fmt, format, sizeof(*fmt));
 678                 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
 679                 break;
 680         }
 681
 682         fmt->field = V4L2_FIELD_NONE;
 683         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 684 }
 685
 686 /*
 687  * ccp2_enum_mbus_code - Handle pixel format enumeration
 688  * @sd     : pointer to v4l2 subdev structure
 689  * @fh     : V4L2 subdev file handle
 690  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
 691  * return -EINVAL or zero on success
 692  */
 693 static int ccp2_enum_mbus_code(struct v4l2_subdev *sd,
 694                                   struct v4l2_subdev_fh *fh,
 695                                   struct v4l2_subdev_mbus_code_enum *code)
 696 {
 697         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 698         struct v4l2_mbus_framefmt *format;
 699
 700         if (code->pad == CCP2_PAD_SINK) {
 701                 if (code->index >= ARRAY_SIZE(ccp2_fmts))
 702                         return -EINVAL;
 703
 704                 code->code = ccp2_fmts[code->index];
 705         } else {
 706                 if (code->index != 0)
 707                         return -EINVAL;
 708
 709                 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK,
 710                                               V4L2_SUBDEV_FORMAT_TRY);
 711                 code->code = format->code;
 712         }
 713
 714         return 0;
 715 }
 716
 717 static int ccp2_enum_frame_size(struct v4l2_subdev *sd,
 718                                    struct v4l2_subdev_fh *fh,
 719                                    struct v4l2_subdev_frame_size_enum *fse)
 720 {
 721         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 722         struct v4l2_mbus_framefmt format;
 723
 724         if (fse->index != 0)
 725                 return -EINVAL;
 726
 727         format.code = fse->code;
 728         format.width = 1;
 729         format.height = 1;
 730         ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
 731         fse->min_width = format.width;
 732         fse->min_height = format.height;
 733
 734         if (format.code != fse->code)
 735                 return -EINVAL;
 736
 737         format.code = fse->code;
 738         format.width = -1;
 739         format.height = -1;
 740         ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
 741         fse->max_width = format.width;
 742         fse->max_height = format.height;
 743
 744         return 0;
 745 }
 746
 747 /*
 748  * ccp2_get_format - Handle get format by pads subdev method
 749  * @sd    : pointer to v4l2 subdev structure
 750  * @fh    : V4L2 subdev file handle
 751  * @fmt   : pointer to v4l2 subdev format structure
 752  * return -EINVAL or zero on success
 753  */
 754 static int ccp2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 755                               struct v4l2_subdev_format *fmt)
 756 {
 757         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 758         struct v4l2_mbus_framefmt *format;
 759
 760         format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
 761         if (format == NULL)
 762                 return -EINVAL;
 763
 764         fmt->format = *format;
 765         return 0;
 766 }
 767
 768 /*
 769  * ccp2_set_format - Handle set format by pads subdev method
 770  * @sd    : pointer to v4l2 subdev structure
 771  * @fh    : V4L2 subdev file handle
 772  * @fmt   : pointer to v4l2 subdev format structure
 773  * returns zero
 774  */
 775 static int ccp2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 776                               struct v4l2_subdev_format *fmt)
 777 {
 778         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 779         struct v4l2_mbus_framefmt *format;
 780
 781         format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
 782         if (format == NULL)
 783                 return -EINVAL;
 784
 785         ccp2_try_format(ccp2, fh, fmt->pad, &fmt->format, fmt->which);
 786         *format = fmt->format;
 787
 788         /* Propagate the format from sink to source */
 789         if (fmt->pad == CCP2_PAD_SINK) {
 790                 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SOURCE,
 791                                            fmt->which);
 792                 *format = fmt->format;
 793                 ccp2_try_format(ccp2, fh, CCP2_PAD_SOURCE, format, fmt->which);
 794         }
 795
 796         return 0;
 797 }
 798
 799 /*
 800  * ccp2_init_formats - Initialize formats on all pads
 801  * @sd: ISP CCP2 V4L2 subdevice
 802  * @fh: V4L2 subdev file handle
 803  *
 804  * Initialize all pad formats with default values. If fh is not NULL, try
 805  * formats are initialized on the file handle. Otherwise active formats are
 806  * initialized on the device.
 807  */
 808 static int ccp2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 809 {
 810         struct v4l2_subdev_format format;
 811
 812         memset(&format, 0, sizeof(format));
 813         format.pad = CCP2_PAD_SINK;
 814         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
 815         format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
 816         format.format.width = 4096;
 817         format.format.height = 4096;
 818         ccp2_set_format(sd, fh, &format);
 819
 820         return 0;
 821 }
 822
 823 /*
 824  * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
 825  * @sd    : pointer to v4l2 subdev structure
 826  * @enable: 1 == Enable, 0 == Disable
 827  * return zero
 828  */
 829 static int ccp2_s_stream(struct v4l2_subdev *sd, int enable)
 830 {
 831         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 832         struct isp_device *isp = to_isp_device(ccp2);
 833         struct device *dev = to_device(ccp2);
 834         int ret;
 835
 836         if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) {
 837                 if (enable == ISP_PIPELINE_STREAM_STOPPED)
 838                         return 0;
 839                 atomic_set(&ccp2->stopping, 0);
 840         }
 841
 842         switch (enable) {
 843         case ISP_PIPELINE_STREAM_CONTINUOUS:
 844                 if (ccp2->phy) {
 845                         ret = omap3isp_csiphy_acquire(ccp2->phy);
 846                         if (ret < 0)
 847                                 return ret;
 848                 }
 849
 850                 ccp2_if_configure(ccp2);
 851                 ccp2_print_status(ccp2);
 852
 853                 /* Enable CSI1/CCP2 interface */
 854                 ccp2_if_enable(ccp2, 1);
 855                 break;
 856
 857         case ISP_PIPELINE_STREAM_SINGLESHOT:
 858                 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) {
 859                         struct v4l2_mbus_framefmt *format;
 860
 861                         format = &ccp2->formats[CCP2_PAD_SINK];
 862
 863                         ccp2->mem_cfg.hsize_count = format->width;
 864                         ccp2->mem_cfg.vsize_count = format->height;
 865                         ccp2->mem_cfg.src_ofst = 0;
 866
 867                         ccp2_mem_configure(ccp2, &ccp2->mem_cfg);
 868                         omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI1_READ);
 869                         ccp2_print_status(ccp2);
 870                 }
 871                 ccp2_mem_enable(ccp2, 1);
 872                 break;
 873
 874         case ISP_PIPELINE_STREAM_STOPPED:
 875                 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait,
 876                                               &ccp2->stopping))
 877                         dev_dbg(dev, "%s: module stop timeout.\n", sd->name);
 878                 if (ccp2->input == CCP2_INPUT_MEMORY) {
 879                         ccp2_mem_enable(ccp2, 0);
 880                         omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI1_READ);
 881                 } else if (ccp2->input == CCP2_INPUT_SENSOR) {
 882                         /* Disable CSI1/CCP2 interface */
 883                         ccp2_if_enable(ccp2, 0);
 884                         if (ccp2->phy)
 885                                 omap3isp_csiphy_release(ccp2->phy);
 886                 }
 887                 break;
 888         }
 889
 890         ccp2->state = enable;
 891         return 0;
 892 }
 893
 894 /* subdev video operations */
 895 static const struct v4l2_subdev_video_ops ccp2_sd_video_ops = {
 896         .s_stream = ccp2_s_stream,
 897 };
 898
 899 /* subdev pad operations */
 900 static const struct v4l2_subdev_pad_ops ccp2_sd_pad_ops = {
 901         .enum_mbus_code = ccp2_enum_mbus_code,
 902         .enum_frame_size = ccp2_enum_frame_size,
 903         .get_fmt = ccp2_get_format,
 904         .set_fmt = ccp2_set_format,
 905 };
 906
 907 /* subdev operations */
 908 static const struct v4l2_subdev_ops ccp2_sd_ops = {
 909         .video = &ccp2_sd_video_ops,
 910         .pad = &ccp2_sd_pad_ops,
 911 };
 912
 913 /* subdev internal operations */
 914 static const struct v4l2_subdev_internal_ops ccp2_sd_internal_ops = {
 915         .open = ccp2_init_formats,
 916 };
 917
 918 /* --------------------------------------------------------------------------
 919  * ISP ccp2 video device node
 920  */
 921
 922 /*
 923  * ccp2_video_queue - Queue video buffer.
 924  * @video : Pointer to isp video structure
 925  * @buffer: Pointer to isp_buffer structure
 926  * return -EIO or zero on success
 927  */
 928 static int ccp2_video_queue(struct isp_video *video, struct isp_buffer *buffer)
 929 {
 930         struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2;
 931
 932         ccp2_set_inaddr(ccp2, buffer->isp_addr);
 933         return 0;
 934 }
 935
 936 static const struct isp_video_operations ccp2_video_ops = {
 937         .queue = ccp2_video_queue,
 938 };
 939
 940 /* -----------------------------------------------------------------------------
 941  * Media entity operations
 942  */
 943
 944 /*
 945  * ccp2_link_setup - Setup ccp2 connections.
 946  * @entity : Pointer to media entity structure
 947  * @local  : Pointer to local pad array
 948  * @remote : Pointer to remote pad array
 949  * @flags  : Link flags
 950  * return -EINVAL on error or zero on success
 951  */
 952 static int ccp2_link_setup(struct media_entity *entity,
 953                            const struct media_pad *local,
 954                            const struct media_pad *remote, u32 flags)
 955 {
 956         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
 957         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 958
 959         switch (local->index | media_entity_type(remote->entity)) {
 960         case CCP2_PAD_SINK | MEDIA_ENT_T_DEVNODE:
 961                 /* read from memory */
 962                 if (flags & MEDIA_LNK_FL_ENABLED) {
 963                         if (ccp2->input == CCP2_INPUT_SENSOR)
 964                                 return -EBUSY;
 965                         ccp2->input = CCP2_INPUT_MEMORY;
 966                 } else {
 967                         if (ccp2->input == CCP2_INPUT_MEMORY)
 968                                 ccp2->input = CCP2_INPUT_NONE;
 969                 }
 970                 break;
 971
 972         case CCP2_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
 973                 /* read from sensor/phy */
 974                 if (flags & MEDIA_LNK_FL_ENABLED) {
 975                         if (ccp2->input == CCP2_INPUT_MEMORY)
 976                                 return -EBUSY;
 977                         ccp2->input = CCP2_INPUT_SENSOR;
 978                 } else {
 979                         if (ccp2->input == CCP2_INPUT_SENSOR)
 980                                 ccp2->input = CCP2_INPUT_NONE;
 981                 } break;
 982
 983         case CCP2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
 984                 /* write to video port/ccdc */
 985                 if (flags & MEDIA_LNK_FL_ENABLED)
 986                         ccp2->output = CCP2_OUTPUT_CCDC;
 987                 else
 988                         ccp2->output = CCP2_OUTPUT_NONE;
 989                 break;
 990
 991         default:
 992                 return -EINVAL;
 993         }
 994
 995         return 0;
 996 }
 997
 998 /* media operations */
 999 static const struct media_entity_operations ccp2_media_ops = {
1000         .link_setup = ccp2_link_setup,
1001         .link_validate = v4l2_subdev_link_validate,
1002 };
1003
1004 /*
1005  * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1006  * @ccp2: Pointer to ISP CCP2 device
1007  */
1008 void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2)
1009 {
1010         v4l2_device_unregister_subdev(&ccp2->subdev);
1011         omap3isp_video_unregister(&ccp2->video_in);
1012 }
1013
1014 /*
1015  * omap3isp_ccp2_register_entities - Register the subdev media entity
1016  * @ccp2: Pointer to ISP CCP2 device
1017  * @vdev: Pointer to v4l device
1018  * return negative error code or zero on success
1019  */
1020
1021 int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
1022                                     struct v4l2_device *vdev)
1023 {
1024         int ret;
1025
1026         /* Register the subdev and video nodes. */
1027         ret = v4l2_device_register_subdev(vdev, &ccp2->subdev);
1028         if (ret < 0)
1029                 goto error;
1030
1031         ret = omap3isp_video_register(&ccp2->video_in, vdev);
1032         if (ret < 0)
1033                 goto error;
1034
1035         return 0;
1036
1037 error:
1038         omap3isp_ccp2_unregister_entities(ccp2);
1039         return ret;
1040 }
1041
1042 /* -----------------------------------------------------------------------------
1043  * ISP ccp2 initialisation and cleanup
1044  */
1045
1046 /*
1047  * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1048  * @ccp2: Pointer to ISP CCP2 device
1049  * return negative error code or zero on success
1050  */
1051 static int ccp2_init_entities(struct isp_ccp2_device *ccp2)
1052 {
1053         struct v4l2_subdev *sd = &ccp2->subdev;
1054         struct media_pad *pads = ccp2->pads;
1055         struct media_entity *me = &sd->entity;
1056         int ret;
1057
1058         ccp2->input = CCP2_INPUT_NONE;
1059         ccp2->output = CCP2_OUTPUT_NONE;
1060
1061         v4l2_subdev_init(sd, &ccp2_sd_ops);
1062         sd->internal_ops = &ccp2_sd_internal_ops;
1063         strlcpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name));
1064         sd->grp_id = 1 << 16;   /* group ID for isp subdevs */
1065         v4l2_set_subdevdata(sd, ccp2);
1066         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1067
1068         pads[CCP2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1069         pads[CCP2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1070
1071         me->ops = &ccp2_media_ops;
1072         ret = media_entity_init(me, CCP2_PADS_NUM, pads, 0);
1073         if (ret < 0)
1074                 return ret;
1075
1076         ccp2_init_formats(sd, NULL);
1077
1078         /*
1079          * The CCP2 has weird line alignment requirements, possibly caused by
1080          * DPCM8 decompression. Line length for data read from memory must be a
1081          * multiple of 128 bits (16 bytes) in continuous mode (when no padding
1082          * is present at end of lines). Additionally, if padding is used, the
1083          * padded line length must be a multiple of 32 bytes. To simplify the
1084          * implementation we use a fixed 32 bytes alignment regardless of the
1085          * input format and width. If strict 128 bits alignment support is
1086          * required ispvideo will need to be made aware of this special dual
1087          * alignement requirements.
1088          */
1089         ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1090         ccp2->video_in.bpl_alignment = 32;
1091         ccp2->video_in.bpl_max = 0xffffffe0;
1092         ccp2->video_in.isp = to_isp_device(ccp2);
1093         ccp2->video_in.ops = &ccp2_video_ops;
1094         ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1095
1096         ret = omap3isp_video_init(&ccp2->video_in, "CCP2");
1097         if (ret < 0)
1098                 goto error_video;
1099
1100         /* Connect the video node to the ccp2 subdev. */
1101         ret = media_entity_create_link(&ccp2->video_in.video.entity, 0,
1102                                        &ccp2->subdev.entity, CCP2_PAD_SINK, 0);
1103         if (ret < 0)
1104                 goto error_link;
1105
1106         return 0;
1107
1108 error_link:
1109         omap3isp_video_cleanup(&ccp2->video_in);
1110 error_video:
1111         media_entity_cleanup(&ccp2->subdev.entity);
1112         return ret;
1113 }
1114
1115 /*
1116  * omap3isp_ccp2_init - CCP2 initialization.
1117  * @isp : Pointer to ISP device
1118  * return negative error code or zero on success
1119  */
1120 int omap3isp_ccp2_init(struct isp_device *isp)
1121 {
1122         struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1123         int ret;
1124
1125         init_waitqueue_head(&ccp2->wait);
1126
1127         /*
1128          * On the OMAP34xx the CSI1 receiver is operated in the CSIb IO
1129          * complex, which is powered by vdds_csib power rail. Hence the
1130          * request for the regulator.
1131          *
1132          * On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
1133          * the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
1134          * configured.
1135          *
1136          * TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
1137          */
1138         if (isp->revision == ISP_REVISION_2_0) {
1139                 ccp2->vdds_csib = regulator_get(isp->dev, "vdds_csib");
1140                 if (IS_ERR(ccp2->vdds_csib)) {
1141                         dev_dbg(isp->dev,
1142                                 "Could not get regulator vdds_csib\n");
1143                         ccp2->vdds_csib = NULL;
1144                 }
1145         } else if (isp->revision == ISP_REVISION_15_0) {
1146                 ccp2->phy = &isp->isp_csiphy1;
1147         }
1148
1149         ret = ccp2_init_entities(ccp2);
1150         if (ret < 0) {
1151                 regulator_put(ccp2->vdds_csib);
1152                 return ret;
1153         }
1154
1155         ccp2_reset(ccp2);
1156         return 0;
1157 }
1158
1159 /*
1160  * omap3isp_ccp2_cleanup - CCP2 un-initialization
1161  * @isp : Pointer to ISP device
1162  */
1163 void omap3isp_ccp2_cleanup(struct isp_device *isp)
1164 {
1165         struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1166
1167         omap3isp_video_cleanup(&ccp2->video_in);
1168         media_entity_cleanup(&ccp2->subdev.entity);
1169
1170         regulator_put(ccp2->vdds_csib);
1171 }