drivers/media/pci/tw68/tw68-video.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  tw68 functions to handle video data
   4  *
   5  *  Much of this code is derived from the cx88 and sa7134 drivers, which
   6  *  were in turn derived from the bt87x driver.  The original work was by
   7  *  Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
   8  *  Hans Verkuil, Andy Walls and many others.  Their work is gratefully
   9  *  acknowledged.  Full credit goes to them - any problems within this code
  10  *  are mine.
  11  *
  12  *  Copyright (C) 2009  William M. Brack
  13  *
  14  *  Refactored and updated to the latest v4l core frameworks:
  15  *
  16  *  Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
  17  */
  18
  19 #include <linux/module.h>
  20 #include <media/v4l2-common.h>
  21 #include <media/v4l2-event.h>
  22 #include <media/videobuf2-dma-sg.h>
  23
  24 #include "tw68.h"
  25 #include "tw68-reg.h"
  26
  27 /* ------------------------------------------------------------------ */
  28 /* data structs for video                                             */
  29 /*
  30  * FIXME -
  31  * Note that the saa7134 has formats, e.g. YUV420, which are classified
  32  * as "planar".  These affect overlay mode, and are flagged with a field
  33  * ".planar" in the format.  Do we need to implement this in this driver?
  34  */
  35 static const struct tw68_format formats[] = {
  36         {
  37                 .name           = "15 bpp RGB, le",
  38                 .fourcc         = V4L2_PIX_FMT_RGB555,
  39                 .depth          = 16,
  40                 .twformat       = ColorFormatRGB15,
  41         }, {
  42                 .name           = "15 bpp RGB, be",
  43                 .fourcc         = V4L2_PIX_FMT_RGB555X,
  44                 .depth          = 16,
  45                 .twformat       = ColorFormatRGB15 | ColorFormatBSWAP,
  46         }, {
  47                 .name           = "16 bpp RGB, le",
  48                 .fourcc         = V4L2_PIX_FMT_RGB565,
  49                 .depth          = 16,
  50                 .twformat       = ColorFormatRGB16,
  51         }, {
  52                 .name           = "16 bpp RGB, be",
  53                 .fourcc         = V4L2_PIX_FMT_RGB565X,
  54                 .depth          = 16,
  55                 .twformat       = ColorFormatRGB16 | ColorFormatBSWAP,
  56         }, {
  57                 .name           = "24 bpp RGB, le",
  58                 .fourcc         = V4L2_PIX_FMT_BGR24,
  59                 .depth          = 24,
  60                 .twformat       = ColorFormatRGB24,
  61         }, {
  62                 .name           = "24 bpp RGB, be",
  63                 .fourcc         = V4L2_PIX_FMT_RGB24,
  64                 .depth          = 24,
  65                 .twformat       = ColorFormatRGB24 | ColorFormatBSWAP,
  66         }, {
  67                 .name           = "32 bpp RGB, le",
  68                 .fourcc         = V4L2_PIX_FMT_BGR32,
  69                 .depth          = 32,
  70                 .twformat       = ColorFormatRGB32,
  71         }, {
  72                 .name           = "32 bpp RGB, be",
  73                 .fourcc         = V4L2_PIX_FMT_RGB32,
  74                 .depth          = 32,
  75                 .twformat       = ColorFormatRGB32 | ColorFormatBSWAP |
  76                                   ColorFormatWSWAP,
  77         }, {
  78                 .name           = "4:2:2 packed, YUYV",
  79                 .fourcc         = V4L2_PIX_FMT_YUYV,
  80                 .depth          = 16,
  81                 .twformat       = ColorFormatYUY2,
  82         }, {
  83                 .name           = "4:2:2 packed, UYVY",
  84                 .fourcc         = V4L2_PIX_FMT_UYVY,
  85                 .depth          = 16,
  86                 .twformat       = ColorFormatYUY2 | ColorFormatBSWAP,
  87         }
  88 };
  89 #define FORMATS ARRAY_SIZE(formats)
  90
  91 #define NORM_625_50                     \
  92                 .h_delay        = 3,    \
  93                 .h_delay0       = 133,  \
  94                 .h_start        = 0,    \
  95                 .h_stop         = 719,  \
  96                 .v_delay        = 24,   \
  97                 .vbi_v_start_0  = 7,    \
  98                 .vbi_v_stop_0   = 22,   \
  99                 .video_v_start  = 24,   \
 100                 .video_v_stop   = 311,  \
 101                 .vbi_v_start_1  = 319
 102
 103 #define NORM_525_60                     \
 104                 .h_delay        = 8,    \
 105                 .h_delay0       = 138,  \
 106                 .h_start        = 0,    \
 107                 .h_stop         = 719,  \
 108                 .v_delay        = 22,   \
 109                 .vbi_v_start_0  = 10,   \
 110                 .vbi_v_stop_0   = 21,   \
 111                 .video_v_start  = 22,   \
 112                 .video_v_stop   = 262,  \
 113                 .vbi_v_start_1  = 273
 114
 115 /*
 116  * The following table is searched by tw68_s_std, first for a specific
 117  * match, then for an entry which contains the desired id.  The table
 118  * entries should therefore be ordered in ascending order of specificity.
 119  */
 120 static const struct tw68_tvnorm tvnorms[] = {
 121         {
 122                 .name           = "PAL", /* autodetect */
 123                 .id             = V4L2_STD_PAL,
 124                 NORM_625_50,
 125
 126                 .sync_control   = 0x18,
 127                 .luma_control   = 0x40,
 128                 .chroma_ctrl1   = 0x81,
 129                 .chroma_gain    = 0x2a,
 130                 .chroma_ctrl2   = 0x06,
 131                 .vgate_misc     = 0x1c,
 132                 .format         = VideoFormatPALBDGHI,
 133         }, {
 134                 .name           = "NTSC",
 135                 .id             = V4L2_STD_NTSC,
 136                 NORM_525_60,
 137
 138                 .sync_control   = 0x59,
 139                 .luma_control   = 0x40,
 140                 .chroma_ctrl1   = 0x89,
 141                 .chroma_gain    = 0x2a,
 142                 .chroma_ctrl2   = 0x0e,
 143                 .vgate_misc     = 0x18,
 144                 .format         = VideoFormatNTSC,
 145         }, {
 146                 .name           = "SECAM",
 147                 .id             = V4L2_STD_SECAM,
 148                 NORM_625_50,
 149
 150                 .sync_control   = 0x18,
 151                 .luma_control   = 0x1b,
 152                 .chroma_ctrl1   = 0xd1,
 153                 .chroma_gain    = 0x80,
 154                 .chroma_ctrl2   = 0x00,
 155                 .vgate_misc     = 0x1c,
 156                 .format         = VideoFormatSECAM,
 157         }, {
 158                 .name           = "PAL-M",
 159                 .id             = V4L2_STD_PAL_M,
 160                 NORM_525_60,
 161
 162                 .sync_control   = 0x59,
 163                 .luma_control   = 0x40,
 164                 .chroma_ctrl1   = 0xb9,
 165                 .chroma_gain    = 0x2a,
 166                 .chroma_ctrl2   = 0x0e,
 167                 .vgate_misc     = 0x18,
 168                 .format         = VideoFormatPALM,
 169         }, {
 170                 .name           = "PAL-Nc",
 171                 .id             = V4L2_STD_PAL_Nc,
 172                 NORM_625_50,
 173
 174                 .sync_control   = 0x18,
 175                 .luma_control   = 0x40,
 176                 .chroma_ctrl1   = 0xa1,
 177                 .chroma_gain    = 0x2a,
 178                 .chroma_ctrl2   = 0x06,
 179                 .vgate_misc     = 0x1c,
 180                 .format         = VideoFormatPALNC,
 181         }, {
 182                 .name           = "PAL-60",
 183                 .id             = V4L2_STD_PAL_60,
 184                 .h_delay        = 186,
 185                 .h_start        = 0,
 186                 .h_stop         = 719,
 187                 .v_delay        = 26,
 188                 .video_v_start  = 23,
 189                 .video_v_stop   = 262,
 190                 .vbi_v_start_0  = 10,
 191                 .vbi_v_stop_0   = 21,
 192                 .vbi_v_start_1  = 273,
 193
 194                 .sync_control   = 0x18,
 195                 .luma_control   = 0x40,
 196                 .chroma_ctrl1   = 0x81,
 197                 .chroma_gain    = 0x2a,
 198                 .chroma_ctrl2   = 0x06,
 199                 .vgate_misc     = 0x1c,
 200                 .format         = VideoFormatPAL60,
 201         }
 202 };
 203 #define TVNORMS ARRAY_SIZE(tvnorms)
 204
 205 static const struct tw68_format *format_by_fourcc(unsigned int fourcc)
 206 {
 207         unsigned int i;
 208
 209         for (i = 0; i < FORMATS; i++)
 210                 if (formats[i].fourcc == fourcc)
 211                         return formats+i;
 212         return NULL;
 213 }
 214
 215
 216 /* ------------------------------------------------------------------ */
 217 /*
 218  * Note that the cropping rectangles are described in terms of a single
 219  * frame, i.e. line positions are only 1/2 the interlaced equivalent
 220  */
 221 static void set_tvnorm(struct tw68_dev *dev, const struct tw68_tvnorm *norm)
 222 {
 223         if (norm != dev->tvnorm) {
 224                 dev->width = 720;
 225                 dev->height = (norm->id & V4L2_STD_525_60) ? 480 : 576;
 226                 dev->tvnorm = norm;
 227                 tw68_set_tvnorm_hw(dev);
 228         }
 229 }
 230
 231 /*
 232  * tw68_set_scale
 233  *
 234  * Scaling and Cropping for video decoding
 235  *
 236  * We are working with 3 values for horizontal and vertical - scale,
 237  * delay and active.
 238  *
 239  * HACTIVE represent the actual number of pixels in the "usable" image,
 240  * before scaling.  HDELAY represents the number of pixels skipped
 241  * between the start of the horizontal sync and the start of the image.
 242  * HSCALE is calculated using the formula
 243  *      HSCALE = (HACTIVE / (#pixels desired)) * 256
 244  *
 245  * The vertical registers are similar, except based upon the total number
 246  * of lines in the image, and the first line of the image (i.e. ignoring
 247  * vertical sync and VBI).
 248  *
 249  * Note that the number of bytes reaching the FIFO (and hence needing
 250  * to be processed by the DMAP program) is completely dependent upon
 251  * these values, especially HSCALE.
 252  *
 253  * Parameters:
 254  *      @dev            pointer to the device structure, needed for
 255  *                      getting current norm (as well as debug print)
 256  *      @width          actual image width (from user buffer)
 257  *      @height         actual image height
 258  *      @field          indicates Top, Bottom or Interlaced
 259  */
 260 static int tw68_set_scale(struct tw68_dev *dev, unsigned int width,
 261                           unsigned int height, enum v4l2_field field)
 262 {
 263         const struct tw68_tvnorm *norm = dev->tvnorm;
 264         /* set individually for debugging clarity */
 265         int hactive, hdelay, hscale;
 266         int vactive, vdelay, vscale;
 267         int comb;
 268
 269         if (V4L2_FIELD_HAS_BOTH(field)) /* if field is interlaced */
 270                 height /= 2;            /* we must set for 1-frame */
 271
 272         pr_debug("%s: width=%d, height=%d, both=%d\n"
 273                  "  tvnorm h_delay=%d, h_start=%d, h_stop=%d, v_delay=%d, v_start=%d, v_stop=%d\n",
 274                 __func__, width, height, V4L2_FIELD_HAS_BOTH(field),
 275                 norm->h_delay, norm->h_start, norm->h_stop,
 276                 norm->v_delay, norm->video_v_start,
 277                 norm->video_v_stop);
 278
 279         switch (dev->vdecoder) {
 280         case TW6800:
 281                 hdelay = norm->h_delay0;
 282                 break;
 283         default:
 284                 hdelay = norm->h_delay;
 285                 break;
 286         }
 287
 288         hdelay += norm->h_start;
 289         hactive = norm->h_stop - norm->h_start + 1;
 290
 291         hscale = (hactive * 256) / (width);
 292
 293         vdelay = norm->v_delay;
 294         vactive = ((norm->id & V4L2_STD_525_60) ? 524 : 624) / 2 - norm->video_v_start;
 295         vscale = (vactive * 256) / height;
 296
 297         pr_debug("%s: %dx%d [%s%s,%s]\n", __func__,
 298                 width, height,
 299                 V4L2_FIELD_HAS_TOP(field)    ? "T" : "",
 300                 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
 301                 v4l2_norm_to_name(dev->tvnorm->id));
 302         pr_debug("%s: hactive=%d, hdelay=%d, hscale=%d; vactive=%d, vdelay=%d, vscale=%d\n",
 303                  __func__,
 304                 hactive, hdelay, hscale, vactive, vdelay, vscale);
 305
 306         comb =  ((vdelay & 0x300)  >> 2) |
 307                 ((vactive & 0x300) >> 4) |
 308                 ((hdelay & 0x300)  >> 6) |
 309                 ((hactive & 0x300) >> 8);
 310         pr_debug("%s: setting CROP_HI=%02x, VDELAY_LO=%02x, VACTIVE_LO=%02x, HDELAY_LO=%02x, HACTIVE_LO=%02x\n",
 311                 __func__, comb, vdelay, vactive, hdelay, hactive);
 312         tw_writeb(TW68_CROP_HI, comb);
 313         tw_writeb(TW68_VDELAY_LO, vdelay & 0xff);
 314         tw_writeb(TW68_VACTIVE_LO, vactive & 0xff);
 315         tw_writeb(TW68_HDELAY_LO, hdelay & 0xff);
 316         tw_writeb(TW68_HACTIVE_LO, hactive & 0xff);
 317
 318         comb = ((vscale & 0xf00) >> 4) | ((hscale & 0xf00) >> 8);
 319         pr_debug("%s: setting SCALE_HI=%02x, VSCALE_LO=%02x, HSCALE_LO=%02x\n",
 320                  __func__, comb, vscale, hscale);
 321         tw_writeb(TW68_SCALE_HI, comb);
 322         tw_writeb(TW68_VSCALE_LO, vscale);
 323         tw_writeb(TW68_HSCALE_LO, hscale);
 324
 325         return 0;
 326 }
 327
 328 /* ------------------------------------------------------------------ */
 329
 330 int tw68_video_start_dma(struct tw68_dev *dev, struct tw68_buf *buf)
 331 {
 332         /* Set cropping and scaling */
 333         tw68_set_scale(dev, dev->width, dev->height, dev->field);
 334         /*
 335          *  Set start address for RISC program.  Note that if the DMAP
 336          *  processor is currently running, it must be stopped before
 337          *  a new address can be set.
 338          */
 339         tw_clearl(TW68_DMAC, TW68_DMAP_EN);
 340         tw_writel(TW68_DMAP_SA, buf->dma);
 341         /* Clear any pending interrupts */
 342         tw_writel(TW68_INTSTAT, dev->board_virqmask);
 343         /* Enable the risc engine and the fifo */
 344         tw_andorl(TW68_DMAC, 0xff, dev->fmt->twformat |
 345                 ColorFormatGamma | TW68_DMAP_EN | TW68_FIFO_EN);
 346         dev->pci_irqmask |= dev->board_virqmask;
 347         tw_setl(TW68_INTMASK, dev->pci_irqmask);
 348         return 0;
 349 }
 350
 351 /* ------------------------------------------------------------------ */
 352
 353 /* calc max # of buffers from size (must not exceed the 4MB virtual
 354  * address space per DMA channel) */
 355 static int tw68_buffer_count(unsigned int size, unsigned int count)
 356 {
 357         unsigned int maxcount;
 358
 359         maxcount = (4 * 1024 * 1024) / roundup(size, PAGE_SIZE);
 360         if (count > maxcount)
 361                 count = maxcount;
 362         return count;
 363 }
 364
 365 /* ------------------------------------------------------------- */
 366 /* vb2 queue operations                                          */
 367
 368 static int tw68_queue_setup(struct vb2_queue *q,
 369                            unsigned int *num_buffers, unsigned int *num_planes,
 370                            unsigned int sizes[], struct device *alloc_devs[])
 371 {
 372         struct tw68_dev *dev = vb2_get_drv_priv(q);
 373         unsigned tot_bufs = q->num_buffers + *num_buffers;
 374         unsigned size = (dev->fmt->depth * dev->width * dev->height) >> 3;
 375
 376         if (tot_bufs < 2)
 377                 tot_bufs = 2;
 378         tot_bufs = tw68_buffer_count(size, tot_bufs);
 379         *num_buffers = tot_bufs - q->num_buffers;
 380         /*
 381          * We allow create_bufs, but only if the sizeimage is >= as the
 382          * current sizeimage. The tw68_buffer_count calculation becomes quite
 383          * difficult otherwise.
 384          */
 385         if (*num_planes)
 386                 return sizes[0] < size ? -EINVAL : 0;
 387         *num_planes = 1;
 388         sizes[0] = size;
 389
 390         return 0;
 391 }
 392
 393 /*
 394  * The risc program for each buffers works as follows: it starts with a simple
 395  * 'JUMP to addr + 8', which is effectively a NOP. Then the program to DMA the
 396  * buffer follows and at the end we have a JUMP back to the start + 8 (skipping
 397  * the initial JUMP).
 398  *
 399  * This is the program of the first buffer to be queued if the active list is
 400  * empty and it just keeps DMAing this buffer without generating any interrupts.
 401  *
 402  * If a new buffer is added then the initial JUMP in the program generates an
 403  * interrupt as well which signals that the previous buffer has been DMAed
 404  * successfully and that it can be returned to userspace.
 405  *
 406  * It also sets the final jump of the previous buffer to the start of the new
 407  * buffer, thus chaining the new buffer into the DMA chain. This is a single
 408  * atomic u32 write, so there is no race condition.
 409  *
 410  * The end-result of all this that you only get an interrupt when a buffer
 411  * is ready, so the control flow is very easy.
 412  */
 413 static void tw68_buf_queue(struct vb2_buffer *vb)
 414 {
 415         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 416         struct vb2_queue *vq = vb->vb2_queue;
 417         struct tw68_dev *dev = vb2_get_drv_priv(vq);
 418         struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
 419         struct tw68_buf *prev;
 420         unsigned long flags;
 421
 422         spin_lock_irqsave(&dev->slock, flags);
 423
 424         /* append a 'JUMP to start of buffer' to the buffer risc program */
 425         buf->jmp[0] = cpu_to_le32(RISC_JUMP);
 426         buf->jmp[1] = cpu_to_le32(buf->dma + 8);
 427
 428         if (!list_empty(&dev->active)) {
 429                 prev = list_entry(dev->active.prev, struct tw68_buf, list);
 430                 buf->cpu[0] |= cpu_to_le32(RISC_INT_BIT);
 431                 prev->jmp[1] = cpu_to_le32(buf->dma);
 432         }
 433         list_add_tail(&buf->list, &dev->active);
 434         spin_unlock_irqrestore(&dev->slock, flags);
 435 }
 436
 437 /*
 438  * buffer_prepare
 439  *
 440  * Set the ancillary information into the buffer structure.  This
 441  * includes generating the necessary risc program if it hasn't already
 442  * been done for the current buffer format.
 443  * The structure fh contains the details of the format requested by the
 444  * user - type, width, height and #fields.  This is compared with the
 445  * last format set for the current buffer.  If they differ, the risc
 446  * code (which controls the filling of the buffer) is (re-)generated.
 447  */
 448 static int tw68_buf_prepare(struct vb2_buffer *vb)
 449 {
 450         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 451         struct vb2_queue *vq = vb->vb2_queue;
 452         struct tw68_dev *dev = vb2_get_drv_priv(vq);
 453         struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
 454         struct sg_table *dma = vb2_dma_sg_plane_desc(vb, 0);
 455         unsigned size, bpl;
 456
 457         size = (dev->width * dev->height * dev->fmt->depth) >> 3;
 458         if (vb2_plane_size(vb, 0) < size)
 459                 return -EINVAL;
 460         vb2_set_plane_payload(vb, 0, size);
 461
 462         bpl = (dev->width * dev->fmt->depth) >> 3;
 463         switch (dev->field) {
 464         case V4L2_FIELD_TOP:
 465                 tw68_risc_buffer(dev->pci, buf, dma->sgl,
 466                                  0, UNSET, bpl, 0, dev->height);
 467                 break;
 468         case V4L2_FIELD_BOTTOM:
 469                 tw68_risc_buffer(dev->pci, buf, dma->sgl,
 470                                  UNSET, 0, bpl, 0, dev->height);
 471                 break;
 472         case V4L2_FIELD_SEQ_TB:
 473                 tw68_risc_buffer(dev->pci, buf, dma->sgl,
 474                                  0, bpl * (dev->height >> 1),
 475                                  bpl, 0, dev->height >> 1);
 476                 break;
 477         case V4L2_FIELD_SEQ_BT:
 478                 tw68_risc_buffer(dev->pci, buf, dma->sgl,
 479                                  bpl * (dev->height >> 1), 0,
 480                                  bpl, 0, dev->height >> 1);
 481                 break;
 482         case V4L2_FIELD_INTERLACED:
 483         default:
 484                 tw68_risc_buffer(dev->pci, buf, dma->sgl,
 485                                  0, bpl, bpl, bpl, dev->height >> 1);
 486                 break;
 487         }
 488         return 0;
 489 }
 490
 491 static void tw68_buf_finish(struct vb2_buffer *vb)
 492 {
 493         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 494         struct vb2_queue *vq = vb->vb2_queue;
 495         struct tw68_dev *dev = vb2_get_drv_priv(vq);
 496         struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
 497
 498         pci_free_consistent(dev->pci, buf->size, buf->cpu, buf->dma);
 499 }
 500
 501 static int tw68_start_streaming(struct vb2_queue *q, unsigned int count)
 502 {
 503         struct tw68_dev *dev = vb2_get_drv_priv(q);
 504         struct tw68_buf *buf =
 505                 container_of(dev->active.next, struct tw68_buf, list);
 506
 507         dev->seqnr = 0;
 508         tw68_video_start_dma(dev, buf);
 509         return 0;
 510 }
 511
 512 static void tw68_stop_streaming(struct vb2_queue *q)
 513 {
 514         struct tw68_dev *dev = vb2_get_drv_priv(q);
 515
 516         /* Stop risc & fifo */
 517         tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN);
 518         while (!list_empty(&dev->active)) {
 519                 struct tw68_buf *buf =
 520                         container_of(dev->active.next, struct tw68_buf, list);
 521
 522                 list_del(&buf->list);
 523                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 524         }
 525 }
 526
 527 static const struct vb2_ops tw68_video_qops = {
 528         .queue_setup    = tw68_queue_setup,
 529         .buf_queue      = tw68_buf_queue,
 530         .buf_prepare    = tw68_buf_prepare,
 531         .buf_finish     = tw68_buf_finish,
 532         .start_streaming = tw68_start_streaming,
 533         .stop_streaming = tw68_stop_streaming,
 534         .wait_prepare   = vb2_ops_wait_prepare,
 535         .wait_finish    = vb2_ops_wait_finish,
 536 };
 537
 538 /* ------------------------------------------------------------------ */
 539
 540 static int tw68_s_ctrl(struct v4l2_ctrl *ctrl)
 541 {
 542         struct tw68_dev *dev =
 543                 container_of(ctrl->handler, struct tw68_dev, hdl);
 544
 545         switch (ctrl->id) {
 546         case V4L2_CID_BRIGHTNESS:
 547                 tw_writeb(TW68_BRIGHT, ctrl->val);
 548                 break;
 549         case V4L2_CID_HUE:
 550                 tw_writeb(TW68_HUE, ctrl->val);
 551                 break;
 552         case V4L2_CID_CONTRAST:
 553                 tw_writeb(TW68_CONTRAST, ctrl->val);
 554                 break;
 555         case V4L2_CID_SATURATION:
 556                 tw_writeb(TW68_SAT_U, ctrl->val);
 557                 tw_writeb(TW68_SAT_V, ctrl->val);
 558                 break;
 559         case V4L2_CID_COLOR_KILLER:
 560                 if (ctrl->val)
 561                         tw_andorb(TW68_MISC2, 0xe0, 0xe0);
 562                 else
 563                         tw_andorb(TW68_MISC2, 0xe0, 0x00);
 564                 break;
 565         case V4L2_CID_CHROMA_AGC:
 566                 if (ctrl->val)
 567                         tw_andorb(TW68_LOOP, 0x30, 0x20);
 568                 else
 569                         tw_andorb(TW68_LOOP, 0x30, 0x00);
 570                 break;
 571         }
 572         return 0;
 573 }
 574
 575 /* ------------------------------------------------------------------ */
 576
 577 /*
 578  * Note that this routine returns what is stored in the fh structure, and
 579  * does not interrogate any of the device registers.
 580  */
 581 static int tw68_g_fmt_vid_cap(struct file *file, void *priv,
 582                                 struct v4l2_format *f)
 583 {
 584         struct tw68_dev *dev = video_drvdata(file);
 585
 586         f->fmt.pix.width        = dev->width;
 587         f->fmt.pix.height       = dev->height;
 588         f->fmt.pix.field        = dev->field;
 589         f->fmt.pix.pixelformat  = dev->fmt->fourcc;
 590         f->fmt.pix.bytesperline =
 591                 (f->fmt.pix.width * (dev->fmt->depth)) >> 3;
 592         f->fmt.pix.sizeimage =
 593                 f->fmt.pix.height * f->fmt.pix.bytesperline;
 594         f->fmt.pix.colorspace   = V4L2_COLORSPACE_SMPTE170M;
 595         f->fmt.pix.priv = 0;
 596         return 0;
 597 }
 598
 599 static int tw68_try_fmt_vid_cap(struct file *file, void *priv,
 600                                                 struct v4l2_format *f)
 601 {
 602         struct tw68_dev *dev = video_drvdata(file);
 603         const struct tw68_format *fmt;
 604         enum v4l2_field field;
 605         unsigned int maxh;
 606
 607         fmt = format_by_fourcc(f->fmt.pix.pixelformat);
 608         if (NULL == fmt)
 609                 return -EINVAL;
 610
 611         field = f->fmt.pix.field;
 612         maxh  = (dev->tvnorm->id & V4L2_STD_525_60) ? 480 : 576;
 613
 614         switch (field) {
 615         case V4L2_FIELD_TOP:
 616         case V4L2_FIELD_BOTTOM:
 617                 break;
 618         case V4L2_FIELD_INTERLACED:
 619         case V4L2_FIELD_SEQ_BT:
 620         case V4L2_FIELD_SEQ_TB:
 621                 maxh = maxh * 2;
 622                 break;
 623         default:
 624                 field = (f->fmt.pix.height > maxh / 2)
 625                         ? V4L2_FIELD_INTERLACED
 626                         : V4L2_FIELD_BOTTOM;
 627                 break;
 628         }
 629
 630         f->fmt.pix.field = field;
 631         if (f->fmt.pix.width  < 48)
 632                 f->fmt.pix.width  = 48;
 633         if (f->fmt.pix.height < 32)
 634                 f->fmt.pix.height = 32;
 635         if (f->fmt.pix.width > 720)
 636                 f->fmt.pix.width = 720;
 637         if (f->fmt.pix.height > maxh)
 638                 f->fmt.pix.height = maxh;
 639         f->fmt.pix.width &= ~0x03;
 640         f->fmt.pix.bytesperline =
 641                 (f->fmt.pix.width * (fmt->depth)) >> 3;
 642         f->fmt.pix.sizeimage =
 643                 f->fmt.pix.height * f->fmt.pix.bytesperline;
 644         f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
 645         return 0;
 646 }
 647
 648 /*
 649  * Note that tw68_s_fmt_vid_cap sets the information into the fh structure,
 650  * and it will be used for all future new buffers.  However, there could be
 651  * some number of buffers on the "active" chain which will be filled before
 652  * the change takes place.
 653  */
 654 static int tw68_s_fmt_vid_cap(struct file *file, void *priv,
 655                                         struct v4l2_format *f)
 656 {
 657         struct tw68_dev *dev = video_drvdata(file);
 658         int err;
 659
 660         err = tw68_try_fmt_vid_cap(file, priv, f);
 661         if (0 != err)
 662                 return err;
 663
 664         dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
 665         dev->width = f->fmt.pix.width;
 666         dev->height = f->fmt.pix.height;
 667         dev->field = f->fmt.pix.field;
 668         return 0;
 669 }
 670
 671 static int tw68_enum_input(struct file *file, void *priv,
 672                                         struct v4l2_input *i)
 673 {
 674         struct tw68_dev *dev = video_drvdata(file);
 675         unsigned int n;
 676
 677         n = i->index;
 678         if (n >= TW68_INPUT_MAX)
 679                 return -EINVAL;
 680         i->index = n;
 681         i->type = V4L2_INPUT_TYPE_CAMERA;
 682         snprintf(i->name, sizeof(i->name), "Composite %d", n);
 683
 684         /* If the query is for the current input, get live data */
 685         if (n == dev->input) {
 686                 int v1 = tw_readb(TW68_STATUS1);
 687                 int v2 = tw_readb(TW68_MVSN);
 688
 689                 if (0 != (v1 & (1 << 7)))
 690                         i->status |= V4L2_IN_ST_NO_SYNC;
 691                 if (0 != (v1 & (1 << 6)))
 692                         i->status |= V4L2_IN_ST_NO_H_LOCK;
 693                 if (0 != (v1 & (1 << 2)))
 694                         i->status |= V4L2_IN_ST_NO_SIGNAL;
 695                 if (0 != (v1 & 1 << 1))
 696                         i->status |= V4L2_IN_ST_NO_COLOR;
 697                 if (0 != (v2 & (1 << 2)))
 698                         i->status |= V4L2_IN_ST_MACROVISION;
 699         }
 700         i->std = video_devdata(file)->tvnorms;
 701         return 0;
 702 }
 703
 704 static int tw68_g_input(struct file *file, void *priv, unsigned int *i)
 705 {
 706         struct tw68_dev *dev = video_drvdata(file);
 707
 708         *i = dev->input;
 709         return 0;
 710 }
 711
 712 static int tw68_s_input(struct file *file, void *priv, unsigned int i)
 713 {
 714         struct tw68_dev *dev = video_drvdata(file);
 715
 716         if (i >= TW68_INPUT_MAX)
 717                 return -EINVAL;
 718         dev->input = i;
 719         tw_andorb(TW68_INFORM, 0x03 << 2, dev->input << 2);
 720         return 0;
 721 }
 722
 723 static int tw68_querycap(struct file *file, void  *priv,
 724                                         struct v4l2_capability *cap)
 725 {
 726         struct tw68_dev *dev = video_drvdata(file);
 727
 728         strscpy(cap->driver, "tw68", sizeof(cap->driver));
 729         strscpy(cap->card, "Techwell Capture Card",
 730                 sizeof(cap->card));
 731         sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
 732         return 0;
 733 }
 734
 735 static int tw68_s_std(struct file *file, void *priv, v4l2_std_id id)
 736 {
 737         struct tw68_dev *dev = video_drvdata(file);
 738         unsigned int i;
 739
 740         if (vb2_is_busy(&dev->vidq))
 741                 return -EBUSY;
 742
 743         /* Look for match on complete norm id (may have mult bits) */
 744         for (i = 0; i < TVNORMS; i++) {
 745                 if (id == tvnorms[i].id)
 746                         break;
 747         }
 748
 749         /* If no exact match, look for norm which contains this one */
 750         if (i == TVNORMS) {
 751                 for (i = 0; i < TVNORMS; i++)
 752                         if (id & tvnorms[i].id)
 753                                 break;
 754         }
 755         /* If still not matched, give up */
 756         if (i == TVNORMS)
 757                 return -EINVAL;
 758
 759         set_tvnorm(dev, &tvnorms[i]);   /* do the actual setting */
 760         return 0;
 761 }
 762
 763 static int tw68_g_std(struct file *file, void *priv, v4l2_std_id *id)
 764 {
 765         struct tw68_dev *dev = video_drvdata(file);
 766
 767         *id = dev->tvnorm->id;
 768         return 0;
 769 }
 770
 771 static int tw68_enum_fmt_vid_cap(struct file *file, void  *priv,
 772                                         struct v4l2_fmtdesc *f)
 773 {
 774         if (f->index >= FORMATS)
 775                 return -EINVAL;
 776
 777         strscpy(f->description, formats[f->index].name,
 778                 sizeof(f->description));
 779
 780         f->pixelformat = formats[f->index].fourcc;
 781
 782         return 0;
 783 }
 784
 785 /*
 786  * Used strictly for internal development and debugging, this routine
 787  * prints out the current register contents for the tw68xx device.
 788  */
 789 static void tw68_dump_regs(struct tw68_dev *dev)
 790 {
 791         unsigned char line[80];
 792         int i, j, k;
 793         unsigned char *cptr;
 794
 795         pr_info("Full dump of TW68 registers:\n");
 796         /* First we do the PCI regs, 8 4-byte regs per line */
 797         for (i = 0; i < 0x100; i += 32) {
 798                 cptr = line;
 799                 cptr += sprintf(cptr, "%03x  ", i);
 800                 /* j steps through the next 4 words */
 801                 for (j = i; j < i + 16; j += 4)
 802                         cptr += sprintf(cptr, "%08x ", tw_readl(j));
 803                 *cptr++ = ' ';
 804                 for (; j < i + 32; j += 4)
 805                         cptr += sprintf(cptr, "%08x ", tw_readl(j));
 806                 *cptr++ = '\n';
 807                 *cptr = 0;
 808                 pr_info("%s", line);
 809         }
 810         /* Next the control regs, which are single-byte, address mod 4 */
 811         while (i < 0x400) {
 812                 cptr = line;
 813                 cptr += sprintf(cptr, "%03x ", i);
 814                 /* Print out 4 groups of 4 bytes */
 815                 for (j = 0; j < 4; j++) {
 816                         for (k = 0; k < 4; k++) {
 817                                 cptr += sprintf(cptr, "%02x ",
 818                                         tw_readb(i));
 819                                 i += 4;
 820                         }
 821                         *cptr++ = ' ';
 822                 }
 823                 *cptr++ = '\n';
 824                 *cptr = 0;
 825                 pr_info("%s", line);
 826         }
 827 }
 828
 829 static int vidioc_log_status(struct file *file, void *priv)
 830 {
 831         struct tw68_dev *dev = video_drvdata(file);
 832
 833         tw68_dump_regs(dev);
 834         return v4l2_ctrl_log_status(file, priv);
 835 }
 836
 837 #ifdef CONFIG_VIDEO_ADV_DEBUG
 838 static int vidioc_g_register(struct file *file, void *priv,
 839                               struct v4l2_dbg_register *reg)
 840 {
 841         struct tw68_dev *dev = video_drvdata(file);
 842
 843         if (reg->size == 1)
 844                 reg->val = tw_readb(reg->reg);
 845         else
 846                 reg->val = tw_readl(reg->reg);
 847         return 0;
 848 }
 849
 850 static int vidioc_s_register(struct file *file, void *priv,
 851                                 const struct v4l2_dbg_register *reg)
 852 {
 853         struct tw68_dev *dev = video_drvdata(file);
 854
 855         if (reg->size == 1)
 856                 tw_writeb(reg->reg, reg->val);
 857         else
 858                 tw_writel(reg->reg & 0xffff, reg->val);
 859         return 0;
 860 }
 861 #endif
 862
 863 static const struct v4l2_ctrl_ops tw68_ctrl_ops = {
 864         .s_ctrl = tw68_s_ctrl,
 865 };
 866
 867 static const struct v4l2_file_operations video_fops = {
 868         .owner                  = THIS_MODULE,
 869         .open                   = v4l2_fh_open,
 870         .release                = vb2_fop_release,
 871         .read                   = vb2_fop_read,
 872         .poll                   = vb2_fop_poll,
 873         .mmap                   = vb2_fop_mmap,
 874         .unlocked_ioctl         = video_ioctl2,
 875 };
 876
 877 static const struct v4l2_ioctl_ops video_ioctl_ops = {
 878         .vidioc_querycap                = tw68_querycap,
 879         .vidioc_enum_fmt_vid_cap        = tw68_enum_fmt_vid_cap,
 880         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
 881         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
 882         .vidioc_querybuf                = vb2_ioctl_querybuf,
 883         .vidioc_qbuf                    = vb2_ioctl_qbuf,
 884         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
 885         .vidioc_s_std                   = tw68_s_std,
 886         .vidioc_g_std                   = tw68_g_std,
 887         .vidioc_enum_input              = tw68_enum_input,
 888         .vidioc_g_input                 = tw68_g_input,
 889         .vidioc_s_input                 = tw68_s_input,
 890         .vidioc_streamon                = vb2_ioctl_streamon,
 891         .vidioc_streamoff               = vb2_ioctl_streamoff,
 892         .vidioc_g_fmt_vid_cap           = tw68_g_fmt_vid_cap,
 893         .vidioc_try_fmt_vid_cap         = tw68_try_fmt_vid_cap,
 894         .vidioc_s_fmt_vid_cap           = tw68_s_fmt_vid_cap,
 895         .vidioc_log_status              = vidioc_log_status,
 896         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
 897         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
 898 #ifdef CONFIG_VIDEO_ADV_DEBUG
 899         .vidioc_g_register              = vidioc_g_register,
 900         .vidioc_s_register              = vidioc_s_register,
 901 #endif
 902 };
 903
 904 static const struct video_device tw68_video_template = {
 905         .name                   = "tw68_video",
 906         .fops                   = &video_fops,
 907         .ioctl_ops              = &video_ioctl_ops,
 908         .release                = video_device_release_empty,
 909         .tvnorms                = TW68_NORMS,
 910         .device_caps            = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
 911                                   V4L2_CAP_STREAMING,
 912 };
 913
 914 /* ------------------------------------------------------------------ */
 915 /* exported stuff                                                     */
 916 void tw68_set_tvnorm_hw(struct tw68_dev *dev)
 917 {
 918         tw_andorb(TW68_SDT, 0x07, dev->tvnorm->format);
 919 }
 920
 921 int tw68_video_init1(struct tw68_dev *dev)
 922 {
 923         struct v4l2_ctrl_handler *hdl = &dev->hdl;
 924
 925         v4l2_ctrl_handler_init(hdl, 6);
 926         v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
 927                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 20);
 928         v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
 929                         V4L2_CID_CONTRAST, 0, 255, 1, 100);
 930         v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
 931                         V4L2_CID_SATURATION, 0, 255, 1, 128);
 932         /* NTSC only */
 933         v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
 934                         V4L2_CID_HUE, -128, 127, 1, 0);
 935         v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
 936                         V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
 937         v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
 938                         V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
 939         if (hdl->error) {
 940                 v4l2_ctrl_handler_free(hdl);
 941                 return hdl->error;
 942         }
 943         dev->v4l2_dev.ctrl_handler = hdl;
 944         v4l2_ctrl_handler_setup(hdl);
 945         return 0;
 946 }
 947
 948 int tw68_video_init2(struct tw68_dev *dev, int video_nr)
 949 {
 950         int ret;
 951
 952         set_tvnorm(dev, &tvnorms[0]);
 953
 954         dev->fmt      = format_by_fourcc(V4L2_PIX_FMT_BGR24);
 955         dev->width    = 720;
 956         dev->height   = 576;
 957         dev->field    = V4L2_FIELD_INTERLACED;
 958
 959         INIT_LIST_HEAD(&dev->active);
 960         dev->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 961         dev->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
 962         dev->vidq.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ | VB2_DMABUF;
 963         dev->vidq.ops = &tw68_video_qops;
 964         dev->vidq.mem_ops = &vb2_dma_sg_memops;
 965         dev->vidq.drv_priv = dev;
 966         dev->vidq.gfp_flags = __GFP_DMA32 | __GFP_KSWAPD_RECLAIM;
 967         dev->vidq.buf_struct_size = sizeof(struct tw68_buf);
 968         dev->vidq.lock = &dev->lock;
 969         dev->vidq.min_buffers_needed = 2;
 970         dev->vidq.dev = &dev->pci->dev;
 971         ret = vb2_queue_init(&dev->vidq);
 972         if (ret)
 973                 return ret;
 974         dev->vdev = tw68_video_template;
 975         dev->vdev.v4l2_dev = &dev->v4l2_dev;
 976         dev->vdev.lock = &dev->lock;
 977         dev->vdev.queue = &dev->vidq;
 978         video_set_drvdata(&dev->vdev, dev);
 979         return video_register_device(&dev->vdev, VFL_TYPE_GRABBER, video_nr);
 980 }
 981
 982 /*
 983  * tw68_irq_video_done
 984  */
 985 void tw68_irq_video_done(struct tw68_dev *dev, unsigned long status)
 986 {
 987         __u32 reg;
 988
 989         /* reset interrupts handled by this routine */
 990         tw_writel(TW68_INTSTAT, status);
 991         /*
 992          * Check most likely first
 993          *
 994          * DMAPI shows we have reached the end of the risc code
 995          * for the current buffer.
 996          */
 997         if (status & TW68_DMAPI) {
 998                 struct tw68_buf *buf;
 999
1000                 spin_lock(&dev->slock);
1001                 buf = list_entry(dev->active.next, struct tw68_buf, list);
1002                 list_del(&buf->list);
1003                 spin_unlock(&dev->slock);
1004                 buf->vb.vb2_buf.timestamp = ktime_get_ns();
1005                 buf->vb.field = dev->field;
1006                 buf->vb.sequence = dev->seqnr++;
1007                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
1008                 status &= ~(TW68_DMAPI);
1009                 if (0 == status)
1010                         return;
1011         }
1012         if (status & (TW68_VLOCK | TW68_HLOCK))
1013                 dev_dbg(&dev->pci->dev, "Lost sync\n");
1014         if (status & TW68_PABORT)
1015                 dev_err(&dev->pci->dev, "PABORT interrupt\n");
1016         if (status & TW68_DMAPERR)
1017                 dev_err(&dev->pci->dev, "DMAPERR interrupt\n");
1018         /*
1019          * On TW6800, FDMIS is apparently generated if video input is switched
1020          * during operation.  Therefore, it is not enabled for that chip.
1021          */
1022         if (status & TW68_FDMIS)
1023                 dev_dbg(&dev->pci->dev, "FDMIS interrupt\n");
1024         if (status & TW68_FFOF) {
1025                 /* probably a logic error */
1026                 reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN;
1027                 tw_clearl(TW68_DMAC, TW68_FIFO_EN);
1028                 dev_dbg(&dev->pci->dev, "FFOF interrupt\n");
1029                 tw_setl(TW68_DMAC, reg);
1030         }
1031         if (status & TW68_FFERR)
1032                 dev_dbg(&dev->pci->dev, "FFERR interrupt\n");
1033 }