drivers/media/pci/ngene/ngene-core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ngene.c: nGene PCIe bridge driver
   4  *
   5  * Copyright (C) 2005-2007 Micronas
   6  *
   7  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   8  *                         Modifications for new nGene firmware,
   9  *                         support for EEPROM-copying,
  10  *                         support for new dual DVB-S2 card prototype
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/poll.h>
  17 #include <linux/io.h>
  18 #include <asm/div64.h>
  19 #include <linux/pci.h>
  20 #include <linux/timer.h>
  21 #include <linux/byteorder/generic.h>
  22 #include <linux/firmware.h>
  23 #include <linux/vmalloc.h>
  24
  25 #include "ngene.h"
  26
  27 static int one_adapter;
  28 module_param(one_adapter, int, 0444);
  29 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
  30
  31 static int shutdown_workaround;
  32 module_param(shutdown_workaround, int, 0644);
  33 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
  34
  35 static int debug;
  36 module_param(debug, int, 0444);
  37 MODULE_PARM_DESC(debug, "Print debugging information.");
  38
  39 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  40
  41 #define ngwriteb(dat, adr)         writeb((dat), dev->iomem + (adr))
  42 #define ngwritel(dat, adr)         writel((dat), dev->iomem + (adr))
  43 #define ngwriteb(dat, adr)         writeb((dat), dev->iomem + (adr))
  44 #define ngreadl(adr)               readl(dev->iomem + (adr))
  45 #define ngreadb(adr)               readb(dev->iomem + (adr))
  46 #define ngcpyto(adr, src, count)   memcpy_toio(dev->iomem + (adr), (src), (count))
  47 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count))
  48
  49 /****************************************************************************/
  50 /* nGene interrupt handler **************************************************/
  51 /****************************************************************************/
  52
  53 static void event_tasklet(unsigned long data)
  54 {
  55         struct ngene *dev = (struct ngene *)data;
  56
  57         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
  58                 struct EVENT_BUFFER Event =
  59                         dev->EventQueue[dev->EventQueueReadIndex];
  60                 dev->EventQueueReadIndex =
  61                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
  62
  63                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
  64                         dev->TxEventNotify(dev, Event.TimeStamp);
  65                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
  66                         dev->RxEventNotify(dev, Event.TimeStamp,
  67                                            Event.RXCharacter);
  68         }
  69 }
  70
  71 static void demux_tasklet(unsigned long data)
  72 {
  73         struct ngene_channel *chan = (struct ngene_channel *)data;
  74         struct device *pdev = &chan->dev->pci_dev->dev;
  75         struct SBufferHeader *Cur = chan->nextBuffer;
  76
  77         spin_lock_irq(&chan->state_lock);
  78
  79         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
  80                 if (chan->mode & NGENE_IO_TSOUT) {
  81                         u32 Flags = chan->DataFormatFlags;
  82                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
  83                                 Flags |= BEF_OVERFLOW;
  84                         if (chan->pBufferExchange) {
  85                                 if (!chan->pBufferExchange(chan,
  86                                                            Cur->Buffer1,
  87                                                            chan->Capture1Length,
  88                                                            Cur->ngeneBuffer.SR.
  89                                                            Clock, Flags)) {
  90                                         /*
  91                                            We didn't get data
  92                                            Clear in service flag to make sure we
  93                                            get called on next interrupt again.
  94                                            leave fill/empty (0x80) flag alone
  95                                            to avoid hardware running out of
  96                                            buffers during startup, we hold only
  97                                            in run state ( the source may be late
  98                                            delivering data )
  99                                         */
 100
 101                                         if (chan->HWState == HWSTATE_RUN) {
 102                                                 Cur->ngeneBuffer.SR.Flags &=
 103                                                         ~0x40;
 104                                                 break;
 105                                                 /* Stop processing stream */
 106                                         }
 107                                 } else {
 108                                         /* We got a valid buffer,
 109                                            so switch to run state */
 110                                         chan->HWState = HWSTATE_RUN;
 111                                 }
 112                         } else {
 113                                 dev_err(pdev, "OOPS\n");
 114                                 if (chan->HWState == HWSTATE_RUN) {
 115                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 116                                         break;  /* Stop processing stream */
 117                                 }
 118                         }
 119                         if (chan->AudioDTOUpdated) {
 120                                 dev_info(pdev, "Update AudioDTO = %d\n",
 121                                          chan->AudioDTOValue);
 122                                 Cur->ngeneBuffer.SR.DTOUpdate =
 123                                         chan->AudioDTOValue;
 124                                 chan->AudioDTOUpdated = 0;
 125                         }
 126                 } else {
 127                         if (chan->HWState == HWSTATE_RUN) {
 128                                 u32 Flags = chan->DataFormatFlags;
 129                                 IBufferExchange *exch1 = chan->pBufferExchange;
 130                                 IBufferExchange *exch2 = chan->pBufferExchange2;
 131                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 132                                         Flags |= BEF_EVEN_FIELD;
 133                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 134                                         Flags |= BEF_OVERFLOW;
 135                                 spin_unlock_irq(&chan->state_lock);
 136                                 if (exch1)
 137                                         exch1(chan, Cur->Buffer1,
 138                                                 chan->Capture1Length,
 139                                                 Cur->ngeneBuffer.SR.Clock,
 140                                                 Flags);
 141                                 if (exch2)
 142                                         exch2(chan, Cur->Buffer2,
 143                                                 chan->Capture2Length,
 144                                                 Cur->ngeneBuffer.SR.Clock,
 145                                                 Flags);
 146                                 spin_lock_irq(&chan->state_lock);
 147                         } else if (chan->HWState != HWSTATE_STOP)
 148                                 chan->HWState = HWSTATE_RUN;
 149                 }
 150                 Cur->ngeneBuffer.SR.Flags = 0x00;
 151                 Cur = Cur->Next;
 152         }
 153         chan->nextBuffer = Cur;
 154
 155         spin_unlock_irq(&chan->state_lock);
 156 }
 157
 158 static irqreturn_t irq_handler(int irq, void *dev_id)
 159 {
 160         struct ngene *dev = (struct ngene *)dev_id;
 161         struct device *pdev = &dev->pci_dev->dev;
 162         u32 icounts = 0;
 163         irqreturn_t rc = IRQ_NONE;
 164         u32 i = MAX_STREAM;
 165         u8 *tmpCmdDoneByte;
 166
 167         if (dev->BootFirmware) {
 168                 icounts = ngreadl(NGENE_INT_COUNTS);
 169                 if (icounts != dev->icounts) {
 170                         ngwritel(0, FORCE_NMI);
 171                         dev->cmd_done = 1;
 172                         wake_up(&dev->cmd_wq);
 173                         dev->icounts = icounts;
 174                         rc = IRQ_HANDLED;
 175                 }
 176                 return rc;
 177         }
 178
 179         ngwritel(0, FORCE_NMI);
 180
 181         spin_lock(&dev->cmd_lock);
 182         tmpCmdDoneByte = dev->CmdDoneByte;
 183         if (tmpCmdDoneByte &&
 184             (*tmpCmdDoneByte ||
 185             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 186                 dev->CmdDoneByte = NULL;
 187                 dev->cmd_done = 1;
 188                 wake_up(&dev->cmd_wq);
 189                 rc = IRQ_HANDLED;
 190         }
 191         spin_unlock(&dev->cmd_lock);
 192
 193         if (dev->EventBuffer->EventStatus & 0x80) {
 194                 u8 nextWriteIndex =
 195                         (dev->EventQueueWriteIndex + 1) &
 196                         (EVENT_QUEUE_SIZE - 1);
 197                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 198                         dev->EventQueue[dev->EventQueueWriteIndex] =
 199                                 *(dev->EventBuffer);
 200                         dev->EventQueueWriteIndex = nextWriteIndex;
 201                 } else {
 202                         dev_err(pdev, "event overflow\n");
 203                         dev->EventQueueOverflowCount += 1;
 204                         dev->EventQueueOverflowFlag = 1;
 205                 }
 206                 dev->EventBuffer->EventStatus &= ~0x80;
 207                 tasklet_schedule(&dev->event_tasklet);
 208                 rc = IRQ_HANDLED;
 209         }
 210
 211         while (i > 0) {
 212                 i--;
 213                 spin_lock(&dev->channel[i].state_lock);
 214                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 215                 if (dev->channel[i].nextBuffer) {
 216                         if ((dev->channel[i].nextBuffer->
 217                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 218                                 dev->channel[i].nextBuffer->
 219                                         ngeneBuffer.SR.Flags |= 0x40;
 220                                 tasklet_schedule(
 221                                         &dev->channel[i].demux_tasklet);
 222                                 rc = IRQ_HANDLED;
 223                         }
 224                 }
 225                 spin_unlock(&dev->channel[i].state_lock);
 226         }
 227
 228         /* Request might have been processed by a previous call. */
 229         return IRQ_HANDLED;
 230 }
 231
 232 /****************************************************************************/
 233 /* nGene command interface **************************************************/
 234 /****************************************************************************/
 235
 236 static void dump_command_io(struct ngene *dev)
 237 {
 238         struct device *pdev = &dev->pci_dev->dev;
 239         u8 buf[8], *b;
 240
 241         ngcpyfrom(buf, HOST_TO_NGENE, 8);
 242         dev_err(pdev, "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf);
 243
 244         ngcpyfrom(buf, NGENE_TO_HOST, 8);
 245         dev_err(pdev, "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf);
 246
 247         b = dev->hosttongene;
 248         dev_err(pdev, "dev->hosttongene (%p): %*ph\n", b, 8, b);
 249
 250         b = dev->ngenetohost;
 251         dev_err(pdev, "dev->ngenetohost (%p): %*ph\n", b, 8, b);
 252 }
 253
 254 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 255 {
 256         struct device *pdev = &dev->pci_dev->dev;
 257         int ret;
 258         u8 *tmpCmdDoneByte;
 259
 260         dev->cmd_done = 0;
 261
 262         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 263                 dev->BootFirmware = 1;
 264                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 265                 ngwritel(0, NGENE_COMMAND);
 266                 ngwritel(0, NGENE_COMMAND_HI);
 267                 ngwritel(0, NGENE_STATUS);
 268                 ngwritel(0, NGENE_STATUS_HI);
 269                 ngwritel(0, NGENE_EVENT);
 270                 ngwritel(0, NGENE_EVENT_HI);
 271         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 272                 u64 fwio = dev->PAFWInterfaceBuffer;
 273
 274                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 275                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 276                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 277                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 278                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 279                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 280         }
 281
 282         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 283
 284         if (dev->BootFirmware)
 285                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 286
 287         spin_lock_irq(&dev->cmd_lock);
 288         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 289         if (!com->out_len)
 290                 tmpCmdDoneByte++;
 291         *tmpCmdDoneByte = 0;
 292         dev->ngenetohost[0] = 0;
 293         dev->ngenetohost[1] = 0;
 294         dev->CmdDoneByte = tmpCmdDoneByte;
 295         spin_unlock_irq(&dev->cmd_lock);
 296
 297         /* Notify 8051. */
 298         ngwritel(1, FORCE_INT);
 299
 300         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 301         if (!ret) {
 302                 /*ngwritel(0, FORCE_NMI);*/
 303
 304                 dev_err(pdev, "Command timeout cmd=%02x prev=%02x\n",
 305                         com->cmd.hdr.Opcode, dev->prev_cmd);
 306                 dump_command_io(dev);
 307                 return -1;
 308         }
 309         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 310                 dev->BootFirmware = 0;
 311
 312         dev->prev_cmd = com->cmd.hdr.Opcode;
 313
 314         if (!com->out_len)
 315                 return 0;
 316
 317         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 318
 319         return 0;
 320 }
 321
 322 int ngene_command(struct ngene *dev, struct ngene_command *com)
 323 {
 324         int result;
 325
 326         mutex_lock(&dev->cmd_mutex);
 327         result = ngene_command_mutex(dev, com);
 328         mutex_unlock(&dev->cmd_mutex);
 329         return result;
 330 }
 331
 332
 333 static int ngene_command_load_firmware(struct ngene *dev,
 334                                        u8 *ngene_fw, u32 size)
 335 {
 336 #define FIRSTCHUNK (1024)
 337         u32 cleft;
 338         struct ngene_command com;
 339
 340         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 341         com.cmd.hdr.Length = 0;
 342         com.in_len = 0;
 343         com.out_len = 0;
 344
 345         ngene_command(dev, &com);
 346
 347         cleft = (size + 3) & ~3;
 348         if (cleft > FIRSTCHUNK) {
 349                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 350                         cleft - FIRSTCHUNK);
 351                 cleft = FIRSTCHUNK;
 352         }
 353         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 354
 355         memset(&com, 0, sizeof(struct ngene_command));
 356         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 357         com.cmd.hdr.Length = 4;
 358         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 359         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 360         com.in_len = 4;
 361         com.out_len = 0;
 362
 363         return ngene_command(dev, &com);
 364 }
 365
 366
 367 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 368 {
 369         struct ngene_command com;
 370
 371         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 372         com.cmd.hdr.Length = 1;
 373         com.cmd.ConfigureBuffers.config = config;
 374         com.in_len = 1;
 375         com.out_len = 0;
 376
 377         if (ngene_command(dev, &com) < 0)
 378                 return -EIO;
 379         return 0;
 380 }
 381
 382 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 383 {
 384         struct ngene_command com;
 385
 386         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 387         com.cmd.hdr.Length = 6;
 388         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
 389         com.in_len = 6;
 390         com.out_len = 0;
 391
 392         if (ngene_command(dev, &com) < 0)
 393                 return -EIO;
 394
 395         return 0;
 396 }
 397
 398 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 399 {
 400         struct ngene_command com;
 401
 402         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 403         com.cmd.hdr.Length = 1;
 404         com.cmd.SetGpioPin.select = select | (level << 7);
 405         com.in_len = 1;
 406         com.out_len = 0;
 407
 408         return ngene_command(dev, &com);
 409 }
 410
 411
 412 /*
 413  02000640 is sample on rising edge.
 414  02000740 is sample on falling edge.
 415  02000040 is ignore "valid" signal
 416
 417  0: FD_CTL1 Bit 7,6 must be 0,1
 418     7   disable(fw controlled)
 419     6   0-AUX,1-TS
 420     5   0-par,1-ser
 421     4   0-lsb/1-msb
 422     3,2 reserved
 423     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 424  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 425  2: FD_STA is read-only. 0-sync
 426  3: FD_INSYNC is number of 47s to trigger "in sync".
 427  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 428  5: FD_MAXBYTE1 is low-order of bytes per packet.
 429  6: FD_MAXBYTE2 is high-order of bytes per packet.
 430  7: Top byte is unused.
 431 */
 432
 433 /****************************************************************************/
 434
 435 static u8 TSFeatureDecoderSetup[8 * 5] = {
 436         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 437         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 438         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 439         0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 440         0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
 441 };
 442
 443 /* Set NGENE I2S Config to 16 bit packed */
 444 static u8 I2SConfiguration[] = {
 445         0x00, 0x10, 0x00, 0x00,
 446         0x80, 0x10, 0x00, 0x00,
 447 };
 448
 449 static u8 SPDIFConfiguration[10] = {
 450         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 451 };
 452
 453 /* Set NGENE I2S Config to transport stream compatible mode */
 454
 455 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
 456
 457 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
 458
 459 static u8 ITUDecoderSetup[4][16] = {
 460         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 461          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 462         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 463          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 464         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 465          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 466         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 467          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 468 };
 469
 470 /*
 471  * 50 48 60 gleich
 472  * 27p50 9f 00 22 80 42 69 18 ...
 473  * 27p60 93 00 22 80 82 69 1c ...
 474  */
 475
 476 /* Maxbyte to 1144 (for raw data) */
 477 static u8 ITUFeatureDecoderSetup[8] = {
 478         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 479 };
 480
 481 void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 482 {
 483         u32 *ptr = Buffer;
 484
 485         memset(Buffer, TS_FILLER, Length);
 486         while (Length > 0) {
 487                 if (Flags & DF_SWAP32)
 488                         *ptr = 0x471FFF10;
 489                 else
 490                         *ptr = 0x10FF1F47;
 491                 ptr += (188 / 4);
 492                 Length -= 188;
 493         }
 494 }
 495
 496
 497 static void flush_buffers(struct ngene_channel *chan)
 498 {
 499         u8 val;
 500
 501         do {
 502                 msleep(1);
 503                 spin_lock_irq(&chan->state_lock);
 504                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 505                 spin_unlock_irq(&chan->state_lock);
 506         } while (val);
 507 }
 508
 509 static void clear_buffers(struct ngene_channel *chan)
 510 {
 511         struct SBufferHeader *Cur = chan->nextBuffer;
 512
 513         do {
 514                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 515                 if (chan->mode & NGENE_IO_TSOUT)
 516                         FillTSBuffer(Cur->Buffer1,
 517                                      chan->Capture1Length,
 518                                      chan->DataFormatFlags);
 519                 Cur = Cur->Next;
 520         } while (Cur != chan->nextBuffer);
 521
 522         if (chan->mode & NGENE_IO_TSOUT) {
 523                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 524                         chan->AudioDTOValue;
 525                 chan->AudioDTOUpdated = 0;
 526
 527                 Cur = chan->TSIdleBuffer.Head;
 528
 529                 do {
 530                         memset(&Cur->ngeneBuffer.SR, 0,
 531                                sizeof(Cur->ngeneBuffer.SR));
 532                         FillTSBuffer(Cur->Buffer1,
 533                                      chan->Capture1Length,
 534                                      chan->DataFormatFlags);
 535                         Cur = Cur->Next;
 536                 } while (Cur != chan->TSIdleBuffer.Head);
 537         }
 538 }
 539
 540 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
 541                                         u8 control, u8 mode, u8 flags)
 542 {
 543         struct device *pdev = &dev->pci_dev->dev;
 544         struct ngene_channel *chan = &dev->channel[stream];
 545         struct ngene_command com;
 546         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 547         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 548         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 549         u16 BsSDO = 0x9B00;
 550
 551         memset(&com, 0, sizeof(com));
 552         com.cmd.hdr.Opcode = CMD_CONTROL;
 553         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 554         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 555         if (chan->mode & NGENE_IO_TSOUT)
 556                 com.cmd.StreamControl.Stream |= 0x07;
 557         com.cmd.StreamControl.Control = control |
 558                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 559         com.cmd.StreamControl.Mode = mode;
 560         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 561         com.out_len = 0;
 562
 563         dev_dbg(pdev, "Stream=%02x, Control=%02x, Mode=%02x\n",
 564                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 565                 com.cmd.StreamControl.Mode);
 566
 567         chan->Mode = mode;
 568
 569         if (!(control & 0x80)) {
 570                 spin_lock_irq(&chan->state_lock);
 571                 if (chan->State == KSSTATE_RUN) {
 572                         chan->State = KSSTATE_ACQUIRE;
 573                         chan->HWState = HWSTATE_STOP;
 574                         spin_unlock_irq(&chan->state_lock);
 575                         if (ngene_command(dev, &com) < 0)
 576                                 return -1;
 577                         /* clear_buffers(chan); */
 578                         flush_buffers(chan);
 579                         return 0;
 580                 }
 581                 spin_unlock_irq(&chan->state_lock);
 582                 return 0;
 583         }
 584
 585         if (mode & SMODE_AUDIO_CAPTURE) {
 586                 com.cmd.StreamControl.CaptureBlockCount =
 587                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 588                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 589         } else if (mode & SMODE_TRANSPORT_STREAM) {
 590                 com.cmd.StreamControl.CaptureBlockCount =
 591                         chan->Capture1Length / TS_BLOCK_SIZE;
 592                 com.cmd.StreamControl.MaxLinesPerField =
 593                         chan->Capture1Length / TS_BLOCK_SIZE;
 594                 com.cmd.StreamControl.Buffer_Address =
 595                         chan->TSRingBuffer.PAHead;
 596                 if (chan->mode & NGENE_IO_TSOUT) {
 597                         com.cmd.StreamControl.BytesPerVBILine =
 598                                 chan->Capture1Length / TS_BLOCK_SIZE;
 599                         com.cmd.StreamControl.Stream |= 0x07;
 600                 }
 601         } else {
 602                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 603                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 604                 com.cmd.StreamControl.MinLinesPerField = 100;
 605                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 606
 607                 if (mode & SMODE_VBI_CAPTURE) {
 608                         com.cmd.StreamControl.MaxVBILinesPerField =
 609                                 chan->nVBILines;
 610                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 611                         com.cmd.StreamControl.BytesPerVBILine =
 612                                 chan->nBytesPerVBILine;
 613                 }
 614                 if (flags & SFLAG_COLORBAR)
 615                         com.cmd.StreamControl.Stream |= 0x04;
 616         }
 617
 618         spin_lock_irq(&chan->state_lock);
 619         if (mode & SMODE_AUDIO_CAPTURE) {
 620                 chan->nextBuffer = chan->RingBuffer.Head;
 621                 if (mode & SMODE_AUDIO_SPDIF) {
 622                         com.cmd.StreamControl.SetupDataLen =
 623                                 sizeof(SPDIFConfiguration);
 624                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 625                         memcpy(com.cmd.StreamControl.SetupData,
 626                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 627                 } else {
 628                         com.cmd.StreamControl.SetupDataLen = 4;
 629                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 630                         memcpy(com.cmd.StreamControl.SetupData,
 631                                I2SConfiguration +
 632                                4 * dev->card_info->i2s[stream], 4);
 633                 }
 634         } else if (mode & SMODE_TRANSPORT_STREAM) {
 635                 chan->nextBuffer = chan->TSRingBuffer.Head;
 636                 if (stream >= STREAM_AUDIOIN1) {
 637                         if (chan->mode & NGENE_IO_TSOUT) {
 638                                 com.cmd.StreamControl.SetupDataLen =
 639                                         sizeof(TS_I2SOutConfiguration);
 640                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 641                                 memcpy(com.cmd.StreamControl.SetupData,
 642                                        TS_I2SOutConfiguration,
 643                                        sizeof(TS_I2SOutConfiguration));
 644                         } else {
 645                                 com.cmd.StreamControl.SetupDataLen =
 646                                         sizeof(TS_I2SConfiguration);
 647                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 648                                 memcpy(com.cmd.StreamControl.SetupData,
 649                                        TS_I2SConfiguration,
 650                                        sizeof(TS_I2SConfiguration));
 651                         }
 652                 } else {
 653                         com.cmd.StreamControl.SetupDataLen = 8;
 654                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 655                         memcpy(com.cmd.StreamControl.SetupData,
 656                                TSFeatureDecoderSetup +
 657                                8 * dev->card_info->tsf[stream], 8);
 658                 }
 659         } else {
 660                 chan->nextBuffer = chan->RingBuffer.Head;
 661                 com.cmd.StreamControl.SetupDataLen =
 662                         16 + sizeof(ITUFeatureDecoderSetup);
 663                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 664                 memcpy(com.cmd.StreamControl.SetupData,
 665                        ITUDecoderSetup[chan->itumode], 16);
 666                 memcpy(com.cmd.StreamControl.SetupData + 16,
 667                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 668         }
 669         clear_buffers(chan);
 670         chan->State = KSSTATE_RUN;
 671         if (mode & SMODE_TRANSPORT_STREAM)
 672                 chan->HWState = HWSTATE_RUN;
 673         else
 674                 chan->HWState = HWSTATE_STARTUP;
 675         spin_unlock_irq(&chan->state_lock);
 676
 677         if (ngene_command(dev, &com) < 0)
 678                 return -1;
 679
 680         return 0;
 681 }
 682
 683 void set_transfer(struct ngene_channel *chan, int state)
 684 {
 685         struct device *pdev = &chan->dev->pci_dev->dev;
 686         u8 control = 0, mode = 0, flags = 0;
 687         struct ngene *dev = chan->dev;
 688         int ret;
 689
 690         /*
 691         dev_info(pdev, "st %d\n", state);
 692         msleep(100);
 693         */
 694
 695         if (state) {
 696                 if (chan->running) {
 697                         dev_info(pdev, "already running\n");
 698                         return;
 699                 }
 700         } else {
 701                 if (!chan->running) {
 702                         dev_info(pdev, "already stopped\n");
 703                         return;
 704                 }
 705         }
 706
 707         if (dev->card_info->switch_ctrl)
 708                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
 709
 710         if (state) {
 711                 spin_lock_irq(&chan->state_lock);
 712
 713                 /* dev_info(pdev, "lock=%08x\n",
 714                           ngreadl(0x9310)); */
 715                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 716                 control = 0x80;
 717                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
 718                         chan->Capture1Length = 512 * 188;
 719                         mode = SMODE_TRANSPORT_STREAM;
 720                 }
 721                 if (chan->mode & NGENE_IO_TSOUT) {
 722                         chan->pBufferExchange = tsout_exchange;
 723                         /* 0x66666666 = 50MHz *2^33 /250MHz */
 724                         chan->AudioDTOValue = 0x80000000;
 725                         chan->AudioDTOUpdated = 1;
 726                 }
 727                 if (chan->mode & NGENE_IO_TSIN)
 728                         chan->pBufferExchange = tsin_exchange;
 729                 spin_unlock_irq(&chan->state_lock);
 730         }
 731                 /* else dev_info(pdev, "lock=%08x\n",
 732                            ngreadl(0x9310)); */
 733
 734         mutex_lock(&dev->stream_mutex);
 735         ret = ngene_command_stream_control(dev, chan->number,
 736                                            control, mode, flags);
 737         mutex_unlock(&dev->stream_mutex);
 738
 739         if (!ret)
 740                 chan->running = state;
 741         else
 742                 dev_err(pdev, "%s %d failed\n", __func__, state);
 743         if (!state) {
 744                 spin_lock_irq(&chan->state_lock);
 745                 chan->pBufferExchange = NULL;
 746                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 747                 spin_unlock_irq(&chan->state_lock);
 748         }
 749 }
 750
 751
 752 /****************************************************************************/
 753 /* nGene hardware init and release functions ********************************/
 754 /****************************************************************************/
 755
 756 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
 757 {
 758         struct SBufferHeader *Cur = rb->Head;
 759         u32 j;
 760
 761         if (!Cur)
 762                 return;
 763
 764         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
 765                 if (Cur->Buffer1)
 766                         pci_free_consistent(dev->pci_dev,
 767                                             rb->Buffer1Length,
 768                                             Cur->Buffer1,
 769                                             Cur->scList1->Address);
 770
 771                 if (Cur->Buffer2)
 772                         pci_free_consistent(dev->pci_dev,
 773                                             rb->Buffer2Length,
 774                                             Cur->Buffer2,
 775                                             Cur->scList2->Address);
 776         }
 777
 778         if (rb->SCListMem)
 779                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
 780                                     rb->SCListMem, rb->PASCListMem);
 781
 782         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
 783 }
 784
 785 static void free_idlebuffer(struct ngene *dev,
 786                      struct SRingBufferDescriptor *rb,
 787                      struct SRingBufferDescriptor *tb)
 788 {
 789         int j;
 790         struct SBufferHeader *Cur = tb->Head;
 791
 792         if (!rb->Head)
 793                 return;
 794         free_ringbuffer(dev, rb);
 795         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
 796                 Cur->Buffer2 = NULL;
 797                 Cur->scList2 = NULL;
 798                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
 799                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
 800         }
 801 }
 802
 803 static void free_common_buffers(struct ngene *dev)
 804 {
 805         u32 i;
 806         struct ngene_channel *chan;
 807
 808         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
 809                 chan = &dev->channel[i];
 810                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
 811                 free_ringbuffer(dev, &chan->RingBuffer);
 812                 free_ringbuffer(dev, &chan->TSRingBuffer);
 813         }
 814
 815         if (dev->OverflowBuffer)
 816                 pci_free_consistent(dev->pci_dev,
 817                                     OVERFLOW_BUFFER_SIZE,
 818                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
 819
 820         if (dev->FWInterfaceBuffer)
 821                 pci_free_consistent(dev->pci_dev,
 822                                     4096,
 823                                     dev->FWInterfaceBuffer,
 824                                     dev->PAFWInterfaceBuffer);
 825 }
 826
 827 /****************************************************************************/
 828 /* Ring buffer handling *****************************************************/
 829 /****************************************************************************/
 830
 831 static int create_ring_buffer(struct pci_dev *pci_dev,
 832                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
 833 {
 834         dma_addr_t tmp;
 835         struct SBufferHeader *Head;
 836         u32 i;
 837         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
 838         u64 PARingBufferHead;
 839         u64 PARingBufferCur;
 840         u64 PARingBufferNext;
 841         struct SBufferHeader *Cur, *Next;
 842
 843         descr->Head = NULL;
 844         descr->MemSize = 0;
 845         descr->PAHead = 0;
 846         descr->NumBuffers = 0;
 847
 848         if (MemSize < 4096)
 849                 MemSize = 4096;
 850
 851         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
 852         PARingBufferHead = tmp;
 853
 854         if (!Head)
 855                 return -ENOMEM;
 856
 857         memset(Head, 0, MemSize);
 858
 859         PARingBufferCur = PARingBufferHead;
 860         Cur = Head;
 861
 862         for (i = 0; i < NumBuffers - 1; i++) {
 863                 Next = (struct SBufferHeader *)
 864                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
 865                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
 866                 Cur->Next = Next;
 867                 Cur->ngeneBuffer.Next = PARingBufferNext;
 868                 Cur = Next;
 869                 PARingBufferCur = PARingBufferNext;
 870         }
 871         /* Last Buffer points back to first one */
 872         Cur->Next = Head;
 873         Cur->ngeneBuffer.Next = PARingBufferHead;
 874
 875         descr->Head       = Head;
 876         descr->MemSize    = MemSize;
 877         descr->PAHead     = PARingBufferHead;
 878         descr->NumBuffers = NumBuffers;
 879
 880         return 0;
 881 }
 882
 883 static int AllocateRingBuffers(struct pci_dev *pci_dev,
 884                                dma_addr_t of,
 885                                struct SRingBufferDescriptor *pRingBuffer,
 886                                u32 Buffer1Length, u32 Buffer2Length)
 887 {
 888         dma_addr_t tmp;
 889         u32 i, j;
 890         u32 SCListMemSize = pRingBuffer->NumBuffers
 891                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
 892                     NUM_SCATTER_GATHER_ENTRIES)
 893                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 894
 895         u64 PASCListMem;
 896         struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
 897         u64 PASCListEntry;
 898         struct SBufferHeader *Cur;
 899         void *SCListMem;
 900
 901         if (SCListMemSize < 4096)
 902                 SCListMemSize = 4096;
 903
 904         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
 905
 906         PASCListMem = tmp;
 907         if (SCListMem == NULL)
 908                 return -ENOMEM;
 909
 910         memset(SCListMem, 0, SCListMemSize);
 911
 912         pRingBuffer->SCListMem = SCListMem;
 913         pRingBuffer->PASCListMem = PASCListMem;
 914         pRingBuffer->SCListMemSize = SCListMemSize;
 915         pRingBuffer->Buffer1Length = Buffer1Length;
 916         pRingBuffer->Buffer2Length = Buffer2Length;
 917
 918         SCListEntry = SCListMem;
 919         PASCListEntry = PASCListMem;
 920         Cur = pRingBuffer->Head;
 921
 922         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
 923                 u64 PABuffer;
 924
 925                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
 926                                                     &tmp);
 927                 PABuffer = tmp;
 928
 929                 if (Buffer == NULL)
 930                         return -ENOMEM;
 931
 932                 Cur->Buffer1 = Buffer;
 933
 934                 SCListEntry->Address = PABuffer;
 935                 SCListEntry->Length  = Buffer1Length;
 936
 937                 Cur->scList1 = SCListEntry;
 938                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
 939                 Cur->ngeneBuffer.Number_of_entries_1 =
 940                         NUM_SCATTER_GATHER_ENTRIES;
 941
 942                 SCListEntry += 1;
 943                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 944
 945 #if NUM_SCATTER_GATHER_ENTRIES > 1
 946                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
 947                         SCListEntry->Address = of;
 948                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
 949                         SCListEntry += 1;
 950                         PASCListEntry +=
 951                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 952                 }
 953 #endif
 954
 955                 if (!Buffer2Length)
 956                         continue;
 957
 958                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
 959                 PABuffer = tmp;
 960
 961                 if (Buffer == NULL)
 962                         return -ENOMEM;
 963
 964                 Cur->Buffer2 = Buffer;
 965
 966                 SCListEntry->Address = PABuffer;
 967                 SCListEntry->Length  = Buffer2Length;
 968
 969                 Cur->scList2 = SCListEntry;
 970                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
 971                 Cur->ngeneBuffer.Number_of_entries_2 =
 972                         NUM_SCATTER_GATHER_ENTRIES;
 973
 974                 SCListEntry   += 1;
 975                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 976
 977 #if NUM_SCATTER_GATHER_ENTRIES > 1
 978                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
 979                         SCListEntry->Address = of;
 980                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
 981                         SCListEntry += 1;
 982                         PASCListEntry +=
 983                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 984                 }
 985 #endif
 986
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
 993                             struct SRingBufferDescriptor *pRingBuffer)
 994 {
 995         /* Copy pointer to scatter gather list in TSRingbuffer
 996            structure for buffer 2
 997            Load number of buffer
 998         */
 999         u32 n = pRingBuffer->NumBuffers;
1000
1001         /* Point to first buffer entry */
1002         struct SBufferHeader *Cur = pRingBuffer->Head;
1003         int i;
1004         /* Loop through all buffer and set Buffer 2 pointers to TSIdlebuffer */
1005         for (i = 0; i < n; i++) {
1006                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1007                 Cur->scList2 = pIdleBuffer->Head->scList1;
1008                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1009                         pIdleBuffer->Head->ngeneBuffer.
1010                         Address_of_first_entry_1;
1011                 Cur->ngeneBuffer.Number_of_entries_2 =
1012                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1013                 Cur = Cur->Next;
1014         }
1015         return 0;
1016 }
1017
1018 static u32 RingBufferSizes[MAX_STREAM] = {
1019         RING_SIZE_VIDEO,
1020         RING_SIZE_VIDEO,
1021         RING_SIZE_AUDIO,
1022         RING_SIZE_AUDIO,
1023         RING_SIZE_AUDIO,
1024 };
1025
1026 static u32 Buffer1Sizes[MAX_STREAM] = {
1027         MAX_VIDEO_BUFFER_SIZE,
1028         MAX_VIDEO_BUFFER_SIZE,
1029         MAX_AUDIO_BUFFER_SIZE,
1030         MAX_AUDIO_BUFFER_SIZE,
1031         MAX_AUDIO_BUFFER_SIZE
1032 };
1033
1034 static u32 Buffer2Sizes[MAX_STREAM] = {
1035         MAX_VBI_BUFFER_SIZE,
1036         MAX_VBI_BUFFER_SIZE,
1037         0,
1038         0,
1039         0
1040 };
1041
1042
1043 static int AllocCommonBuffers(struct ngene *dev)
1044 {
1045         int status = 0, i;
1046
1047         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1048                                                      &dev->PAFWInterfaceBuffer);
1049         if (!dev->FWInterfaceBuffer)
1050                 return -ENOMEM;
1051         dev->hosttongene = dev->FWInterfaceBuffer;
1052         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1053         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1054
1055         dev->OverflowBuffer = pci_zalloc_consistent(dev->pci_dev,
1056                                                     OVERFLOW_BUFFER_SIZE,
1057                                                     &dev->PAOverflowBuffer);
1058         if (!dev->OverflowBuffer)
1059                 return -ENOMEM;
1060
1061         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1062                 int type = dev->card_info->io_type[i];
1063
1064                 dev->channel[i].State = KSSTATE_STOP;
1065
1066                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1067                         status = create_ring_buffer(dev->pci_dev,
1068                                                     &dev->channel[i].RingBuffer,
1069                                                     RingBufferSizes[i]);
1070                         if (status < 0)
1071                                 break;
1072
1073                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1074                                 status = AllocateRingBuffers(dev->pci_dev,
1075                                                              dev->
1076                                                              PAOverflowBuffer,
1077                                                              &dev->channel[i].
1078                                                              RingBuffer,
1079                                                              Buffer1Sizes[i],
1080                                                              Buffer2Sizes[i]);
1081                                 if (status < 0)
1082                                         break;
1083                         } else if (type & NGENE_IO_HDTV) {
1084                                 status = AllocateRingBuffers(dev->pci_dev,
1085                                                              dev->
1086                                                              PAOverflowBuffer,
1087                                                              &dev->channel[i].
1088                                                              RingBuffer,
1089                                                            MAX_HDTV_BUFFER_SIZE,
1090                                                              0);
1091                                 if (status < 0)
1092                                         break;
1093                         }
1094                 }
1095
1096                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1097
1098                         status = create_ring_buffer(dev->pci_dev,
1099                                                     &dev->channel[i].
1100                                                     TSRingBuffer, RING_SIZE_TS);
1101                         if (status < 0)
1102                                 break;
1103
1104                         status = AllocateRingBuffers(dev->pci_dev,
1105                                                      dev->PAOverflowBuffer,
1106                                                      &dev->channel[i].
1107                                                      TSRingBuffer,
1108                                                      MAX_TS_BUFFER_SIZE, 0);
1109                         if (status)
1110                                 break;
1111                 }
1112
1113                 if (type & NGENE_IO_TSOUT) {
1114                         status = create_ring_buffer(dev->pci_dev,
1115                                                     &dev->channel[i].
1116                                                     TSIdleBuffer, 1);
1117                         if (status < 0)
1118                                 break;
1119                         status = AllocateRingBuffers(dev->pci_dev,
1120                                                      dev->PAOverflowBuffer,
1121                                                      &dev->channel[i].
1122                                                      TSIdleBuffer,
1123                                                      MAX_TS_BUFFER_SIZE, 0);
1124                         if (status)
1125                                 break;
1126                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1127                                          &dev->channel[i].TSRingBuffer);
1128                 }
1129         }
1130         return status;
1131 }
1132
1133 static void ngene_release_buffers(struct ngene *dev)
1134 {
1135         if (dev->iomem)
1136                 iounmap(dev->iomem);
1137         free_common_buffers(dev);
1138         vfree(dev->tsout_buf);
1139         vfree(dev->tsin_buf);
1140         vfree(dev->ain_buf);
1141         vfree(dev->vin_buf);
1142         vfree(dev);
1143 }
1144
1145 static int ngene_get_buffers(struct ngene *dev)
1146 {
1147         if (AllocCommonBuffers(dev))
1148                 return -ENOMEM;
1149         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1150                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1151                 if (!dev->tsout_buf)
1152                         return -ENOMEM;
1153                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1154                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1155         }
1156         if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1157                 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1158                 if (!dev->tsin_buf)
1159                         return -ENOMEM;
1160                 dvb_ringbuffer_init(&dev->tsin_rbuf,
1161                                     dev->tsin_buf, TSIN_BUF_SIZE);
1162         }
1163         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1164                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1165                 if (!dev->ain_buf)
1166                         return -ENOMEM;
1167                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1168         }
1169         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1170                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1171                 if (!dev->vin_buf)
1172                         return -ENOMEM;
1173                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1174         }
1175         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1176                              pci_resource_len(dev->pci_dev, 0));
1177         if (!dev->iomem)
1178                 return -ENOMEM;
1179
1180         return 0;
1181 }
1182
1183 static void ngene_init(struct ngene *dev)
1184 {
1185         struct device *pdev = &dev->pci_dev->dev;
1186         int i;
1187
1188         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1189
1190         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1191         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1192
1193         for (i = 0; i < MAX_STREAM; i++) {
1194                 dev->channel[i].dev = dev;
1195                 dev->channel[i].number = i;
1196         }
1197
1198         dev->fw_interface_version = 0;
1199
1200         ngwritel(0, NGENE_INT_ENABLE);
1201
1202         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1203
1204         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1205         dev_info(pdev, "Device version %d\n", dev->device_version);
1206 }
1207
1208 static int ngene_load_firm(struct ngene *dev)
1209 {
1210         struct device *pdev = &dev->pci_dev->dev;
1211         u32 size;
1212         const struct firmware *fw = NULL;
1213         u8 *ngene_fw;
1214         char *fw_name;
1215         int err, version;
1216
1217         version = dev->card_info->fw_version;
1218
1219         switch (version) {
1220         default:
1221         case 15:
1222                 version = 15;
1223                 size = 23466;
1224                 fw_name = "ngene_15.fw";
1225                 dev->cmd_timeout_workaround = true;
1226                 break;
1227         case 16:
1228                 size = 23498;
1229                 fw_name = "ngene_16.fw";
1230                 dev->cmd_timeout_workaround = true;
1231                 break;
1232         case 17:
1233                 size = 24446;
1234                 fw_name = "ngene_17.fw";
1235                 dev->cmd_timeout_workaround = true;
1236                 break;
1237         case 18:
1238                 size = 0;
1239                 fw_name = "ngene_18.fw";
1240                 break;
1241         }
1242
1243         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1244                 dev_err(pdev, "Could not load firmware file %s.\n", fw_name);
1245                 dev_info(pdev, "Copy %s to your hotplug directory!\n",
1246                          fw_name);
1247                 return -1;
1248         }
1249         if (size == 0)
1250                 size = fw->size;
1251         if (size != fw->size) {
1252                 dev_err(pdev, "Firmware %s has invalid size!", fw_name);
1253                 err = -1;
1254         } else {
1255                 dev_info(pdev, "Loading firmware file %s.\n", fw_name);
1256                 ngene_fw = (u8 *) fw->data;
1257                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1258         }
1259
1260         release_firmware(fw);
1261
1262         return err;
1263 }
1264
1265 static void ngene_stop(struct ngene *dev)
1266 {
1267         mutex_destroy(&dev->cmd_mutex);
1268         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1269         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1270         ngwritel(0, NGENE_INT_ENABLE);
1271         ngwritel(0, NGENE_COMMAND);
1272         ngwritel(0, NGENE_COMMAND_HI);
1273         ngwritel(0, NGENE_STATUS);
1274         ngwritel(0, NGENE_STATUS_HI);
1275         ngwritel(0, NGENE_EVENT);
1276         ngwritel(0, NGENE_EVENT_HI);
1277         free_irq(dev->pci_dev->irq, dev);
1278 #ifdef CONFIG_PCI_MSI
1279         if (dev->msi_enabled)
1280                 pci_disable_msi(dev->pci_dev);
1281 #endif
1282 }
1283
1284 static int ngene_buffer_config(struct ngene *dev)
1285 {
1286         int stat;
1287
1288         if (dev->card_info->fw_version >= 17) {
1289                 u8 tsin12_config[6]   = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1290                 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1291                 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1292                 u8 *bconf = tsin12_config;
1293
1294                 if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1295                     dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1296                         bconf = tsin1234_config;
1297                         if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1298                             dev->ci.en)
1299                                 bconf = tsio1235_config;
1300                 }
1301                 stat = ngene_command_config_free_buf(dev, bconf);
1302         } else {
1303                 int bconf = BUFFER_CONFIG_4422;
1304
1305                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1306                         bconf = BUFFER_CONFIG_3333;
1307                 stat = ngene_command_config_buf(dev, bconf);
1308         }
1309         return stat;
1310 }
1311
1312
1313 static int ngene_start(struct ngene *dev)
1314 {
1315         int stat;
1316         int i;
1317
1318         pci_set_master(dev->pci_dev);
1319         ngene_init(dev);
1320
1321         stat = request_irq(dev->pci_dev->irq, irq_handler,
1322                            IRQF_SHARED, "nGene",
1323                            (void *)dev);
1324         if (stat < 0)
1325                 return stat;
1326
1327         init_waitqueue_head(&dev->cmd_wq);
1328         init_waitqueue_head(&dev->tx_wq);
1329         init_waitqueue_head(&dev->rx_wq);
1330         mutex_init(&dev->cmd_mutex);
1331         mutex_init(&dev->stream_mutex);
1332         sema_init(&dev->pll_mutex, 1);
1333         mutex_init(&dev->i2c_switch_mutex);
1334         spin_lock_init(&dev->cmd_lock);
1335         for (i = 0; i < MAX_STREAM; i++)
1336                 spin_lock_init(&dev->channel[i].state_lock);
1337         ngwritel(1, TIMESTAMPS);
1338
1339         ngwritel(1, NGENE_INT_ENABLE);
1340
1341         stat = ngene_load_firm(dev);
1342         if (stat < 0)
1343                 goto fail;
1344
1345 #ifdef CONFIG_PCI_MSI
1346         /* enable MSI if kernel and card support it */
1347         if (pci_msi_enabled() && dev->card_info->msi_supported) {
1348                 struct device *pdev = &dev->pci_dev->dev;
1349                 unsigned long flags;
1350
1351                 ngwritel(0, NGENE_INT_ENABLE);
1352                 free_irq(dev->pci_dev->irq, dev);
1353                 stat = pci_enable_msi(dev->pci_dev);
1354                 if (stat) {
1355                         dev_info(pdev, "MSI not available\n");
1356                         flags = IRQF_SHARED;
1357                 } else {
1358                         flags = 0;
1359                         dev->msi_enabled = true;
1360                 }
1361                 stat = request_irq(dev->pci_dev->irq, irq_handler,
1362                                         flags, "nGene", dev);
1363                 if (stat < 0)
1364                         goto fail2;
1365                 ngwritel(1, NGENE_INT_ENABLE);
1366         }
1367 #endif
1368
1369         stat = ngene_i2c_init(dev, 0);
1370         if (stat < 0)
1371                 goto fail;
1372
1373         stat = ngene_i2c_init(dev, 1);
1374         if (stat < 0)
1375                 goto fail;
1376
1377         return 0;
1378
1379 fail:
1380         ngwritel(0, NGENE_INT_ENABLE);
1381         free_irq(dev->pci_dev->irq, dev);
1382 #ifdef CONFIG_PCI_MSI
1383 fail2:
1384         if (dev->msi_enabled)
1385                 pci_disable_msi(dev->pci_dev);
1386 #endif
1387         return stat;
1388 }
1389
1390 /****************************************************************************/
1391 /****************************************************************************/
1392 /****************************************************************************/
1393
1394 static void release_channel(struct ngene_channel *chan)
1395 {
1396         struct dvb_demux *dvbdemux = &chan->demux;
1397         struct ngene *dev = chan->dev;
1398
1399         if (chan->running)
1400                 set_transfer(chan, 0);
1401
1402         tasklet_kill(&chan->demux_tasklet);
1403
1404         if (chan->ci_dev) {
1405                 dvb_unregister_device(chan->ci_dev);
1406                 chan->ci_dev = NULL;
1407         }
1408
1409         if (chan->fe2)
1410                 dvb_unregister_frontend(chan->fe2);
1411
1412         if (chan->fe) {
1413                 dvb_unregister_frontend(chan->fe);
1414
1415                 /* release I2C client (tuner) if needed */
1416                 if (chan->i2c_client_fe) {
1417                         dvb_module_release(chan->i2c_client[0]);
1418                         chan->i2c_client[0] = NULL;
1419                 }
1420
1421                 dvb_frontend_detach(chan->fe);
1422                 chan->fe = NULL;
1423         }
1424
1425         if (chan->has_demux) {
1426                 dvb_net_release(&chan->dvbnet);
1427                 dvbdemux->dmx.close(&dvbdemux->dmx);
1428                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1429                                               &chan->hw_frontend);
1430                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1431                                               &chan->mem_frontend);
1432                 dvb_dmxdev_release(&chan->dmxdev);
1433                 dvb_dmx_release(&chan->demux);
1434                 chan->has_demux = false;
1435         }
1436
1437         if (chan->has_adapter) {
1438                 dvb_unregister_adapter(&dev->adapter[chan->number]);
1439                 chan->has_adapter = false;
1440         }
1441 }
1442
1443 static int init_channel(struct ngene_channel *chan)
1444 {
1445         int ret = 0, nr = chan->number;
1446         struct dvb_adapter *adapter = NULL;
1447         struct dvb_demux *dvbdemux = &chan->demux;
1448         struct ngene *dev = chan->dev;
1449         struct ngene_info *ni = dev->card_info;
1450         int io = ni->io_type[nr];
1451
1452         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1453         chan->users = 0;
1454         chan->type = io;
1455         chan->mode = chan->type;        /* for now only one mode */
1456         chan->i2c_client_fe = 0;        /* be sure this is set to zero */
1457
1458         if (io & NGENE_IO_TSIN) {
1459                 chan->fe = NULL;
1460                 if (ni->demod_attach[nr]) {
1461                         ret = ni->demod_attach[nr](chan);
1462                         if (ret < 0)
1463                                 goto err;
1464                 }
1465                 if (chan->fe && ni->tuner_attach[nr]) {
1466                         ret = ni->tuner_attach[nr](chan);
1467                         if (ret < 0)
1468                                 goto err;
1469                 }
1470         }
1471
1472         if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1473                 return 0;
1474
1475         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1476                 if (nr >= STREAM_AUDIOIN1)
1477                         chan->DataFormatFlags = DF_SWAP32;
1478
1479                 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1480                         adapter = &dev->adapter[nr];
1481                         ret = dvb_register_adapter(adapter, "nGene",
1482                                                    THIS_MODULE,
1483                                                    &chan->dev->pci_dev->dev,
1484                                                    adapter_nr);
1485                         if (ret < 0)
1486                                 goto err;
1487                         if (dev->first_adapter == NULL)
1488                                 dev->first_adapter = adapter;
1489                         chan->has_adapter = true;
1490                 } else
1491                         adapter = dev->first_adapter;
1492         }
1493
1494         if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1495                 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1496                 set_transfer(chan, 1);
1497                 chan->dev->channel[2].DataFormatFlags = DF_SWAP32;
1498                 set_transfer(&chan->dev->channel[2], 1);
1499                 dvb_register_device(adapter, &chan->ci_dev,
1500                                     &ngene_dvbdev_ci, (void *) chan,
1501                                     DVB_DEVICE_SEC, 0);
1502                 if (!chan->ci_dev)
1503                         goto err;
1504         }
1505
1506         if (chan->fe) {
1507                 if (dvb_register_frontend(adapter, chan->fe) < 0)
1508                         goto err;
1509                 chan->has_demux = true;
1510         }
1511         if (chan->fe2) {
1512                 if (dvb_register_frontend(adapter, chan->fe2) < 0)
1513                         goto err;
1514                 if (chan->fe) {
1515                         chan->fe2->tuner_priv = chan->fe->tuner_priv;
1516                         memcpy(&chan->fe2->ops.tuner_ops,
1517                                &chan->fe->ops.tuner_ops,
1518                                sizeof(struct dvb_tuner_ops));
1519                 }
1520         }
1521
1522         if (chan->has_demux) {
1523                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1524                                               ngene_start_feed,
1525                                               ngene_stop_feed, chan);
1526                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1527                                                  &chan->hw_frontend,
1528                                                  &chan->mem_frontend, adapter);
1529                 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
1530         }
1531
1532         return ret;
1533
1534 err:
1535         if (chan->fe) {
1536                 dvb_frontend_detach(chan->fe);
1537                 chan->fe = NULL;
1538         }
1539         release_channel(chan);
1540         return 0;
1541 }
1542
1543 static int init_channels(struct ngene *dev)
1544 {
1545         int i, j;
1546
1547         for (i = 0; i < MAX_STREAM; i++) {
1548                 dev->channel[i].number = i;
1549                 if (init_channel(&dev->channel[i]) < 0) {
1550                         for (j = i - 1; j >= 0; j--)
1551                                 release_channel(&dev->channel[j]);
1552                         return -1;
1553                 }
1554         }
1555         return 0;
1556 }
1557
1558 static const struct cxd2099_cfg cxd_cfgtmpl = {
1559         .bitrate = 62000,
1560         .polarity = 0,
1561         .clock_mode = 0,
1562 };
1563
1564 static void cxd_attach(struct ngene *dev)
1565 {
1566         struct device *pdev = &dev->pci_dev->dev;
1567         struct ngene_ci *ci = &dev->ci;
1568         struct cxd2099_cfg cxd_cfg = cxd_cfgtmpl;
1569         struct i2c_client *client;
1570         int ret;
1571         u8 type;
1572
1573         /* check for CXD2099AR presence before attaching */
1574         ret = ngene_port_has_cxd2099(&dev->channel[0].i2c_adapter, &type);
1575         if (!ret) {
1576                 dev_dbg(pdev, "No CXD2099AR found\n");
1577                 return;
1578         }
1579
1580         if (type != 1) {
1581                 dev_warn(pdev, "CXD2099AR is uninitialized!\n");
1582                 return;
1583         }
1584
1585         cxd_cfg.en = &ci->en;
1586         client = dvb_module_probe("cxd2099", NULL,
1587                                   &dev->channel[0].i2c_adapter,
1588                                   0x40, &cxd_cfg);
1589         if (!client)
1590                 goto err;
1591
1592         ci->dev = dev;
1593         dev->channel[0].i2c_client[0] = client;
1594         return;
1595
1596 err:
1597         dev_err(pdev, "CXD2099AR attach failed\n");
1598         return;
1599 }
1600
1601 static void cxd_detach(struct ngene *dev)
1602 {
1603         struct ngene_ci *ci = &dev->ci;
1604
1605         dvb_ca_en50221_release(ci->en);
1606
1607         dvb_module_release(dev->channel[0].i2c_client[0]);
1608         dev->channel[0].i2c_client[0] = NULL;
1609         ci->en = NULL;
1610 }
1611
1612 /***********************************/
1613 /* workaround for shutdown failure */
1614 /***********************************/
1615
1616 static void ngene_unlink(struct ngene *dev)
1617 {
1618         struct ngene_command com;
1619
1620         com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1621         com.cmd.hdr.Length = 3;
1622         com.cmd.MemoryWrite.address = 0x910c;
1623         com.cmd.MemoryWrite.data = 0xff;
1624         com.in_len = 3;
1625         com.out_len = 1;
1626
1627         mutex_lock(&dev->cmd_mutex);
1628         ngwritel(0, NGENE_INT_ENABLE);
1629         ngene_command_mutex(dev, &com);
1630         mutex_unlock(&dev->cmd_mutex);
1631 }
1632
1633 void ngene_shutdown(struct pci_dev *pdev)
1634 {
1635         struct ngene *dev = pci_get_drvdata(pdev);
1636
1637         if (!dev || !shutdown_workaround)
1638                 return;
1639
1640         dev_info(&pdev->dev, "shutdown workaround...\n");
1641         ngene_unlink(dev);
1642         pci_disable_device(pdev);
1643 }
1644
1645 /****************************************************************************/
1646 /* device probe/remove calls ************************************************/
1647 /****************************************************************************/
1648
1649 void ngene_remove(struct pci_dev *pdev)
1650 {
1651         struct ngene *dev = pci_get_drvdata(pdev);
1652         int i;
1653
1654         tasklet_kill(&dev->event_tasklet);
1655         for (i = MAX_STREAM - 1; i >= 0; i--)
1656                 release_channel(&dev->channel[i]);
1657         if (dev->ci.en)
1658                 cxd_detach(dev);
1659         ngene_stop(dev);
1660         ngene_release_buffers(dev);
1661         pci_disable_device(pdev);
1662 }
1663
1664 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1665 {
1666         struct ngene *dev;
1667         int stat = 0;
1668
1669         if (pci_enable_device(pci_dev) < 0)
1670                 return -ENODEV;
1671
1672         dev = vzalloc(sizeof(struct ngene));
1673         if (dev == NULL) {
1674                 stat = -ENOMEM;
1675                 goto fail0;
1676         }
1677
1678         dev->pci_dev = pci_dev;
1679         dev->card_info = (struct ngene_info *)id->driver_data;
1680         dev_info(&pci_dev->dev, "Found %s\n", dev->card_info->name);
1681
1682         pci_set_drvdata(pci_dev, dev);
1683
1684         /* Alloc buffers and start nGene */
1685         stat = ngene_get_buffers(dev);
1686         if (stat < 0)
1687                 goto fail1;
1688         stat = ngene_start(dev);
1689         if (stat < 0)
1690                 goto fail1;
1691
1692         cxd_attach(dev);
1693
1694         stat = ngene_buffer_config(dev);
1695         if (stat < 0)
1696                 goto fail1;
1697
1698
1699         dev->i2c_current_bus = -1;
1700
1701         /* Register DVB adapters and devices for both channels */
1702         stat = init_channels(dev);
1703         if (stat < 0)
1704                 goto fail2;
1705
1706         return 0;
1707
1708 fail2:
1709         ngene_stop(dev);
1710 fail1:
1711         ngene_release_buffers(dev);
1712 fail0:
1713         pci_disable_device(pci_dev);
1714         return stat;
1715 }