treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
[sfrench/cifs-2.6.git] / drivers / media / pci / dt3155 / dt3155.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /***************************************************************************
3  *   Copyright (C) 2006-2010 by Marin Mitov                                *
4  *   mitov@issp.bas.bg                                                     *
5  *                                                                         *
6  *                                                                         *
7  ***************************************************************************/
8
9 #include <linux/module.h>
10 #include <linux/stringify.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/slab.h>
14 #include <media/v4l2-dev.h>
15 #include <media/v4l2-ioctl.h>
16 #include <media/v4l2-common.h>
17 #include <media/videobuf2-dma-contig.h>
18
19 #include "dt3155.h"
20
21 #define DT3155_DEVICE_ID 0x1223
22
23 /**
24  * read_i2c_reg - reads an internal i2c register
25  *
26  * @addr:       dt3155 mmio base address
27  * @index:      index (internal address) of register to read
28  * @data:       pointer to byte the read data will be placed in
29  *
30  * returns:     zero on success or error code
31  *
32  * This function starts reading the specified (by index) register
33  * and busy waits for the process to finish. The result is placed
34  * in a byte pointed by data.
35  */
36 static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
37 {
38         u32 tmp = index;
39
40         iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
41         udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
42         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
43                 return -EIO; /* error: NEW_CYCLE not cleared */
44         tmp = ioread32(addr + IIC_CSR1);
45         if (tmp & DIRECT_ABORT) {
46                 /* reset DIRECT_ABORT bit */
47                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
48                 return -EIO; /* error: DIRECT_ABORT set */
49         }
50         *data = tmp >> 24;
51         return 0;
52 }
53
54 /**
55  * write_i2c_reg - writes to an internal i2c register
56  *
57  * @addr:       dt3155 mmio base address
58  * @index:      index (internal address) of register to read
59  * @data:       data to be written
60  *
61  * returns:     zero on success or error code
62  *
63  * This function starts writing the specified (by index) register
64  * and busy waits for the process to finish.
65  */
66 static int write_i2c_reg(void __iomem *addr, u8 index, u8 data)
67 {
68         u32 tmp = index;
69
70         iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
71         udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
72         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
73                 return -EIO; /* error: NEW_CYCLE not cleared */
74         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
75                 /* reset DIRECT_ABORT bit */
76                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
77                 return -EIO; /* error: DIRECT_ABORT set */
78         }
79         return 0;
80 }
81
82 /**
83  * write_i2c_reg_nowait - writes to an internal i2c register
84  *
85  * @addr:       dt3155 mmio base address
86  * @index:      index (internal address) of register to read
87  * @data:       data to be written
88  *
89  * This function starts writing the specified (by index) register
90  * and then returns.
91  */
92 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
93 {
94         u32 tmp = index;
95
96         iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
97 }
98
99 /**
100  * wait_i2c_reg - waits the read/write to finish
101  *
102  * @addr:       dt3155 mmio base address
103  *
104  * returns:     zero on success or error code
105  *
106  * This function waits reading/writing to finish.
107  */
108 static int wait_i2c_reg(void __iomem *addr)
109 {
110         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
111                 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
112         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
113                 return -EIO; /* error: NEW_CYCLE not cleared */
114         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
115                 /* reset DIRECT_ABORT bit */
116                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
117                 return -EIO; /* error: DIRECT_ABORT set */
118         }
119         return 0;
120 }
121
122 static int
123 dt3155_queue_setup(struct vb2_queue *vq,
124                 unsigned int *nbuffers, unsigned int *num_planes,
125                 unsigned int sizes[], struct device *alloc_devs[])
126
127 {
128         struct dt3155_priv *pd = vb2_get_drv_priv(vq);
129         unsigned size = pd->width * pd->height;
130
131         if (vq->num_buffers + *nbuffers < 2)
132                 *nbuffers = 2 - vq->num_buffers;
133         if (*num_planes)
134                 return sizes[0] < size ? -EINVAL : 0;
135         *num_planes = 1;
136         sizes[0] = size;
137         return 0;
138 }
139
140 static int dt3155_buf_prepare(struct vb2_buffer *vb)
141 {
142         struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
143
144         vb2_set_plane_payload(vb, 0, pd->width * pd->height);
145         return 0;
146 }
147
148 static int dt3155_start_streaming(struct vb2_queue *q, unsigned count)
149 {
150         struct dt3155_priv *pd = vb2_get_drv_priv(q);
151         struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
152         dma_addr_t dma_addr;
153
154         pd->sequence = 0;
155         dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
156         iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
157         iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
158         iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
159         iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
160         /* enable interrupts, clear all irq flags */
161         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
162                         FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
163         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
164                   FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
165                                                         pd->regs + CSR1);
166         wait_i2c_reg(pd->regs);
167         write_i2c_reg(pd->regs, CONFIG, pd->config);
168         write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
169         write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
170
171         /*  start the board  */
172         write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
173         return 0;
174 }
175
176 static void dt3155_stop_streaming(struct vb2_queue *q)
177 {
178         struct dt3155_priv *pd = vb2_get_drv_priv(q);
179         struct vb2_buffer *vb;
180
181         spin_lock_irq(&pd->lock);
182         /* stop the board */
183         write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
184         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
185                   FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
186         /* disable interrupts, clear all irq flags */
187         iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
188         spin_unlock_irq(&pd->lock);
189
190         /*
191          * It is not clear whether the DMA stops at once or whether it
192          * will finish the current frame or field first. To be on the
193          * safe side we wait a bit.
194          */
195         msleep(45);
196
197         spin_lock_irq(&pd->lock);
198         if (pd->curr_buf) {
199                 vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
200                 pd->curr_buf = NULL;
201         }
202
203         while (!list_empty(&pd->dmaq)) {
204                 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
205                 list_del(&vb->done_entry);
206                 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
207         }
208         spin_unlock_irq(&pd->lock);
209 }
210
211 static void dt3155_buf_queue(struct vb2_buffer *vb)
212 {
213         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
214         struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
215
216         /*  pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked  */
217         spin_lock_irq(&pd->lock);
218         if (pd->curr_buf)
219                 list_add_tail(&vb->done_entry, &pd->dmaq);
220         else
221                 pd->curr_buf = vbuf;
222         spin_unlock_irq(&pd->lock);
223 }
224
225 static const struct vb2_ops q_ops = {
226         .queue_setup = dt3155_queue_setup,
227         .wait_prepare = vb2_ops_wait_prepare,
228         .wait_finish = vb2_ops_wait_finish,
229         .buf_prepare = dt3155_buf_prepare,
230         .start_streaming = dt3155_start_streaming,
231         .stop_streaming = dt3155_stop_streaming,
232         .buf_queue = dt3155_buf_queue,
233 };
234
235 static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id)
236 {
237         struct dt3155_priv *ipd = dev_id;
238         struct vb2_buffer *ivb;
239         dma_addr_t dma_addr;
240         u32 tmp;
241
242         tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
243         if (!tmp)
244                 return IRQ_NONE;  /* not our irq */
245         if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
246                 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
247                                                         ipd->regs + INT_CSR);
248                 return IRQ_HANDLED; /* start of field irq */
249         }
250         tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
251         if (tmp) {
252                 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
253                                                 FLD_DN_ODD | FLD_DN_EVEN |
254                                                 CAP_CONT_EVEN | CAP_CONT_ODD,
255                                                         ipd->regs + CSR1);
256         }
257
258         spin_lock(&ipd->lock);
259         if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {
260                 ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns();
261                 ipd->curr_buf->sequence = ipd->sequence++;
262                 ipd->curr_buf->field = V4L2_FIELD_NONE;
263                 vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE);
264
265                 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
266                 list_del(&ivb->done_entry);
267                 ipd->curr_buf = to_vb2_v4l2_buffer(ivb);
268                 dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
269                 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
270                 iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
271                 iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
272                 iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
273         }
274
275         /* enable interrupts, clear all irq flags */
276         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
277                         FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
278         spin_unlock(&ipd->lock);
279         return IRQ_HANDLED;
280 }
281
282 static const struct v4l2_file_operations dt3155_fops = {
283         .owner = THIS_MODULE,
284         .open = v4l2_fh_open,
285         .release = vb2_fop_release,
286         .unlocked_ioctl = video_ioctl2,
287         .read = vb2_fop_read,
288         .mmap = vb2_fop_mmap,
289         .poll = vb2_fop_poll
290 };
291
292 static int dt3155_querycap(struct file *filp, void *p,
293                            struct v4l2_capability *cap)
294 {
295         struct dt3155_priv *pd = video_drvdata(filp);
296
297         strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver));
298         strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card));
299         sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
300         cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
301                 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
302         cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
303         return 0;
304 }
305
306 static int dt3155_enum_fmt_vid_cap(struct file *filp,
307                                    void *p, struct v4l2_fmtdesc *f)
308 {
309         if (f->index)
310                 return -EINVAL;
311         f->pixelformat = V4L2_PIX_FMT_GREY;
312         strscpy(f->description, "8-bit Greyscale", sizeof(f->description));
313         return 0;
314 }
315
316 static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
317 {
318         struct dt3155_priv *pd = video_drvdata(filp);
319
320         f->fmt.pix.width = pd->width;
321         f->fmt.pix.height = pd->height;
322         f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
323         f->fmt.pix.field = V4L2_FIELD_NONE;
324         f->fmt.pix.bytesperline = f->fmt.pix.width;
325         f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
326         f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
327         return 0;
328 }
329
330 static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm)
331 {
332         struct dt3155_priv *pd = video_drvdata(filp);
333
334         *norm = pd->std;
335         return 0;
336 }
337
338 static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm)
339 {
340         struct dt3155_priv *pd = video_drvdata(filp);
341
342         if (pd->std == norm)
343                 return 0;
344         if (vb2_is_busy(&pd->vidq))
345                 return -EBUSY;
346         pd->std = norm;
347         if (pd->std & V4L2_STD_525_60) {
348                 pd->csr2 = VT_60HZ;
349                 pd->width = 640;
350                 pd->height = 480;
351         } else {
352                 pd->csr2 = VT_50HZ;
353                 pd->width = 768;
354                 pd->height = 576;
355         }
356         return 0;
357 }
358
359 static int dt3155_enum_input(struct file *filp, void *p,
360                              struct v4l2_input *input)
361 {
362         if (input->index > 3)
363                 return -EINVAL;
364         if (input->index)
365                 snprintf(input->name, sizeof(input->name), "VID%d",
366                          input->index);
367         else
368                 strscpy(input->name, "J2/VID0", sizeof(input->name));
369         input->type = V4L2_INPUT_TYPE_CAMERA;
370         input->std = V4L2_STD_ALL;
371         input->status = 0;
372         return 0;
373 }
374
375 static int dt3155_g_input(struct file *filp, void *p, unsigned int *i)
376 {
377         struct dt3155_priv *pd = video_drvdata(filp);
378
379         *i = pd->input;
380         return 0;
381 }
382
383 static int dt3155_s_input(struct file *filp, void *p, unsigned int i)
384 {
385         struct dt3155_priv *pd = video_drvdata(filp);
386
387         if (i > 3)
388                 return -EINVAL;
389         pd->input = i;
390         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
391         write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
392         return 0;
393 }
394
395 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
396         .vidioc_querycap = dt3155_querycap,
397         .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap,
398         .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap,
399         .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap,
400         .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap,
401         .vidioc_reqbufs = vb2_ioctl_reqbufs,
402         .vidioc_create_bufs = vb2_ioctl_create_bufs,
403         .vidioc_querybuf = vb2_ioctl_querybuf,
404         .vidioc_expbuf = vb2_ioctl_expbuf,
405         .vidioc_qbuf = vb2_ioctl_qbuf,
406         .vidioc_dqbuf = vb2_ioctl_dqbuf,
407         .vidioc_streamon = vb2_ioctl_streamon,
408         .vidioc_streamoff = vb2_ioctl_streamoff,
409         .vidioc_g_std = dt3155_g_std,
410         .vidioc_s_std = dt3155_s_std,
411         .vidioc_enum_input = dt3155_enum_input,
412         .vidioc_g_input = dt3155_g_input,
413         .vidioc_s_input = dt3155_s_input,
414 };
415
416 static int dt3155_init_board(struct dt3155_priv *pd)
417 {
418         struct pci_dev *pdev = pd->pdev;
419         int i;
420         u8 tmp = 0;
421
422         pci_set_master(pdev); /* dt3155 needs it */
423
424         /*  resetting the adapter  */
425         iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
426                         FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
427         msleep(20);
428
429         /*  initializing adapter registers  */
430         iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
431         iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
432         iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
433         iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
434         iowrite32(0x00000103, pd->regs + XFER_MODE);
435         iowrite32(0, pd->regs + RETRY_WAIT_CNT);
436         iowrite32(0, pd->regs + INT_CSR);
437         iowrite32(1, pd->regs + EVEN_FLD_MASK);
438         iowrite32(1, pd->regs + ODD_FLD_MASK);
439         iowrite32(0, pd->regs + MASK_LENGTH);
440         iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
441         iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
442
443         /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
444         read_i2c_reg(pd->regs, DT_ID, &tmp);
445         if (tmp != DT3155_ID)
446                 return -ENODEV;
447
448         /* initialize AD LUT */
449         write_i2c_reg(pd->regs, AD_ADDR, 0);
450         for (i = 0; i < 256; i++)
451                 write_i2c_reg(pd->regs, AD_LUT, i);
452
453         /* initialize ADC references */
454         /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
455         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
456         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
457         write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
458         write_i2c_reg(pd->regs, AD_CMD, 34);
459         write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
460         write_i2c_reg(pd->regs, AD_CMD, 0);
461
462         /* initialize PM LUT */
463         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
464         for (i = 0; i < 256; i++) {
465                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
466                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
467         }
468         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
469         for (i = 0; i < 256; i++) {
470                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
471                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
472         }
473         write_i2c_reg(pd->regs, CONFIG, pd->config); /*  ACQ_MODE_EVEN  */
474
475         /* select channel 1 for input and set sync level */
476         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
477         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
478
479         /* disable all irqs, clear all irq flags */
480         iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
481                         pd->regs + INT_CSR);
482
483         return 0;
484 }
485
486 static const struct video_device dt3155_vdev = {
487         .name = DT3155_NAME,
488         .fops = &dt3155_fops,
489         .ioctl_ops = &dt3155_ioctl_ops,
490         .minor = -1,
491         .release = video_device_release_empty,
492         .tvnorms = V4L2_STD_ALL,
493 };
494
495 static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
496 {
497         int err;
498         struct dt3155_priv *pd;
499
500         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
501         if (err)
502                 return -ENODEV;
503         pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
504         if (!pd)
505                 return -ENOMEM;
506
507         err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
508         if (err)
509                 return err;
510         pd->vdev = dt3155_vdev;
511         pd->vdev.v4l2_dev = &pd->v4l2_dev;
512         video_set_drvdata(&pd->vdev, pd);  /* for use in video_fops */
513         pd->pdev = pdev;
514         pd->std = V4L2_STD_625_50;
515         pd->csr2 = VT_50HZ;
516         pd->width = 768;
517         pd->height = 576;
518         INIT_LIST_HEAD(&pd->dmaq);
519         mutex_init(&pd->mux);
520         pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
521         pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
522         pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
523         pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
524         pd->vidq.ops = &q_ops;
525         pd->vidq.mem_ops = &vb2_dma_contig_memops;
526         pd->vidq.drv_priv = pd;
527         pd->vidq.min_buffers_needed = 2;
528         pd->vidq.gfp_flags = GFP_DMA32;
529         pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
530         pd->vidq.dev = &pdev->dev;
531         pd->vdev.queue = &pd->vidq;
532         err = vb2_queue_init(&pd->vidq);
533         if (err < 0)
534                 goto err_v4l2_dev_unreg;
535         spin_lock_init(&pd->lock);
536         pd->config = ACQ_MODE_EVEN;
537         err = pci_enable_device(pdev);
538         if (err)
539                 goto err_v4l2_dev_unreg;
540         err = pci_request_region(pdev, 0, pci_name(pdev));
541         if (err)
542                 goto err_pci_disable;
543         pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
544         if (!pd->regs) {
545                 err = -ENOMEM;
546                 goto err_free_reg;
547         }
548         err = dt3155_init_board(pd);
549         if (err)
550                 goto err_iounmap;
551         err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
552                                         IRQF_SHARED, DT3155_NAME, pd);
553         if (err)
554                 goto err_iounmap;
555         err = video_register_device(&pd->vdev, VFL_TYPE_GRABBER, -1);
556         if (err)
557                 goto err_free_irq;
558         dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
559         return 0;  /*   success   */
560
561 err_free_irq:
562         free_irq(pd->pdev->irq, pd);
563 err_iounmap:
564         pci_iounmap(pdev, pd->regs);
565 err_free_reg:
566         pci_release_region(pdev, 0);
567 err_pci_disable:
568         pci_disable_device(pdev);
569 err_v4l2_dev_unreg:
570         v4l2_device_unregister(&pd->v4l2_dev);
571         return err;
572 }
573
574 static void dt3155_remove(struct pci_dev *pdev)
575 {
576         struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
577         struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
578                                               v4l2_dev);
579
580         video_unregister_device(&pd->vdev);
581         free_irq(pd->pdev->irq, pd);
582         vb2_queue_release(&pd->vidq);
583         v4l2_device_unregister(&pd->v4l2_dev);
584         pci_iounmap(pdev, pd->regs);
585         pci_release_region(pdev, 0);
586         pci_disable_device(pdev);
587 }
588
589 static const struct pci_device_id pci_ids[] = {
590         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
591         { 0, /* zero marks the end */ },
592 };
593 MODULE_DEVICE_TABLE(pci, pci_ids);
594
595 static struct pci_driver pci_driver = {
596         .name = DT3155_NAME,
597         .id_table = pci_ids,
598         .probe = dt3155_probe,
599         .remove = dt3155_remove,
600 };
601
602 module_pci_driver(pci_driver);
603
604 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
605 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
606 MODULE_VERSION(DT3155_VERSION);
607 MODULE_LICENSE("GPL");