[media] cx25821: make cx25821_sram_channels const
[sfrench/cifs-2.6.git] / drivers / media / pci / cx25821 / cx25821-video-upstream.c
1 /*
2  *  Driver for the Conexant CX25821 PCIe bridge
3  *
4  *  Copyright (C) 2009 Conexant Systems Inc.
5  *  Authors  <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License
19  *  along with this program; if not, write to the Free Software
20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25 #include "cx25821-video.h"
26 #include "cx25821-video-upstream.h"
27
28 #include <linux/fs.h>
29 #include <linux/errno.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/syscalls.h>
34 #include <linux/file.h>
35 #include <linux/fcntl.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41 MODULE_LICENSE("GPL");
42
43 static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC |
44                         FLD_VID_SRC_OPC_ERR;
45
46 int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
47                                         const struct sram_channel *ch,
48                                         unsigned int bpl, u32 risc)
49 {
50         unsigned int i, lines;
51         u32 cdt;
52
53         if (ch->cmds_start == 0) {
54                 cx_write(ch->ptr1_reg, 0);
55                 cx_write(ch->ptr2_reg, 0);
56                 cx_write(ch->cnt2_reg, 0);
57                 cx_write(ch->cnt1_reg, 0);
58                 return 0;
59         }
60
61         bpl = (bpl + 7) & ~7;   /* alignment */
62         cdt = ch->cdt;
63         lines = ch->fifo_size / bpl;
64
65         if (lines > 4)
66                 lines = 4;
67
68         BUG_ON(lines < 2);
69
70         /* write CDT */
71         for (i = 0; i < lines; i++) {
72                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
73                 cx_write(cdt + 16 * i + 4, 0);
74                 cx_write(cdt + 16 * i + 8, 0);
75                 cx_write(cdt + 16 * i + 12, 0);
76         }
77
78         /* write CMDS */
79         cx_write(ch->cmds_start + 0, risc);
80
81         cx_write(ch->cmds_start + 4, 0);
82         cx_write(ch->cmds_start + 8, cdt);
83         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
84         cx_write(ch->cmds_start + 16, ch->ctrl_start);
85
86         cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
87
88         for (i = 24; i < 80; i += 4)
89                 cx_write(ch->cmds_start + i, 0);
90
91         /* fill registers */
92         cx_write(ch->ptr1_reg, ch->fifo_start);
93         cx_write(ch->ptr2_reg, cdt);
94         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
95         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
96
97         return 0;
98 }
99
100 static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
101                                           __le32 *rp, unsigned int offset,
102                                           unsigned int bpl, u32 sync_line,
103                                           unsigned int lines, int fifo_enable,
104                                           int field_type)
105 {
106         unsigned int line, i;
107         int dist_betwn_starts = bpl * 2;
108
109         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
110
111         if (USE_RISC_NOOP_VIDEO) {
112                 for (i = 0; i < NUM_NO_OPS; i++)
113                         *(rp++) = cpu_to_le32(RISC_NOOP);
114         }
115
116         /* scan lines */
117         for (line = 0; line < lines; line++) {
118                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
119                 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
120                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
121
122                 if ((lines <= NTSC_FIELD_HEIGHT)
123                     || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
124                         offset += dist_betwn_starts;
125                 }
126         }
127
128         return rp;
129 }
130
131 static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
132                                            dma_addr_t databuf_phys_addr,
133                                            unsigned int offset, u32 sync_line,
134                                            unsigned int bpl, unsigned int lines,
135                                            int fifo_enable, int field_type)
136 {
137         unsigned int line, i;
138         const struct sram_channel *sram_ch =
139                 dev->channels[dev->_channel_upstream_select].sram_channels;
140         int dist_betwn_starts = bpl * 2;
141
142         /* sync instruction */
143         if (sync_line != NO_SYNC_LINE)
144                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
145
146         if (USE_RISC_NOOP_VIDEO) {
147                 for (i = 0; i < NUM_NO_OPS; i++)
148                         *(rp++) = cpu_to_le32(RISC_NOOP);
149         }
150
151         /* scan lines */
152         for (line = 0; line < lines; line++) {
153                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
154                 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
155                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
156
157                 if ((lines <= NTSC_FIELD_HEIGHT)
158                     || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC))
159                         /* to skip the other field line */
160                         offset += dist_betwn_starts;
161
162                 /* check if we need to enable the FIFO after the first 4 lines
163                  * For the upstream video channel, the risc engine will enable
164                  * the FIFO. */
165                 if (fifo_enable && line == 3) {
166                         *(rp++) = RISC_WRITECR;
167                         *(rp++) = sram_ch->dma_ctl;
168                         *(rp++) = FLD_VID_FIFO_EN;
169                         *(rp++) = 0x00000001;
170                 }
171         }
172
173         return rp;
174 }
175
176 static int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
177                                         struct pci_dev *pci,
178                                         unsigned int top_offset,
179                                         unsigned int bpl, unsigned int lines)
180 {
181         __le32 *rp;
182         int fifo_enable = 0;
183         /* get line count for single field */
184         int singlefield_lines = lines >> 1;
185         int odd_num_lines = singlefield_lines;
186         int frame = 0;
187         int frame_size = 0;
188         int databuf_offset = 0;
189         int risc_program_size = 0;
190         int risc_flag = RISC_CNT_RESET;
191         unsigned int bottom_offset = bpl;
192         dma_addr_t risc_phys_jump_addr;
193
194         if (dev->_isNTSC) {
195                 odd_num_lines = singlefield_lines + 1;
196                 risc_program_size = FRAME1_VID_PROG_SIZE;
197                 frame_size = (bpl == Y411_LINE_SZ) ?
198                         FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
199         } else {
200                 risc_program_size = PAL_VID_PROG_SIZE;
201                 frame_size = (bpl == Y411_LINE_SZ) ?
202                         FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
203         }
204
205         /* Virtual address of Risc buffer program */
206         rp = dev->_dma_virt_addr;
207
208         for (frame = 0; frame < NUM_FRAMES; frame++) {
209                 databuf_offset = frame_size * frame;
210
211                 if (UNSET != top_offset) {
212                         fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
213                         rp = cx25821_risc_field_upstream(dev, rp,
214                                         dev->_data_buf_phys_addr +
215                                         databuf_offset, top_offset, 0, bpl,
216                                         odd_num_lines, fifo_enable, ODD_FIELD);
217                 }
218
219                 fifo_enable = FIFO_DISABLE;
220
221                 /* Even Field */
222                 rp = cx25821_risc_field_upstream(dev, rp,
223                                                  dev->_data_buf_phys_addr +
224                                                  databuf_offset, bottom_offset,
225                                                  0x200, bpl, singlefield_lines,
226                                                  fifo_enable, EVEN_FIELD);
227
228                 if (frame == 0) {
229                         risc_flag = RISC_CNT_RESET;
230                         risc_phys_jump_addr = dev->_dma_phys_start_addr +
231                                 risc_program_size;
232                 } else {
233                         risc_phys_jump_addr = dev->_dma_phys_start_addr;
234                         risc_flag = RISC_CNT_INC;
235                 }
236
237                 /* Loop to 2ndFrameRISC or to Start of Risc
238                  * program & generate IRQ
239                  */
240                 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
241                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
242                 *(rp++) = cpu_to_le32(0);
243         }
244
245         return 0;
246 }
247
248 void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
249 {
250         const struct sram_channel *sram_ch =
251                 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_I].sram_channels;
252         u32 tmp = 0;
253
254         if (!dev->_is_running) {
255                 pr_info("No video file is currently running so return!\n");
256                 return;
257         }
258         /* Disable RISC interrupts */
259         tmp = cx_read(sram_ch->int_msk);
260         cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
261
262         /* Turn OFF risc and fifo enable */
263         tmp = cx_read(sram_ch->dma_ctl);
264         cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
265
266         /* Clear data buffer memory */
267         if (dev->_data_buf_virt_addr)
268                 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
269
270         dev->_is_running = 0;
271         dev->_is_first_frame = 0;
272         dev->_frame_count = 0;
273         dev->_file_status = END_OF_FILE;
274
275         kfree(dev->_irq_queues);
276         dev->_irq_queues = NULL;
277
278         kfree(dev->_filename);
279
280         tmp = cx_read(VID_CH_MODE_SEL);
281         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
282 }
283
284 void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
285 {
286         if (dev->_is_running)
287                 cx25821_stop_upstream_video_ch1(dev);
288
289         if (dev->_dma_virt_addr) {
290                 pci_free_consistent(dev->pci, dev->_risc_size,
291                                     dev->_dma_virt_addr, dev->_dma_phys_addr);
292                 dev->_dma_virt_addr = NULL;
293         }
294
295         if (dev->_data_buf_virt_addr) {
296                 pci_free_consistent(dev->pci, dev->_data_buf_size,
297                                     dev->_data_buf_virt_addr,
298                                     dev->_data_buf_phys_addr);
299                 dev->_data_buf_virt_addr = NULL;
300         }
301 }
302
303 static int cx25821_get_frame(struct cx25821_dev *dev,
304                              const struct sram_channel *sram_ch)
305 {
306         struct file *myfile;
307         int frame_index_temp = dev->_frame_index;
308         int i = 0;
309         int line_size = (dev->_pixel_format == PIXEL_FRMT_411) ?
310                 Y411_LINE_SZ : Y422_LINE_SZ;
311         int frame_size = 0;
312         int frame_offset = 0;
313         ssize_t vfs_read_retval = 0;
314         char mybuf[line_size];
315         loff_t file_offset;
316         loff_t pos;
317         mm_segment_t old_fs;
318
319         if (dev->_file_status == END_OF_FILE)
320                 return 0;
321
322         if (dev->_isNTSC)
323                 frame_size = (line_size == Y411_LINE_SZ) ?
324                         FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
325         else
326                 frame_size = (line_size == Y411_LINE_SZ) ?
327                         FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
328
329         frame_offset = (frame_index_temp > 0) ? frame_size : 0;
330         file_offset = dev->_frame_count * frame_size;
331
332         myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
333
334         if (IS_ERR(myfile)) {
335                 const int open_errno = -PTR_ERR(myfile);
336                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
337                        __func__, dev->_filename, open_errno);
338                 return PTR_ERR(myfile);
339         } else {
340                 if (!(myfile->f_op)) {
341                         pr_err("%s(): File has no file operations registered!\n",
342                                __func__);
343                         filp_close(myfile, NULL);
344                         return -EIO;
345                 }
346
347                 if (!myfile->f_op->read) {
348                         pr_err("%s(): File has no READ operations registered!\n",
349                                __func__);
350                         filp_close(myfile, NULL);
351                         return -EIO;
352                 }
353
354                 pos = myfile->f_pos;
355                 old_fs = get_fs();
356                 set_fs(KERNEL_DS);
357
358                 for (i = 0; i < dev->_lines_count; i++) {
359                         pos = file_offset;
360
361                         vfs_read_retval = vfs_read(myfile, mybuf, line_size,
362                                         &pos);
363
364                         if (vfs_read_retval > 0 && vfs_read_retval == line_size
365                             && dev->_data_buf_virt_addr != NULL) {
366                                 memcpy((void *)(dev->_data_buf_virt_addr +
367                                                 frame_offset / 4), mybuf,
368                                        vfs_read_retval);
369                         }
370
371                         file_offset += vfs_read_retval;
372                         frame_offset += vfs_read_retval;
373
374                         if (vfs_read_retval < line_size) {
375                                 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
376                                         __func__);
377                                 break;
378                         }
379                 }
380
381                 if (i > 0)
382                         dev->_frame_count++;
383
384                 dev->_file_status = (vfs_read_retval == line_size) ?
385                         IN_PROGRESS : END_OF_FILE;
386
387                 set_fs(old_fs);
388                 filp_close(myfile, NULL);
389         }
390
391         return 0;
392 }
393
394 static void cx25821_vidups_handler(struct work_struct *work)
395 {
396         struct cx25821_dev *dev = container_of(work, struct cx25821_dev,
397                         _irq_work_entry);
398
399         if (!dev) {
400                 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
401                        __func__);
402                 return;
403         }
404
405         cx25821_get_frame(dev, dev->channels[dev->_channel_upstream_select].
406                         sram_channels);
407 }
408
409 static int cx25821_openfile(struct cx25821_dev *dev,
410                             const struct sram_channel *sram_ch)
411 {
412         struct file *myfile;
413         int i = 0, j = 0;
414         int line_size = (dev->_pixel_format == PIXEL_FRMT_411) ?
415                 Y411_LINE_SZ : Y422_LINE_SZ;
416         ssize_t vfs_read_retval = 0;
417         char mybuf[line_size];
418         loff_t pos;
419         loff_t offset = (unsigned long)0;
420         mm_segment_t old_fs;
421
422         myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
423
424         if (IS_ERR(myfile)) {
425                 const int open_errno = -PTR_ERR(myfile);
426                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
427                        __func__, dev->_filename, open_errno);
428                 return PTR_ERR(myfile);
429         } else {
430                 if (!(myfile->f_op)) {
431                         pr_err("%s(): File has no file operations registered!\n",
432                                __func__);
433                         filp_close(myfile, NULL);
434                         return -EIO;
435                 }
436
437                 if (!myfile->f_op->read) {
438                         pr_err("%s(): File has no READ operations registered!  Returning\n",
439                                __func__);
440                         filp_close(myfile, NULL);
441                         return -EIO;
442                 }
443
444                 pos = myfile->f_pos;
445                 old_fs = get_fs();
446                 set_fs(KERNEL_DS);
447
448                 for (j = 0; j < NUM_FRAMES; j++) {
449                         for (i = 0; i < dev->_lines_count; i++) {
450                                 pos = offset;
451
452                                 vfs_read_retval = vfs_read(myfile, mybuf,
453                                                 line_size, &pos);
454
455                                 if (vfs_read_retval > 0
456                                     && vfs_read_retval == line_size
457                                     && dev->_data_buf_virt_addr != NULL) {
458                                         memcpy((void *)(dev->
459                                                         _data_buf_virt_addr +
460                                                         offset / 4), mybuf,
461                                                vfs_read_retval);
462                                 }
463
464                                 offset += vfs_read_retval;
465
466                                 if (vfs_read_retval < line_size) {
467                                         pr_info("Done: exit %s() since no more bytes to read from Video file\n",
468                                                 __func__);
469                                         break;
470                                 }
471                         }
472
473                         if (i > 0)
474                                 dev->_frame_count++;
475
476                         if (vfs_read_retval < line_size)
477                                 break;
478                 }
479
480                 dev->_file_status = (vfs_read_retval == line_size) ?
481                         IN_PROGRESS : END_OF_FILE;
482
483                 set_fs(old_fs);
484                 myfile->f_pos = 0;
485                 filp_close(myfile, NULL);
486         }
487
488         return 0;
489 }
490
491 static int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
492                                            const struct sram_channel *sram_ch,
493                                            int bpl)
494 {
495         int ret = 0;
496         dma_addr_t dma_addr;
497         dma_addr_t data_dma_addr;
498
499         if (dev->_dma_virt_addr != NULL)
500                 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
501                                 dev->_dma_virt_addr, dev->_dma_phys_addr);
502
503         dev->_dma_virt_addr = pci_alloc_consistent(dev->pci,
504                         dev->upstream_riscbuf_size, &dma_addr);
505         dev->_dma_virt_start_addr = dev->_dma_virt_addr;
506         dev->_dma_phys_start_addr = dma_addr;
507         dev->_dma_phys_addr = dma_addr;
508         dev->_risc_size = dev->upstream_riscbuf_size;
509
510         if (!dev->_dma_virt_addr) {
511                 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
512                 return -ENOMEM;
513         }
514
515         /* Clear memory at address */
516         memset(dev->_dma_virt_addr, 0, dev->_risc_size);
517
518         if (dev->_data_buf_virt_addr != NULL)
519                 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
520                                 dev->_data_buf_virt_addr,
521                                 dev->_data_buf_phys_addr);
522         /* For Video Data buffer allocation */
523         dev->_data_buf_virt_addr = pci_alloc_consistent(dev->pci,
524                         dev->upstream_databuf_size, &data_dma_addr);
525         dev->_data_buf_phys_addr = data_dma_addr;
526         dev->_data_buf_size = dev->upstream_databuf_size;
527
528         if (!dev->_data_buf_virt_addr) {
529                 pr_err("FAILED to allocate memory for data buffer! Returning\n");
530                 return -ENOMEM;
531         }
532
533         /* Clear memory at address */
534         memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
535
536         ret = cx25821_openfile(dev, sram_ch);
537         if (ret < 0)
538                 return ret;
539
540         /* Create RISC programs */
541         ret = cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
542                         dev->_lines_count);
543         if (ret < 0) {
544                 pr_info("Failed creating Video Upstream Risc programs!\n");
545                 goto error;
546         }
547
548         return 0;
549
550 error:
551         return ret;
552 }
553
554 static int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
555                                       u32 status)
556 {
557         u32 int_msk_tmp;
558         const struct sram_channel *channel = dev->channels[chan_num].sram_channels;
559         int singlefield_lines = NTSC_FIELD_HEIGHT;
560         int line_size_in_bytes = Y422_LINE_SZ;
561         int odd_risc_prog_size = 0;
562         dma_addr_t risc_phys_jump_addr;
563         __le32 *rp;
564
565         if (status & FLD_VID_SRC_RISC1) {
566                 /* We should only process one program per call */
567                 u32 prog_cnt = cx_read(channel->gpcnt);
568
569                 /* Since we've identified our IRQ, clear our bits from the
570                  * interrupt mask and interrupt status registers */
571                 int_msk_tmp = cx_read(channel->int_msk);
572                 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
573                 cx_write(channel->int_stat, _intr_msk);
574
575                 spin_lock(&dev->slock);
576
577                 dev->_frame_index = prog_cnt;
578
579                 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
580
581                 if (dev->_is_first_frame) {
582                         dev->_is_first_frame = 0;
583
584                         if (dev->_isNTSC) {
585                                 singlefield_lines += 1;
586                                 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
587                         } else {
588                                 singlefield_lines = PAL_FIELD_HEIGHT;
589                                 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
590                         }
591
592                         if (dev->_dma_virt_start_addr != NULL) {
593                                 line_size_in_bytes =
594                                     (dev->_pixel_format ==
595                                      PIXEL_FRMT_411) ? Y411_LINE_SZ :
596                                     Y422_LINE_SZ;
597                                 risc_phys_jump_addr =
598                                     dev->_dma_phys_start_addr +
599                                     odd_risc_prog_size;
600
601                                 rp = cx25821_update_riscprogram(dev,
602                                         dev->_dma_virt_start_addr, TOP_OFFSET,
603                                         line_size_in_bytes, 0x0,
604                                         singlefield_lines, FIFO_DISABLE,
605                                         ODD_FIELD);
606
607                                 /* Jump to Even Risc program of 1st Frame */
608                                 *(rp++) = cpu_to_le32(RISC_JUMP);
609                                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
610                                 *(rp++) = cpu_to_le32(0);
611                         }
612                 }
613
614                 spin_unlock(&dev->slock);
615         } else {
616                 if (status & FLD_VID_SRC_UF)
617                         pr_err("%s(): Video Received Underflow Error Interrupt!\n",
618                                __func__);
619
620                 if (status & FLD_VID_SRC_SYNC)
621                         pr_err("%s(): Video Received Sync Error Interrupt!\n",
622                                __func__);
623
624                 if (status & FLD_VID_SRC_OPC_ERR)
625                         pr_err("%s(): Video Received OpCode Error Interrupt!\n",
626                                __func__);
627         }
628
629         if (dev->_file_status == END_OF_FILE) {
630                 pr_err("EOF Channel 1 Framecount = %d\n", dev->_frame_count);
631                 return -1;
632         }
633         /* ElSE, set the interrupt mask register, re-enable irq. */
634         int_msk_tmp = cx_read(channel->int_msk);
635         cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
636
637         return 0;
638 }
639
640 static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
641 {
642         struct cx25821_dev *dev = dev_id;
643         u32 vid_status;
644         int handled = 0;
645         int channel_num = 0;
646         const struct sram_channel *sram_ch;
647
648         if (!dev)
649                 return -1;
650
651         channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
652
653         sram_ch = dev->channels[channel_num].sram_channels;
654
655         vid_status = cx_read(sram_ch->int_stat);
656
657         /* Only deal with our interrupt */
658         if (vid_status)
659                 handled = cx25821_video_upstream_irq(dev, channel_num,
660                                 vid_status);
661
662         if (handled < 0)
663                 cx25821_stop_upstream_video_ch1(dev);
664         else
665                 handled += handled;
666
667         return IRQ_RETVAL(handled);
668 }
669
670 static void cx25821_set_pixelengine(struct cx25821_dev *dev,
671                                     const struct sram_channel *ch,
672                                     int pix_format)
673 {
674         int width = WIDTH_D1;
675         int height = dev->_lines_count;
676         int num_lines, odd_num_lines;
677         u32 value;
678         int vip_mode = OUTPUT_FRMT_656;
679
680         value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
681         value &= 0xFFFFFFEF;
682         value |= dev->_isNTSC ? 0 : 0x10;
683         cx_write(ch->vid_fmt_ctl, value);
684
685         /* set number of active pixels in each line.
686          * Default is 720 pixels in both NTSC and PAL format */
687         cx_write(ch->vid_active_ctl1, width);
688
689         num_lines = (height / 2) & 0x3FF;
690         odd_num_lines = num_lines;
691
692         if (dev->_isNTSC)
693                 odd_num_lines += 1;
694
695         value = (num_lines << 16) | odd_num_lines;
696
697         /* set number of active lines in field 0 (top) and field 1 (bottom) */
698         cx_write(ch->vid_active_ctl2, value);
699
700         cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
701 }
702
703 static int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
704                                             const struct sram_channel *sram_ch)
705 {
706         u32 tmp = 0;
707         int err = 0;
708
709         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
710          * channel A-C
711          */
712         tmp = cx_read(VID_CH_MODE_SEL);
713         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
714
715         /* Set the physical start address of the RISC program in the initial
716          * program counter(IPC) member of the cmds.
717          */
718         cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
719         /* Risc IPC High 64 bits 63-32 */
720         cx_write(sram_ch->cmds_start + 4, 0);
721
722         /* reset counter */
723         cx_write(sram_ch->gpcnt_ctl, 3);
724
725         /* Clear our bits from the interrupt status register. */
726         cx_write(sram_ch->int_stat, _intr_msk);
727
728         /* Set the interrupt mask register, enable irq. */
729         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
730         tmp = cx_read(sram_ch->int_msk);
731         cx_write(sram_ch->int_msk, tmp |= _intr_msk);
732
733         err = request_irq(dev->pci->irq, cx25821_upstream_irq,
734                         IRQF_SHARED, dev->name, dev);
735         if (err < 0) {
736                 pr_err("%s: can't get upstream IRQ %d\n",
737                        dev->name, dev->pci->irq);
738                 goto fail_irq;
739         }
740
741         /* Start the DMA  engine */
742         tmp = cx_read(sram_ch->dma_ctl);
743         cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
744
745         dev->_is_running = 1;
746         dev->_is_first_frame = 1;
747
748         return 0;
749
750 fail_irq:
751         cx25821_dev_unregister(dev);
752         return err;
753 }
754
755 int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
756                                  int pixel_format)
757 {
758         const struct sram_channel *sram_ch;
759         u32 tmp;
760         int err = 0;
761         int data_frame_size = 0;
762         int risc_buffer_size = 0;
763         int str_length = 0;
764
765         if (dev->_is_running) {
766                 pr_info("Video Channel is still running so return!\n");
767                 return 0;
768         }
769
770         dev->_channel_upstream_select = channel_select;
771         sram_ch = dev->channels[channel_select].sram_channels;
772
773         INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
774         dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
775
776         if (!dev->_irq_queues) {
777                 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
778                 return -ENOMEM;
779         }
780         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
781          * channel A-C
782          */
783         tmp = cx_read(VID_CH_MODE_SEL);
784         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
785
786         dev->_is_running = 0;
787         dev->_frame_count = 0;
788         dev->_file_status = RESET_STATUS;
789         dev->_lines_count = dev->_isNTSC ? 480 : 576;
790         dev->_pixel_format = pixel_format;
791         dev->_line_size = (dev->_pixel_format == PIXEL_FRMT_422) ?
792                 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
793         data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
794         risc_buffer_size = dev->_isNTSC ?
795                 NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
796
797         if (dev->input_filename) {
798                 str_length = strlen(dev->input_filename);
799                 dev->_filename = kmemdup(dev->input_filename, str_length + 1,
800                                          GFP_KERNEL);
801
802                 if (!dev->_filename) {
803                         err = -ENOENT;
804                         goto error;
805                 }
806         } else {
807                 str_length = strlen(dev->_defaultname);
808                 dev->_filename = kmemdup(dev->_defaultname, str_length + 1,
809                                          GFP_KERNEL);
810
811                 if (!dev->_filename) {
812                         err = -ENOENT;
813                         goto error;
814                 }
815         }
816
817         /* Default if filename is empty string */
818         if (strcmp(dev->_filename, "") == 0) {
819                 if (dev->_isNTSC) {
820                         dev->_filename =
821                                 (dev->_pixel_format == PIXEL_FRMT_411) ?
822                                 "/root/vid411.yuv" : "/root/vidtest.yuv";
823                 } else {
824                         dev->_filename =
825                                 (dev->_pixel_format == PIXEL_FRMT_411) ?
826                                 "/root/pal411.yuv" : "/root/pal422.yuv";
827                 }
828         }
829
830         dev->_is_running = 0;
831         dev->_frame_count = 0;
832         dev->_file_status = RESET_STATUS;
833         dev->_lines_count = dev->_isNTSC ? 480 : 576;
834         dev->_pixel_format = pixel_format;
835         dev->_line_size = (dev->_pixel_format == PIXEL_FRMT_422) ?
836                 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
837
838         err = cx25821_sram_channel_setup_upstream(dev, sram_ch,
839                         dev->_line_size, 0);
840
841         /* setup fifo + format */
842         cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
843
844         dev->upstream_riscbuf_size = risc_buffer_size * 2;
845         dev->upstream_databuf_size = data_frame_size * 2;
846
847         /* Allocating buffers and prepare RISC program */
848         err = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
849         if (err < 0) {
850                 pr_err("%s: Failed to set up Video upstream buffers!\n",
851                        dev->name);
852                 goto error;
853         }
854
855         cx25821_start_video_dma_upstream(dev, sram_ch);
856
857         return 0;
858
859 error:
860         cx25821_dev_unregister(dev);
861
862         return err;
863 }