[media] cx25821: make cx25821_sram_channels const
[sfrench/cifs-2.6.git] / drivers / media / pci / cx25821 / cx25821-video-upstream-ch2.c
1 /*
2  *  Driver for the Conexant CX25821 PCIe bridge
3  *
4  *  Copyright (C) 2009 Conexant Systems Inc.
5  *  Authors  <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License
19  *  along with this program; if not, write to the Free Software
20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25 #include "cx25821-video.h"
26 #include "cx25821-video-upstream-ch2.h"
27
28 #include <linux/fs.h>
29 #include <linux/errno.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/syscalls.h>
34 #include <linux/file.h>
35 #include <linux/fcntl.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41 MODULE_LICENSE("GPL");
42
43 static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC |
44                         FLD_VID_SRC_OPC_ERR;
45
46 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
47                                               __le32 *rp, unsigned int offset,
48                                               unsigned int bpl, u32 sync_line,
49                                               unsigned int lines,
50                                               int fifo_enable, int field_type)
51 {
52         unsigned int line, i;
53         int dist_betwn_starts = bpl * 2;
54
55         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
56
57         if (USE_RISC_NOOP_VIDEO) {
58                 for (i = 0; i < NUM_NO_OPS; i++)
59                         *(rp++) = cpu_to_le32(RISC_NOOP);
60         }
61
62         /* scan lines */
63         for (line = 0; line < lines; line++) {
64                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
65                 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
66                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
67
68                 if ((lines <= NTSC_FIELD_HEIGHT) ||
69                     (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC_ch2)) {
70                         offset += dist_betwn_starts;
71                 }
72         }
73
74         return rp;
75 }
76
77 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
78                                                __le32 *rp,
79                                                dma_addr_t databuf_phys_addr,
80                                                unsigned int offset,
81                                                u32 sync_line, unsigned int bpl,
82                                                unsigned int lines,
83                                                int fifo_enable, int field_type)
84 {
85         unsigned int line, i;
86         const struct sram_channel *sram_ch =
87                 dev->channels[dev->_channel2_upstream_select].sram_channels;
88         int dist_betwn_starts = bpl * 2;
89
90         /* sync instruction */
91         if (sync_line != NO_SYNC_LINE)
92                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
93
94         if (USE_RISC_NOOP_VIDEO) {
95                 for (i = 0; i < NUM_NO_OPS; i++)
96                         *(rp++) = cpu_to_le32(RISC_NOOP);
97         }
98
99         /* scan lines */
100         for (line = 0; line < lines; line++) {
101                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
102                 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
103                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
104
105                 if ((lines <= NTSC_FIELD_HEIGHT) ||
106                     (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC_ch2)) {
107                         offset += dist_betwn_starts;
108                 }
109
110                /*
111                  check if we need to enable the FIFO after the first 4 lines
112                   For the upstream video channel, the risc engine will enable
113                   the FIFO.
114                */
115                 if (fifo_enable && line == 3) {
116                         *(rp++) = RISC_WRITECR;
117                         *(rp++) = sram_ch->dma_ctl;
118                         *(rp++) = FLD_VID_FIFO_EN;
119                         *(rp++) = 0x00000001;
120                 }
121         }
122
123         return rp;
124 }
125
126 static int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
127                                             struct pci_dev *pci,
128                                             unsigned int top_offset,
129                                             unsigned int bpl,
130                                             unsigned int lines)
131 {
132         __le32 *rp;
133         int fifo_enable = 0;
134         int singlefield_lines = lines >> 1; /*get line count for single field */
135         int odd_num_lines = singlefield_lines;
136         int frame = 0;
137         int frame_size = 0;
138         int databuf_offset = 0;
139         int risc_program_size = 0;
140         int risc_flag = RISC_CNT_RESET;
141         unsigned int bottom_offset = bpl;
142         dma_addr_t risc_phys_jump_addr;
143
144         if (dev->_isNTSC_ch2) {
145                 odd_num_lines = singlefield_lines + 1;
146                 risc_program_size = FRAME1_VID_PROG_SIZE;
147                 if (bpl == Y411_LINE_SZ)
148                         frame_size = FRAME_SIZE_NTSC_Y411;
149                 else
150                         frame_size = FRAME_SIZE_NTSC_Y422;
151         } else {
152                 risc_program_size = PAL_VID_PROG_SIZE;
153                 if (bpl == Y411_LINE_SZ)
154                         frame_size = FRAME_SIZE_PAL_Y411;
155                 else
156                         frame_size = FRAME_SIZE_PAL_Y422;
157         }
158
159         /* Virtual address of Risc buffer program */
160         rp = dev->_dma_virt_addr_ch2;
161
162         for (frame = 0; frame < NUM_FRAMES; frame++) {
163                 databuf_offset = frame_size * frame;
164
165                 if (UNSET != top_offset) {
166                         fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
167                         rp = cx25821_risc_field_upstream_ch2(dev, rp,
168                                 dev->_data_buf_phys_addr_ch2 + databuf_offset,
169                                 top_offset, 0, bpl, odd_num_lines, fifo_enable,
170                                 ODD_FIELD);
171                 }
172
173                 fifo_enable = FIFO_DISABLE;
174
175                 /* Even field */
176                 rp = cx25821_risc_field_upstream_ch2(dev, rp,
177                                 dev->_data_buf_phys_addr_ch2 + databuf_offset,
178                                 bottom_offset, 0x200, bpl, singlefield_lines,
179                                 fifo_enable, EVEN_FIELD);
180
181                 if (frame == 0) {
182                         risc_flag = RISC_CNT_RESET;
183                         risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2 +
184                                         risc_program_size;
185                 } else {
186                         risc_flag = RISC_CNT_INC;
187                         risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
188                 }
189
190                /*
191                 * Loop to 2ndFrameRISC or to Start of
192                 * Risc program & generate IRQ
193                 */
194                 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
195                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
196                 *(rp++) = cpu_to_le32(0);
197         }
198
199         return 0;
200 }
201
202 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
203 {
204         const struct sram_channel *sram_ch =
205                 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
206         u32 tmp = 0;
207
208         if (!dev->_is_running_ch2) {
209                 pr_info("No video file is currently running so return!\n");
210                 return;
211         }
212         /* Disable RISC interrupts */
213         tmp = cx_read(sram_ch->int_msk);
214         cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
215
216         /* Turn OFF risc and fifo */
217         tmp = cx_read(sram_ch->dma_ctl);
218         cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
219
220         /* Clear data buffer memory */
221         if (dev->_data_buf_virt_addr_ch2)
222                 memset(dev->_data_buf_virt_addr_ch2, 0,
223                        dev->_data_buf_size_ch2);
224
225         dev->_is_running_ch2 = 0;
226         dev->_is_first_frame_ch2 = 0;
227         dev->_frame_count_ch2 = 0;
228         dev->_file_status_ch2 = END_OF_FILE;
229
230         kfree(dev->_irq_queues_ch2);
231         dev->_irq_queues_ch2 = NULL;
232
233         kfree(dev->_filename_ch2);
234
235         tmp = cx_read(VID_CH_MODE_SEL);
236         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
237 }
238
239 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
240 {
241         if (dev->_is_running_ch2)
242                 cx25821_stop_upstream_video_ch2(dev);
243
244         if (dev->_dma_virt_addr_ch2) {
245                 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
246                                     dev->_dma_virt_addr_ch2,
247                                     dev->_dma_phys_addr_ch2);
248                 dev->_dma_virt_addr_ch2 = NULL;
249         }
250
251         if (dev->_data_buf_virt_addr_ch2) {
252                 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
253                                     dev->_data_buf_virt_addr_ch2,
254                                     dev->_data_buf_phys_addr_ch2);
255                 dev->_data_buf_virt_addr_ch2 = NULL;
256         }
257 }
258
259 static int cx25821_get_frame_ch2(struct cx25821_dev *dev,
260                                  const struct sram_channel *sram_ch)
261 {
262         struct file *myfile;
263         int frame_index_temp = dev->_frame_index_ch2;
264         int i = 0;
265         int line_size = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ?
266                 Y411_LINE_SZ : Y422_LINE_SZ;
267         int frame_size = 0;
268         int frame_offset = 0;
269         ssize_t vfs_read_retval = 0;
270         char mybuf[line_size];
271         loff_t file_offset;
272         loff_t pos;
273         mm_segment_t old_fs;
274
275         if (dev->_file_status_ch2 == END_OF_FILE)
276                 return 0;
277
278         if (dev->_isNTSC_ch2) {
279                 frame_size = (line_size == Y411_LINE_SZ) ?
280                         FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
281         } else {
282                 frame_size = (line_size == Y411_LINE_SZ) ?
283                         FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
284         }
285
286         frame_offset = (frame_index_temp > 0) ? frame_size : 0;
287         file_offset = dev->_frame_count_ch2 * frame_size;
288
289         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
290         if (IS_ERR(myfile)) {
291                 const int open_errno = -PTR_ERR(myfile);
292                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
293                        __func__, dev->_filename_ch2, open_errno);
294                 return PTR_ERR(myfile);
295         } else {
296                 if (!(myfile->f_op)) {
297                         pr_err("%s(): File has no file operations registered!\n",
298                                __func__);
299                         filp_close(myfile, NULL);
300                         return -EIO;
301                 }
302
303                 if (!myfile->f_op->read) {
304                         pr_err("%s(): File has no READ operations registered!\n",
305                                __func__);
306                         filp_close(myfile, NULL);
307                         return -EIO;
308                 }
309
310                 pos = myfile->f_pos;
311                 old_fs = get_fs();
312                 set_fs(KERNEL_DS);
313
314                 for (i = 0; i < dev->_lines_count_ch2; i++) {
315                         pos = file_offset;
316
317                         vfs_read_retval = vfs_read(myfile, mybuf, line_size,
318                                         &pos);
319
320                         if (vfs_read_retval > 0 && vfs_read_retval == line_size
321                             && dev->_data_buf_virt_addr_ch2 != NULL) {
322                                 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
323                                                 frame_offset / 4), mybuf,
324                                                 vfs_read_retval);
325                         }
326
327                         file_offset += vfs_read_retval;
328                         frame_offset += vfs_read_retval;
329
330                         if (vfs_read_retval < line_size) {
331                                 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
332                                         __func__);
333                                 break;
334                         }
335                 }
336
337                 if (i > 0)
338                         dev->_frame_count_ch2++;
339
340                 dev->_file_status_ch2 = (vfs_read_retval == line_size) ?
341                         IN_PROGRESS : END_OF_FILE;
342
343                 set_fs(old_fs);
344                 filp_close(myfile, NULL);
345         }
346
347         return 0;
348 }
349
350 static void cx25821_vidups_handler_ch2(struct work_struct *work)
351 {
352         struct cx25821_dev *dev = container_of(work, struct cx25821_dev,
353                         _irq_work_entry_ch2);
354
355         if (!dev) {
356                 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
357                        __func__);
358                 return;
359         }
360
361         cx25821_get_frame_ch2(dev, dev->channels[dev->
362                         _channel2_upstream_select].sram_channels);
363 }
364
365 static int cx25821_openfile_ch2(struct cx25821_dev *dev,
366                                 const struct sram_channel *sram_ch)
367 {
368         struct file *myfile;
369         int i = 0, j = 0;
370         int line_size = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ?
371                 Y411_LINE_SZ : Y422_LINE_SZ;
372         ssize_t vfs_read_retval = 0;
373         char mybuf[line_size];
374         loff_t pos;
375         loff_t offset = (unsigned long)0;
376         mm_segment_t old_fs;
377
378         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
379
380         if (IS_ERR(myfile)) {
381                 const int open_errno = -PTR_ERR(myfile);
382                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
383                        __func__, dev->_filename_ch2, open_errno);
384                 return PTR_ERR(myfile);
385         } else {
386                 if (!(myfile->f_op)) {
387                         pr_err("%s(): File has no file operations registered!\n",
388                                __func__);
389                         filp_close(myfile, NULL);
390                         return -EIO;
391                 }
392
393                 if (!myfile->f_op->read) {
394                         pr_err("%s(): File has no READ operations registered!  Returning\n",
395                                __func__);
396                         filp_close(myfile, NULL);
397                         return -EIO;
398                 }
399
400                 pos = myfile->f_pos;
401                 old_fs = get_fs();
402                 set_fs(KERNEL_DS);
403
404                 for (j = 0; j < NUM_FRAMES; j++) {
405                         for (i = 0; i < dev->_lines_count_ch2; i++) {
406                                 pos = offset;
407
408                                 vfs_read_retval = vfs_read(myfile, mybuf,
409                                                 line_size, &pos);
410
411                                 if (vfs_read_retval > 0 &&
412                                     vfs_read_retval == line_size &&
413                                     dev->_data_buf_virt_addr_ch2 != NULL) {
414                                         memcpy((void *)(dev->
415                                                         _data_buf_virt_addr_ch2
416                                                         + offset / 4), mybuf,
417                                                         vfs_read_retval);
418                                 }
419
420                                 offset += vfs_read_retval;
421
422                                 if (vfs_read_retval < line_size) {
423                                         pr_info("Done: exit %s() since no more bytes to read from Video file\n",
424                                                 __func__);
425                                         break;
426                                 }
427                         }
428
429                         if (i > 0)
430                                 dev->_frame_count_ch2++;
431
432                         if (vfs_read_retval < line_size)
433                                 break;
434                 }
435
436                 dev->_file_status_ch2 = (vfs_read_retval == line_size) ?
437                         IN_PROGRESS : END_OF_FILE;
438
439                 set_fs(old_fs);
440                 myfile->f_pos = 0;
441                 filp_close(myfile, NULL);
442         }
443
444         return 0;
445 }
446
447 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
448                                                const struct sram_channel *sram_ch,
449                                                int bpl)
450 {
451         int ret = 0;
452         dma_addr_t dma_addr;
453         dma_addr_t data_dma_addr;
454
455         if (dev->_dma_virt_addr_ch2 != NULL) {
456                 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
457                                     dev->_dma_virt_addr_ch2,
458                                     dev->_dma_phys_addr_ch2);
459         }
460
461         dev->_dma_virt_addr_ch2 = pci_alloc_consistent(dev->pci,
462                         dev->upstream_riscbuf_size_ch2, &dma_addr);
463         dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
464         dev->_dma_phys_start_addr_ch2 = dma_addr;
465         dev->_dma_phys_addr_ch2 = dma_addr;
466         dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
467
468         if (!dev->_dma_virt_addr_ch2) {
469                 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
470                 return -ENOMEM;
471         }
472
473         /* Iniitize at this address until n bytes to 0 */
474         memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
475
476         if (dev->_data_buf_virt_addr_ch2 != NULL) {
477                 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
478                                     dev->_data_buf_virt_addr_ch2,
479                                     dev->_data_buf_phys_addr_ch2);
480         }
481         /* For Video Data buffer allocation */
482         dev->_data_buf_virt_addr_ch2 = pci_alloc_consistent(dev->pci,
483                         dev->upstream_databuf_size_ch2, &data_dma_addr);
484         dev->_data_buf_phys_addr_ch2 = data_dma_addr;
485         dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
486
487         if (!dev->_data_buf_virt_addr_ch2) {
488                 pr_err("FAILED to allocate memory for data buffer! Returning\n");
489                 return -ENOMEM;
490         }
491
492         /* Initialize at this address until n bytes to 0 */
493         memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
494
495         ret = cx25821_openfile_ch2(dev, sram_ch);
496         if (ret < 0)
497                 return ret;
498
499         /* Creating RISC programs */
500         ret = cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
501                                                 dev->_lines_count_ch2);
502         if (ret < 0) {
503                 pr_info("Failed creating Video Upstream Risc programs!\n");
504                 goto error;
505         }
506
507         return 0;
508
509 error:
510         return ret;
511 }
512
513 static int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev,
514                                           int chan_num,
515                                           u32 status)
516 {
517         u32 int_msk_tmp;
518         const struct sram_channel *channel = dev->channels[chan_num].sram_channels;
519         int singlefield_lines = NTSC_FIELD_HEIGHT;
520         int line_size_in_bytes = Y422_LINE_SZ;
521         int odd_risc_prog_size = 0;
522         dma_addr_t risc_phys_jump_addr;
523         __le32 *rp;
524
525         if (status & FLD_VID_SRC_RISC1) {
526                 /* We should only process one program per call */
527                 u32 prog_cnt = cx_read(channel->gpcnt);
528
529                 /*
530                  *  Since we've identified our IRQ, clear our bits from the
531                  *  interrupt mask and interrupt status registers
532                  */
533                 int_msk_tmp = cx_read(channel->int_msk);
534                 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
535                 cx_write(channel->int_stat, _intr_msk);
536
537                 spin_lock(&dev->slock);
538
539                 dev->_frame_index_ch2 = prog_cnt;
540
541                 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
542
543                 if (dev->_is_first_frame_ch2) {
544                         dev->_is_first_frame_ch2 = 0;
545
546                         if (dev->_isNTSC_ch2) {
547                                 singlefield_lines += 1;
548                                 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
549                         } else {
550                                 singlefield_lines = PAL_FIELD_HEIGHT;
551                                 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
552                         }
553
554                         if (dev->_dma_virt_start_addr_ch2 != NULL) {
555                                 if (dev->_pixel_format_ch2 == PIXEL_FRMT_411)
556                                         line_size_in_bytes = Y411_LINE_SZ;
557                                 else
558                                         line_size_in_bytes = Y422_LINE_SZ;
559                                 risc_phys_jump_addr =
560                                         dev->_dma_phys_start_addr_ch2 +
561                                         odd_risc_prog_size;
562
563                                 rp = cx25821_update_riscprogram_ch2(dev,
564                                                 dev->_dma_virt_start_addr_ch2,
565                                                 TOP_OFFSET, line_size_in_bytes,
566                                                 0x0, singlefield_lines,
567                                                 FIFO_DISABLE, ODD_FIELD);
568
569                                /* Jump to Even Risc program of 1st Frame */
570                                 *(rp++) = cpu_to_le32(RISC_JUMP);
571                                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
572                                 *(rp++) = cpu_to_le32(0);
573                         }
574                 }
575
576                 spin_unlock(&dev->slock);
577         }
578
579         if (dev->_file_status_ch2 == END_OF_FILE) {
580                 pr_info("EOF Channel 2 Framecount = %d\n",
581                         dev->_frame_count_ch2);
582                 return -1;
583         }
584         /* ElSE, set the interrupt mask register, re-enable irq. */
585         int_msk_tmp = cx_read(channel->int_msk);
586         cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
587
588         return 0;
589 }
590
591 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
592 {
593         struct cx25821_dev *dev = dev_id;
594         u32 vid_status;
595         int handled = 0;
596         int channel_num = 0;
597         const struct sram_channel *sram_ch;
598
599         if (!dev)
600                 return -1;
601
602         channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
603         sram_ch = dev->channels[channel_num].sram_channels;
604
605         vid_status = cx_read(sram_ch->int_stat);
606
607         /* Only deal with our interrupt */
608         if (vid_status)
609                 handled = cx25821_video_upstream_irq_ch2(dev, channel_num,
610                                 vid_status);
611
612         if (handled < 0)
613                 cx25821_stop_upstream_video_ch2(dev);
614         else
615                 handled += handled;
616
617         return IRQ_RETVAL(handled);
618 }
619
620 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
621                                         const struct sram_channel *ch, int pix_format)
622 {
623         int width = WIDTH_D1;
624         int height = dev->_lines_count_ch2;
625         int num_lines, odd_num_lines;
626         u32 value;
627         int vip_mode = PIXEL_ENGINE_VIP1;
628
629         value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
630         value &= 0xFFFFFFEF;
631         value |= dev->_isNTSC_ch2 ? 0 : 0x10;
632         cx_write(ch->vid_fmt_ctl, value);
633
634         /*
635          *  set number of active pixels in each line. Default is 720
636          * pixels in both NTSC and PAL format
637          */
638         cx_write(ch->vid_active_ctl1, width);
639
640         num_lines = (height / 2) & 0x3FF;
641         odd_num_lines = num_lines;
642
643         if (dev->_isNTSC_ch2)
644                 odd_num_lines += 1;
645
646         value = (num_lines << 16) | odd_num_lines;
647
648         /* set number of active lines in field 0 (top) and field 1 (bottom) */
649         cx_write(ch->vid_active_ctl2, value);
650
651         cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
652 }
653
654 static int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
655                                                 const struct sram_channel *sram_ch)
656 {
657         u32 tmp = 0;
658         int err = 0;
659
660         /*
661          *  656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
662          * for channel A-C
663          */
664         tmp = cx_read(VID_CH_MODE_SEL);
665         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
666
667         /*
668          *  Set the physical start address of the RISC program in the initial
669          *  program counter(IPC) member of the cmds.
670          */
671         cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
672         cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
673
674         /* reset counter */
675         cx_write(sram_ch->gpcnt_ctl, 3);
676
677         /* Clear our bits from the interrupt status register. */
678         cx_write(sram_ch->int_stat, _intr_msk);
679
680         /* Set the interrupt mask register, enable irq. */
681         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
682         tmp = cx_read(sram_ch->int_msk);
683         cx_write(sram_ch->int_msk, tmp |= _intr_msk);
684
685         err = request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
686                         IRQF_SHARED, dev->name, dev);
687         if (err < 0) {
688                 pr_err("%s: can't get upstream IRQ %d\n",
689                        dev->name, dev->pci->irq);
690                 goto fail_irq;
691         }
692         /* Start the DMA  engine */
693         tmp = cx_read(sram_ch->dma_ctl);
694         cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
695
696         dev->_is_running_ch2 = 1;
697         dev->_is_first_frame_ch2 = 1;
698
699         return 0;
700
701 fail_irq:
702         cx25821_dev_unregister(dev);
703         return err;
704 }
705
706 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
707                                  int pixel_format)
708 {
709         const struct sram_channel *sram_ch;
710         u32 tmp;
711         int err = 0;
712         int data_frame_size = 0;
713         int risc_buffer_size = 0;
714
715         if (dev->_is_running_ch2) {
716                 pr_info("Video Channel is still running so return!\n");
717                 return 0;
718         }
719
720         dev->_channel2_upstream_select = channel_select;
721         sram_ch = dev->channels[channel_select].sram_channels;
722
723         INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
724         dev->_irq_queues_ch2 =
725             create_singlethread_workqueue("cx25821_workqueue2");
726
727         if (!dev->_irq_queues_ch2) {
728                 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
729                 return -ENOMEM;
730         }
731         /*
732          * 656/VIP SRC Upstream Channel I & J and 7 -
733          * Host Bus Interface for channel A-C
734          */
735         tmp = cx_read(VID_CH_MODE_SEL);
736         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
737
738         dev->_is_running_ch2 = 0;
739         dev->_frame_count_ch2 = 0;
740         dev->_file_status_ch2 = RESET_STATUS;
741         dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
742         dev->_pixel_format_ch2 = pixel_format;
743         dev->_line_size_ch2 = (dev->_pixel_format_ch2 == PIXEL_FRMT_422) ?
744                 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
745         data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
746         risc_buffer_size = dev->_isNTSC_ch2 ?
747                 NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
748
749         if (dev->input_filename_ch2)
750                 dev->_filename_ch2 = kstrdup(dev->input_filename_ch2,
751                                                                 GFP_KERNEL);
752         else
753                 dev->_filename_ch2 = kstrdup(dev->_defaultname_ch2,
754                                                                 GFP_KERNEL);
755
756         if (!dev->_filename_ch2) {
757                 err = -ENOENT;
758                 goto error;
759         }
760
761         /* Default if filename is empty string */
762         if (strcmp(dev->_filename_ch2, "") == 0) {
763                 if (dev->_isNTSC_ch2) {
764                         dev->_filename_ch2 = (dev->_pixel_format_ch2 ==
765                                 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
766                                 "/root/vidtest.yuv";
767                 } else {
768                         dev->_filename_ch2 = (dev->_pixel_format_ch2 ==
769                                 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
770                                 "/root/pal422.yuv";
771                 }
772         }
773
774         err = cx25821_sram_channel_setup_upstream(dev, sram_ch,
775                                                 dev->_line_size_ch2, 0);
776
777         /* setup fifo + format */
778         cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
779
780         dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
781         dev->upstream_databuf_size_ch2 = data_frame_size * 2;
782
783         /* Allocating buffers and prepare RISC program */
784         err = cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
785                                                 dev->_line_size_ch2);
786         if (err < 0) {
787                 pr_err("%s: Failed to set up Video upstream buffers!\n",
788                        dev->name);
789                 goto error;
790         }
791
792         cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
793
794         return 0;
795
796 error:
797         cx25821_dev_unregister(dev);
798
799         return err;
800 }