[media] cx25821: make cx25821_sram_channels const
[sfrench/cifs-2.6.git] / drivers / media / pci / cx25821 / cx25821-core.c
1 /*
2  *  Driver for the Conexant CX25821 PCIe bridge
3  *
4  *  Copyright (C) 2009 Conexant Systems Inc.
5  *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6  *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation; either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *
17  *  GNU General Public License for more details.
18  *
19  *  You should have received a copy of the GNU General Public License
20  *  along with this program; if not, write to the Free Software
21  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/i2c.h>
27 #include <linux/slab.h>
28 #include "cx25821.h"
29 #include "cx25821-sram.h"
30 #include "cx25821-video.h"
31
32 MODULE_DESCRIPTION("Driver for Athena cards");
33 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
34 MODULE_LICENSE("GPL");
35
36 static unsigned int debug;
37 module_param(debug, int, 0644);
38 MODULE_PARM_DESC(debug, "enable debug messages");
39
40 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
41 module_param_array(card, int, NULL, 0444);
42 MODULE_PARM_DESC(card, "card type");
43
44 static unsigned int cx25821_devcount;
45
46 DEFINE_MUTEX(cx25821_devlist_mutex);
47 EXPORT_SYMBOL(cx25821_devlist_mutex);
48 LIST_HEAD(cx25821_devlist);
49 EXPORT_SYMBOL(cx25821_devlist);
50
51 const struct sram_channel cx25821_sram_channels[] = {
52         [SRAM_CH00] = {
53                 .i = SRAM_CH00,
54                 .name = "VID A",
55                 .cmds_start = VID_A_DOWN_CMDS,
56                 .ctrl_start = VID_A_IQ,
57                 .cdt = VID_A_CDT,
58                 .fifo_start = VID_A_DOWN_CLUSTER_1,
59                 .fifo_size = (VID_CLUSTER_SIZE << 2),
60                 .ptr1_reg = DMA1_PTR1,
61                 .ptr2_reg = DMA1_PTR2,
62                 .cnt1_reg = DMA1_CNT1,
63                 .cnt2_reg = DMA1_CNT2,
64                 .int_msk = VID_A_INT_MSK,
65                 .int_stat = VID_A_INT_STAT,
66                 .int_mstat = VID_A_INT_MSTAT,
67                 .dma_ctl = VID_DST_A_DMA_CTL,
68                 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
69                 .gpcnt = VID_DST_A_GPCNT,
70                 .vip_ctl = VID_DST_A_VIP_CTL,
71                 .pix_frmt = VID_DST_A_PIX_FRMT,
72         },
73
74         [SRAM_CH01] = {
75                 .i = SRAM_CH01,
76                 .name = "VID B",
77                 .cmds_start = VID_B_DOWN_CMDS,
78                 .ctrl_start = VID_B_IQ,
79                 .cdt = VID_B_CDT,
80                 .fifo_start = VID_B_DOWN_CLUSTER_1,
81                 .fifo_size = (VID_CLUSTER_SIZE << 2),
82                 .ptr1_reg = DMA2_PTR1,
83                 .ptr2_reg = DMA2_PTR2,
84                 .cnt1_reg = DMA2_CNT1,
85                 .cnt2_reg = DMA2_CNT2,
86                 .int_msk = VID_B_INT_MSK,
87                 .int_stat = VID_B_INT_STAT,
88                 .int_mstat = VID_B_INT_MSTAT,
89                 .dma_ctl = VID_DST_B_DMA_CTL,
90                 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
91                 .gpcnt = VID_DST_B_GPCNT,
92                 .vip_ctl = VID_DST_B_VIP_CTL,
93                 .pix_frmt = VID_DST_B_PIX_FRMT,
94         },
95
96         [SRAM_CH02] = {
97                 .i = SRAM_CH02,
98                 .name = "VID C",
99                 .cmds_start = VID_C_DOWN_CMDS,
100                 .ctrl_start = VID_C_IQ,
101                 .cdt = VID_C_CDT,
102                 .fifo_start = VID_C_DOWN_CLUSTER_1,
103                 .fifo_size = (VID_CLUSTER_SIZE << 2),
104                 .ptr1_reg = DMA3_PTR1,
105                 .ptr2_reg = DMA3_PTR2,
106                 .cnt1_reg = DMA3_CNT1,
107                 .cnt2_reg = DMA3_CNT2,
108                 .int_msk = VID_C_INT_MSK,
109                 .int_stat = VID_C_INT_STAT,
110                 .int_mstat = VID_C_INT_MSTAT,
111                 .dma_ctl = VID_DST_C_DMA_CTL,
112                 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
113                 .gpcnt = VID_DST_C_GPCNT,
114                 .vip_ctl = VID_DST_C_VIP_CTL,
115                 .pix_frmt = VID_DST_C_PIX_FRMT,
116         },
117
118         [SRAM_CH03] = {
119                 .i = SRAM_CH03,
120                 .name = "VID D",
121                 .cmds_start = VID_D_DOWN_CMDS,
122                 .ctrl_start = VID_D_IQ,
123                 .cdt = VID_D_CDT,
124                 .fifo_start = VID_D_DOWN_CLUSTER_1,
125                 .fifo_size = (VID_CLUSTER_SIZE << 2),
126                 .ptr1_reg = DMA4_PTR1,
127                 .ptr2_reg = DMA4_PTR2,
128                 .cnt1_reg = DMA4_CNT1,
129                 .cnt2_reg = DMA4_CNT2,
130                 .int_msk = VID_D_INT_MSK,
131                 .int_stat = VID_D_INT_STAT,
132                 .int_mstat = VID_D_INT_MSTAT,
133                 .dma_ctl = VID_DST_D_DMA_CTL,
134                 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
135                 .gpcnt = VID_DST_D_GPCNT,
136                 .vip_ctl = VID_DST_D_VIP_CTL,
137                 .pix_frmt = VID_DST_D_PIX_FRMT,
138         },
139
140         [SRAM_CH04] = {
141                 .i = SRAM_CH04,
142                 .name = "VID E",
143                 .cmds_start = VID_E_DOWN_CMDS,
144                 .ctrl_start = VID_E_IQ,
145                 .cdt = VID_E_CDT,
146                 .fifo_start = VID_E_DOWN_CLUSTER_1,
147                 .fifo_size = (VID_CLUSTER_SIZE << 2),
148                 .ptr1_reg = DMA5_PTR1,
149                 .ptr2_reg = DMA5_PTR2,
150                 .cnt1_reg = DMA5_CNT1,
151                 .cnt2_reg = DMA5_CNT2,
152                 .int_msk = VID_E_INT_MSK,
153                 .int_stat = VID_E_INT_STAT,
154                 .int_mstat = VID_E_INT_MSTAT,
155                 .dma_ctl = VID_DST_E_DMA_CTL,
156                 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
157                 .gpcnt = VID_DST_E_GPCNT,
158                 .vip_ctl = VID_DST_E_VIP_CTL,
159                 .pix_frmt = VID_DST_E_PIX_FRMT,
160         },
161
162         [SRAM_CH05] = {
163                 .i = SRAM_CH05,
164                 .name = "VID F",
165                 .cmds_start = VID_F_DOWN_CMDS,
166                 .ctrl_start = VID_F_IQ,
167                 .cdt = VID_F_CDT,
168                 .fifo_start = VID_F_DOWN_CLUSTER_1,
169                 .fifo_size = (VID_CLUSTER_SIZE << 2),
170                 .ptr1_reg = DMA6_PTR1,
171                 .ptr2_reg = DMA6_PTR2,
172                 .cnt1_reg = DMA6_CNT1,
173                 .cnt2_reg = DMA6_CNT2,
174                 .int_msk = VID_F_INT_MSK,
175                 .int_stat = VID_F_INT_STAT,
176                 .int_mstat = VID_F_INT_MSTAT,
177                 .dma_ctl = VID_DST_F_DMA_CTL,
178                 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
179                 .gpcnt = VID_DST_F_GPCNT,
180                 .vip_ctl = VID_DST_F_VIP_CTL,
181                 .pix_frmt = VID_DST_F_PIX_FRMT,
182         },
183
184         [SRAM_CH06] = {
185                 .i = SRAM_CH06,
186                 .name = "VID G",
187                 .cmds_start = VID_G_DOWN_CMDS,
188                 .ctrl_start = VID_G_IQ,
189                 .cdt = VID_G_CDT,
190                 .fifo_start = VID_G_DOWN_CLUSTER_1,
191                 .fifo_size = (VID_CLUSTER_SIZE << 2),
192                 .ptr1_reg = DMA7_PTR1,
193                 .ptr2_reg = DMA7_PTR2,
194                 .cnt1_reg = DMA7_CNT1,
195                 .cnt2_reg = DMA7_CNT2,
196                 .int_msk = VID_G_INT_MSK,
197                 .int_stat = VID_G_INT_STAT,
198                 .int_mstat = VID_G_INT_MSTAT,
199                 .dma_ctl = VID_DST_G_DMA_CTL,
200                 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
201                 .gpcnt = VID_DST_G_GPCNT,
202                 .vip_ctl = VID_DST_G_VIP_CTL,
203                 .pix_frmt = VID_DST_G_PIX_FRMT,
204         },
205
206         [SRAM_CH07] = {
207                 .i = SRAM_CH07,
208                 .name = "VID H",
209                 .cmds_start = VID_H_DOWN_CMDS,
210                 .ctrl_start = VID_H_IQ,
211                 .cdt = VID_H_CDT,
212                 .fifo_start = VID_H_DOWN_CLUSTER_1,
213                 .fifo_size = (VID_CLUSTER_SIZE << 2),
214                 .ptr1_reg = DMA8_PTR1,
215                 .ptr2_reg = DMA8_PTR2,
216                 .cnt1_reg = DMA8_CNT1,
217                 .cnt2_reg = DMA8_CNT2,
218                 .int_msk = VID_H_INT_MSK,
219                 .int_stat = VID_H_INT_STAT,
220                 .int_mstat = VID_H_INT_MSTAT,
221                 .dma_ctl = VID_DST_H_DMA_CTL,
222                 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
223                 .gpcnt = VID_DST_H_GPCNT,
224                 .vip_ctl = VID_DST_H_VIP_CTL,
225                 .pix_frmt = VID_DST_H_PIX_FRMT,
226         },
227
228         [SRAM_CH08] = {
229                 .name = "audio from",
230                 .cmds_start = AUD_A_DOWN_CMDS,
231                 .ctrl_start = AUD_A_IQ,
232                 .cdt = AUD_A_CDT,
233                 .fifo_start = AUD_A_DOWN_CLUSTER_1,
234                 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
235                 .ptr1_reg = DMA17_PTR1,
236                 .ptr2_reg = DMA17_PTR2,
237                 .cnt1_reg = DMA17_CNT1,
238                 .cnt2_reg = DMA17_CNT2,
239         },
240
241         [SRAM_CH09] = {
242                 .i = SRAM_CH09,
243                 .name = "VID Upstream I",
244                 .cmds_start = VID_I_UP_CMDS,
245                 .ctrl_start = VID_I_IQ,
246                 .cdt = VID_I_CDT,
247                 .fifo_start = VID_I_UP_CLUSTER_1,
248                 .fifo_size = (VID_CLUSTER_SIZE << 2),
249                 .ptr1_reg = DMA15_PTR1,
250                 .ptr2_reg = DMA15_PTR2,
251                 .cnt1_reg = DMA15_CNT1,
252                 .cnt2_reg = DMA15_CNT2,
253                 .int_msk = VID_I_INT_MSK,
254                 .int_stat = VID_I_INT_STAT,
255                 .int_mstat = VID_I_INT_MSTAT,
256                 .dma_ctl = VID_SRC_I_DMA_CTL,
257                 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
258                 .gpcnt = VID_SRC_I_GPCNT,
259
260                 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
261                 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
262                 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
263                 .vid_cdt_size = VID_SRC_I_CDT_SZ,
264                 .irq_bit = 8,
265         },
266
267         [SRAM_CH10] = {
268                 .i = SRAM_CH10,
269                 .name = "VID Upstream J",
270                 .cmds_start = VID_J_UP_CMDS,
271                 .ctrl_start = VID_J_IQ,
272                 .cdt = VID_J_CDT,
273                 .fifo_start = VID_J_UP_CLUSTER_1,
274                 .fifo_size = (VID_CLUSTER_SIZE << 2),
275                 .ptr1_reg = DMA16_PTR1,
276                 .ptr2_reg = DMA16_PTR2,
277                 .cnt1_reg = DMA16_CNT1,
278                 .cnt2_reg = DMA16_CNT2,
279                 .int_msk = VID_J_INT_MSK,
280                 .int_stat = VID_J_INT_STAT,
281                 .int_mstat = VID_J_INT_MSTAT,
282                 .dma_ctl = VID_SRC_J_DMA_CTL,
283                 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
284                 .gpcnt = VID_SRC_J_GPCNT,
285
286                 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
287                 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
288                 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
289                 .vid_cdt_size = VID_SRC_J_CDT_SZ,
290                 .irq_bit = 9,
291         },
292
293         [SRAM_CH11] = {
294                 .i = SRAM_CH11,
295                 .name = "Audio Upstream Channel B",
296                 .cmds_start = AUD_B_UP_CMDS,
297                 .ctrl_start = AUD_B_IQ,
298                 .cdt = AUD_B_CDT,
299                 .fifo_start = AUD_B_UP_CLUSTER_1,
300                 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
301                 .ptr1_reg = DMA22_PTR1,
302                 .ptr2_reg = DMA22_PTR2,
303                 .cnt1_reg = DMA22_CNT1,
304                 .cnt2_reg = DMA22_CNT2,
305                 .int_msk = AUD_B_INT_MSK,
306                 .int_stat = AUD_B_INT_STAT,
307                 .int_mstat = AUD_B_INT_MSTAT,
308                 .dma_ctl = AUD_INT_DMA_CTL,
309                 .gpcnt_ctl = AUD_B_GPCNT_CTL,
310                 .gpcnt = AUD_B_GPCNT,
311                 .aud_length = AUD_B_LNGTH,
312                 .aud_cfg = AUD_B_CFG,
313                 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
314                 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
315                 .irq_bit = 11,
316         },
317 };
318 EXPORT_SYMBOL(cx25821_sram_channels);
319
320 static int cx25821_risc_decode(u32 risc)
321 {
322         static const char * const instr[16] = {
323                 [RISC_SYNC >> 28] = "sync",
324                 [RISC_WRITE >> 28] = "write",
325                 [RISC_WRITEC >> 28] = "writec",
326                 [RISC_READ >> 28] = "read",
327                 [RISC_READC >> 28] = "readc",
328                 [RISC_JUMP >> 28] = "jump",
329                 [RISC_SKIP >> 28] = "skip",
330                 [RISC_WRITERM >> 28] = "writerm",
331                 [RISC_WRITECM >> 28] = "writecm",
332                 [RISC_WRITECR >> 28] = "writecr",
333         };
334         static const int incr[16] = {
335                 [RISC_WRITE >> 28] = 3,
336                 [RISC_JUMP >> 28] = 3,
337                 [RISC_SKIP >> 28] = 1,
338                 [RISC_SYNC >> 28] = 1,
339                 [RISC_WRITERM >> 28] = 3,
340                 [RISC_WRITECM >> 28] = 3,
341                 [RISC_WRITECR >> 28] = 4,
342         };
343         static const char * const bits[] = {
344                 "12", "13", "14", "resync",
345                 "cnt0", "cnt1", "18", "19",
346                 "20", "21", "22", "23",
347                 "irq1", "irq2", "eol", "sol",
348         };
349         int i;
350
351         pr_cont("0x%08x [ %s",
352                 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
353         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
354                 if (risc & (1 << (i + 12)))
355                         pr_cont(" %s", bits[i]);
356         }
357         pr_cont(" count=%d ]\n", risc & 0xfff);
358         return incr[risc >> 28] ? incr[risc >> 28] : 1;
359 }
360
361 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
362 {
363         struct cx25821_i2c *bus = i2c_adap->algo_data;
364         struct cx25821_dev *dev = bus->dev;
365         return cx_read(bus->reg_stat) & 0x01;
366 }
367
368 static void cx25821_registers_init(struct cx25821_dev *dev)
369 {
370         u32 tmp;
371
372         /* enable RUN_RISC in Pecos */
373         cx_write(DEV_CNTRL2, 0x20);
374
375         /* Set the master PCI interrupt masks to enable video, audio, MBIF,
376          * and GPIO interrupts
377          * I2C interrupt masking is handled by the I2C objects themselves. */
378         cx_write(PCI_INT_MSK, 0x2001FFFF);
379
380         tmp = cx_read(RDR_TLCTL0);
381         tmp &= ~FLD_CFG_RCB_CK_EN;      /* Clear the RCB_CK_EN bit */
382         cx_write(RDR_TLCTL0, tmp);
383
384         /* PLL-A setting for the Audio Master Clock */
385         cx_write(PLL_A_INT_FRAC, 0x9807A58B);
386
387         /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
388         cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
389
390         /* clear reset bit [31] */
391         tmp = cx_read(PLL_A_INT_FRAC);
392         cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
393
394         /* PLL-B setting for Mobilygen Host Bus Interface */
395         cx_write(PLL_B_INT_FRAC, 0x9883A86F);
396
397         /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
398         cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
399
400         /* clear reset bit [31] */
401         tmp = cx_read(PLL_B_INT_FRAC);
402         cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
403
404         /* PLL-C setting for video upstream channel */
405         cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
406
407         /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
408         cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
409
410         /* clear reset bit [31] */
411         tmp = cx_read(PLL_C_INT_FRAC);
412         cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
413
414         /* PLL-D setting for audio upstream channel */
415         cx_write(PLL_D_INT_FRAC, 0x98757F5B);
416
417         /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
418         cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
419
420         /* clear reset bit [31] */
421         tmp = cx_read(PLL_D_INT_FRAC);
422         cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
423
424         /* This selects the PLL C clock source for the video upstream channel
425          * I and J */
426         tmp = cx_read(VID_CH_CLK_SEL);
427         cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
428
429         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
430          * channel A-C
431          * select 656/VIP DST for downstream Channel A - C */
432         tmp = cx_read(VID_CH_MODE_SEL);
433         /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
434         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
435
436         /* enables 656 port I and J as output */
437         tmp = cx_read(CLK_RST);
438         /* use external ALT_PLL_REF pin as its reference clock instead */
439         tmp |= FLD_USE_ALT_PLL_REF;
440         cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
441
442         mdelay(100);
443 }
444
445 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
446                                const struct sram_channel *ch,
447                                unsigned int bpl, u32 risc)
448 {
449         unsigned int i, lines;
450         u32 cdt;
451
452         if (ch->cmds_start == 0) {
453                 cx_write(ch->ptr1_reg, 0);
454                 cx_write(ch->ptr2_reg, 0);
455                 cx_write(ch->cnt2_reg, 0);
456                 cx_write(ch->cnt1_reg, 0);
457                 return 0;
458         }
459
460         bpl = (bpl + 7) & ~7;   /* alignment */
461         cdt = ch->cdt;
462         lines = ch->fifo_size / bpl;
463
464         if (lines > 4)
465                 lines = 4;
466
467         BUG_ON(lines < 2);
468
469         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
470         cx_write(8 + 4, 8);
471         cx_write(8 + 8, 0);
472
473         /* write CDT */
474         for (i = 0; i < lines; i++) {
475                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
476                 cx_write(cdt + 16 * i + 4, 0);
477                 cx_write(cdt + 16 * i + 8, 0);
478                 cx_write(cdt + 16 * i + 12, 0);
479         }
480
481         /* init the first cdt buffer */
482         for (i = 0; i < 128; i++)
483                 cx_write(ch->fifo_start + 4 * i, i);
484
485         /* write CMDS */
486         if (ch->jumponly)
487                 cx_write(ch->cmds_start + 0, 8);
488         else
489                 cx_write(ch->cmds_start + 0, risc);
490
491         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
492         cx_write(ch->cmds_start + 8, cdt);
493         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
494         cx_write(ch->cmds_start + 16, ch->ctrl_start);
495
496         if (ch->jumponly)
497                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
498         else
499                 cx_write(ch->cmds_start + 20, 64 >> 2);
500
501         for (i = 24; i < 80; i += 4)
502                 cx_write(ch->cmds_start + i, 0);
503
504         /* fill registers */
505         cx_write(ch->ptr1_reg, ch->fifo_start);
506         cx_write(ch->ptr2_reg, cdt);
507         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
508         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
509
510         return 0;
511 }
512
513 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
514                                      const struct sram_channel *ch,
515                                      unsigned int bpl, u32 risc)
516 {
517         unsigned int i, lines;
518         u32 cdt;
519
520         if (ch->cmds_start == 0) {
521                 cx_write(ch->ptr1_reg, 0);
522                 cx_write(ch->ptr2_reg, 0);
523                 cx_write(ch->cnt2_reg, 0);
524                 cx_write(ch->cnt1_reg, 0);
525                 return 0;
526         }
527
528         bpl = (bpl + 7) & ~7;   /* alignment */
529         cdt = ch->cdt;
530         lines = ch->fifo_size / bpl;
531
532         if (lines > 3)
533                 lines = 3;      /* for AUDIO */
534
535         BUG_ON(lines < 2);
536
537         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
538         cx_write(8 + 4, 8);
539         cx_write(8 + 8, 0);
540
541         /* write CDT */
542         for (i = 0; i < lines; i++) {
543                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
544                 cx_write(cdt + 16 * i + 4, 0);
545                 cx_write(cdt + 16 * i + 8, 0);
546                 cx_write(cdt + 16 * i + 12, 0);
547         }
548
549         /* write CMDS */
550         if (ch->jumponly)
551                 cx_write(ch->cmds_start + 0, 8);
552         else
553                 cx_write(ch->cmds_start + 0, risc);
554
555         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
556         cx_write(ch->cmds_start + 8, cdt);
557         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
558         cx_write(ch->cmds_start + 16, ch->ctrl_start);
559
560         /* IQ size */
561         if (ch->jumponly)
562                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
563         else
564                 cx_write(ch->cmds_start + 20, 64 >> 2);
565
566         /* zero out */
567         for (i = 24; i < 80; i += 4)
568                 cx_write(ch->cmds_start + i, 0);
569
570         /* fill registers */
571         cx_write(ch->ptr1_reg, ch->fifo_start);
572         cx_write(ch->ptr2_reg, cdt);
573         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
574         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
575
576         return 0;
577 }
578 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
579
580 void cx25821_sram_channel_dump(struct cx25821_dev *dev, const struct sram_channel *ch)
581 {
582         static char *name[] = {
583                 "init risc lo",
584                 "init risc hi",
585                 "cdt base",
586                 "cdt size",
587                 "iq base",
588                 "iq size",
589                 "risc pc lo",
590                 "risc pc hi",
591                 "iq wr ptr",
592                 "iq rd ptr",
593                 "cdt current",
594                 "pci target lo",
595                 "pci target hi",
596                 "line / byte",
597         };
598         u32 risc;
599         unsigned int i, j, n;
600
601         pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
602         for (i = 0; i < ARRAY_SIZE(name); i++)
603                 pr_warn("cmds + 0x%2x:   %-15s: 0x%08x\n",
604                         i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
605
606         j = i * 4;
607         for (i = 0; i < 4;) {
608                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
609                 pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
610                 i += cx25821_risc_decode(risc);
611         }
612
613         for (i = 0; i < (64 >> 2); i += n) {
614                 risc = cx_read(ch->ctrl_start + 4 * i);
615                 /* No consideration for bits 63-32 */
616
617                 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
618                         i * 4, ch->ctrl_start + 4 * i, i);
619                 n = cx25821_risc_decode(risc);
620                 for (j = 1; j < n; j++) {
621                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
622                         pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
623                                 4 * (i + j), i + j, risc, j);
624                 }
625         }
626
627         pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
628                 ch->fifo_start, ch->fifo_start + ch->fifo_size);
629         pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
630                 ch->ctrl_start, ch->ctrl_start + 6 * 16);
631         pr_warn("        :   ptr1_reg: 0x%08x\n",
632                 cx_read(ch->ptr1_reg));
633         pr_warn("        :   ptr2_reg: 0x%08x\n",
634                 cx_read(ch->ptr2_reg));
635         pr_warn("        :   cnt1_reg: 0x%08x\n",
636                 cx_read(ch->cnt1_reg));
637         pr_warn("        :   cnt2_reg: 0x%08x\n",
638                 cx_read(ch->cnt2_reg));
639 }
640
641 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
642                                      const struct sram_channel *ch)
643 {
644         static const char * const name[] = {
645                 "init risc lo",
646                 "init risc hi",
647                 "cdt base",
648                 "cdt size",
649                 "iq base",
650                 "iq size",
651                 "risc pc lo",
652                 "risc pc hi",
653                 "iq wr ptr",
654                 "iq rd ptr",
655                 "cdt current",
656                 "pci target lo",
657                 "pci target hi",
658                 "line / byte",
659         };
660
661         u32 risc, value, tmp;
662         unsigned int i, j, n;
663
664         pr_info("\n%s: %s - dma Audio channel status dump\n",
665                 dev->name, ch->name);
666
667         for (i = 0; i < ARRAY_SIZE(name); i++)
668                 pr_info("%s: cmds + 0x%2x:   %-15s: 0x%08x\n",
669                         dev->name, i * 4, name[i],
670                         cx_read(ch->cmds_start + 4 * i));
671
672         j = i * 4;
673         for (i = 0; i < 4;) {
674                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
675                 pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
676                 i += cx25821_risc_decode(risc);
677         }
678
679         for (i = 0; i < (64 >> 2); i += n) {
680                 risc = cx_read(ch->ctrl_start + 4 * i);
681                 /* No consideration for bits 63-32 */
682
683                 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
684                         i * 4, ch->ctrl_start + 4 * i, i);
685                 n = cx25821_risc_decode(risc);
686
687                 for (j = 1; j < n; j++) {
688                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
689                         pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
690                                 4 * (i + j), i + j, risc, j);
691                 }
692         }
693
694         pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
695                 ch->fifo_start, ch->fifo_start + ch->fifo_size);
696         pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
697                 ch->ctrl_start, ch->ctrl_start + 6 * 16);
698         pr_warn("        :   ptr1_reg: 0x%08x\n",
699                 cx_read(ch->ptr1_reg));
700         pr_warn("        :   ptr2_reg: 0x%08x\n",
701                 cx_read(ch->ptr2_reg));
702         pr_warn("        :   cnt1_reg: 0x%08x\n",
703                 cx_read(ch->cnt1_reg));
704         pr_warn("        :   cnt2_reg: 0x%08x\n",
705                 cx_read(ch->cnt2_reg));
706
707         for (i = 0; i < 4; i++) {
708                 risc = cx_read(ch->cmds_start + 56 + (i * 4));
709                 pr_warn("instruction %d = 0x%x\n", i, risc);
710         }
711
712         /* read data from the first cdt buffer */
713         risc = cx_read(AUD_A_CDT);
714         pr_warn("\nread cdt loc=0x%x\n", risc);
715         for (i = 0; i < 8; i++) {
716                 n = cx_read(risc + i * 4);
717                 pr_cont("0x%x ", n);
718         }
719         pr_cont("\n\n");
720
721         value = cx_read(CLK_RST);
722         CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
723
724         value = cx_read(PLL_A_POST_STAT_BIST);
725         CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
726         value = cx_read(PLL_A_INT_FRAC);
727         CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
728
729         value = cx_read(PLL_B_POST_STAT_BIST);
730         CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
731         value = cx_read(PLL_B_INT_FRAC);
732         CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
733
734         value = cx_read(PLL_C_POST_STAT_BIST);
735         CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
736         value = cx_read(PLL_C_INT_FRAC);
737         CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
738
739         value = cx_read(PLL_D_POST_STAT_BIST);
740         CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
741         value = cx_read(PLL_D_INT_FRAC);
742         CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
743
744         value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
745         CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
746 }
747 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
748
749 static void cx25821_shutdown(struct cx25821_dev *dev)
750 {
751         int i;
752
753         /* disable RISC controller */
754         cx_write(DEV_CNTRL2, 0);
755
756         /* Disable Video A/B activity */
757         for (i = 0; i < VID_CHANNEL_NUM; i++) {
758                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
759                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
760         }
761
762         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
763                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
764                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
765                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
766         }
767
768         /* Disable Audio activity */
769         cx_write(AUD_INT_DMA_CTL, 0);
770
771         /* Disable Serial port */
772         cx_write(UART_CTL, 0);
773
774         /* Disable Interrupts */
775         cx_write(PCI_INT_MSK, 0);
776         cx_write(AUD_A_INT_MSK, 0);
777 }
778
779 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
780                               u32 format)
781 {
782         if (channel_select <= 7 && channel_select >= 0) {
783                 cx_write(dev->channels[channel_select].sram_channels->pix_frmt,
784                                 format);
785                 dev->channels[channel_select].pixel_formats = format;
786         }
787 }
788
789 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
790                                  const struct sram_channel *ch)
791 {
792         cx_write(ch->pix_frmt, PIXEL_FRMT_422);
793         cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
794 }
795
796 static void cx25821_initialize(struct cx25821_dev *dev)
797 {
798         int i;
799
800         dprintk(1, "%s()\n", __func__);
801
802         cx25821_shutdown(dev);
803         cx_write(PCI_INT_STAT, 0xffffffff);
804
805         for (i = 0; i < VID_CHANNEL_NUM; i++)
806                 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
807
808         cx_write(AUD_A_INT_STAT, 0xffffffff);
809         cx_write(AUD_B_INT_STAT, 0xffffffff);
810         cx_write(AUD_C_INT_STAT, 0xffffffff);
811         cx_write(AUD_D_INT_STAT, 0xffffffff);
812         cx_write(AUD_E_INT_STAT, 0xffffffff);
813
814         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
815         cx_write(PAD_CTRL, 0x12);       /* for I2C */
816         cx25821_registers_init(dev);    /* init Pecos registers */
817         mdelay(100);
818
819         for (i = 0; i < VID_CHANNEL_NUM; i++) {
820                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
821                 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
822                                                 1440, 0);
823                 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
824                 dev->channels[i].use_cif_resolution = FALSE;
825         }
826
827         /* Probably only affect Downstream */
828         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
829                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
830                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
831         }
832
833         cx25821_sram_channel_setup_audio(dev,
834                         dev->channels[SRAM_CH08].sram_channels, 128, 0);
835
836         cx25821_gpio_init(dev);
837 }
838
839 static int cx25821_get_resources(struct cx25821_dev *dev)
840 {
841         if (request_mem_region(pci_resource_start(dev->pci, 0),
842                                 pci_resource_len(dev->pci, 0), dev->name))
843                 return 0;
844
845         pr_err("%s: can't get MMIO memory @ 0x%llx\n",
846                 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
847
848         return -EBUSY;
849 }
850
851 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
852 {
853         dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
854
855         pr_info("%s(): Hardware revision = 0x%02x\n",
856                 __func__, dev->hwrevision);
857 }
858
859 static void cx25821_iounmap(struct cx25821_dev *dev)
860 {
861         if (dev == NULL)
862                 return;
863
864         /* Releasing IO memory */
865         if (dev->lmmio != NULL) {
866                 CX25821_INFO("Releasing lmmio.\n");
867                 iounmap(dev->lmmio);
868                 dev->lmmio = NULL;
869         }
870 }
871
872 static int cx25821_dev_setup(struct cx25821_dev *dev)
873 {
874         int i;
875
876         pr_info("\n***********************************\n");
877         pr_info("cx25821 set up\n");
878         pr_info("***********************************\n\n");
879
880         mutex_init(&dev->lock);
881
882         atomic_inc(&dev->refcount);
883
884         dev->nr = ++cx25821_devcount;
885         sprintf(dev->name, "cx25821[%d]", dev->nr);
886
887         mutex_lock(&cx25821_devlist_mutex);
888         list_add_tail(&dev->devlist, &cx25821_devlist);
889         mutex_unlock(&cx25821_devlist_mutex);
890
891         if (dev->pci->device != 0x8210) {
892                 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
893                         __func__, dev->pci->device);
894                 return -1;
895         } else {
896                 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
897         }
898
899         /* Apply a sensible clock frequency for the PCIe bridge */
900         dev->clk_freq = 28000000;
901         for (i = 0; i < MAX_VID_CHANNEL_NUM; i++)
902                 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
903
904         if (dev->nr > 1)
905                 CX25821_INFO("dev->nr > 1!");
906
907         /* board config */
908         dev->board = 1;         /* card[dev->nr]; */
909         dev->_max_num_decoders = MAX_DECODERS;
910
911         dev->pci_bus = dev->pci->bus->number;
912         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
913         dev->pci_irqmask = 0x001f00;
914
915         /* External Master 1 Bus */
916         dev->i2c_bus[0].nr = 0;
917         dev->i2c_bus[0].dev = dev;
918         dev->i2c_bus[0].reg_stat = I2C1_STAT;
919         dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
920         dev->i2c_bus[0].reg_addr = I2C1_ADDR;
921         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
922         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
923         dev->i2c_bus[0].i2c_period = (0x07 << 24);      /* 1.95MHz */
924
925         if (cx25821_get_resources(dev) < 0) {
926                 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
927                        dev->name, dev->pci->subsystem_vendor,
928                        dev->pci->subsystem_device);
929
930                 cx25821_devcount--;
931                 return -EBUSY;
932         }
933
934         /* PCIe stuff */
935         dev->base_io_addr = pci_resource_start(dev->pci, 0);
936
937         if (!dev->base_io_addr) {
938                 CX25821_ERR("No PCI Memory resources, exiting!\n");
939                 return -ENODEV;
940         }
941
942         dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
943
944         if (!dev->lmmio) {
945                 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
946                 cx25821_iounmap(dev);
947                 return -ENOMEM;
948         }
949
950         dev->bmmio = (u8 __iomem *) dev->lmmio;
951
952         pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
953                 dev->name, dev->pci->subsystem_vendor,
954                 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
955                 dev->board, card[dev->nr] == dev->board ?
956                 "insmod option" : "autodetected");
957
958         /* init hardware */
959         cx25821_initialize(dev);
960
961         cx25821_i2c_register(&dev->i2c_bus[0]);
962 /*  cx25821_i2c_register(&dev->i2c_bus[1]);
963  *  cx25821_i2c_register(&dev->i2c_bus[2]); */
964
965         CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
966                         dev->i2c_bus[0].i2c_rc);
967
968         cx25821_card_setup(dev);
969
970         if (medusa_video_init(dev) < 0)
971                 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
972
973         cx25821_video_register(dev);
974
975         cx25821_dev_checkrevision(dev);
976         CX25821_INFO("setup done!\n");
977
978         return 0;
979 }
980
981 void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
982                                       struct upstream_user_struct *up_data)
983 {
984         dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
985
986         dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
987         medusa_set_videostandard(dev);
988
989         cx25821_vidupstream_init_ch1(dev, dev->channel_select,
990                                      dev->pixel_format);
991 }
992
993 void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
994                                       struct upstream_user_struct *up_data)
995 {
996         dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
997
998         dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
999         medusa_set_videostandard(dev);
1000
1001         cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1002                                      dev->pixel_format_ch2);
1003 }
1004
1005 void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1006                                   struct upstream_user_struct *up_data)
1007 {
1008         cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1009 }
1010
1011 void cx25821_dev_unregister(struct cx25821_dev *dev)
1012 {
1013         int i;
1014
1015         if (!dev->base_io_addr)
1016                 return;
1017
1018         cx25821_free_mem_upstream_ch1(dev);
1019         cx25821_free_mem_upstream_ch2(dev);
1020         cx25821_free_mem_upstream_audio(dev);
1021
1022         release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1023
1024         if (!atomic_dec_and_test(&dev->refcount))
1025                 return;
1026
1027         for (i = 0; i < MAX_VID_CHANNEL_NUM - 1; i++) {
1028                 if (i == SRAM_CH08) /* audio channel */
1029                         continue;
1030                 cx25821_video_unregister(dev, i);
1031         }
1032
1033         cx25821_i2c_unregister(&dev->i2c_bus[0]);
1034         cx25821_iounmap(dev);
1035 }
1036 EXPORT_SYMBOL(cx25821_dev_unregister);
1037
1038 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1039                                   unsigned int offset, u32 sync_line,
1040                                   unsigned int bpl, unsigned int padding,
1041                                   unsigned int lines)
1042 {
1043         struct scatterlist *sg;
1044         unsigned int line, todo;
1045
1046         /* sync instruction */
1047         if (sync_line != NO_SYNC_LINE)
1048                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1049
1050         /* scan lines */
1051         sg = sglist;
1052         for (line = 0; line < lines; line++) {
1053                 while (offset && offset >= sg_dma_len(sg)) {
1054                         offset -= sg_dma_len(sg);
1055                         sg++;
1056                 }
1057                 if (bpl <= sg_dma_len(sg) - offset) {
1058                         /* fits into current chunk */
1059                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL |
1060                                         bpl);
1061                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1062                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1063                         offset += bpl;
1064                 } else {
1065                         /* scanline needs to be split */
1066                         todo = bpl;
1067                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL |
1068                                         (sg_dma_len(sg) - offset));
1069                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1070                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1071                         todo -= (sg_dma_len(sg) - offset);
1072                         offset = 0;
1073                         sg++;
1074                         while (todo > sg_dma_len(sg)) {
1075                                 *(rp++) = cpu_to_le32(RISC_WRITE |
1076                                                 sg_dma_len(sg));
1077                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1078                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1079                                 todo -= sg_dma_len(sg);
1080                                 sg++;
1081                         }
1082                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1083                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1084                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1085                         offset += todo;
1086                 }
1087
1088                 offset += padding;
1089         }
1090
1091         return rp;
1092 }
1093
1094 int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1095                         struct scatterlist *sglist, unsigned int top_offset,
1096                         unsigned int bottom_offset, unsigned int bpl,
1097                         unsigned int padding, unsigned int lines)
1098 {
1099         u32 instructions;
1100         u32 fields;
1101         __le32 *rp;
1102         int rc;
1103
1104         fields = 0;
1105         if (UNSET != top_offset)
1106                 fields++;
1107         if (UNSET != bottom_offset)
1108                 fields++;
1109
1110         /* estimate risc mem: worst case is one write per page border +
1111            one write per scan line + syncs + jump (all 2 dwords).  Padding
1112            can cause next bpl to start close to a page border.  First DMA
1113            region may be smaller than PAGE_SIZE */
1114         /* write and jump need and extra dword */
1115         instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE +
1116                         lines);
1117         instructions += 2;
1118         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1119
1120         if (rc < 0)
1121                 return rc;
1122
1123         /* write risc instructions */
1124         rp = risc->cpu;
1125
1126         if (UNSET != top_offset) {
1127                 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1128                                         lines);
1129         }
1130
1131         if (UNSET != bottom_offset) {
1132                 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1133                                         padding, lines);
1134         }
1135
1136         /* save pointer to jmp instruction address */
1137         risc->jmp = rp;
1138         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1139
1140         return 0;
1141 }
1142
1143 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1144                                         unsigned int offset, u32 sync_line,
1145                                         unsigned int bpl, unsigned int padding,
1146                                         unsigned int lines, unsigned int lpi)
1147 {
1148         struct scatterlist *sg;
1149         unsigned int line, todo, sol;
1150
1151         /* sync instruction */
1152         if (sync_line != NO_SYNC_LINE)
1153                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1154
1155         /* scan lines */
1156         sg = sglist;
1157         for (line = 0; line < lines; line++) {
1158                 while (offset && offset >= sg_dma_len(sg)) {
1159                         offset -= sg_dma_len(sg);
1160                         sg++;
1161                 }
1162
1163                 if (lpi && line > 0 && !(line % lpi))
1164                         sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1165                 else
1166                         sol = RISC_SOL;
1167
1168                 if (bpl <= sg_dma_len(sg) - offset) {
1169                         /* fits into current chunk */
1170                         *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL |
1171                                         bpl);
1172                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1173                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1174                         offset += bpl;
1175                 } else {
1176                         /* scanline needs to be split */
1177                         todo = bpl;
1178                         *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1179                                         (sg_dma_len(sg) - offset));
1180                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1181                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1182                         todo -= (sg_dma_len(sg) - offset);
1183                         offset = 0;
1184                         sg++;
1185                         while (todo > sg_dma_len(sg)) {
1186                                 *(rp++) = cpu_to_le32(RISC_WRITE |
1187                                                 sg_dma_len(sg));
1188                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1189                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1190                                 todo -= sg_dma_len(sg);
1191                                 sg++;
1192                         }
1193                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1194                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1195                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1196                         offset += todo;
1197                 }
1198                 offset += padding;
1199         }
1200
1201         return rp;
1202 }
1203
1204 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1205                                   struct btcx_riscmem *risc,
1206                                   struct scatterlist *sglist,
1207                                   unsigned int bpl,
1208                                   unsigned int lines, unsigned int lpi)
1209 {
1210         u32 instructions;
1211         __le32 *rp;
1212         int rc;
1213
1214         /* estimate risc mem: worst case is one write per page border +
1215            one write per scan line + syncs + jump (all 2 dwords).  Here
1216            there is no padding and no sync.  First DMA region may be smaller
1217            than PAGE_SIZE */
1218         /* Jump and write need an extra dword */
1219         instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1220         instructions += 1;
1221
1222         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1223         if (rc < 0)
1224                 return rc;
1225
1226         /* write risc instructions */
1227         rp = risc->cpu;
1228         rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1229                                       lines, lpi);
1230
1231         /* save pointer to jmp instruction address */
1232         risc->jmp = rp;
1233         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1234         return 0;
1235 }
1236 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1237
1238 int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1239                          u32 reg, u32 mask, u32 value)
1240 {
1241         __le32 *rp;
1242         int rc;
1243
1244         rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1245
1246         if (rc < 0)
1247                 return rc;
1248
1249         /* write risc instructions */
1250         rp = risc->cpu;
1251
1252         *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1253         *(rp++) = cpu_to_le32(reg);
1254         *(rp++) = cpu_to_le32(value);
1255         *(rp++) = cpu_to_le32(mask);
1256         *(rp++) = cpu_to_le32(RISC_JUMP);
1257         *(rp++) = cpu_to_le32(risc->dma);
1258         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1259         return 0;
1260 }
1261
1262 void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1263 {
1264         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1265
1266         BUG_ON(in_interrupt());
1267         videobuf_waiton(q, &buf->vb, 0, 0);
1268         videobuf_dma_unmap(q->dev, dma);
1269         videobuf_dma_free(dma);
1270         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1271         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1272 }
1273
1274 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1275 {
1276         struct cx25821_dev *dev = dev_id;
1277         u32 pci_status;
1278         u32 vid_status;
1279         int i, handled = 0;
1280         u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1281
1282         pci_status = cx_read(PCI_INT_STAT);
1283
1284         if (pci_status == 0)
1285                 goto out;
1286
1287         for (i = 0; i < VID_CHANNEL_NUM; i++) {
1288                 if (pci_status & mask[i]) {
1289                         vid_status = cx_read(dev->channels[i].
1290                                 sram_channels->int_stat);
1291
1292                         if (vid_status)
1293                                 handled += cx25821_video_irq(dev, i,
1294                                                 vid_status);
1295
1296                         cx_write(PCI_INT_STAT, mask[i]);
1297                 }
1298         }
1299
1300 out:
1301         return IRQ_RETVAL(handled);
1302 }
1303
1304 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1305                            int len, u32 bits, u32 mask)
1306 {
1307         unsigned int i;
1308
1309         printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1310
1311         for (i = 0; i < len; i++) {
1312                 if (!(bits & (1 << i)))
1313                         continue;
1314                 if (strings[i])
1315                         pr_cont(" %s", strings[i]);
1316                 else
1317                         pr_cont(" %d", i);
1318                 if (!(mask & (1 << i)))
1319                         continue;
1320                 pr_cont("*");
1321         }
1322         pr_cont("\n");
1323 }
1324 EXPORT_SYMBOL(cx25821_print_irqbits);
1325
1326 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1327 {
1328         struct cx25821_dev *dev = pci_get_drvdata(pci);
1329         return dev;
1330 }
1331 EXPORT_SYMBOL(cx25821_dev_get);
1332
1333 static int cx25821_initdev(struct pci_dev *pci_dev,
1334                            const struct pci_device_id *pci_id)
1335 {
1336         struct cx25821_dev *dev;
1337         int err = 0;
1338
1339         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1340         if (NULL == dev)
1341                 return -ENOMEM;
1342
1343         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1344         if (err < 0)
1345                 goto fail_free;
1346
1347         /* pci init */
1348         dev->pci = pci_dev;
1349         if (pci_enable_device(pci_dev)) {
1350                 err = -EIO;
1351
1352                 pr_info("pci enable failed!\n");
1353
1354                 goto fail_unregister_device;
1355         }
1356
1357         pr_info("Athena pci enable !\n");
1358
1359         err = cx25821_dev_setup(dev);
1360         if (err) {
1361                 if (err == -EBUSY)
1362                         goto fail_unregister_device;
1363                 else
1364                         goto fail_unregister_pci;
1365         }
1366
1367         /* print pci info */
1368         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1369         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1370         pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1371                 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1372                 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1373
1374         pci_set_master(pci_dev);
1375         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1376                 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1377                 err = -EIO;
1378                 goto fail_irq;
1379         }
1380
1381         err = request_irq(pci_dev->irq, cx25821_irq,
1382                         IRQF_SHARED, dev->name, dev);
1383
1384         if (err < 0) {
1385                 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1386                 goto fail_irq;
1387         }
1388
1389         return 0;
1390
1391 fail_irq:
1392         pr_info("cx25821_initdev() can't get IRQ !\n");
1393         cx25821_dev_unregister(dev);
1394
1395 fail_unregister_pci:
1396         pci_disable_device(pci_dev);
1397 fail_unregister_device:
1398         v4l2_device_unregister(&dev->v4l2_dev);
1399
1400 fail_free:
1401         kfree(dev);
1402         return err;
1403 }
1404
1405 static void cx25821_finidev(struct pci_dev *pci_dev)
1406 {
1407         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1408         struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1409
1410         cx25821_shutdown(dev);
1411         pci_disable_device(pci_dev);
1412
1413         /* unregister stuff */
1414         if (pci_dev->irq)
1415                 free_irq(pci_dev->irq, dev);
1416
1417         mutex_lock(&cx25821_devlist_mutex);
1418         list_del(&dev->devlist);
1419         mutex_unlock(&cx25821_devlist_mutex);
1420
1421         cx25821_dev_unregister(dev);
1422         v4l2_device_unregister(v4l2_dev);
1423         kfree(dev);
1424 }
1425
1426 static DEFINE_PCI_DEVICE_TABLE(cx25821_pci_tbl) = {
1427         {
1428                 /* CX25821 Athena */
1429                 .vendor = 0x14f1,
1430                 .device = 0x8210,
1431                 .subvendor = 0x14f1,
1432                 .subdevice = 0x0920,
1433         }, {
1434                 /* CX25821 No Brand */
1435                 .vendor = 0x14f1,
1436                 .device = 0x8210,
1437                 .subvendor = 0x0000,
1438                 .subdevice = 0x0000,
1439         }, {
1440                 /* --- end of list --- */
1441         }
1442 };
1443
1444 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1445
1446 static struct pci_driver cx25821_pci_driver = {
1447         .name = "cx25821",
1448         .id_table = cx25821_pci_tbl,
1449         .probe = cx25821_initdev,
1450         .remove = cx25821_finidev,
1451         /* TODO */
1452         .suspend = NULL,
1453         .resume = NULL,
1454 };
1455
1456 static int __init cx25821_init(void)
1457 {
1458         pr_info("driver version %d.%d.%d loaded\n",
1459                 (CX25821_VERSION_CODE >> 16) & 0xff,
1460                 (CX25821_VERSION_CODE >> 8) & 0xff,
1461                 CX25821_VERSION_CODE & 0xff);
1462         return pci_register_driver(&cx25821_pci_driver);
1463 }
1464
1465 static void __exit cx25821_fini(void)
1466 {
1467         pci_unregister_driver(&cx25821_pci_driver);
1468 }
1469
1470 module_init(cx25821_init);
1471 module_exit(cx25821_fini);