2b38a5005d0e3269be9face3796fd62983bf99fd
[sfrench/cifs-2.6.git] / drivers / media / pci / cx25821 / cx25821-core.c
1 /*
2  *  Driver for the Conexant CX25821 PCIe bridge
3  *
4  *  Copyright (C) 2009 Conexant Systems Inc.
5  *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6  *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation; either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *
17  *  GNU General Public License for more details.
18  *
19  *  You should have received a copy of the GNU General Public License
20  *  along with this program; if not, write to the Free Software
21  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/i2c.h>
27 #include <linux/slab.h>
28 #include "cx25821.h"
29 #include "cx25821-sram.h"
30 #include "cx25821-video.h"
31
32 MODULE_DESCRIPTION("Driver for Athena cards");
33 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
34 MODULE_LICENSE("GPL");
35
36 static unsigned int debug;
37 module_param(debug, int, 0644);
38 MODULE_PARM_DESC(debug, "enable debug messages");
39
40 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
41 module_param_array(card, int, NULL, 0444);
42 MODULE_PARM_DESC(card, "card type");
43
44 static unsigned int cx25821_devcount;
45
46 DEFINE_MUTEX(cx25821_devlist_mutex);
47 EXPORT_SYMBOL(cx25821_devlist_mutex);
48 LIST_HEAD(cx25821_devlist);
49 EXPORT_SYMBOL(cx25821_devlist);
50
51 struct sram_channel cx25821_sram_channels[] = {
52         [SRAM_CH00] = {
53                 .i = SRAM_CH00,
54                 .name = "VID A",
55                 .cmds_start = VID_A_DOWN_CMDS,
56                 .ctrl_start = VID_A_IQ,
57                 .cdt = VID_A_CDT,
58                 .fifo_start = VID_A_DOWN_CLUSTER_1,
59                 .fifo_size = (VID_CLUSTER_SIZE << 2),
60                 .ptr1_reg = DMA1_PTR1,
61                 .ptr2_reg = DMA1_PTR2,
62                 .cnt1_reg = DMA1_CNT1,
63                 .cnt2_reg = DMA1_CNT2,
64                 .int_msk = VID_A_INT_MSK,
65                 .int_stat = VID_A_INT_STAT,
66                 .int_mstat = VID_A_INT_MSTAT,
67                 .dma_ctl = VID_DST_A_DMA_CTL,
68                 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
69                 .gpcnt = VID_DST_A_GPCNT,
70                 .vip_ctl = VID_DST_A_VIP_CTL,
71                 .pix_frmt = VID_DST_A_PIX_FRMT,
72         },
73
74         [SRAM_CH01] = {
75                 .i = SRAM_CH01,
76                 .name = "VID B",
77                 .cmds_start = VID_B_DOWN_CMDS,
78                 .ctrl_start = VID_B_IQ,
79                 .cdt = VID_B_CDT,
80                 .fifo_start = VID_B_DOWN_CLUSTER_1,
81                 .fifo_size = (VID_CLUSTER_SIZE << 2),
82                 .ptr1_reg = DMA2_PTR1,
83                 .ptr2_reg = DMA2_PTR2,
84                 .cnt1_reg = DMA2_CNT1,
85                 .cnt2_reg = DMA2_CNT2,
86                 .int_msk = VID_B_INT_MSK,
87                 .int_stat = VID_B_INT_STAT,
88                 .int_mstat = VID_B_INT_MSTAT,
89                 .dma_ctl = VID_DST_B_DMA_CTL,
90                 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
91                 .gpcnt = VID_DST_B_GPCNT,
92                 .vip_ctl = VID_DST_B_VIP_CTL,
93                 .pix_frmt = VID_DST_B_PIX_FRMT,
94         },
95
96         [SRAM_CH02] = {
97                 .i = SRAM_CH02,
98                 .name = "VID C",
99                 .cmds_start = VID_C_DOWN_CMDS,
100                 .ctrl_start = VID_C_IQ,
101                 .cdt = VID_C_CDT,
102                 .fifo_start = VID_C_DOWN_CLUSTER_1,
103                 .fifo_size = (VID_CLUSTER_SIZE << 2),
104                 .ptr1_reg = DMA3_PTR1,
105                 .ptr2_reg = DMA3_PTR2,
106                 .cnt1_reg = DMA3_CNT1,
107                 .cnt2_reg = DMA3_CNT2,
108                 .int_msk = VID_C_INT_MSK,
109                 .int_stat = VID_C_INT_STAT,
110                 .int_mstat = VID_C_INT_MSTAT,
111                 .dma_ctl = VID_DST_C_DMA_CTL,
112                 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
113                 .gpcnt = VID_DST_C_GPCNT,
114                 .vip_ctl = VID_DST_C_VIP_CTL,
115                 .pix_frmt = VID_DST_C_PIX_FRMT,
116         },
117
118         [SRAM_CH03] = {
119                 .i = SRAM_CH03,
120                 .name = "VID D",
121                 .cmds_start = VID_D_DOWN_CMDS,
122                 .ctrl_start = VID_D_IQ,
123                 .cdt = VID_D_CDT,
124                 .fifo_start = VID_D_DOWN_CLUSTER_1,
125                 .fifo_size = (VID_CLUSTER_SIZE << 2),
126                 .ptr1_reg = DMA4_PTR1,
127                 .ptr2_reg = DMA4_PTR2,
128                 .cnt1_reg = DMA4_CNT1,
129                 .cnt2_reg = DMA4_CNT2,
130                 .int_msk = VID_D_INT_MSK,
131                 .int_stat = VID_D_INT_STAT,
132                 .int_mstat = VID_D_INT_MSTAT,
133                 .dma_ctl = VID_DST_D_DMA_CTL,
134                 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
135                 .gpcnt = VID_DST_D_GPCNT,
136                 .vip_ctl = VID_DST_D_VIP_CTL,
137                 .pix_frmt = VID_DST_D_PIX_FRMT,
138         },
139
140         [SRAM_CH04] = {
141                 .i = SRAM_CH04,
142                 .name = "VID E",
143                 .cmds_start = VID_E_DOWN_CMDS,
144                 .ctrl_start = VID_E_IQ,
145                 .cdt = VID_E_CDT,
146                 .fifo_start = VID_E_DOWN_CLUSTER_1,
147                 .fifo_size = (VID_CLUSTER_SIZE << 2),
148                 .ptr1_reg = DMA5_PTR1,
149                 .ptr2_reg = DMA5_PTR2,
150                 .cnt1_reg = DMA5_CNT1,
151                 .cnt2_reg = DMA5_CNT2,
152                 .int_msk = VID_E_INT_MSK,
153                 .int_stat = VID_E_INT_STAT,
154                 .int_mstat = VID_E_INT_MSTAT,
155                 .dma_ctl = VID_DST_E_DMA_CTL,
156                 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
157                 .gpcnt = VID_DST_E_GPCNT,
158                 .vip_ctl = VID_DST_E_VIP_CTL,
159                 .pix_frmt = VID_DST_E_PIX_FRMT,
160         },
161
162         [SRAM_CH05] = {
163                 .i = SRAM_CH05,
164                 .name = "VID F",
165                 .cmds_start = VID_F_DOWN_CMDS,
166                 .ctrl_start = VID_F_IQ,
167                 .cdt = VID_F_CDT,
168                 .fifo_start = VID_F_DOWN_CLUSTER_1,
169                 .fifo_size = (VID_CLUSTER_SIZE << 2),
170                 .ptr1_reg = DMA6_PTR1,
171                 .ptr2_reg = DMA6_PTR2,
172                 .cnt1_reg = DMA6_CNT1,
173                 .cnt2_reg = DMA6_CNT2,
174                 .int_msk = VID_F_INT_MSK,
175                 .int_stat = VID_F_INT_STAT,
176                 .int_mstat = VID_F_INT_MSTAT,
177                 .dma_ctl = VID_DST_F_DMA_CTL,
178                 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
179                 .gpcnt = VID_DST_F_GPCNT,
180                 .vip_ctl = VID_DST_F_VIP_CTL,
181                 .pix_frmt = VID_DST_F_PIX_FRMT,
182         },
183
184         [SRAM_CH06] = {
185                 .i = SRAM_CH06,
186                 .name = "VID G",
187                 .cmds_start = VID_G_DOWN_CMDS,
188                 .ctrl_start = VID_G_IQ,
189                 .cdt = VID_G_CDT,
190                 .fifo_start = VID_G_DOWN_CLUSTER_1,
191                 .fifo_size = (VID_CLUSTER_SIZE << 2),
192                 .ptr1_reg = DMA7_PTR1,
193                 .ptr2_reg = DMA7_PTR2,
194                 .cnt1_reg = DMA7_CNT1,
195                 .cnt2_reg = DMA7_CNT2,
196                 .int_msk = VID_G_INT_MSK,
197                 .int_stat = VID_G_INT_STAT,
198                 .int_mstat = VID_G_INT_MSTAT,
199                 .dma_ctl = VID_DST_G_DMA_CTL,
200                 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
201                 .gpcnt = VID_DST_G_GPCNT,
202                 .vip_ctl = VID_DST_G_VIP_CTL,
203                 .pix_frmt = VID_DST_G_PIX_FRMT,
204         },
205
206         [SRAM_CH07] = {
207                 .i = SRAM_CH07,
208                 .name = "VID H",
209                 .cmds_start = VID_H_DOWN_CMDS,
210                 .ctrl_start = VID_H_IQ,
211                 .cdt = VID_H_CDT,
212                 .fifo_start = VID_H_DOWN_CLUSTER_1,
213                 .fifo_size = (VID_CLUSTER_SIZE << 2),
214                 .ptr1_reg = DMA8_PTR1,
215                 .ptr2_reg = DMA8_PTR2,
216                 .cnt1_reg = DMA8_CNT1,
217                 .cnt2_reg = DMA8_CNT2,
218                 .int_msk = VID_H_INT_MSK,
219                 .int_stat = VID_H_INT_STAT,
220                 .int_mstat = VID_H_INT_MSTAT,
221                 .dma_ctl = VID_DST_H_DMA_CTL,
222                 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
223                 .gpcnt = VID_DST_H_GPCNT,
224                 .vip_ctl = VID_DST_H_VIP_CTL,
225                 .pix_frmt = VID_DST_H_PIX_FRMT,
226         },
227
228         [SRAM_CH08] = {
229                 .name = "audio from",
230                 .cmds_start = AUD_A_DOWN_CMDS,
231                 .ctrl_start = AUD_A_IQ,
232                 .cdt = AUD_A_CDT,
233                 .fifo_start = AUD_A_DOWN_CLUSTER_1,
234                 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
235                 .ptr1_reg = DMA17_PTR1,
236                 .ptr2_reg = DMA17_PTR2,
237                 .cnt1_reg = DMA17_CNT1,
238                 .cnt2_reg = DMA17_CNT2,
239         },
240
241         [SRAM_CH09] = {
242                 .i = SRAM_CH09,
243                 .name = "VID Upstream I",
244                 .cmds_start = VID_I_UP_CMDS,
245                 .ctrl_start = VID_I_IQ,
246                 .cdt = VID_I_CDT,
247                 .fifo_start = VID_I_UP_CLUSTER_1,
248                 .fifo_size = (VID_CLUSTER_SIZE << 2),
249                 .ptr1_reg = DMA15_PTR1,
250                 .ptr2_reg = DMA15_PTR2,
251                 .cnt1_reg = DMA15_CNT1,
252                 .cnt2_reg = DMA15_CNT2,
253                 .int_msk = VID_I_INT_MSK,
254                 .int_stat = VID_I_INT_STAT,
255                 .int_mstat = VID_I_INT_MSTAT,
256                 .dma_ctl = VID_SRC_I_DMA_CTL,
257                 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
258                 .gpcnt = VID_SRC_I_GPCNT,
259
260                 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
261                 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
262                 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
263                 .vid_cdt_size = VID_SRC_I_CDT_SZ,
264                 .irq_bit = 8,
265         },
266
267         [SRAM_CH10] = {
268                 .i = SRAM_CH10,
269                 .name = "VID Upstream J",
270                 .cmds_start = VID_J_UP_CMDS,
271                 .ctrl_start = VID_J_IQ,
272                 .cdt = VID_J_CDT,
273                 .fifo_start = VID_J_UP_CLUSTER_1,
274                 .fifo_size = (VID_CLUSTER_SIZE << 2),
275                 .ptr1_reg = DMA16_PTR1,
276                 .ptr2_reg = DMA16_PTR2,
277                 .cnt1_reg = DMA16_CNT1,
278                 .cnt2_reg = DMA16_CNT2,
279                 .int_msk = VID_J_INT_MSK,
280                 .int_stat = VID_J_INT_STAT,
281                 .int_mstat = VID_J_INT_MSTAT,
282                 .dma_ctl = VID_SRC_J_DMA_CTL,
283                 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
284                 .gpcnt = VID_SRC_J_GPCNT,
285
286                 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
287                 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
288                 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
289                 .vid_cdt_size = VID_SRC_J_CDT_SZ,
290                 .irq_bit = 9,
291         },
292
293         [SRAM_CH11] = {
294                 .i = SRAM_CH11,
295                 .name = "Audio Upstream Channel B",
296                 .cmds_start = AUD_B_UP_CMDS,
297                 .ctrl_start = AUD_B_IQ,
298                 .cdt = AUD_B_CDT,
299                 .fifo_start = AUD_B_UP_CLUSTER_1,
300                 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
301                 .ptr1_reg = DMA22_PTR1,
302                 .ptr2_reg = DMA22_PTR2,
303                 .cnt1_reg = DMA22_CNT1,
304                 .cnt2_reg = DMA22_CNT2,
305                 .int_msk = AUD_B_INT_MSK,
306                 .int_stat = AUD_B_INT_STAT,
307                 .int_mstat = AUD_B_INT_MSTAT,
308                 .dma_ctl = AUD_INT_DMA_CTL,
309                 .gpcnt_ctl = AUD_B_GPCNT_CTL,
310                 .gpcnt = AUD_B_GPCNT,
311                 .aud_length = AUD_B_LNGTH,
312                 .aud_cfg = AUD_B_CFG,
313                 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
314                 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
315                 .irq_bit = 11,
316         },
317 };
318 EXPORT_SYMBOL(cx25821_sram_channels);
319
320 struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00];
321 struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01];
322 struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02];
323 struct sram_channel *channel3 = &cx25821_sram_channels[SRAM_CH03];
324 struct sram_channel *channel4 = &cx25821_sram_channels[SRAM_CH04];
325 struct sram_channel *channel5 = &cx25821_sram_channels[SRAM_CH05];
326 struct sram_channel *channel6 = &cx25821_sram_channels[SRAM_CH06];
327 struct sram_channel *channel7 = &cx25821_sram_channels[SRAM_CH07];
328 struct sram_channel *channel9 = &cx25821_sram_channels[SRAM_CH09];
329 struct sram_channel *channel10 = &cx25821_sram_channels[SRAM_CH10];
330 struct sram_channel *channel11 = &cx25821_sram_channels[SRAM_CH11];
331
332 struct cx25821_dmaqueue mpegq;
333
334 static int cx25821_risc_decode(u32 risc)
335 {
336         static const char * const instr[16] = {
337                 [RISC_SYNC >> 28] = "sync",
338                 [RISC_WRITE >> 28] = "write",
339                 [RISC_WRITEC >> 28] = "writec",
340                 [RISC_READ >> 28] = "read",
341                 [RISC_READC >> 28] = "readc",
342                 [RISC_JUMP >> 28] = "jump",
343                 [RISC_SKIP >> 28] = "skip",
344                 [RISC_WRITERM >> 28] = "writerm",
345                 [RISC_WRITECM >> 28] = "writecm",
346                 [RISC_WRITECR >> 28] = "writecr",
347         };
348         static const int incr[16] = {
349                 [RISC_WRITE >> 28] = 3,
350                 [RISC_JUMP >> 28] = 3,
351                 [RISC_SKIP >> 28] = 1,
352                 [RISC_SYNC >> 28] = 1,
353                 [RISC_WRITERM >> 28] = 3,
354                 [RISC_WRITECM >> 28] = 3,
355                 [RISC_WRITECR >> 28] = 4,
356         };
357         static const char * const bits[] = {
358                 "12", "13", "14", "resync",
359                 "cnt0", "cnt1", "18", "19",
360                 "20", "21", "22", "23",
361                 "irq1", "irq2", "eol", "sol",
362         };
363         int i;
364
365         pr_cont("0x%08x [ %s",
366                 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
367         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
368                 if (risc & (1 << (i + 12)))
369                         pr_cont(" %s", bits[i]);
370         }
371         pr_cont(" count=%d ]\n", risc & 0xfff);
372         return incr[risc >> 28] ? incr[risc >> 28] : 1;
373 }
374
375 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
376 {
377         struct cx25821_i2c *bus = i2c_adap->algo_data;
378         struct cx25821_dev *dev = bus->dev;
379         return cx_read(bus->reg_stat) & 0x01;
380 }
381
382 static void cx25821_registers_init(struct cx25821_dev *dev)
383 {
384         u32 tmp;
385
386         /* enable RUN_RISC in Pecos */
387         cx_write(DEV_CNTRL2, 0x20);
388
389         /* Set the master PCI interrupt masks to enable video, audio, MBIF,
390          * and GPIO interrupts
391          * I2C interrupt masking is handled by the I2C objects themselves. */
392         cx_write(PCI_INT_MSK, 0x2001FFFF);
393
394         tmp = cx_read(RDR_TLCTL0);
395         tmp &= ~FLD_CFG_RCB_CK_EN;      /* Clear the RCB_CK_EN bit */
396         cx_write(RDR_TLCTL0, tmp);
397
398         /* PLL-A setting for the Audio Master Clock */
399         cx_write(PLL_A_INT_FRAC, 0x9807A58B);
400
401         /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
402         cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
403
404         /* clear reset bit [31] */
405         tmp = cx_read(PLL_A_INT_FRAC);
406         cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
407
408         /* PLL-B setting for Mobilygen Host Bus Interface */
409         cx_write(PLL_B_INT_FRAC, 0x9883A86F);
410
411         /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
412         cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
413
414         /* clear reset bit [31] */
415         tmp = cx_read(PLL_B_INT_FRAC);
416         cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
417
418         /* PLL-C setting for video upstream channel */
419         cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
420
421         /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
422         cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
423
424         /* clear reset bit [31] */
425         tmp = cx_read(PLL_C_INT_FRAC);
426         cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
427
428         /* PLL-D setting for audio upstream channel */
429         cx_write(PLL_D_INT_FRAC, 0x98757F5B);
430
431         /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
432         cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
433
434         /* clear reset bit [31] */
435         tmp = cx_read(PLL_D_INT_FRAC);
436         cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
437
438         /* This selects the PLL C clock source for the video upstream channel
439          * I and J */
440         tmp = cx_read(VID_CH_CLK_SEL);
441         cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
442
443         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
444          * channel A-C
445          * select 656/VIP DST for downstream Channel A - C */
446         tmp = cx_read(VID_CH_MODE_SEL);
447         /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
448         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
449
450         /* enables 656 port I and J as output */
451         tmp = cx_read(CLK_RST);
452         /* use external ALT_PLL_REF pin as its reference clock instead */
453         tmp |= FLD_USE_ALT_PLL_REF;
454         cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
455
456         mdelay(100);
457 }
458
459 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
460                                struct sram_channel *ch,
461                                unsigned int bpl, u32 risc)
462 {
463         unsigned int i, lines;
464         u32 cdt;
465
466         if (ch->cmds_start == 0) {
467                 cx_write(ch->ptr1_reg, 0);
468                 cx_write(ch->ptr2_reg, 0);
469                 cx_write(ch->cnt2_reg, 0);
470                 cx_write(ch->cnt1_reg, 0);
471                 return 0;
472         }
473
474         bpl = (bpl + 7) & ~7;   /* alignment */
475         cdt = ch->cdt;
476         lines = ch->fifo_size / bpl;
477
478         if (lines > 4)
479                 lines = 4;
480
481         BUG_ON(lines < 2);
482
483         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
484         cx_write(8 + 4, 8);
485         cx_write(8 + 8, 0);
486
487         /* write CDT */
488         for (i = 0; i < lines; i++) {
489                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
490                 cx_write(cdt + 16 * i + 4, 0);
491                 cx_write(cdt + 16 * i + 8, 0);
492                 cx_write(cdt + 16 * i + 12, 0);
493         }
494
495         /* init the first cdt buffer */
496         for (i = 0; i < 128; i++)
497                 cx_write(ch->fifo_start + 4 * i, i);
498
499         /* write CMDS */
500         if (ch->jumponly)
501                 cx_write(ch->cmds_start + 0, 8);
502         else
503                 cx_write(ch->cmds_start + 0, risc);
504
505         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
506         cx_write(ch->cmds_start + 8, cdt);
507         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
508         cx_write(ch->cmds_start + 16, ch->ctrl_start);
509
510         if (ch->jumponly)
511                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
512         else
513                 cx_write(ch->cmds_start + 20, 64 >> 2);
514
515         for (i = 24; i < 80; i += 4)
516                 cx_write(ch->cmds_start + i, 0);
517
518         /* fill registers */
519         cx_write(ch->ptr1_reg, ch->fifo_start);
520         cx_write(ch->ptr2_reg, cdt);
521         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
522         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
523
524         return 0;
525 }
526 EXPORT_SYMBOL(cx25821_sram_channel_setup);
527
528 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
529                                      struct sram_channel *ch,
530                                      unsigned int bpl, u32 risc)
531 {
532         unsigned int i, lines;
533         u32 cdt;
534
535         if (ch->cmds_start == 0) {
536                 cx_write(ch->ptr1_reg, 0);
537                 cx_write(ch->ptr2_reg, 0);
538                 cx_write(ch->cnt2_reg, 0);
539                 cx_write(ch->cnt1_reg, 0);
540                 return 0;
541         }
542
543         bpl = (bpl + 7) & ~7;   /* alignment */
544         cdt = ch->cdt;
545         lines = ch->fifo_size / bpl;
546
547         if (lines > 3)
548                 lines = 3;      /* for AUDIO */
549
550         BUG_ON(lines < 2);
551
552         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
553         cx_write(8 + 4, 8);
554         cx_write(8 + 8, 0);
555
556         /* write CDT */
557         for (i = 0; i < lines; i++) {
558                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
559                 cx_write(cdt + 16 * i + 4, 0);
560                 cx_write(cdt + 16 * i + 8, 0);
561                 cx_write(cdt + 16 * i + 12, 0);
562         }
563
564         /* write CMDS */
565         if (ch->jumponly)
566                 cx_write(ch->cmds_start + 0, 8);
567         else
568                 cx_write(ch->cmds_start + 0, risc);
569
570         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
571         cx_write(ch->cmds_start + 8, cdt);
572         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
573         cx_write(ch->cmds_start + 16, ch->ctrl_start);
574
575         /* IQ size */
576         if (ch->jumponly)
577                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
578         else
579                 cx_write(ch->cmds_start + 20, 64 >> 2);
580
581         /* zero out */
582         for (i = 24; i < 80; i += 4)
583                 cx_write(ch->cmds_start + i, 0);
584
585         /* fill registers */
586         cx_write(ch->ptr1_reg, ch->fifo_start);
587         cx_write(ch->ptr2_reg, cdt);
588         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
589         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
590
591         return 0;
592 }
593 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
594
595 void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch)
596 {
597         static char *name[] = {
598                 "init risc lo",
599                 "init risc hi",
600                 "cdt base",
601                 "cdt size",
602                 "iq base",
603                 "iq size",
604                 "risc pc lo",
605                 "risc pc hi",
606                 "iq wr ptr",
607                 "iq rd ptr",
608                 "cdt current",
609                 "pci target lo",
610                 "pci target hi",
611                 "line / byte",
612         };
613         u32 risc;
614         unsigned int i, j, n;
615
616         pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
617         for (i = 0; i < ARRAY_SIZE(name); i++)
618                 pr_warn("cmds + 0x%2x:   %-15s: 0x%08x\n",
619                         i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
620
621         j = i * 4;
622         for (i = 0; i < 4;) {
623                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
624                 pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
625                 i += cx25821_risc_decode(risc);
626         }
627
628         for (i = 0; i < (64 >> 2); i += n) {
629                 risc = cx_read(ch->ctrl_start + 4 * i);
630                 /* No consideration for bits 63-32 */
631
632                 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
633                         i * 4, ch->ctrl_start + 4 * i, i);
634                 n = cx25821_risc_decode(risc);
635                 for (j = 1; j < n; j++) {
636                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
637                         pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
638                                 4 * (i + j), i + j, risc, j);
639                 }
640         }
641
642         pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
643                 ch->fifo_start, ch->fifo_start + ch->fifo_size);
644         pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
645                 ch->ctrl_start, ch->ctrl_start + 6 * 16);
646         pr_warn("        :   ptr1_reg: 0x%08x\n",
647                 cx_read(ch->ptr1_reg));
648         pr_warn("        :   ptr2_reg: 0x%08x\n",
649                 cx_read(ch->ptr2_reg));
650         pr_warn("        :   cnt1_reg: 0x%08x\n",
651                 cx_read(ch->cnt1_reg));
652         pr_warn("        :   cnt2_reg: 0x%08x\n",
653                 cx_read(ch->cnt2_reg));
654 }
655 EXPORT_SYMBOL(cx25821_sram_channel_dump);
656
657 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
658                                      struct sram_channel *ch)
659 {
660         static const char * const name[] = {
661                 "init risc lo",
662                 "init risc hi",
663                 "cdt base",
664                 "cdt size",
665                 "iq base",
666                 "iq size",
667                 "risc pc lo",
668                 "risc pc hi",
669                 "iq wr ptr",
670                 "iq rd ptr",
671                 "cdt current",
672                 "pci target lo",
673                 "pci target hi",
674                 "line / byte",
675         };
676
677         u32 risc, value, tmp;
678         unsigned int i, j, n;
679
680         pr_info("\n%s: %s - dma Audio channel status dump\n",
681                 dev->name, ch->name);
682
683         for (i = 0; i < ARRAY_SIZE(name); i++)
684                 pr_info("%s: cmds + 0x%2x:   %-15s: 0x%08x\n",
685                         dev->name, i * 4, name[i],
686                         cx_read(ch->cmds_start + 4 * i));
687
688         j = i * 4;
689         for (i = 0; i < 4;) {
690                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
691                 pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
692                 i += cx25821_risc_decode(risc);
693         }
694
695         for (i = 0; i < (64 >> 2); i += n) {
696                 risc = cx_read(ch->ctrl_start + 4 * i);
697                 /* No consideration for bits 63-32 */
698
699                 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
700                         i * 4, ch->ctrl_start + 4 * i, i);
701                 n = cx25821_risc_decode(risc);
702
703                 for (j = 1; j < n; j++) {
704                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
705                         pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
706                                 4 * (i + j), i + j, risc, j);
707                 }
708         }
709
710         pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
711                 ch->fifo_start, ch->fifo_start + ch->fifo_size);
712         pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
713                 ch->ctrl_start, ch->ctrl_start + 6 * 16);
714         pr_warn("        :   ptr1_reg: 0x%08x\n",
715                 cx_read(ch->ptr1_reg));
716         pr_warn("        :   ptr2_reg: 0x%08x\n",
717                 cx_read(ch->ptr2_reg));
718         pr_warn("        :   cnt1_reg: 0x%08x\n",
719                 cx_read(ch->cnt1_reg));
720         pr_warn("        :   cnt2_reg: 0x%08x\n",
721                 cx_read(ch->cnt2_reg));
722
723         for (i = 0; i < 4; i++) {
724                 risc = cx_read(ch->cmds_start + 56 + (i * 4));
725                 pr_warn("instruction %d = 0x%x\n", i, risc);
726         }
727
728         /* read data from the first cdt buffer */
729         risc = cx_read(AUD_A_CDT);
730         pr_warn("\nread cdt loc=0x%x\n", risc);
731         for (i = 0; i < 8; i++) {
732                 n = cx_read(risc + i * 4);
733                 pr_cont("0x%x ", n);
734         }
735         pr_cont("\n\n");
736
737         value = cx_read(CLK_RST);
738         CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
739
740         value = cx_read(PLL_A_POST_STAT_BIST);
741         CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
742         value = cx_read(PLL_A_INT_FRAC);
743         CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
744
745         value = cx_read(PLL_B_POST_STAT_BIST);
746         CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
747         value = cx_read(PLL_B_INT_FRAC);
748         CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
749
750         value = cx_read(PLL_C_POST_STAT_BIST);
751         CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
752         value = cx_read(PLL_C_INT_FRAC);
753         CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
754
755         value = cx_read(PLL_D_POST_STAT_BIST);
756         CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
757         value = cx_read(PLL_D_INT_FRAC);
758         CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
759
760         value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
761         CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
762 }
763 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
764
765 static void cx25821_shutdown(struct cx25821_dev *dev)
766 {
767         int i;
768
769         /* disable RISC controller */
770         cx_write(DEV_CNTRL2, 0);
771
772         /* Disable Video A/B activity */
773         for (i = 0; i < VID_CHANNEL_NUM; i++) {
774                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
775                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
776         }
777
778         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
779                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
780                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
781                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
782         }
783
784         /* Disable Audio activity */
785         cx_write(AUD_INT_DMA_CTL, 0);
786
787         /* Disable Serial port */
788         cx_write(UART_CTL, 0);
789
790         /* Disable Interrupts */
791         cx_write(PCI_INT_MSK, 0);
792         cx_write(AUD_A_INT_MSK, 0);
793 }
794
795 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
796                               u32 format)
797 {
798         if (channel_select <= 7 && channel_select >= 0) {
799                 cx_write(dev->channels[channel_select].sram_channels->pix_frmt,
800                                 format);
801                 dev->channels[channel_select].pixel_formats = format;
802         }
803 }
804
805 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
806                                  struct sram_channel *ch)
807 {
808         cx_write(ch->pix_frmt, PIXEL_FRMT_422);
809         cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
810 }
811
812 static void cx25821_initialize(struct cx25821_dev *dev)
813 {
814         int i;
815
816         dprintk(1, "%s()\n", __func__);
817
818         cx25821_shutdown(dev);
819         cx_write(PCI_INT_STAT, 0xffffffff);
820
821         for (i = 0; i < VID_CHANNEL_NUM; i++)
822                 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
823
824         cx_write(AUD_A_INT_STAT, 0xffffffff);
825         cx_write(AUD_B_INT_STAT, 0xffffffff);
826         cx_write(AUD_C_INT_STAT, 0xffffffff);
827         cx_write(AUD_D_INT_STAT, 0xffffffff);
828         cx_write(AUD_E_INT_STAT, 0xffffffff);
829
830         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
831         cx_write(PAD_CTRL, 0x12);       /* for I2C */
832         cx25821_registers_init(dev);    /* init Pecos registers */
833         mdelay(100);
834
835         for (i = 0; i < VID_CHANNEL_NUM; i++) {
836                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
837                 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
838                                                 1440, 0);
839                 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
840                 dev->channels[i].use_cif_resolution = FALSE;
841         }
842
843         /* Probably only affect Downstream */
844         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
845                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
846                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
847         }
848
849         cx25821_sram_channel_setup_audio(dev,
850                         dev->channels[SRAM_CH08].sram_channels, 128, 0);
851
852         cx25821_gpio_init(dev);
853 }
854
855 static int cx25821_get_resources(struct cx25821_dev *dev)
856 {
857         if (request_mem_region(pci_resource_start(dev->pci, 0),
858                                 pci_resource_len(dev->pci, 0), dev->name))
859                 return 0;
860
861         pr_err("%s: can't get MMIO memory @ 0x%llx\n",
862                 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
863
864         return -EBUSY;
865 }
866
867 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
868 {
869         dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
870
871         pr_info("%s(): Hardware revision = 0x%02x\n",
872                 __func__, dev->hwrevision);
873 }
874
875 static void cx25821_iounmap(struct cx25821_dev *dev)
876 {
877         if (dev == NULL)
878                 return;
879
880         /* Releasing IO memory */
881         if (dev->lmmio != NULL) {
882                 CX25821_INFO("Releasing lmmio.\n");
883                 iounmap(dev->lmmio);
884                 dev->lmmio = NULL;
885         }
886 }
887
888 static int cx25821_dev_setup(struct cx25821_dev *dev)
889 {
890         int i;
891
892         pr_info("\n***********************************\n");
893         pr_info("cx25821 set up\n");
894         pr_info("***********************************\n\n");
895
896         mutex_init(&dev->lock);
897
898         atomic_inc(&dev->refcount);
899
900         dev->nr = ++cx25821_devcount;
901         sprintf(dev->name, "cx25821[%d]", dev->nr);
902
903         mutex_lock(&cx25821_devlist_mutex);
904         list_add_tail(&dev->devlist, &cx25821_devlist);
905         mutex_unlock(&cx25821_devlist_mutex);
906
907         if (dev->pci->device != 0x8210) {
908                 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
909                         __func__, dev->pci->device);
910                 return -1;
911         } else {
912                 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
913         }
914
915         /* Apply a sensible clock frequency for the PCIe bridge */
916         dev->clk_freq = 28000000;
917         for (i = 0; i < MAX_VID_CHANNEL_NUM; i++)
918                 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
919
920         if (dev->nr > 1)
921                 CX25821_INFO("dev->nr > 1!");
922
923         /* board config */
924         dev->board = 1;         /* card[dev->nr]; */
925         dev->_max_num_decoders = MAX_DECODERS;
926
927         dev->pci_bus = dev->pci->bus->number;
928         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
929         dev->pci_irqmask = 0x001f00;
930
931         /* External Master 1 Bus */
932         dev->i2c_bus[0].nr = 0;
933         dev->i2c_bus[0].dev = dev;
934         dev->i2c_bus[0].reg_stat = I2C1_STAT;
935         dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
936         dev->i2c_bus[0].reg_addr = I2C1_ADDR;
937         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
938         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
939         dev->i2c_bus[0].i2c_period = (0x07 << 24);      /* 1.95MHz */
940
941         if (cx25821_get_resources(dev) < 0) {
942                 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
943                        dev->name, dev->pci->subsystem_vendor,
944                        dev->pci->subsystem_device);
945
946                 cx25821_devcount--;
947                 return -EBUSY;
948         }
949
950         /* PCIe stuff */
951         dev->base_io_addr = pci_resource_start(dev->pci, 0);
952
953         if (!dev->base_io_addr) {
954                 CX25821_ERR("No PCI Memory resources, exiting!\n");
955                 return -ENODEV;
956         }
957
958         dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
959
960         if (!dev->lmmio) {
961                 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
962                 cx25821_iounmap(dev);
963                 return -ENOMEM;
964         }
965
966         dev->bmmio = (u8 __iomem *) dev->lmmio;
967
968         pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
969                 dev->name, dev->pci->subsystem_vendor,
970                 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
971                 dev->board, card[dev->nr] == dev->board ?
972                 "insmod option" : "autodetected");
973
974         /* init hardware */
975         cx25821_initialize(dev);
976
977         cx25821_i2c_register(&dev->i2c_bus[0]);
978 /*  cx25821_i2c_register(&dev->i2c_bus[1]);
979  *  cx25821_i2c_register(&dev->i2c_bus[2]); */
980
981         CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
982                         dev->i2c_bus[0].i2c_rc);
983
984         cx25821_card_setup(dev);
985
986         if (medusa_video_init(dev) < 0)
987                 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
988
989         cx25821_video_register(dev);
990
991         cx25821_dev_checkrevision(dev);
992         CX25821_INFO("setup done!\n");
993
994         return 0;
995 }
996
997 void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
998                                       struct upstream_user_struct *up_data)
999 {
1000         dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
1001
1002         dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1003         medusa_set_videostandard(dev);
1004
1005         cx25821_vidupstream_init_ch1(dev, dev->channel_select,
1006                                      dev->pixel_format);
1007 }
1008
1009 void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
1010                                       struct upstream_user_struct *up_data)
1011 {
1012         dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
1013
1014         dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1015         medusa_set_videostandard(dev);
1016
1017         cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1018                                      dev->pixel_format_ch2);
1019 }
1020
1021 void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1022                                   struct upstream_user_struct *up_data)
1023 {
1024         cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1025 }
1026
1027 void cx25821_dev_unregister(struct cx25821_dev *dev)
1028 {
1029         int i;
1030
1031         if (!dev->base_io_addr)
1032                 return;
1033
1034         cx25821_free_mem_upstream_ch1(dev);
1035         cx25821_free_mem_upstream_ch2(dev);
1036         cx25821_free_mem_upstream_audio(dev);
1037
1038         release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1039
1040         if (!atomic_dec_and_test(&dev->refcount))
1041                 return;
1042
1043         for (i = 0; i < MAX_VID_CHANNEL_NUM - 1; i++) {
1044                 if (i == SRAM_CH08) /* audio channel */
1045                         continue;
1046                 cx25821_video_unregister(dev, i);
1047         }
1048
1049         cx25821_i2c_unregister(&dev->i2c_bus[0]);
1050         cx25821_iounmap(dev);
1051 }
1052 EXPORT_SYMBOL(cx25821_dev_unregister);
1053
1054 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1055                                   unsigned int offset, u32 sync_line,
1056                                   unsigned int bpl, unsigned int padding,
1057                                   unsigned int lines)
1058 {
1059         struct scatterlist *sg;
1060         unsigned int line, todo;
1061
1062         /* sync instruction */
1063         if (sync_line != NO_SYNC_LINE)
1064                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1065
1066         /* scan lines */
1067         sg = sglist;
1068         for (line = 0; line < lines; line++) {
1069                 while (offset && offset >= sg_dma_len(sg)) {
1070                         offset -= sg_dma_len(sg);
1071                         sg++;
1072                 }
1073                 if (bpl <= sg_dma_len(sg) - offset) {
1074                         /* fits into current chunk */
1075                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL |
1076                                         bpl);
1077                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1078                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1079                         offset += bpl;
1080                 } else {
1081                         /* scanline needs to be split */
1082                         todo = bpl;
1083                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL |
1084                                         (sg_dma_len(sg) - offset));
1085                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1086                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1087                         todo -= (sg_dma_len(sg) - offset);
1088                         offset = 0;
1089                         sg++;
1090                         while (todo > sg_dma_len(sg)) {
1091                                 *(rp++) = cpu_to_le32(RISC_WRITE |
1092                                                 sg_dma_len(sg));
1093                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1094                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1095                                 todo -= sg_dma_len(sg);
1096                                 sg++;
1097                         }
1098                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1099                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1100                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1101                         offset += todo;
1102                 }
1103
1104                 offset += padding;
1105         }
1106
1107         return rp;
1108 }
1109
1110 int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1111                         struct scatterlist *sglist, unsigned int top_offset,
1112                         unsigned int bottom_offset, unsigned int bpl,
1113                         unsigned int padding, unsigned int lines)
1114 {
1115         u32 instructions;
1116         u32 fields;
1117         __le32 *rp;
1118         int rc;
1119
1120         fields = 0;
1121         if (UNSET != top_offset)
1122                 fields++;
1123         if (UNSET != bottom_offset)
1124                 fields++;
1125
1126         /* estimate risc mem: worst case is one write per page border +
1127            one write per scan line + syncs + jump (all 2 dwords).  Padding
1128            can cause next bpl to start close to a page border.  First DMA
1129            region may be smaller than PAGE_SIZE */
1130         /* write and jump need and extra dword */
1131         instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE +
1132                         lines);
1133         instructions += 2;
1134         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1135
1136         if (rc < 0)
1137                 return rc;
1138
1139         /* write risc instructions */
1140         rp = risc->cpu;
1141
1142         if (UNSET != top_offset) {
1143                 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1144                                         lines);
1145         }
1146
1147         if (UNSET != bottom_offset) {
1148                 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1149                                         padding, lines);
1150         }
1151
1152         /* save pointer to jmp instruction address */
1153         risc->jmp = rp;
1154         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1155
1156         return 0;
1157 }
1158
1159 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1160                                         unsigned int offset, u32 sync_line,
1161                                         unsigned int bpl, unsigned int padding,
1162                                         unsigned int lines, unsigned int lpi)
1163 {
1164         struct scatterlist *sg;
1165         unsigned int line, todo, sol;
1166
1167         /* sync instruction */
1168         if (sync_line != NO_SYNC_LINE)
1169                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1170
1171         /* scan lines */
1172         sg = sglist;
1173         for (line = 0; line < lines; line++) {
1174                 while (offset && offset >= sg_dma_len(sg)) {
1175                         offset -= sg_dma_len(sg);
1176                         sg++;
1177                 }
1178
1179                 if (lpi && line > 0 && !(line % lpi))
1180                         sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1181                 else
1182                         sol = RISC_SOL;
1183
1184                 if (bpl <= sg_dma_len(sg) - offset) {
1185                         /* fits into current chunk */
1186                         *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL |
1187                                         bpl);
1188                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1189                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1190                         offset += bpl;
1191                 } else {
1192                         /* scanline needs to be split */
1193                         todo = bpl;
1194                         *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1195                                         (sg_dma_len(sg) - offset));
1196                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1197                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1198                         todo -= (sg_dma_len(sg) - offset);
1199                         offset = 0;
1200                         sg++;
1201                         while (todo > sg_dma_len(sg)) {
1202                                 *(rp++) = cpu_to_le32(RISC_WRITE |
1203                                                 sg_dma_len(sg));
1204                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1205                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1206                                 todo -= sg_dma_len(sg);
1207                                 sg++;
1208                         }
1209                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1210                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1211                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1212                         offset += todo;
1213                 }
1214                 offset += padding;
1215         }
1216
1217         return rp;
1218 }
1219
1220 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1221                                   struct btcx_riscmem *risc,
1222                                   struct scatterlist *sglist,
1223                                   unsigned int bpl,
1224                                   unsigned int lines, unsigned int lpi)
1225 {
1226         u32 instructions;
1227         __le32 *rp;
1228         int rc;
1229
1230         /* estimate risc mem: worst case is one write per page border +
1231            one write per scan line + syncs + jump (all 2 dwords).  Here
1232            there is no padding and no sync.  First DMA region may be smaller
1233            than PAGE_SIZE */
1234         /* Jump and write need an extra dword */
1235         instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1236         instructions += 1;
1237
1238         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1239         if (rc < 0)
1240                 return rc;
1241
1242         /* write risc instructions */
1243         rp = risc->cpu;
1244         rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1245                                       lines, lpi);
1246
1247         /* save pointer to jmp instruction address */
1248         risc->jmp = rp;
1249         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1250         return 0;
1251 }
1252 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1253
1254 int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1255                          u32 reg, u32 mask, u32 value)
1256 {
1257         __le32 *rp;
1258         int rc;
1259
1260         rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1261
1262         if (rc < 0)
1263                 return rc;
1264
1265         /* write risc instructions */
1266         rp = risc->cpu;
1267
1268         *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1269         *(rp++) = cpu_to_le32(reg);
1270         *(rp++) = cpu_to_le32(value);
1271         *(rp++) = cpu_to_le32(mask);
1272         *(rp++) = cpu_to_le32(RISC_JUMP);
1273         *(rp++) = cpu_to_le32(risc->dma);
1274         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1275         return 0;
1276 }
1277
1278 void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1279 {
1280         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1281
1282         BUG_ON(in_interrupt());
1283         videobuf_waiton(q, &buf->vb, 0, 0);
1284         videobuf_dma_unmap(q->dev, dma);
1285         videobuf_dma_free(dma);
1286         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1287         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1288 }
1289
1290 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1291 {
1292         struct cx25821_dev *dev = dev_id;
1293         u32 pci_status;
1294         u32 vid_status;
1295         int i, handled = 0;
1296         u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1297
1298         pci_status = cx_read(PCI_INT_STAT);
1299
1300         if (pci_status == 0)
1301                 goto out;
1302
1303         for (i = 0; i < VID_CHANNEL_NUM; i++) {
1304                 if (pci_status & mask[i]) {
1305                         vid_status = cx_read(dev->channels[i].
1306                                 sram_channels->int_stat);
1307
1308                         if (vid_status)
1309                                 handled += cx25821_video_irq(dev, i,
1310                                                 vid_status);
1311
1312                         cx_write(PCI_INT_STAT, mask[i]);
1313                 }
1314         }
1315
1316 out:
1317         return IRQ_RETVAL(handled);
1318 }
1319
1320 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1321                            int len, u32 bits, u32 mask)
1322 {
1323         unsigned int i;
1324
1325         printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1326
1327         for (i = 0; i < len; i++) {
1328                 if (!(bits & (1 << i)))
1329                         continue;
1330                 if (strings[i])
1331                         pr_cont(" %s", strings[i]);
1332                 else
1333                         pr_cont(" %d", i);
1334                 if (!(mask & (1 << i)))
1335                         continue;
1336                 pr_cont("*");
1337         }
1338         pr_cont("\n");
1339 }
1340 EXPORT_SYMBOL(cx25821_print_irqbits);
1341
1342 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1343 {
1344         struct cx25821_dev *dev = pci_get_drvdata(pci);
1345         return dev;
1346 }
1347 EXPORT_SYMBOL(cx25821_dev_get);
1348
1349 static int cx25821_initdev(struct pci_dev *pci_dev,
1350                            const struct pci_device_id *pci_id)
1351 {
1352         struct cx25821_dev *dev;
1353         int err = 0;
1354
1355         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1356         if (NULL == dev)
1357                 return -ENOMEM;
1358
1359         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1360         if (err < 0)
1361                 goto fail_free;
1362
1363         /* pci init */
1364         dev->pci = pci_dev;
1365         if (pci_enable_device(pci_dev)) {
1366                 err = -EIO;
1367
1368                 pr_info("pci enable failed!\n");
1369
1370                 goto fail_unregister_device;
1371         }
1372
1373         pr_info("Athena pci enable !\n");
1374
1375         err = cx25821_dev_setup(dev);
1376         if (err) {
1377                 if (err == -EBUSY)
1378                         goto fail_unregister_device;
1379                 else
1380                         goto fail_unregister_pci;
1381         }
1382
1383         /* print pci info */
1384         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1385         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1386         pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1387                 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1388                 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1389
1390         pci_set_master(pci_dev);
1391         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1392                 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1393                 err = -EIO;
1394                 goto fail_irq;
1395         }
1396
1397         err = request_irq(pci_dev->irq, cx25821_irq,
1398                         IRQF_SHARED, dev->name, dev);
1399
1400         if (err < 0) {
1401                 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1402                 goto fail_irq;
1403         }
1404
1405         return 0;
1406
1407 fail_irq:
1408         pr_info("cx25821_initdev() can't get IRQ !\n");
1409         cx25821_dev_unregister(dev);
1410
1411 fail_unregister_pci:
1412         pci_disable_device(pci_dev);
1413 fail_unregister_device:
1414         v4l2_device_unregister(&dev->v4l2_dev);
1415
1416 fail_free:
1417         kfree(dev);
1418         return err;
1419 }
1420
1421 static void cx25821_finidev(struct pci_dev *pci_dev)
1422 {
1423         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1424         struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1425
1426         cx25821_shutdown(dev);
1427         pci_disable_device(pci_dev);
1428
1429         /* unregister stuff */
1430         if (pci_dev->irq)
1431                 free_irq(pci_dev->irq, dev);
1432
1433         mutex_lock(&cx25821_devlist_mutex);
1434         list_del(&dev->devlist);
1435         mutex_unlock(&cx25821_devlist_mutex);
1436
1437         cx25821_dev_unregister(dev);
1438         v4l2_device_unregister(v4l2_dev);
1439         kfree(dev);
1440 }
1441
1442 static DEFINE_PCI_DEVICE_TABLE(cx25821_pci_tbl) = {
1443         {
1444                 /* CX25821 Athena */
1445                 .vendor = 0x14f1,
1446                 .device = 0x8210,
1447                 .subvendor = 0x14f1,
1448                 .subdevice = 0x0920,
1449         }, {
1450                 /* CX25821 No Brand */
1451                 .vendor = 0x14f1,
1452                 .device = 0x8210,
1453                 .subvendor = 0x0000,
1454                 .subdevice = 0x0000,
1455         }, {
1456                 /* --- end of list --- */
1457         }
1458 };
1459
1460 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1461
1462 static struct pci_driver cx25821_pci_driver = {
1463         .name = "cx25821",
1464         .id_table = cx25821_pci_tbl,
1465         .probe = cx25821_initdev,
1466         .remove = cx25821_finidev,
1467         /* TODO */
1468         .suspend = NULL,
1469         .resume = NULL,
1470 };
1471
1472 static int __init cx25821_init(void)
1473 {
1474         pr_info("driver version %d.%d.%d loaded\n",
1475                 (CX25821_VERSION_CODE >> 16) & 0xff,
1476                 (CX25821_VERSION_CODE >> 8) & 0xff,
1477                 CX25821_VERSION_CODE & 0xff);
1478         return pci_register_driver(&cx25821_pci_driver);
1479 }
1480
1481 static void __exit cx25821_fini(void)
1482 {
1483         pci_unregister_driver(&cx25821_pci_driver);
1484 }
1485
1486 module_init(cx25821_init);
1487 module_exit(cx25821_fini);