drivers/media/i2c/s5k6aa.c

   1 /*
   2  * Driver for Samsung S5K6AAFX SXGA 1/6" 1.3M CMOS Image Sensor
   3  * with embedded SoC ISP.
   4  *
   5  * Copyright (C) 2011, Samsung Electronics Co., Ltd.
   6  * Sylwester Nawrocki <s.nawrocki@samsung.com>
   7  *
   8  * Based on a driver authored by Dongsoo Nathaniel Kim.
   9  * Copyright (C) 2009, Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/gpio.h>
  20 #include <linux/i2c.h>
  21 #include <linux/media.h>
  22 #include <linux/module.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/slab.h>
  25
  26 #include <media/media-entity.h>
  27 #include <media/v4l2-ctrls.h>
  28 #include <media/v4l2-device.h>
  29 #include <media/v4l2-subdev.h>
  30 #include <media/v4l2-mediabus.h>
  31 #include <media/i2c/s5k6aa.h>
  32
  33 static int debug;
  34 module_param(debug, int, 0644);
  35
  36 #define DRIVER_NAME                     "S5K6AA"
  37
  38 /* The token to indicate array termination */
  39 #define S5K6AA_TERM                     0xffff
  40 #define S5K6AA_OUT_WIDTH_DEF            640
  41 #define S5K6AA_OUT_HEIGHT_DEF           480
  42 #define S5K6AA_WIN_WIDTH_MAX            1280
  43 #define S5K6AA_WIN_HEIGHT_MAX           1024
  44 #define S5K6AA_WIN_WIDTH_MIN            8
  45 #define S5K6AA_WIN_HEIGHT_MIN           8
  46
  47 /*
  48  * H/W register Interface (0xD0000000 - 0xD0000FFF)
  49  */
  50 #define AHB_MSB_ADDR_PTR                0xfcfc
  51 #define GEN_REG_OFFSH                   0xd000
  52 #define REG_CMDWR_ADDRH                 0x0028
  53 #define REG_CMDWR_ADDRL                 0x002a
  54 #define REG_CMDRD_ADDRH                 0x002c
  55 #define REG_CMDRD_ADDRL                 0x002e
  56 #define REG_CMDBUF0_ADDR                0x0f12
  57 #define REG_CMDBUF1_ADDR                0x0f10
  58
  59 /*
  60  * Host S/W Register interface (0x70000000 - 0x70002000)
  61  * The value of the two most significant address bytes is 0x7000,
  62  * (HOST_SWIF_OFFS_H). The register addresses below specify 2 LSBs.
  63  */
  64 #define HOST_SWIF_OFFSH                 0x7000
  65
  66 /* Initialization parameters */
  67 /* Master clock frequency in KHz */
  68 #define REG_I_INCLK_FREQ_L              0x01b8
  69 #define REG_I_INCLK_FREQ_H              0x01ba
  70 #define  MIN_MCLK_FREQ_KHZ              6000U
  71 #define  MAX_MCLK_FREQ_KHZ              27000U
  72 #define REG_I_USE_NPVI_CLOCKS           0x01c6
  73 #define REG_I_USE_NMIPI_CLOCKS          0x01c8
  74
  75 /* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */
  76 #define REG_I_OPCLK_4KHZ(n)             ((n) * 6 + 0x01cc)
  77 #define REG_I_MIN_OUTRATE_4KHZ(n)       ((n) * 6 + 0x01ce)
  78 #define REG_I_MAX_OUTRATE_4KHZ(n)       ((n) * 6 + 0x01d0)
  79 #define  SYS_PLL_OUT_FREQ               (48000000 / 4000)
  80 #define  PCLK_FREQ_MIN                  (24000000 / 4000)
  81 #define  PCLK_FREQ_MAX                  (48000000 / 4000)
  82 #define REG_I_INIT_PARAMS_UPDATED       0x01e0
  83 #define REG_I_ERROR_INFO                0x01e2
  84
  85 /* General purpose parameters */
  86 #define REG_USER_BRIGHTNESS             0x01e4
  87 #define REG_USER_CONTRAST               0x01e6
  88 #define REG_USER_SATURATION             0x01e8
  89 #define REG_USER_SHARPBLUR              0x01ea
  90
  91 #define REG_G_SPEC_EFFECTS              0x01ee
  92 #define REG_G_ENABLE_PREV               0x01f0
  93 #define REG_G_ENABLE_PREV_CHG           0x01f2
  94 #define REG_G_NEW_CFG_SYNC              0x01f8
  95 #define REG_G_PREVZOOM_IN_WIDTH         0x020a
  96 #define REG_G_PREVZOOM_IN_HEIGHT        0x020c
  97 #define REG_G_PREVZOOM_IN_XOFFS         0x020e
  98 #define REG_G_PREVZOOM_IN_YOFFS         0x0210
  99 #define REG_G_INPUTS_CHANGE_REQ         0x021a
 100 #define REG_G_ACTIVE_PREV_CFG           0x021c
 101 #define REG_G_PREV_CFG_CHG              0x021e
 102 #define REG_G_PREV_OPEN_AFTER_CH        0x0220
 103 #define REG_G_PREV_CFG_ERROR            0x0222
 104
 105 /* Preview control section. n = 0...4. */
 106 #define PREG(n, x)                      ((n) * 0x26 + x)
 107 #define REG_P_OUT_WIDTH(n)              PREG(n, 0x0242)
 108 #define REG_P_OUT_HEIGHT(n)             PREG(n, 0x0244)
 109 #define REG_P_FMT(n)                    PREG(n, 0x0246)
 110 #define REG_P_MAX_OUT_RATE(n)           PREG(n, 0x0248)
 111 #define REG_P_MIN_OUT_RATE(n)           PREG(n, 0x024a)
 112 #define REG_P_PVI_MASK(n)               PREG(n, 0x024c)
 113 #define REG_P_CLK_INDEX(n)              PREG(n, 0x024e)
 114 #define REG_P_FR_RATE_TYPE(n)           PREG(n, 0x0250)
 115 #define  FR_RATE_DYNAMIC                0
 116 #define  FR_RATE_FIXED                  1
 117 #define  FR_RATE_FIXED_ACCURATE         2
 118 #define REG_P_FR_RATE_Q_TYPE(n)         PREG(n, 0x0252)
 119 #define  FR_RATE_Q_BEST_FRRATE          1 /* Binning enabled */
 120 #define  FR_RATE_Q_BEST_QUALITY         2 /* Binning disabled */
 121 /* Frame period in 0.1 ms units */
 122 #define REG_P_MAX_FR_TIME(n)            PREG(n, 0x0254)
 123 #define REG_P_MIN_FR_TIME(n)            PREG(n, 0x0256)
 124 /* Conversion to REG_P_[MAX/MIN]_FR_TIME value; __t: time in us */
 125 #define  US_TO_FR_TIME(__t)             ((__t) / 100)
 126 #define  S5K6AA_MIN_FR_TIME             33300  /* us */
 127 #define  S5K6AA_MAX_FR_TIME             650000 /* us */
 128 #define  S5K6AA_MAX_HIGHRES_FR_TIME     666    /* x100 us */
 129 /* The below 5 registers are for "device correction" values */
 130 #define REG_P_COLORTEMP(n)              PREG(n, 0x025e)
 131 #define REG_P_PREV_MIRROR(n)            PREG(n, 0x0262)
 132
 133 /* Extended image property controls */
 134 /* Exposure time in 10 us units */
 135 #define REG_SF_USR_EXPOSURE_L           0x03c6
 136 #define REG_SF_USR_EXPOSURE_H           0x03c8
 137 #define REG_SF_USR_EXPOSURE_CHG         0x03ca
 138 #define REG_SF_USR_TOT_GAIN             0x03cc
 139 #define REG_SF_USR_TOT_GAIN_CHG         0x03ce
 140 #define REG_SF_RGAIN                    0x03d0
 141 #define REG_SF_RGAIN_CHG                0x03d2
 142 #define REG_SF_GGAIN                    0x03d4
 143 #define REG_SF_GGAIN_CHG                0x03d6
 144 #define REG_SF_BGAIN                    0x03d8
 145 #define REG_SF_BGAIN_CHG                0x03da
 146 #define REG_SF_FLICKER_QUANT            0x03dc
 147 #define REG_SF_FLICKER_QUANT_CHG        0x03de
 148
 149 /* Output interface (parallel/MIPI) setup */
 150 #define REG_OIF_EN_MIPI_LANES           0x03fa
 151 #define REG_OIF_EN_PACKETS              0x03fc
 152 #define REG_OIF_CFG_CHG                 0x03fe
 153
 154 /* Auto-algorithms enable mask */
 155 #define REG_DBG_AUTOALG_EN              0x0400
 156 #define  AALG_ALL_EN_MASK               (1 << 0)
 157 #define  AALG_AE_EN_MASK                (1 << 1)
 158 #define  AALG_DIVLEI_EN_MASK            (1 << 2)
 159 #define  AALG_WB_EN_MASK                (1 << 3)
 160 #define  AALG_FLICKER_EN_MASK           (1 << 5)
 161 #define  AALG_FIT_EN_MASK               (1 << 6)
 162 #define  AALG_WRHW_EN_MASK              (1 << 7)
 163
 164 /* Firmware revision information */
 165 #define REG_FW_APIVER                   0x012e
 166 #define  S5K6AAFX_FW_APIVER             0x0001
 167 #define REG_FW_REVISION                 0x0130
 168
 169 /* For now we use only one user configuration register set */
 170 #define S5K6AA_MAX_PRESETS              1
 171
 172 static const char * const s5k6aa_supply_names[] = {
 173         "vdd_core",     /* Digital core supply 1.5V (1.4V to 1.6V) */
 174         "vdda",         /* Analog power supply 2.8V (2.6V to 3.0V) */
 175         "vdd_reg",      /* Regulator input power 1.8V (1.7V to 1.9V)
 176                            or 2.8V (2.6V to 3.0) */
 177         "vddio",        /* I/O supply 1.8V (1.65V to 1.95V)
 178                            or 2.8V (2.5V to 3.1V) */
 179 };
 180 #define S5K6AA_NUM_SUPPLIES ARRAY_SIZE(s5k6aa_supply_names)
 181
 182 enum s5k6aa_gpio_id {
 183         STBY,
 184         RST,
 185         GPIO_NUM,
 186 };
 187
 188 struct s5k6aa_regval {
 189         u16 addr;
 190         u16 val;
 191 };
 192
 193 struct s5k6aa_pixfmt {
 194         u32 code;
 195         u32 colorspace;
 196         /* REG_P_FMT(x) register value */
 197         u16 reg_p_fmt;
 198 };
 199
 200 struct s5k6aa_preset {
 201         /* output pixel format and resolution */
 202         struct v4l2_mbus_framefmt mbus_fmt;
 203         u8 clk_id;
 204         u8 index;
 205 };
 206
 207 struct s5k6aa_ctrls {
 208         struct v4l2_ctrl_handler handler;
 209         /* Auto / manual white balance cluster */
 210         struct v4l2_ctrl *awb;
 211         struct v4l2_ctrl *gain_red;
 212         struct v4l2_ctrl *gain_blue;
 213         struct v4l2_ctrl *gain_green;
 214         /* Mirror cluster */
 215         struct v4l2_ctrl *hflip;
 216         struct v4l2_ctrl *vflip;
 217         /* Auto exposure / manual exposure and gain cluster */
 218         struct v4l2_ctrl *auto_exp;
 219         struct v4l2_ctrl *exposure;
 220         struct v4l2_ctrl *gain;
 221 };
 222
 223 struct s5k6aa_interval {
 224         u16 reg_fr_time;
 225         struct v4l2_fract interval;
 226         /* Maximum rectangle for the interval */
 227         struct v4l2_frmsize_discrete size;
 228 };
 229
 230 struct s5k6aa {
 231         struct v4l2_subdev sd;
 232         struct media_pad pad;
 233
 234         enum v4l2_mbus_type bus_type;
 235         u8 mipi_lanes;
 236
 237         int (*s_power)(int enable);
 238         struct regulator_bulk_data supplies[S5K6AA_NUM_SUPPLIES];
 239         struct s5k6aa_gpio gpio[GPIO_NUM];
 240
 241         /* external master clock frequency */
 242         unsigned long mclk_frequency;
 243         /* ISP internal master clock frequency */
 244         u16 clk_fop;
 245         /* output pixel clock frequency range */
 246         u16 pclk_fmin;
 247         u16 pclk_fmax;
 248
 249         unsigned int inv_hflip:1;
 250         unsigned int inv_vflip:1;
 251
 252         /* protects the struct members below */
 253         struct mutex lock;
 254
 255         /* sensor matrix scan window */
 256         struct v4l2_rect ccd_rect;
 257
 258         struct s5k6aa_ctrls ctrls;
 259         struct s5k6aa_preset presets[S5K6AA_MAX_PRESETS];
 260         struct s5k6aa_preset *preset;
 261         const struct s5k6aa_interval *fiv;
 262
 263         unsigned int streaming:1;
 264         unsigned int apply_cfg:1;
 265         unsigned int apply_crop:1;
 266         unsigned int power;
 267 };
 268
 269 static struct s5k6aa_regval s5k6aa_analog_config[] = {
 270         /* Analog settings */
 271         { 0x112a, 0x0000 }, { 0x1132, 0x0000 },
 272         { 0x113e, 0x0000 }, { 0x115c, 0x0000 },
 273         { 0x1164, 0x0000 }, { 0x1174, 0x0000 },
 274         { 0x1178, 0x0000 }, { 0x077a, 0x0000 },
 275         { 0x077c, 0x0000 }, { 0x077e, 0x0000 },
 276         { 0x0780, 0x0000 }, { 0x0782, 0x0000 },
 277         { 0x0784, 0x0000 }, { 0x0786, 0x0000 },
 278         { 0x0788, 0x0000 }, { 0x07a2, 0x0000 },
 279         { 0x07a4, 0x0000 }, { 0x07a6, 0x0000 },
 280         { 0x07a8, 0x0000 }, { 0x07b6, 0x0000 },
 281         { 0x07b8, 0x0002 }, { 0x07ba, 0x0004 },
 282         { 0x07bc, 0x0004 }, { 0x07be, 0x0005 },
 283         { 0x07c0, 0x0005 }, { S5K6AA_TERM, 0 },
 284 };
 285
 286 /* TODO: Add RGB888 and Bayer format */
 287 static const struct s5k6aa_pixfmt s5k6aa_formats[] = {
 288         { MEDIA_BUS_FMT_YUYV8_2X8,      V4L2_COLORSPACE_JPEG,   5 },
 289         /* range 16-240 */
 290         { MEDIA_BUS_FMT_YUYV8_2X8,      V4L2_COLORSPACE_REC709, 6 },
 291         { MEDIA_BUS_FMT_RGB565_2X8_BE,  V4L2_COLORSPACE_JPEG,   0 },
 292 };
 293
 294 static const struct s5k6aa_interval s5k6aa_intervals[] = {
 295         { 1000, {10000, 1000000}, {1280, 1024} }, /* 10 fps */
 296         { 666,  {15000, 1000000}, {1280, 1024} }, /* 15 fps */
 297         { 500,  {20000, 1000000}, {1280, 720} },  /* 20 fps */
 298         { 400,  {25000, 1000000}, {640, 480} },   /* 25 fps */
 299         { 333,  {33300, 1000000}, {640, 480} },   /* 30 fps */
 300 };
 301
 302 #define S5K6AA_INTERVAL_DEF_INDEX 1 /* 15 fps */
 303
 304 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
 305 {
 306         return &container_of(ctrl->handler, struct s5k6aa, ctrls.handler)->sd;
 307 }
 308
 309 static inline struct s5k6aa *to_s5k6aa(struct v4l2_subdev *sd)
 310 {
 311         return container_of(sd, struct s5k6aa, sd);
 312 }
 313
 314 /* Set initial values for all preview presets */
 315 static void s5k6aa_presets_data_init(struct s5k6aa *s5k6aa)
 316 {
 317         struct s5k6aa_preset *preset = &s5k6aa->presets[0];
 318         int i;
 319
 320         for (i = 0; i < S5K6AA_MAX_PRESETS; i++) {
 321                 preset->mbus_fmt.width  = S5K6AA_OUT_WIDTH_DEF;
 322                 preset->mbus_fmt.height = S5K6AA_OUT_HEIGHT_DEF;
 323                 preset->mbus_fmt.code   = s5k6aa_formats[0].code;
 324                 preset->index           = i;
 325                 preset->clk_id          = 0;
 326                 preset++;
 327         }
 328
 329         s5k6aa->fiv = &s5k6aa_intervals[S5K6AA_INTERVAL_DEF_INDEX];
 330         s5k6aa->preset = &s5k6aa->presets[0];
 331 }
 332
 333 static int s5k6aa_i2c_read(struct i2c_client *client, u16 addr, u16 *val)
 334 {
 335         u8 wbuf[2] = {addr >> 8, addr & 0xFF};
 336         struct i2c_msg msg[2];
 337         u8 rbuf[2];
 338         int ret;
 339
 340         msg[0].addr = client->addr;
 341         msg[0].flags = 0;
 342         msg[0].len = 2;
 343         msg[0].buf = wbuf;
 344
 345         msg[1].addr = client->addr;
 346         msg[1].flags = I2C_M_RD;
 347         msg[1].len = 2;
 348         msg[1].buf = rbuf;
 349
 350         ret = i2c_transfer(client->adapter, msg, 2);
 351         *val = be16_to_cpu(*((__be16 *)rbuf));
 352
 353         v4l2_dbg(3, debug, client, "i2c_read: 0x%04X : 0x%04x\n", addr, *val);
 354
 355         return ret == 2 ? 0 : ret;
 356 }
 357
 358 static int s5k6aa_i2c_write(struct i2c_client *client, u16 addr, u16 val)
 359 {
 360         u8 buf[4] = {addr >> 8, addr & 0xFF, val >> 8, val & 0xFF};
 361
 362         int ret = i2c_master_send(client, buf, 4);
 363         v4l2_dbg(3, debug, client, "i2c_write: 0x%04X : 0x%04x\n", addr, val);
 364
 365         return ret == 4 ? 0 : ret;
 366 }
 367
 368 /* The command register write, assumes Command_Wr_addH = 0x7000. */
 369 static int s5k6aa_write(struct i2c_client *c, u16 addr, u16 val)
 370 {
 371         int ret = s5k6aa_i2c_write(c, REG_CMDWR_ADDRL, addr);
 372         if (ret)
 373                 return ret;
 374         return s5k6aa_i2c_write(c, REG_CMDBUF0_ADDR, val);
 375 }
 376
 377 /* The command register read, assumes Command_Rd_addH = 0x7000. */
 378 static int s5k6aa_read(struct i2c_client *client, u16 addr, u16 *val)
 379 {
 380         int ret = s5k6aa_i2c_write(client, REG_CMDRD_ADDRL, addr);
 381         if (ret)
 382                 return ret;
 383         return s5k6aa_i2c_read(client, REG_CMDBUF0_ADDR, val);
 384 }
 385
 386 static int s5k6aa_write_array(struct v4l2_subdev *sd,
 387                               const struct s5k6aa_regval *msg)
 388 {
 389         struct i2c_client *client = v4l2_get_subdevdata(sd);
 390         u16 addr_incr = 0;
 391         int ret = 0;
 392
 393         while (msg->addr != S5K6AA_TERM) {
 394                 if (addr_incr != 2)
 395                         ret = s5k6aa_i2c_write(client, REG_CMDWR_ADDRL,
 396                                                msg->addr);
 397                 if (ret)
 398                         break;
 399                 ret = s5k6aa_i2c_write(client, REG_CMDBUF0_ADDR, msg->val);
 400                 if (ret)
 401                         break;
 402                 /* Assume that msg->addr is always less than 0xfffc */
 403                 addr_incr = (msg + 1)->addr - msg->addr;
 404                 msg++;
 405         }
 406
 407         return ret;
 408 }
 409
 410 /* Configure the AHB high address bytes for GTG registers access */
 411 static int s5k6aa_set_ahb_address(struct i2c_client *client)
 412 {
 413         int ret = s5k6aa_i2c_write(client, AHB_MSB_ADDR_PTR, GEN_REG_OFFSH);
 414         if (ret)
 415                 return ret;
 416         ret = s5k6aa_i2c_write(client, REG_CMDRD_ADDRH, HOST_SWIF_OFFSH);
 417         if (ret)
 418                 return ret;
 419         return s5k6aa_i2c_write(client, REG_CMDWR_ADDRH, HOST_SWIF_OFFSH);
 420 }
 421
 422 /**
 423  * s5k6aa_configure_pixel_clock - apply ISP main clock/PLL configuration
 424  * @s5k6aa: pointer to &struct s5k6aa describing the device
 425  *
 426  * Configure the internal ISP PLL for the required output frequency.
 427  * Locking: called with s5k6aa.lock mutex held.
 428  */
 429 static int s5k6aa_configure_pixel_clocks(struct s5k6aa *s5k6aa)
 430 {
 431         struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
 432         unsigned long fmclk = s5k6aa->mclk_frequency / 1000;
 433         u16 status;
 434         int ret;
 435
 436         if (WARN(fmclk < MIN_MCLK_FREQ_KHZ || fmclk > MAX_MCLK_FREQ_KHZ,
 437                  "Invalid clock frequency: %ld\n", fmclk))
 438                 return -EINVAL;
 439
 440         s5k6aa->pclk_fmin = PCLK_FREQ_MIN;
 441         s5k6aa->pclk_fmax = PCLK_FREQ_MAX;
 442         s5k6aa->clk_fop = SYS_PLL_OUT_FREQ;
 443
 444         /* External input clock frequency in kHz */
 445         ret = s5k6aa_write(c, REG_I_INCLK_FREQ_H, fmclk >> 16);
 446         if (!ret)
 447                 ret = s5k6aa_write(c, REG_I_INCLK_FREQ_L, fmclk & 0xFFFF);
 448         if (!ret)
 449                 ret = s5k6aa_write(c, REG_I_USE_NPVI_CLOCKS, 1);
 450         /* Internal PLL frequency */
 451         if (!ret)
 452                 ret = s5k6aa_write(c, REG_I_OPCLK_4KHZ(0), s5k6aa->clk_fop);
 453         if (!ret)
 454                 ret = s5k6aa_write(c, REG_I_MIN_OUTRATE_4KHZ(0),
 455                                    s5k6aa->pclk_fmin);
 456         if (!ret)
 457                 ret = s5k6aa_write(c, REG_I_MAX_OUTRATE_4KHZ(0),
 458                                    s5k6aa->pclk_fmax);
 459         if (!ret)
 460                 ret = s5k6aa_write(c, REG_I_INIT_PARAMS_UPDATED, 1);
 461         if (!ret)
 462                 ret = s5k6aa_read(c, REG_I_ERROR_INFO, &status);
 463
 464         return ret ? ret : (status ? -EINVAL : 0);
 465 }
 466
 467 /* Set horizontal and vertical image flipping */
 468 static int s5k6aa_set_mirror(struct s5k6aa *s5k6aa, int horiz_flip)
 469 {
 470         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
 471         int index = s5k6aa->preset->index;
 472
 473         unsigned int vflip = s5k6aa->ctrls.vflip->val ^ s5k6aa->inv_vflip;
 474         unsigned int flip = (horiz_flip ^ s5k6aa->inv_hflip) | (vflip << 1);
 475
 476         return s5k6aa_write(client, REG_P_PREV_MIRROR(index), flip);
 477 }
 478
 479 /* Configure auto/manual white balance and R/G/B gains */
 480 static int s5k6aa_set_awb(struct s5k6aa *s5k6aa, int awb)
 481 {
 482         struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
 483         struct s5k6aa_ctrls *ctrls = &s5k6aa->ctrls;
 484         u16 reg;
 485
 486         int ret = s5k6aa_read(c, REG_DBG_AUTOALG_EN, &reg);
 487
 488         if (!ret && !awb) {
 489                 ret = s5k6aa_write(c, REG_SF_RGAIN, ctrls->gain_red->val);
 490                 if (!ret)
 491                         ret = s5k6aa_write(c, REG_SF_RGAIN_CHG, 1);
 492                 if (ret)
 493                         return ret;
 494
 495                 ret = s5k6aa_write(c, REG_SF_GGAIN, ctrls->gain_green->val);
 496                 if (!ret)
 497                         ret = s5k6aa_write(c, REG_SF_GGAIN_CHG, 1);
 498                 if (ret)
 499                         return ret;
 500
 501                 ret = s5k6aa_write(c, REG_SF_BGAIN, ctrls->gain_blue->val);
 502                 if (!ret)
 503                         ret = s5k6aa_write(c, REG_SF_BGAIN_CHG, 1);
 504         }
 505         if (!ret) {
 506                 reg = awb ? reg | AALG_WB_EN_MASK : reg & ~AALG_WB_EN_MASK;
 507                 ret = s5k6aa_write(c, REG_DBG_AUTOALG_EN, reg);
 508         }
 509
 510         return ret;
 511 }
 512
 513 /* Program FW with exposure time, 'exposure' in us units */
 514 static int s5k6aa_set_user_exposure(struct i2c_client *client, int exposure)
 515 {
 516         unsigned int time = exposure / 10;
 517
 518         int ret = s5k6aa_write(client, REG_SF_USR_EXPOSURE_L, time & 0xffff);
 519         if (!ret)
 520                 ret = s5k6aa_write(client, REG_SF_USR_EXPOSURE_H, time >> 16);
 521         if (ret)
 522                 return ret;
 523         return s5k6aa_write(client, REG_SF_USR_EXPOSURE_CHG, 1);
 524 }
 525
 526 static int s5k6aa_set_user_gain(struct i2c_client *client, int gain)
 527 {
 528         int ret = s5k6aa_write(client, REG_SF_USR_TOT_GAIN, gain);
 529         if (ret)
 530                 return ret;
 531         return s5k6aa_write(client, REG_SF_USR_TOT_GAIN_CHG, 1);
 532 }
 533
 534 /* Set auto/manual exposure and total gain */
 535 static int s5k6aa_set_auto_exposure(struct s5k6aa *s5k6aa, int value)
 536 {
 537         struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
 538         unsigned int exp_time = s5k6aa->ctrls.exposure->val;
 539         u16 auto_alg;
 540
 541         int ret = s5k6aa_read(c, REG_DBG_AUTOALG_EN, &auto_alg);
 542         if (ret)
 543                 return ret;
 544
 545         v4l2_dbg(1, debug, c, "man_exp: %d, auto_exp: %d, a_alg: 0x%x\n",
 546                  exp_time, value, auto_alg);
 547
 548         if (value == V4L2_EXPOSURE_AUTO) {
 549                 auto_alg |= AALG_AE_EN_MASK | AALG_DIVLEI_EN_MASK;
 550         } else {
 551                 ret = s5k6aa_set_user_exposure(c, exp_time);
 552                 if (ret)
 553                         return ret;
 554                 ret = s5k6aa_set_user_gain(c, s5k6aa->ctrls.gain->val);
 555                 if (ret)
 556                         return ret;
 557                 auto_alg &= ~(AALG_AE_EN_MASK | AALG_DIVLEI_EN_MASK);
 558         }
 559
 560         return s5k6aa_write(c, REG_DBG_AUTOALG_EN, auto_alg);
 561 }
 562
 563 static int s5k6aa_set_anti_flicker(struct s5k6aa *s5k6aa, int value)
 564 {
 565         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
 566         u16 auto_alg;
 567         int ret;
 568
 569         ret = s5k6aa_read(client, REG_DBG_AUTOALG_EN, &auto_alg);
 570         if (ret)
 571                 return ret;
 572
 573         if (value == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) {
 574                 auto_alg |= AALG_FLICKER_EN_MASK;
 575         } else {
 576                 auto_alg &= ~AALG_FLICKER_EN_MASK;
 577                 /* The V4L2_CID_LINE_FREQUENCY control values match
 578                  * the register values */
 579                 ret = s5k6aa_write(client, REG_SF_FLICKER_QUANT, value);
 580                 if (ret)
 581                         return ret;
 582                 ret = s5k6aa_write(client, REG_SF_FLICKER_QUANT_CHG, 1);
 583                 if (ret)
 584                         return ret;
 585         }
 586
 587         return s5k6aa_write(client, REG_DBG_AUTOALG_EN, auto_alg);
 588 }
 589
 590 static int s5k6aa_set_colorfx(struct s5k6aa *s5k6aa, int val)
 591 {
 592         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
 593         static const struct v4l2_control colorfx[] = {
 594                 { V4L2_COLORFX_NONE,     0 },
 595                 { V4L2_COLORFX_BW,       1 },
 596                 { V4L2_COLORFX_NEGATIVE, 2 },
 597                 { V4L2_COLORFX_SEPIA,    3 },
 598                 { V4L2_COLORFX_SKY_BLUE, 4 },
 599                 { V4L2_COLORFX_SKETCH,   5 },
 600         };
 601         int i;
 602
 603         for (i = 0; i < ARRAY_SIZE(colorfx); i++) {
 604                 if (colorfx[i].id == val)
 605                         return s5k6aa_write(client, REG_G_SPEC_EFFECTS,
 606                                             colorfx[i].value);
 607         }
 608         return -EINVAL;
 609 }
 610
 611 static int s5k6aa_preview_config_status(struct i2c_client *client)
 612 {
 613         u16 error = 0;
 614         int ret = s5k6aa_read(client, REG_G_PREV_CFG_ERROR, &error);
 615
 616         v4l2_dbg(1, debug, client, "error: 0x%x (%d)\n", error, ret);
 617         return ret ? ret : (error ? -EINVAL : 0);
 618 }
 619
 620 static int s5k6aa_get_pixfmt_index(struct s5k6aa *s5k6aa,
 621                                    struct v4l2_mbus_framefmt *mf)
 622 {
 623         unsigned int i;
 624
 625         for (i = 0; i < ARRAY_SIZE(s5k6aa_formats); i++)
 626                 if (mf->colorspace == s5k6aa_formats[i].colorspace &&
 627                     mf->code == s5k6aa_formats[i].code)
 628                         return i;
 629         return 0;
 630 }
 631
 632 static int s5k6aa_set_output_framefmt(struct s5k6aa *s5k6aa,
 633                                       struct s5k6aa_preset *preset)
 634 {
 635         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
 636         int fmt_index = s5k6aa_get_pixfmt_index(s5k6aa, &preset->mbus_fmt);
 637         int ret;
 638
 639         ret = s5k6aa_write(client, REG_P_OUT_WIDTH(preset->index),
 640                            preset->mbus_fmt.width);
 641         if (!ret)
 642                 ret = s5k6aa_write(client, REG_P_OUT_HEIGHT(preset->index),
 643                                    preset->mbus_fmt.height);
 644         if (!ret)
 645                 ret = s5k6aa_write(client, REG_P_FMT(preset->index),
 646                                    s5k6aa_formats[fmt_index].reg_p_fmt);
 647         return ret;
 648 }
 649
 650 static int s5k6aa_set_input_params(struct s5k6aa *s5k6aa)
 651 {
 652         struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
 653         struct v4l2_rect *r = &s5k6aa->ccd_rect;
 654         int ret;
 655
 656         ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_WIDTH, r->width);
 657         if (!ret)
 658                 ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_HEIGHT, r->height);
 659         if (!ret)
 660                 ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_XOFFS, r->left);
 661         if (!ret)
 662                 ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_YOFFS, r->top);
 663         if (!ret)
 664                 ret = s5k6aa_write(c, REG_G_INPUTS_CHANGE_REQ, 1);
 665         if (!ret)
 666                 s5k6aa->apply_crop = 0;
 667
 668         return ret;
 669 }
 670
 671 /**
 672  * s5k6aa_configure_video_bus - configure the video output interface
 673  * @s5k6aa: pointer to &struct s5k6aa describing the device
 674  * @bus_type: video bus type: parallel or MIPI-CSI
 675  * @nlanes: number of MIPI lanes to be used (MIPI-CSI only)
 676  *
 677  * Note: Only parallel bus operation has been tested.
 678  */
 679 static int s5k6aa_configure_video_bus(struct s5k6aa *s5k6aa,
 680                                       enum v4l2_mbus_type bus_type, int nlanes)
 681 {
 682         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
 683         u16 cfg = 0;
 684         int ret;
 685
 686         /*
 687          * TODO: The sensor is supposed to support BT.601 and BT.656
 688          * but there is nothing indicating how to switch between both
 689          * in the datasheet. For now default BT.601 interface is assumed.
 690          */
 691         if (bus_type == V4L2_MBUS_CSI2)
 692                 cfg = nlanes;
 693         else if (bus_type != V4L2_MBUS_PARALLEL)
 694                 return -EINVAL;
 695
 696         ret = s5k6aa_write(client, REG_OIF_EN_MIPI_LANES, cfg);
 697         if (ret)
 698                 return ret;
 699         return s5k6aa_write(client, REG_OIF_CFG_CHG, 1);
 700 }
 701
 702 /* This function should be called when switching to new user configuration set*/
 703 static int s5k6aa_new_config_sync(struct i2c_client *client, int timeout,
 704                                   int cid)
 705 {
 706         unsigned long end = jiffies + msecs_to_jiffies(timeout);
 707         u16 reg = 1;
 708         int ret;
 709
 710         ret = s5k6aa_write(client, REG_G_ACTIVE_PREV_CFG, cid);
 711         if (!ret)
 712                 ret = s5k6aa_write(client, REG_G_PREV_CFG_CHG, 1);
 713         if (!ret)
 714                 ret = s5k6aa_write(client, REG_G_NEW_CFG_SYNC, 1);
 715         if (timeout == 0)
 716                 return ret;
 717
 718         while (ret >= 0 && time_is_after_jiffies(end)) {
 719                 ret = s5k6aa_read(client, REG_G_NEW_CFG_SYNC, &reg);
 720                 if (!reg)
 721                         return 0;
 722                 usleep_range(1000, 5000);
 723         }
 724         return ret ? ret : -ETIMEDOUT;
 725 }
 726
 727 /**
 728  * s5k6aa_set_prev_config - write user preview register set
 729  * @s5k6aa: pointer to &struct s5k6aa describing the device
 730  * @preset: s5kaa preset to be applied
 731  *
 732  * Configure output resolution and color fromat, pixel clock
 733  * frequency range, device frame rate type and frame period range.
 734  */
 735 static int s5k6aa_set_prev_config(struct s5k6aa *s5k6aa,
 736                                   struct s5k6aa_preset *preset)
 737 {
 738         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
 739         int idx = preset->index;
 740         u16 frame_rate_q;
 741         int ret;
 742
 743         if (s5k6aa->fiv->reg_fr_time >= S5K6AA_MAX_HIGHRES_FR_TIME)
 744                 frame_rate_q = FR_RATE_Q_BEST_FRRATE;
 745         else
 746                 frame_rate_q = FR_RATE_Q_BEST_QUALITY;
 747
 748         ret = s5k6aa_set_output_framefmt(s5k6aa, preset);
 749         if (!ret)
 750                 ret = s5k6aa_write(client, REG_P_MAX_OUT_RATE(idx),
 751                                    s5k6aa->pclk_fmax);
 752         if (!ret)
 753                 ret = s5k6aa_write(client, REG_P_MIN_OUT_RATE(idx),
 754                                    s5k6aa->pclk_fmin);
 755         if (!ret)
 756                 ret = s5k6aa_write(client, REG_P_CLK_INDEX(idx),
 757                                    preset->clk_id);
 758         if (!ret)
 759                 ret = s5k6aa_write(client, REG_P_FR_RATE_TYPE(idx),
 760                                    FR_RATE_DYNAMIC);
 761         if (!ret)
 762                 ret = s5k6aa_write(client, REG_P_FR_RATE_Q_TYPE(idx),
 763                                    frame_rate_q);
 764         if (!ret)
 765                 ret = s5k6aa_write(client, REG_P_MAX_FR_TIME(idx),
 766                                    s5k6aa->fiv->reg_fr_time + 33);
 767         if (!ret)
 768                 ret = s5k6aa_write(client, REG_P_MIN_FR_TIME(idx),
 769                                    s5k6aa->fiv->reg_fr_time - 33);
 770         if (!ret)
 771                 ret = s5k6aa_new_config_sync(client, 250, idx);
 772         if (!ret)
 773                 ret = s5k6aa_preview_config_status(client);
 774         if (!ret)
 775                 s5k6aa->apply_cfg = 0;
 776
 777         v4l2_dbg(1, debug, client, "Frame interval: %d +/- 3.3ms. (%d)\n",
 778                  s5k6aa->fiv->reg_fr_time, ret);
 779         return ret;
 780 }
 781
 782 /**
 783  * s5k6aa_initialize_isp - basic ISP MCU initialization
 784  * @sd: pointer to V4L2 sub-device descriptor
 785  *
 786  * Configure AHB addresses for registers read/write; configure PLLs for
 787  * required output pixel clock. The ISP power supply needs to be already
 788  * enabled, with an optional H/W reset.
 789  * Locking: called with s5k6aa.lock mutex held.
 790  */
 791 static int s5k6aa_initialize_isp(struct v4l2_subdev *sd)
 792 {
 793         struct i2c_client *client = v4l2_get_subdevdata(sd);
 794         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
 795         int ret;
 796
 797         s5k6aa->apply_crop = 1;
 798         s5k6aa->apply_cfg = 1;
 799         msleep(100);
 800
 801         ret = s5k6aa_set_ahb_address(client);
 802         if (ret)
 803                 return ret;
 804         ret = s5k6aa_configure_video_bus(s5k6aa, s5k6aa->bus_type,
 805                                          s5k6aa->mipi_lanes);
 806         if (ret)
 807                 return ret;
 808         ret = s5k6aa_write_array(sd, s5k6aa_analog_config);
 809         if (ret)
 810                 return ret;
 811         msleep(20);
 812
 813         return s5k6aa_configure_pixel_clocks(s5k6aa);
 814 }
 815
 816 static int s5k6aa_gpio_set_value(struct s5k6aa *priv, int id, u32 val)
 817 {
 818         if (!gpio_is_valid(priv->gpio[id].gpio))
 819                 return 0;
 820         gpio_set_value(priv->gpio[id].gpio, !!val);
 821         return 1;
 822 }
 823
 824 static int s5k6aa_gpio_assert(struct s5k6aa *priv, int id)
 825 {
 826         return s5k6aa_gpio_set_value(priv, id, priv->gpio[id].level);
 827 }
 828
 829 static int s5k6aa_gpio_deassert(struct s5k6aa *priv, int id)
 830 {
 831         return s5k6aa_gpio_set_value(priv, id, !priv->gpio[id].level);
 832 }
 833
 834 static int __s5k6aa_power_on(struct s5k6aa *s5k6aa)
 835 {
 836         int ret;
 837
 838         ret = regulator_bulk_enable(S5K6AA_NUM_SUPPLIES, s5k6aa->supplies);
 839         if (ret)
 840                 return ret;
 841         if (s5k6aa_gpio_deassert(s5k6aa, STBY))
 842                 usleep_range(150, 200);
 843
 844         if (s5k6aa->s_power)
 845                 ret = s5k6aa->s_power(1);
 846         usleep_range(4000, 5000);
 847
 848         if (s5k6aa_gpio_deassert(s5k6aa, RST))
 849                 msleep(20);
 850
 851         return ret;
 852 }
 853
 854 static int __s5k6aa_power_off(struct s5k6aa *s5k6aa)
 855 {
 856         int ret;
 857
 858         if (s5k6aa_gpio_assert(s5k6aa, RST))
 859                 usleep_range(100, 150);
 860
 861         if (s5k6aa->s_power) {
 862                 ret = s5k6aa->s_power(0);
 863                 if (ret)
 864                         return ret;
 865         }
 866         if (s5k6aa_gpio_assert(s5k6aa, STBY))
 867                 usleep_range(50, 100);
 868         s5k6aa->streaming = 0;
 869
 870         return regulator_bulk_disable(S5K6AA_NUM_SUPPLIES, s5k6aa->supplies);
 871 }
 872
 873 /*
 874  * V4L2 subdev core and video operations
 875  */
 876 static int s5k6aa_set_power(struct v4l2_subdev *sd, int on)
 877 {
 878         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
 879         int ret = 0;
 880
 881         mutex_lock(&s5k6aa->lock);
 882
 883         if (s5k6aa->power == !on) {
 884                 if (on) {
 885                         ret = __s5k6aa_power_on(s5k6aa);
 886                         if (!ret)
 887                                 ret = s5k6aa_initialize_isp(sd);
 888                 } else {
 889                         ret = __s5k6aa_power_off(s5k6aa);
 890                 }
 891
 892                 if (!ret)
 893                         s5k6aa->power += on ? 1 : -1;
 894         }
 895
 896         mutex_unlock(&s5k6aa->lock);
 897
 898         if (!on || ret || s5k6aa->power != 1)
 899                 return ret;
 900
 901         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
 902 }
 903
 904 static int __s5k6aa_stream(struct s5k6aa *s5k6aa, int enable)
 905 {
 906         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
 907         int ret = 0;
 908
 909         ret = s5k6aa_write(client, REG_G_ENABLE_PREV, enable);
 910         if (!ret)
 911                 ret = s5k6aa_write(client, REG_G_ENABLE_PREV_CHG, 1);
 912         if (!ret)
 913                 s5k6aa->streaming = enable;
 914
 915         return ret;
 916 }
 917
 918 static int s5k6aa_s_stream(struct v4l2_subdev *sd, int on)
 919 {
 920         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
 921         int ret = 0;
 922
 923         mutex_lock(&s5k6aa->lock);
 924
 925         if (s5k6aa->streaming == !on) {
 926                 if (!ret && s5k6aa->apply_cfg)
 927                         ret = s5k6aa_set_prev_config(s5k6aa, s5k6aa->preset);
 928                 if (s5k6aa->apply_crop)
 929                         ret = s5k6aa_set_input_params(s5k6aa);
 930                 if (!ret)
 931                         ret = __s5k6aa_stream(s5k6aa, !!on);
 932         }
 933         mutex_unlock(&s5k6aa->lock);
 934
 935         return ret;
 936 }
 937
 938 static int s5k6aa_g_frame_interval(struct v4l2_subdev *sd,
 939                                    struct v4l2_subdev_frame_interval *fi)
 940 {
 941         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
 942
 943         mutex_lock(&s5k6aa->lock);
 944         fi->interval = s5k6aa->fiv->interval;
 945         mutex_unlock(&s5k6aa->lock);
 946
 947         return 0;
 948 }
 949
 950 static int __s5k6aa_set_frame_interval(struct s5k6aa *s5k6aa,
 951                                        struct v4l2_subdev_frame_interval *fi)
 952 {
 953         struct v4l2_mbus_framefmt *mbus_fmt = &s5k6aa->preset->mbus_fmt;
 954         const struct s5k6aa_interval *fiv = &s5k6aa_intervals[0];
 955         unsigned int err, min_err = UINT_MAX;
 956         unsigned int i, fr_time;
 957
 958         if (fi->interval.denominator == 0)
 959                 return -EINVAL;
 960
 961         fr_time = fi->interval.numerator * 10000 / fi->interval.denominator;
 962
 963         for (i = 0; i < ARRAY_SIZE(s5k6aa_intervals); i++) {
 964                 const struct s5k6aa_interval *iv = &s5k6aa_intervals[i];
 965
 966                 if (mbus_fmt->width > iv->size.width ||
 967                     mbus_fmt->height > iv->size.height)
 968                         continue;
 969
 970                 err = abs(iv->reg_fr_time - fr_time);
 971                 if (err < min_err) {
 972                         fiv = iv;
 973                         min_err = err;
 974                 }
 975         }
 976         s5k6aa->fiv = fiv;
 977
 978         v4l2_dbg(1, debug, &s5k6aa->sd, "Changed frame interval to %d us\n",
 979                  fiv->reg_fr_time * 100);
 980         return 0;
 981 }
 982
 983 static int s5k6aa_s_frame_interval(struct v4l2_subdev *sd,
 984                                    struct v4l2_subdev_frame_interval *fi)
 985 {
 986         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
 987         int ret;
 988
 989         v4l2_dbg(1, debug, sd, "Setting %d/%d frame interval\n",
 990                  fi->interval.numerator, fi->interval.denominator);
 991
 992         mutex_lock(&s5k6aa->lock);
 993         ret = __s5k6aa_set_frame_interval(s5k6aa, fi);
 994         s5k6aa->apply_cfg = 1;
 995
 996         mutex_unlock(&s5k6aa->lock);
 997         return ret;
 998 }
 999
1000 /*
1001  * V4L2 subdev pad level and video operations
1002  */
1003 static int s5k6aa_enum_frame_interval(struct v4l2_subdev *sd,
1004                               struct v4l2_subdev_pad_config *cfg,
1005                               struct v4l2_subdev_frame_interval_enum *fie)
1006 {
1007         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1008         const struct s5k6aa_interval *fi;
1009         int ret = 0;
1010
1011         if (fie->index >= ARRAY_SIZE(s5k6aa_intervals))
1012                 return -EINVAL;
1013
1014         v4l_bound_align_image(&fie->width, S5K6AA_WIN_WIDTH_MIN,
1015                               S5K6AA_WIN_WIDTH_MAX, 1,
1016                               &fie->height, S5K6AA_WIN_HEIGHT_MIN,
1017                               S5K6AA_WIN_HEIGHT_MAX, 1, 0);
1018
1019         mutex_lock(&s5k6aa->lock);
1020         fi = &s5k6aa_intervals[fie->index];
1021         if (fie->width > fi->size.width || fie->height > fi->size.height)
1022                 ret = -EINVAL;
1023         else
1024                 fie->interval = fi->interval;
1025         mutex_unlock(&s5k6aa->lock);
1026
1027         return ret;
1028 }
1029
1030 static int s5k6aa_enum_mbus_code(struct v4l2_subdev *sd,
1031                                  struct v4l2_subdev_pad_config *cfg,
1032                                  struct v4l2_subdev_mbus_code_enum *code)
1033 {
1034         if (code->index >= ARRAY_SIZE(s5k6aa_formats))
1035                 return -EINVAL;
1036
1037         code->code = s5k6aa_formats[code->index].code;
1038         return 0;
1039 }
1040
1041 static int s5k6aa_enum_frame_size(struct v4l2_subdev *sd,
1042                                   struct v4l2_subdev_pad_config *cfg,
1043                                   struct v4l2_subdev_frame_size_enum *fse)
1044 {
1045         int i = ARRAY_SIZE(s5k6aa_formats);
1046
1047         if (fse->index > 0)
1048                 return -EINVAL;
1049
1050         while (--i)
1051                 if (fse->code == s5k6aa_formats[i].code)
1052                         break;
1053
1054         fse->code = s5k6aa_formats[i].code;
1055         fse->min_width  = S5K6AA_WIN_WIDTH_MIN;
1056         fse->max_width  = S5K6AA_WIN_WIDTH_MAX;
1057         fse->max_height = S5K6AA_WIN_HEIGHT_MIN;
1058         fse->min_height = S5K6AA_WIN_HEIGHT_MAX;
1059
1060         return 0;
1061 }
1062
1063 static struct v4l2_rect *
1064 __s5k6aa_get_crop_rect(struct s5k6aa *s5k6aa, struct v4l2_subdev_pad_config *cfg,
1065                        enum v4l2_subdev_format_whence which)
1066 {
1067         if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
1068                 return &s5k6aa->ccd_rect;
1069
1070         WARN_ON(which != V4L2_SUBDEV_FORMAT_TRY);
1071         return v4l2_subdev_get_try_crop(&s5k6aa->sd, cfg, 0);
1072 }
1073
1074 static void s5k6aa_try_format(struct s5k6aa *s5k6aa,
1075                               struct v4l2_mbus_framefmt *mf)
1076 {
1077         unsigned int index;
1078
1079         v4l_bound_align_image(&mf->width, S5K6AA_WIN_WIDTH_MIN,
1080                               S5K6AA_WIN_WIDTH_MAX, 1,
1081                               &mf->height, S5K6AA_WIN_HEIGHT_MIN,
1082                               S5K6AA_WIN_HEIGHT_MAX, 1, 0);
1083
1084         if (mf->colorspace != V4L2_COLORSPACE_JPEG &&
1085             mf->colorspace != V4L2_COLORSPACE_REC709)
1086                 mf->colorspace = V4L2_COLORSPACE_JPEG;
1087
1088         index = s5k6aa_get_pixfmt_index(s5k6aa, mf);
1089
1090         mf->colorspace  = s5k6aa_formats[index].colorspace;
1091         mf->code        = s5k6aa_formats[index].code;
1092         mf->field       = V4L2_FIELD_NONE;
1093 }
1094
1095 static int s5k6aa_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
1096                           struct v4l2_subdev_format *fmt)
1097 {
1098         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1099         struct v4l2_mbus_framefmt *mf;
1100
1101         memset(fmt->reserved, 0, sizeof(fmt->reserved));
1102
1103         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1104                 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1105                 fmt->format = *mf;
1106                 return 0;
1107         }
1108
1109         mutex_lock(&s5k6aa->lock);
1110         fmt->format = s5k6aa->preset->mbus_fmt;
1111         mutex_unlock(&s5k6aa->lock);
1112
1113         return 0;
1114 }
1115
1116 static int s5k6aa_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
1117                           struct v4l2_subdev_format *fmt)
1118 {
1119         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1120         struct s5k6aa_preset *preset = s5k6aa->preset;
1121         struct v4l2_mbus_framefmt *mf;
1122         struct v4l2_rect *crop;
1123         int ret = 0;
1124
1125         mutex_lock(&s5k6aa->lock);
1126         s5k6aa_try_format(s5k6aa, &fmt->format);
1127
1128         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1129                 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1130                 crop = v4l2_subdev_get_try_crop(sd, cfg, 0);
1131         } else {
1132                 if (s5k6aa->streaming) {
1133                         ret = -EBUSY;
1134                 } else {
1135                         mf = &preset->mbus_fmt;
1136                         crop = &s5k6aa->ccd_rect;
1137                         s5k6aa->apply_cfg = 1;
1138                 }
1139         }
1140
1141         if (ret == 0) {
1142                 struct v4l2_subdev_frame_interval fiv = {
1143                         .interval = {0, 1}
1144                 };
1145
1146                 *mf = fmt->format;
1147                 /*
1148                  * Make sure the crop window is valid, i.e. its size is
1149                  * greater than the output window, as the ISP supports
1150                  * only down-scaling.
1151                  */
1152                 crop->width = clamp_t(unsigned int, crop->width, mf->width,
1153                                       S5K6AA_WIN_WIDTH_MAX);
1154                 crop->height = clamp_t(unsigned int, crop->height, mf->height,
1155                                        S5K6AA_WIN_HEIGHT_MAX);
1156                 crop->left = clamp_t(unsigned int, crop->left, 0,
1157                                      S5K6AA_WIN_WIDTH_MAX - crop->width);
1158                 crop->top  = clamp_t(unsigned int, crop->top, 0,
1159                                      S5K6AA_WIN_HEIGHT_MAX - crop->height);
1160
1161                 /* Reset to minimum possible frame interval */
1162                 ret = __s5k6aa_set_frame_interval(s5k6aa, &fiv);
1163         }
1164         mutex_unlock(&s5k6aa->lock);
1165
1166         return ret;
1167 }
1168
1169 static int s5k6aa_get_selection(struct v4l2_subdev *sd,
1170                                 struct v4l2_subdev_pad_config *cfg,
1171                                 struct v4l2_subdev_selection *sel)
1172 {
1173         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1174         struct v4l2_rect *rect;
1175
1176         if (sel->target != V4L2_SEL_TGT_CROP)
1177                 return -EINVAL;
1178
1179         memset(sel->reserved, 0, sizeof(sel->reserved));
1180
1181         mutex_lock(&s5k6aa->lock);
1182         rect = __s5k6aa_get_crop_rect(s5k6aa, cfg, sel->which);
1183         sel->r = *rect;
1184         mutex_unlock(&s5k6aa->lock);
1185
1186         v4l2_dbg(1, debug, sd, "Current crop rectangle: (%d,%d)/%dx%d\n",
1187                  rect->left, rect->top, rect->width, rect->height);
1188
1189         return 0;
1190 }
1191
1192 static int s5k6aa_set_selection(struct v4l2_subdev *sd,
1193                                 struct v4l2_subdev_pad_config *cfg,
1194                                 struct v4l2_subdev_selection *sel)
1195 {
1196         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1197         struct v4l2_mbus_framefmt *mf;
1198         unsigned int max_x, max_y;
1199         struct v4l2_rect *crop_r;
1200
1201         if (sel->target != V4L2_SEL_TGT_CROP)
1202                 return -EINVAL;
1203
1204         mutex_lock(&s5k6aa->lock);
1205         crop_r = __s5k6aa_get_crop_rect(s5k6aa, cfg, sel->which);
1206
1207         if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1208                 mf = &s5k6aa->preset->mbus_fmt;
1209                 s5k6aa->apply_crop = 1;
1210         } else {
1211                 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1212         }
1213         v4l_bound_align_image(&sel->r.width, mf->width,
1214                               S5K6AA_WIN_WIDTH_MAX, 1,
1215                               &sel->r.height, mf->height,
1216                               S5K6AA_WIN_HEIGHT_MAX, 1, 0);
1217
1218         max_x = (S5K6AA_WIN_WIDTH_MAX - sel->r.width) & ~1;
1219         max_y = (S5K6AA_WIN_HEIGHT_MAX - sel->r.height) & ~1;
1220
1221         sel->r.left = clamp_t(unsigned int, sel->r.left, 0, max_x);
1222         sel->r.top  = clamp_t(unsigned int, sel->r.top, 0, max_y);
1223
1224         *crop_r = sel->r;
1225
1226         mutex_unlock(&s5k6aa->lock);
1227
1228         v4l2_dbg(1, debug, sd, "Set crop rectangle: (%d,%d)/%dx%d\n",
1229                  crop_r->left, crop_r->top, crop_r->width, crop_r->height);
1230
1231         return 0;
1232 }
1233
1234 static const struct v4l2_subdev_pad_ops s5k6aa_pad_ops = {
1235         .enum_mbus_code         = s5k6aa_enum_mbus_code,
1236         .enum_frame_size        = s5k6aa_enum_frame_size,
1237         .enum_frame_interval    = s5k6aa_enum_frame_interval,
1238         .get_fmt                = s5k6aa_get_fmt,
1239         .set_fmt                = s5k6aa_set_fmt,
1240         .get_selection          = s5k6aa_get_selection,
1241         .set_selection          = s5k6aa_set_selection,
1242 };
1243
1244 static const struct v4l2_subdev_video_ops s5k6aa_video_ops = {
1245         .g_frame_interval       = s5k6aa_g_frame_interval,
1246         .s_frame_interval       = s5k6aa_s_frame_interval,
1247         .s_stream               = s5k6aa_s_stream,
1248 };
1249
1250 /*
1251  * V4L2 subdev controls
1252  */
1253
1254 static int s5k6aa_s_ctrl(struct v4l2_ctrl *ctrl)
1255 {
1256         struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
1257         struct i2c_client *client = v4l2_get_subdevdata(sd);
1258         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1259         int idx, err = 0;
1260
1261         v4l2_dbg(1, debug, sd, "ctrl: 0x%x, value: %d\n", ctrl->id, ctrl->val);
1262
1263         mutex_lock(&s5k6aa->lock);
1264         /*
1265          * If the device is not powered up by the host driver do
1266          * not apply any controls to H/W at this time. Instead
1267          * the controls will be restored right after power-up.
1268          */
1269         if (s5k6aa->power == 0)
1270                 goto unlock;
1271         idx = s5k6aa->preset->index;
1272
1273         switch (ctrl->id) {
1274         case V4L2_CID_AUTO_WHITE_BALANCE:
1275                 err = s5k6aa_set_awb(s5k6aa, ctrl->val);
1276                 break;
1277
1278         case V4L2_CID_BRIGHTNESS:
1279                 err = s5k6aa_write(client, REG_USER_BRIGHTNESS, ctrl->val);
1280                 break;
1281
1282         case V4L2_CID_COLORFX:
1283                 err = s5k6aa_set_colorfx(s5k6aa, ctrl->val);
1284                 break;
1285
1286         case V4L2_CID_CONTRAST:
1287                 err = s5k6aa_write(client, REG_USER_CONTRAST, ctrl->val);
1288                 break;
1289
1290         case V4L2_CID_EXPOSURE_AUTO:
1291                 err = s5k6aa_set_auto_exposure(s5k6aa, ctrl->val);
1292                 break;
1293
1294         case V4L2_CID_HFLIP:
1295                 err = s5k6aa_set_mirror(s5k6aa, ctrl->val);
1296                 if (err)
1297                         break;
1298                 err = s5k6aa_write(client, REG_G_PREV_CFG_CHG, 1);
1299                 break;
1300
1301         case V4L2_CID_POWER_LINE_FREQUENCY:
1302                 err = s5k6aa_set_anti_flicker(s5k6aa, ctrl->val);
1303                 break;
1304
1305         case V4L2_CID_SATURATION:
1306                 err = s5k6aa_write(client, REG_USER_SATURATION, ctrl->val);
1307                 break;
1308
1309         case V4L2_CID_SHARPNESS:
1310                 err = s5k6aa_write(client, REG_USER_SHARPBLUR, ctrl->val);
1311                 break;
1312
1313         case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
1314                 err = s5k6aa_write(client, REG_P_COLORTEMP(idx), ctrl->val);
1315                 if (err)
1316                         break;
1317                 err = s5k6aa_write(client, REG_G_PREV_CFG_CHG, 1);
1318                 break;
1319         }
1320 unlock:
1321         mutex_unlock(&s5k6aa->lock);
1322         return err;
1323 }
1324
1325 static const struct v4l2_ctrl_ops s5k6aa_ctrl_ops = {
1326         .s_ctrl = s5k6aa_s_ctrl,
1327 };
1328
1329 static int s5k6aa_log_status(struct v4l2_subdev *sd)
1330 {
1331         v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
1332         return 0;
1333 }
1334
1335 #define V4L2_CID_RED_GAIN       (V4L2_CTRL_CLASS_CAMERA | 0x1001)
1336 #define V4L2_CID_GREEN_GAIN     (V4L2_CTRL_CLASS_CAMERA | 0x1002)
1337 #define V4L2_CID_BLUE_GAIN      (V4L2_CTRL_CLASS_CAMERA | 0x1003)
1338
1339 static const struct v4l2_ctrl_config s5k6aa_ctrls[] = {
1340         {
1341                 .ops    = &s5k6aa_ctrl_ops,
1342                 .id     = V4L2_CID_RED_GAIN,
1343                 .type   = V4L2_CTRL_TYPE_INTEGER,
1344                 .name   = "Gain, Red",
1345                 .min    = 0,
1346                 .max    = 256,
1347                 .def    = 127,
1348                 .step   = 1,
1349         }, {
1350                 .ops    = &s5k6aa_ctrl_ops,
1351                 .id     = V4L2_CID_GREEN_GAIN,
1352                 .type   = V4L2_CTRL_TYPE_INTEGER,
1353                 .name   = "Gain, Green",
1354                 .min    = 0,
1355                 .max    = 256,
1356                 .def    = 127,
1357                 .step   = 1,
1358         }, {
1359                 .ops    = &s5k6aa_ctrl_ops,
1360                 .id     = V4L2_CID_BLUE_GAIN,
1361                 .type   = V4L2_CTRL_TYPE_INTEGER,
1362                 .name   = "Gain, Blue",
1363                 .min    = 0,
1364                 .max    = 256,
1365                 .def    = 127,
1366                 .step   = 1,
1367         },
1368 };
1369
1370 static int s5k6aa_initialize_ctrls(struct s5k6aa *s5k6aa)
1371 {
1372         const struct v4l2_ctrl_ops *ops = &s5k6aa_ctrl_ops;
1373         struct s5k6aa_ctrls *ctrls = &s5k6aa->ctrls;
1374         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1375
1376         int ret = v4l2_ctrl_handler_init(hdl, 16);
1377         if (ret)
1378                 return ret;
1379         /* Auto white balance cluster */
1380         ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE,
1381                                        0, 1, 1, 1);
1382         ctrls->gain_red = v4l2_ctrl_new_custom(hdl, &s5k6aa_ctrls[0], NULL);
1383         ctrls->gain_green = v4l2_ctrl_new_custom(hdl, &s5k6aa_ctrls[1], NULL);
1384         ctrls->gain_blue = v4l2_ctrl_new_custom(hdl, &s5k6aa_ctrls[2], NULL);
1385         v4l2_ctrl_auto_cluster(4, &ctrls->awb, 0, false);
1386
1387         ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1388         ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1389         v4l2_ctrl_cluster(2, &ctrls->hflip);
1390
1391         ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
1392                                 V4L2_CID_EXPOSURE_AUTO,
1393                                 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1394         /* Exposure time: x 1 us */
1395         ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
1396                                             0, 6000000U, 1, 100000U);
1397         /* Total gain: 256 <=> 1x */
1398         ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1399                                         0, 256, 1, 256);
1400         v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false);
1401
1402         v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
1403                                V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
1404                                V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
1405
1406         v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX,
1407                                V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE);
1408
1409         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE,
1410                           0, 256, 1, 0);
1411
1412         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
1413         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0);
1414         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
1415         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0);
1416
1417         if (hdl->error) {
1418                 ret = hdl->error;
1419                 v4l2_ctrl_handler_free(hdl);
1420                 return ret;
1421         }
1422
1423         s5k6aa->sd.ctrl_handler = hdl;
1424         return 0;
1425 }
1426
1427 /*
1428  * V4L2 subdev internal operations
1429  */
1430 static int s5k6aa_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1431 {
1432         struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(sd, fh->pad, 0);
1433         struct v4l2_rect *crop = v4l2_subdev_get_try_crop(sd, fh->pad, 0);
1434
1435         format->colorspace = s5k6aa_formats[0].colorspace;
1436         format->code = s5k6aa_formats[0].code;
1437         format->width = S5K6AA_OUT_WIDTH_DEF;
1438         format->height = S5K6AA_OUT_HEIGHT_DEF;
1439         format->field = V4L2_FIELD_NONE;
1440
1441         crop->width = S5K6AA_WIN_WIDTH_MAX;
1442         crop->height = S5K6AA_WIN_HEIGHT_MAX;
1443         crop->left = 0;
1444         crop->top = 0;
1445
1446         return 0;
1447 }
1448
1449 static int s5k6aa_check_fw_revision(struct s5k6aa *s5k6aa)
1450 {
1451         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
1452         u16 api_ver = 0, fw_rev = 0;
1453
1454         int ret = s5k6aa_set_ahb_address(client);
1455
1456         if (!ret)
1457                 ret = s5k6aa_read(client, REG_FW_APIVER, &api_ver);
1458         if (!ret)
1459                 ret = s5k6aa_read(client, REG_FW_REVISION, &fw_rev);
1460         if (ret) {
1461                 v4l2_err(&s5k6aa->sd, "FW revision check failed!\n");
1462                 return ret;
1463         }
1464
1465         v4l2_info(&s5k6aa->sd, "FW API ver.: 0x%X, FW rev.: 0x%X\n",
1466                   api_ver, fw_rev);
1467
1468         return api_ver == S5K6AAFX_FW_APIVER ? 0 : -ENODEV;
1469 }
1470
1471 static int s5k6aa_registered(struct v4l2_subdev *sd)
1472 {
1473         struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1474         int ret;
1475
1476         mutex_lock(&s5k6aa->lock);
1477         ret = __s5k6aa_power_on(s5k6aa);
1478         if (!ret) {
1479                 msleep(100);
1480                 ret = s5k6aa_check_fw_revision(s5k6aa);
1481                 __s5k6aa_power_off(s5k6aa);
1482         }
1483         mutex_unlock(&s5k6aa->lock);
1484
1485         return ret;
1486 }
1487
1488 static const struct v4l2_subdev_internal_ops s5k6aa_subdev_internal_ops = {
1489         .registered = s5k6aa_registered,
1490         .open = s5k6aa_open,
1491 };
1492
1493 static const struct v4l2_subdev_core_ops s5k6aa_core_ops = {
1494         .s_power = s5k6aa_set_power,
1495         .log_status = s5k6aa_log_status,
1496 };
1497
1498 static const struct v4l2_subdev_ops s5k6aa_subdev_ops = {
1499         .core = &s5k6aa_core_ops,
1500         .pad = &s5k6aa_pad_ops,
1501         .video = &s5k6aa_video_ops,
1502 };
1503
1504 /*
1505  * GPIO setup
1506  */
1507
1508 static int s5k6aa_configure_gpios(struct s5k6aa *s5k6aa,
1509                                   const struct s5k6aa_platform_data *pdata)
1510 {
1511         struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
1512         const struct s5k6aa_gpio *gpio;
1513         unsigned long flags;
1514         int ret;
1515
1516         s5k6aa->gpio[STBY].gpio = -EINVAL;
1517         s5k6aa->gpio[RST].gpio  = -EINVAL;
1518
1519         gpio = &pdata->gpio_stby;
1520         if (gpio_is_valid(gpio->gpio)) {
1521                 flags = (gpio->level ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW)
1522                       | GPIOF_EXPORT;
1523                 ret = devm_gpio_request_one(&client->dev, gpio->gpio, flags,
1524                                             "S5K6AA_STBY");
1525                 if (ret < 0)
1526                         return ret;
1527
1528                 s5k6aa->gpio[STBY] = *gpio;
1529         }
1530
1531         gpio = &pdata->gpio_reset;
1532         if (gpio_is_valid(gpio->gpio)) {
1533                 flags = (gpio->level ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW)
1534                       | GPIOF_EXPORT;
1535                 ret = devm_gpio_request_one(&client->dev, gpio->gpio, flags,
1536                                             "S5K6AA_RST");
1537                 if (ret < 0)
1538                         return ret;
1539
1540                 s5k6aa->gpio[RST] = *gpio;
1541         }
1542
1543         return 0;
1544 }
1545
1546 static int s5k6aa_probe(struct i2c_client *client,
1547                         const struct i2c_device_id *id)
1548 {
1549         const struct s5k6aa_platform_data *pdata = client->dev.platform_data;
1550         struct v4l2_subdev *sd;
1551         struct s5k6aa *s5k6aa;
1552         int i, ret;
1553
1554         if (pdata == NULL) {
1555                 dev_err(&client->dev, "Platform data not specified\n");
1556                 return -EINVAL;
1557         }
1558
1559         if (pdata->mclk_frequency == 0) {
1560                 dev_err(&client->dev, "MCLK frequency not specified\n");
1561                 return -EINVAL;
1562         }
1563
1564         s5k6aa = devm_kzalloc(&client->dev, sizeof(*s5k6aa), GFP_KERNEL);
1565         if (!s5k6aa)
1566                 return -ENOMEM;
1567
1568         mutex_init(&s5k6aa->lock);
1569
1570         s5k6aa->mclk_frequency = pdata->mclk_frequency;
1571         s5k6aa->bus_type = pdata->bus_type;
1572         s5k6aa->mipi_lanes = pdata->nlanes;
1573         s5k6aa->s_power = pdata->set_power;
1574         s5k6aa->inv_hflip = pdata->horiz_flip;
1575         s5k6aa->inv_vflip = pdata->vert_flip;
1576
1577         sd = &s5k6aa->sd;
1578         v4l2_i2c_subdev_init(sd, client, &s5k6aa_subdev_ops);
1579         strlcpy(sd->name, DRIVER_NAME, sizeof(sd->name));
1580
1581         sd->internal_ops = &s5k6aa_subdev_internal_ops;
1582         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1583
1584         s5k6aa->pad.flags = MEDIA_PAD_FL_SOURCE;
1585         sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1586         ret = media_entity_pads_init(&sd->entity, 1, &s5k6aa->pad);
1587         if (ret)
1588                 return ret;
1589
1590         ret = s5k6aa_configure_gpios(s5k6aa, pdata);
1591         if (ret)
1592                 goto out_err;
1593
1594         for (i = 0; i < S5K6AA_NUM_SUPPLIES; i++)
1595                 s5k6aa->supplies[i].supply = s5k6aa_supply_names[i];
1596
1597         ret = devm_regulator_bulk_get(&client->dev, S5K6AA_NUM_SUPPLIES,
1598                                  s5k6aa->supplies);
1599         if (ret) {
1600                 dev_err(&client->dev, "Failed to get regulators\n");
1601                 goto out_err;
1602         }
1603
1604         ret = s5k6aa_initialize_ctrls(s5k6aa);
1605         if (ret)
1606                 goto out_err;
1607
1608         s5k6aa_presets_data_init(s5k6aa);
1609
1610         s5k6aa->ccd_rect.width = S5K6AA_WIN_WIDTH_MAX;
1611         s5k6aa->ccd_rect.height = S5K6AA_WIN_HEIGHT_MAX;
1612         s5k6aa->ccd_rect.left = 0;
1613         s5k6aa->ccd_rect.top = 0;
1614
1615         return 0;
1616
1617 out_err:
1618         media_entity_cleanup(&s5k6aa->sd.entity);
1619         return ret;
1620 }
1621
1622 static int s5k6aa_remove(struct i2c_client *client)
1623 {
1624         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1625
1626         v4l2_device_unregister_subdev(sd);
1627         v4l2_ctrl_handler_free(sd->ctrl_handler);
1628         media_entity_cleanup(&sd->entity);
1629
1630         return 0;
1631 }
1632
1633 static const struct i2c_device_id s5k6aa_id[] = {
1634         { DRIVER_NAME, 0 },
1635         { },
1636 };
1637 MODULE_DEVICE_TABLE(i2c, s5k6aa_id);
1638
1639
1640 static struct i2c_driver s5k6aa_i2c_driver = {
1641         .driver = {
1642                 .name = DRIVER_NAME
1643         },
1644         .probe          = s5k6aa_probe,
1645         .remove         = s5k6aa_remove,
1646         .id_table       = s5k6aa_id,
1647 };
1648
1649 module_i2c_driver(s5k6aa_i2c_driver);
1650
1651 MODULE_DESCRIPTION("Samsung S5K6AA(FX) SXGA camera driver");
1652 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1653 MODULE_LICENSE("GPL");