drivers/media/i2c/ad9389b.c

   1 /*
   2  * Analog Devices AD9389B/AD9889B video encoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  */
  19
  20 /*
  21  * References (c = chapter, p = page):
  22  * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
  23  * HDMI Transitter, Rev. A, October 2010
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/slab.h>
  29 #include <linux/i2c.h>
  30 #include <linux/delay.h>
  31 #include <linux/videodev2.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/v4l2-dv-timings.h>
  34 #include <media/v4l2-device.h>
  35 #include <media/v4l2-chip-ident.h>
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ctrls.h>
  38 #include <media/ad9389b.h>
  39
  40 static int debug;
  41 module_param(debug, int, 0644);
  42 MODULE_PARM_DESC(debug, "debug level (0-2)");
  43
  44 MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
  45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  46 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  47 MODULE_LICENSE("GPL");
  48
  49 #define MASK_AD9389B_EDID_RDY_INT   0x04
  50 #define MASK_AD9389B_MSEN_INT       0x40
  51 #define MASK_AD9389B_HPD_INT        0x80
  52
  53 #define MASK_AD9389B_HPD_DETECT     0x40
  54 #define MASK_AD9389B_MSEN_DETECT    0x20
  55 #define MASK_AD9389B_EDID_RDY       0x10
  56
  57 #define EDID_MAX_RETRIES (8)
  58 #define EDID_DELAY 250
  59 #define EDID_MAX_SEGM 8
  60
  61 /*
  62 **********************************************************************
  63 *
  64 *  Arrays with configuration parameters for the AD9389B
  65 *
  66 **********************************************************************
  67 */
  68
  69 struct i2c_reg_value {
  70         u8 reg;
  71         u8 value;
  72 };
  73
  74 struct ad9389b_state_edid {
  75         /* total number of blocks */
  76         u32 blocks;
  77         /* Number of segments read */
  78         u32 segments;
  79         u8 data[EDID_MAX_SEGM * 256];
  80         /* Number of EDID read retries left */
  81         unsigned read_retries;
  82 };
  83
  84 struct ad9389b_state {
  85         struct ad9389b_platform_data pdata;
  86         struct v4l2_subdev sd;
  87         struct media_pad pad;
  88         struct v4l2_ctrl_handler hdl;
  89         int chip_revision;
  90         /* Is the ad9389b powered on? */
  91         bool power_on;
  92         /* Did we receive hotplug and rx-sense signals? */
  93         bool have_monitor;
  94         /* timings from s_dv_timings */
  95         struct v4l2_dv_timings dv_timings;
  96         /* controls */
  97         struct v4l2_ctrl *hdmi_mode_ctrl;
  98         struct v4l2_ctrl *hotplug_ctrl;
  99         struct v4l2_ctrl *rx_sense_ctrl;
 100         struct v4l2_ctrl *have_edid0_ctrl;
 101         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 102         struct i2c_client *edid_i2c_client;
 103         struct ad9389b_state_edid edid;
 104         /* Running counter of the number of detected EDIDs (for debugging) */
 105         unsigned edid_detect_counter;
 106         struct workqueue_struct *work_queue;
 107         struct delayed_work edid_handler; /* work entry */
 108 };
 109
 110 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
 111 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
 112 static void ad9389b_setup(struct v4l2_subdev *sd);
 113 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
 114 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
 115
 116 static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
 117 {
 118         return container_of(sd, struct ad9389b_state, sd);
 119 }
 120
 121 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 122 {
 123         return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
 124 }
 125
 126 /* ------------------------ I2C ----------------------------------------------- */
 127
 128 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
 129 {
 130         struct i2c_client *client = v4l2_get_subdevdata(sd);
 131
 132         return i2c_smbus_read_byte_data(client, reg);
 133 }
 134
 135 static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
 136 {
 137         struct i2c_client *client = v4l2_get_subdevdata(sd);
 138         int ret;
 139         int i;
 140
 141         for (i = 0; i < 3; i++) {
 142                 ret = i2c_smbus_write_byte_data(client, reg, val);
 143                 if (ret == 0)
 144                         return 0;
 145         }
 146         v4l2_err(sd, "I2C Write Problem\n");
 147         return ret;
 148 }
 149
 150 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
 151    and then the value-mask (to be OR-ed). */
 152 static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
 153                                                 u8 clr_mask, u8 val_mask)
 154 {
 155         ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
 156 }
 157
 158 static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
 159 {
 160         struct ad9389b_state *state = get_ad9389b_state(sd);
 161         int i;
 162
 163         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 164
 165         for (i = 0; i < len; i++)
 166                 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
 167 }
 168
 169 static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
 170 {
 171         return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
 172 }
 173
 174 static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
 175 {
 176         return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
 177 }
 178
 179 static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
 180 {
 181         ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
 182         ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
 183 }
 184
 185 static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
 186                               u16 A1, u16 A2, u16 A3, u16 A4,
 187                               u16 B1, u16 B2, u16 B3, u16 B4,
 188                               u16 C1, u16 C2, u16 C3, u16 C4)
 189 {
 190         /* A */
 191         ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
 192         ad9389b_wr(sd, 0x19, A1);
 193         ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
 194         ad9389b_wr(sd, 0x1B, A2);
 195         ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
 196         ad9389b_wr(sd, 0x1d, A3);
 197         ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
 198         ad9389b_wr(sd, 0x1f, A4);
 199
 200         /* B */
 201         ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
 202         ad9389b_wr(sd, 0x21, B1);
 203         ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
 204         ad9389b_wr(sd, 0x23, B2);
 205         ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
 206         ad9389b_wr(sd, 0x25, B3);
 207         ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
 208         ad9389b_wr(sd, 0x27, B4);
 209
 210         /* C */
 211         ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
 212         ad9389b_wr(sd, 0x29, C1);
 213         ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
 214         ad9389b_wr(sd, 0x2B, C2);
 215         ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
 216         ad9389b_wr(sd, 0x2D, C3);
 217         ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
 218         ad9389b_wr(sd, 0x2F, C4);
 219 }
 220
 221 static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
 222 {
 223         if (enable) {
 224                 u8 csc_mode = 0;
 225
 226                 ad9389b_csc_conversion_mode(sd, csc_mode);
 227                 ad9389b_csc_coeff(sd,
 228                                   4096-564, 0, 0, 256,
 229                                   0, 4096-564, 0, 256,
 230                                   0, 0, 4096-564, 256);
 231                 /* enable CSC */
 232                 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
 233                 /* AVI infoframe: Limited range RGB (16-235) */
 234                 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
 235         } else {
 236                 /* disable CSC */
 237                 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
 238                 /* AVI infoframe: Full range RGB (0-255) */
 239                 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
 240         }
 241 }
 242
 243 static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
 244 {
 245         struct ad9389b_state *state = get_ad9389b_state(sd);
 246
 247         if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 248                 /* CEA format, not IT  */
 249                 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
 250         } else {
 251                 /* IT format */
 252                 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
 253         }
 254 }
 255
 256 static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
 257 {
 258         struct ad9389b_state *state = get_ad9389b_state(sd);
 259
 260         switch (ctrl->val) {
 261         case V4L2_DV_RGB_RANGE_AUTO:
 262                 /* automatic */
 263                 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 264                         /* cea format, RGB limited range (16-235) */
 265                         ad9389b_csc_rgb_full2limit(sd, true);
 266                 } else {
 267                         /* not cea format, RGB full range (0-255) */
 268                         ad9389b_csc_rgb_full2limit(sd, false);
 269                 }
 270                 break;
 271         case V4L2_DV_RGB_RANGE_LIMITED:
 272                 /* RGB limited range (16-235) */
 273                 ad9389b_csc_rgb_full2limit(sd, true);
 274                 break;
 275         case V4L2_DV_RGB_RANGE_FULL:
 276                 /* RGB full range (0-255) */
 277                 ad9389b_csc_rgb_full2limit(sd, false);
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282         return 0;
 283 }
 284
 285 static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
 286 {
 287         u8 gear;
 288
 289         /* Workaround for TMDS PLL problem
 290          * The TMDS PLL in AD9389b change gear when the chip is heated above a
 291          * certain temperature. The output is disabled when the PLL change gear
 292          * so the monitor has to lock on the signal again. A workaround for
 293          * this is to use the manual PLL gears. This is a solution from Analog
 294          * Devices that is not documented in the datasheets.
 295          * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
 296          *
 297          * The pixel frequency ranges are based on readout of the gear the
 298          * automatic gearing selects for different pixel clocks
 299          * (read from 0x9e [3:1]).
 300          */
 301
 302         if (pixelclock > 140000000)
 303                 gear = 0xc0; /* 4th gear */
 304         else if (pixelclock > 117000000)
 305                 gear = 0xb0; /* 3rd gear */
 306         else if (pixelclock > 87000000)
 307                 gear = 0xa0; /* 2nd gear */
 308         else if (pixelclock > 60000000)
 309                 gear = 0x90; /* 1st gear */
 310         else
 311                 gear = 0x80; /* 0th gear */
 312
 313         ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
 314 }
 315
 316 /* ------------------------------ CTRL OPS ------------------------------ */
 317
 318 static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
 319 {
 320         struct v4l2_subdev *sd = to_sd(ctrl);
 321         struct ad9389b_state *state = get_ad9389b_state(sd);
 322
 323         v4l2_dbg(1, debug, sd,
 324                 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
 325
 326         if (state->hdmi_mode_ctrl == ctrl) {
 327                 /* Set HDMI or DVI-D */
 328                 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
 329                                 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
 330                 return 0;
 331         }
 332         if (state->rgb_quantization_range_ctrl == ctrl)
 333                 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
 334         return -EINVAL;
 335 }
 336
 337 static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
 338         .s_ctrl = ad9389b_s_ctrl,
 339 };
 340
 341 /* ---------------------------- CORE OPS ------------------------------------------- */
 342
 343 #ifdef CONFIG_VIDEO_ADV_DEBUG
 344 static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
 345 {
 346         struct i2c_client *client = v4l2_get_subdevdata(sd);
 347
 348         if (!v4l2_chip_match_i2c_client(client, &reg->match))
 349                 return -EINVAL;
 350         if (!capable(CAP_SYS_ADMIN))
 351                 return -EPERM;
 352         reg->val = ad9389b_rd(sd, reg->reg & 0xff);
 353         reg->size = 1;
 354         return 0;
 355 }
 356
 357 static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
 358 {
 359         struct i2c_client *client = v4l2_get_subdevdata(sd);
 360
 361         if (!v4l2_chip_match_i2c_client(client, &reg->match))
 362                 return -EINVAL;
 363         if (!capable(CAP_SYS_ADMIN))
 364                 return -EPERM;
 365         ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
 366         return 0;
 367 }
 368 #endif
 369
 370 static int ad9389b_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
 371 {
 372         struct i2c_client *client = v4l2_get_subdevdata(sd);
 373
 374         return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_AD9389B, 0);
 375 }
 376
 377 static int ad9389b_log_status(struct v4l2_subdev *sd)
 378 {
 379         struct ad9389b_state *state = get_ad9389b_state(sd);
 380         struct ad9389b_state_edid *edid = &state->edid;
 381
 382         static const char * const states[] = {
 383                 "in reset",
 384                 "reading EDID",
 385                 "idle",
 386                 "initializing HDCP",
 387                 "HDCP enabled",
 388                 "initializing HDCP repeater",
 389                 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
 390         };
 391         static const char * const errors[] = {
 392                 "no error",
 393                 "bad receiver BKSV",
 394                 "Ri mismatch",
 395                 "Pj mismatch",
 396                 "i2c error",
 397                 "timed out",
 398                 "max repeater cascade exceeded",
 399                 "hash check failed",
 400                 "too many devices",
 401                 "9", "A", "B", "C", "D", "E", "F"
 402         };
 403
 404         u8 manual_gear;
 405
 406         v4l2_info(sd, "chip revision %d\n", state->chip_revision);
 407         v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
 408         v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
 409                         (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
 410                                                         "detected" : "no",
 411                         (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
 412                                                         "detected" : "no",
 413                         edid->segments ? "found" : "no", edid->blocks);
 414         if (state->have_monitor) {
 415                 v4l2_info(sd, "%s output %s\n",
 416                                   (ad9389b_rd(sd, 0xaf) & 0x02) ?
 417                                   "HDMI" : "DVI-D",
 418                                   (ad9389b_rd(sd, 0xa1) & 0x3c) ?
 419                                   "disabled" : "enabled");
 420         }
 421         v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
 422                                         "encrypted" : "no encryption");
 423         v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
 424                         states[ad9389b_rd(sd, 0xc8) & 0xf],
 425                         errors[ad9389b_rd(sd, 0xc8) >> 4],
 426                         state->edid_detect_counter,
 427                         ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
 428         manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
 429         v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
 430                         ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
 431         v4l2_info(sd, "ad9389b: %s gear %d\n",
 432                   manual_gear ? "manual" : "automatic",
 433                   manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
 434                                 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
 435         if (state->have_monitor) {
 436                 if (ad9389b_rd(sd, 0xaf) & 0x02) {
 437                         /* HDMI only */
 438                         u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
 439                         u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
 440                                  ad9389b_rd(sd, 0x02) << 8 |
 441                                  ad9389b_rd(sd, 0x03);
 442                         u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
 443                         u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
 444                         u32 CTS;
 445
 446                         if (manual_cts)
 447                                 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
 448                                        ad9389b_rd(sd, 0x08) << 8 |
 449                                        ad9389b_rd(sd, 0x09);
 450                         else
 451                                 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
 452                                        ad9389b_rd(sd, 0x05) << 8 |
 453                                        ad9389b_rd(sd, 0x06);
 454                         N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
 455                              ad9389b_rd(sd, 0x02) << 8 |
 456                              ad9389b_rd(sd, 0x03);
 457
 458                         v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
 459                                 manual_cts ? "manual" : "automatic", N, CTS);
 460
 461                         v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
 462                                 vic_detect, vic_sent);
 463                 }
 464         }
 465         if (state->dv_timings.type == V4L2_DV_BT_656_1120) {
 466                 struct v4l2_bt_timings *bt = bt = &state->dv_timings.bt;
 467                 u32 frame_width = bt->width + bt->hfrontporch +
 468                         bt->hsync + bt->hbackporch;
 469                 u32 frame_height = bt->height + bt->vfrontporch +
 470                         bt->vsync + bt->vbackporch;
 471                 u32 frame_size = frame_width * frame_height;
 472
 473                 v4l2_info(sd, "timings: %ux%u%s%u (%ux%u). Pix freq. = %u Hz. Polarities = 0x%x\n",
 474                         bt->width, bt->height, bt->interlaced ? "i" : "p",
 475                         frame_size > 0 ?  (unsigned)bt->pixelclock / frame_size : 0,
 476                         frame_width, frame_height,
 477                         (unsigned)bt->pixelclock, bt->polarities);
 478         } else {
 479                 v4l2_info(sd, "no timings set\n");
 480         }
 481         return 0;
 482 }
 483
 484 /* Power up/down ad9389b */
 485 static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
 486 {
 487         struct ad9389b_state *state = get_ad9389b_state(sd);
 488         struct ad9389b_platform_data *pdata = &state->pdata;
 489         const int retries = 20;
 490         int i;
 491
 492         v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
 493
 494         state->power_on = on;
 495
 496         if (!on) {
 497                 /* Power down */
 498                 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
 499                 return true;
 500         }
 501
 502         /* Power up */
 503         /* The ad9389b does not always come up immediately.
 504            Retry multiple times. */
 505         for (i = 0; i < retries; i++) {
 506                 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
 507                 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
 508                         break;
 509                 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
 510                 msleep(10);
 511         }
 512         if (i == retries) {
 513                 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
 514                 ad9389b_s_power(sd, 0);
 515                 return false;
 516         }
 517         if (i > 1)
 518                 v4l2_dbg(1, debug, sd,
 519                         "needed %d retries to powerup the ad9389b\n", i);
 520
 521         /* Select chip: AD9389B */
 522         ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
 523
 524         /* Reserved registers that must be set according to REF_01 p. 11*/
 525         ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
 526         ad9389b_wr(sd, 0x9c, 0x38);
 527         ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
 528
 529         /* Differential output drive strength */
 530         if (pdata->diff_data_drive_strength > 0)
 531                 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
 532         else
 533                 ad9389b_wr(sd, 0xa2, 0x87);
 534
 535         if (pdata->diff_clk_drive_strength > 0)
 536                 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
 537         else
 538                 ad9389b_wr(sd, 0xa3, 0x87);
 539
 540         ad9389b_wr(sd, 0x0a, 0x01);
 541         ad9389b_wr(sd, 0xbb, 0xff);
 542
 543         /* Set number of attempts to read the EDID */
 544         ad9389b_wr(sd, 0xc9, 0xf);
 545         return true;
 546 }
 547
 548 /* Enable interrupts */
 549 static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
 550 {
 551         u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
 552         u8 irqs_rd;
 553         int retries = 100;
 554
 555         /* The datasheet says that the EDID ready interrupt should be
 556            disabled if there is no hotplug. */
 557         if (!enable)
 558                 irqs = 0;
 559         else if (ad9389b_have_hotplug(sd))
 560                 irqs |= MASK_AD9389B_EDID_RDY_INT;
 561
 562         /*
 563          * This i2c write can fail (approx. 1 in 1000 writes). But it
 564          * is essential that this register is correct, so retry it
 565          * multiple times.
 566          *
 567          * Note that the i2c write does not report an error, but the readback
 568          * clearly shows the wrong value.
 569          */
 570         do {
 571                 ad9389b_wr(sd, 0x94, irqs);
 572                 irqs_rd = ad9389b_rd(sd, 0x94);
 573         } while (retries-- && irqs_rd != irqs);
 574
 575         if (irqs_rd != irqs)
 576                 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
 577 }
 578
 579 /* Interrupt handler */
 580 static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
 581 {
 582         u8 irq_status;
 583
 584         /* disable interrupts to prevent a race condition */
 585         ad9389b_set_isr(sd, false);
 586         irq_status = ad9389b_rd(sd, 0x96);
 587         /* clear detected interrupts */
 588         ad9389b_wr(sd, 0x96, irq_status);
 589
 590         if (irq_status & (MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT))
 591                 ad9389b_check_monitor_present_status(sd);
 592         if (irq_status & MASK_AD9389B_EDID_RDY_INT)
 593                 ad9389b_check_edid_status(sd);
 594
 595         /* enable interrupts */
 596         ad9389b_set_isr(sd, true);
 597         *handled = true;
 598         return 0;
 599 }
 600
 601 static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
 602         .log_status = ad9389b_log_status,
 603         .g_chip_ident = ad9389b_g_chip_ident,
 604 #ifdef CONFIG_VIDEO_ADV_DEBUG
 605         .g_register = ad9389b_g_register,
 606         .s_register = ad9389b_s_register,
 607 #endif
 608         .s_power = ad9389b_s_power,
 609         .interrupt_service_routine = ad9389b_isr,
 610 };
 611
 612 /* ------------------------------ PAD OPS ------------------------------ */
 613
 614 static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
 615 {
 616         struct ad9389b_state *state = get_ad9389b_state(sd);
 617
 618         if (edid->pad != 0)
 619                 return -EINVAL;
 620         if (edid->blocks == 0 || edid->blocks > 256)
 621                 return -EINVAL;
 622         if (!edid->edid)
 623                 return -EINVAL;
 624         if (!state->edid.segments) {
 625                 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
 626                 return -ENODATA;
 627         }
 628         if (edid->start_block >= state->edid.segments * 2)
 629                 return -E2BIG;
 630         if (edid->blocks + edid->start_block >= state->edid.segments * 2)
 631                 edid->blocks = state->edid.segments * 2 - edid->start_block;
 632         memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
 633                                 128 * edid->blocks);
 634         return 0;
 635 }
 636
 637 static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
 638         .get_edid = ad9389b_get_edid,
 639 };
 640
 641 /* ------------------------------ VIDEO OPS ------------------------------ */
 642
 643 /* Enable/disable ad9389b output */
 644 static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
 645 {
 646         struct ad9389b_state *state = get_ad9389b_state(sd);
 647
 648         v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
 649
 650         ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
 651         if (enable) {
 652                 ad9389b_check_monitor_present_status(sd);
 653         } else {
 654                 ad9389b_s_power(sd, 0);
 655                 state->have_monitor = false;
 656         }
 657         return 0;
 658 }
 659
 660 static const struct v4l2_dv_timings ad9389b_timings[] = {
 661         V4L2_DV_BT_CEA_720X480P59_94,
 662         V4L2_DV_BT_CEA_720X576P50,
 663         V4L2_DV_BT_CEA_1280X720P24,
 664         V4L2_DV_BT_CEA_1280X720P25,
 665         V4L2_DV_BT_CEA_1280X720P30,
 666         V4L2_DV_BT_CEA_1280X720P50,
 667         V4L2_DV_BT_CEA_1280X720P60,
 668         V4L2_DV_BT_CEA_1920X1080P24,
 669         V4L2_DV_BT_CEA_1920X1080P25,
 670         V4L2_DV_BT_CEA_1920X1080P30,
 671         V4L2_DV_BT_CEA_1920X1080P50,
 672         V4L2_DV_BT_CEA_1920X1080P60,
 673
 674         V4L2_DV_BT_DMT_640X350P85,
 675         V4L2_DV_BT_DMT_640X400P85,
 676         V4L2_DV_BT_DMT_720X400P85,
 677         V4L2_DV_BT_DMT_640X480P60,
 678         V4L2_DV_BT_DMT_640X480P72,
 679         V4L2_DV_BT_DMT_640X480P75,
 680         V4L2_DV_BT_DMT_640X480P85,
 681         V4L2_DV_BT_DMT_800X600P56,
 682         V4L2_DV_BT_DMT_800X600P60,
 683         V4L2_DV_BT_DMT_800X600P72,
 684         V4L2_DV_BT_DMT_800X600P75,
 685         V4L2_DV_BT_DMT_800X600P85,
 686         V4L2_DV_BT_DMT_848X480P60,
 687         V4L2_DV_BT_DMT_1024X768P60,
 688         V4L2_DV_BT_DMT_1024X768P70,
 689         V4L2_DV_BT_DMT_1024X768P75,
 690         V4L2_DV_BT_DMT_1024X768P85,
 691         V4L2_DV_BT_DMT_1152X864P75,
 692         V4L2_DV_BT_DMT_1280X768P60_RB,
 693         V4L2_DV_BT_DMT_1280X768P60,
 694         V4L2_DV_BT_DMT_1280X768P75,
 695         V4L2_DV_BT_DMT_1280X768P85,
 696         V4L2_DV_BT_DMT_1280X800P60_RB,
 697         V4L2_DV_BT_DMT_1280X800P60,
 698         V4L2_DV_BT_DMT_1280X800P75,
 699         V4L2_DV_BT_DMT_1280X800P85,
 700         V4L2_DV_BT_DMT_1280X960P60,
 701         V4L2_DV_BT_DMT_1280X960P85,
 702         V4L2_DV_BT_DMT_1280X1024P60,
 703         V4L2_DV_BT_DMT_1280X1024P75,
 704         V4L2_DV_BT_DMT_1280X1024P85,
 705         V4L2_DV_BT_DMT_1360X768P60,
 706         V4L2_DV_BT_DMT_1400X1050P60_RB,
 707         V4L2_DV_BT_DMT_1400X1050P60,
 708         V4L2_DV_BT_DMT_1400X1050P75,
 709         V4L2_DV_BT_DMT_1400X1050P85,
 710         V4L2_DV_BT_DMT_1440X900P60_RB,
 711         V4L2_DV_BT_DMT_1440X900P60,
 712         V4L2_DV_BT_DMT_1600X1200P60,
 713         V4L2_DV_BT_DMT_1680X1050P60_RB,
 714         V4L2_DV_BT_DMT_1680X1050P60,
 715         V4L2_DV_BT_DMT_1792X1344P60,
 716         V4L2_DV_BT_DMT_1856X1392P60,
 717         V4L2_DV_BT_DMT_1920X1200P60_RB,
 718         V4L2_DV_BT_DMT_1366X768P60,
 719         V4L2_DV_BT_DMT_1920X1080P60,
 720         {},
 721 };
 722
 723 static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
 724                                 struct v4l2_dv_timings *timings)
 725 {
 726         struct ad9389b_state *state = get_ad9389b_state(sd);
 727         int i;
 728
 729         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 730
 731         /* quick sanity check */
 732         if (timings->type != V4L2_DV_BT_656_1120)
 733                 return -EINVAL;
 734
 735         if (timings->bt.interlaced)
 736                 return -EINVAL;
 737         if (timings->bt.pixelclock < 27000000 ||
 738             timings->bt.pixelclock > 170000000)
 739                 return -EINVAL;
 740
 741         /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
 742            if the format is listed in ad9389b_timings[] */
 743         for (i = 0; ad9389b_timings[i].bt.width; i++) {
 744                 if (v4l_match_dv_timings(timings, &ad9389b_timings[i], 0)) {
 745                         *timings = ad9389b_timings[i];
 746                         break;
 747                 }
 748         }
 749
 750         timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
 751
 752         /* save timings */
 753         state->dv_timings = *timings;
 754
 755         /* update quantization range based on new dv_timings */
 756         ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
 757
 758         /* update PLL gear based on new dv_timings */
 759         if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
 760                 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
 761
 762         /* update AVI infoframe */
 763         ad9389b_set_IT_content_AVI_InfoFrame(sd);
 764
 765         return 0;
 766 }
 767
 768 static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
 769                                 struct v4l2_dv_timings *timings)
 770 {
 771         struct ad9389b_state *state = get_ad9389b_state(sd);
 772
 773         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 774
 775         if (!timings)
 776                 return -EINVAL;
 777
 778         *timings = state->dv_timings;
 779
 780         return 0;
 781 }
 782
 783 static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
 784                         struct v4l2_enum_dv_timings *timings)
 785 {
 786         if (timings->index >= ARRAY_SIZE(ad9389b_timings))
 787                 return -EINVAL;
 788
 789         memset(timings->reserved, 0, sizeof(timings->reserved));
 790         timings->timings = ad9389b_timings[timings->index];
 791         return 0;
 792 }
 793
 794 static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
 795                         struct v4l2_dv_timings_cap *cap)
 796 {
 797         cap->type = V4L2_DV_BT_656_1120;
 798         cap->bt.max_width = 1920;
 799         cap->bt.max_height = 1200;
 800         cap->bt.min_pixelclock = 27000000;
 801         cap->bt.max_pixelclock = 170000000;
 802         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 803                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
 804         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
 805                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
 806         return 0;
 807 }
 808
 809 static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
 810         .s_stream = ad9389b_s_stream,
 811         .s_dv_timings = ad9389b_s_dv_timings,
 812         .g_dv_timings = ad9389b_g_dv_timings,
 813         .enum_dv_timings = ad9389b_enum_dv_timings,
 814         .dv_timings_cap = ad9389b_dv_timings_cap,
 815 };
 816
 817 static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
 818 {
 819         v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
 820
 821         if (enable)
 822                 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
 823         else
 824                 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
 825
 826         return 0;
 827 }
 828
 829 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 830 {
 831         u32 N;
 832
 833         switch (freq) {
 834         case 32000: N = 4096; break;
 835         case 44100: N = 6272; break;
 836         case 48000: N = 6144; break;
 837         case 88200: N = 12544; break;
 838         case 96000: N = 12288; break;
 839         case 176400: N = 25088; break;
 840         case 192000: N = 24576; break;
 841         default:
 842                 return -EINVAL;
 843         }
 844
 845         /* Set N (used with CTS to regenerate the audio clock) */
 846         ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
 847         ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
 848         ad9389b_wr(sd, 0x03, N & 0xff);
 849
 850         return 0;
 851 }
 852
 853 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 854 {
 855         u32 i2s_sf;
 856
 857         switch (freq) {
 858         case 32000: i2s_sf = 0x30; break;
 859         case 44100: i2s_sf = 0x00; break;
 860         case 48000: i2s_sf = 0x20; break;
 861         case 88200: i2s_sf = 0x80; break;
 862         case 96000: i2s_sf = 0xa0; break;
 863         case 176400: i2s_sf = 0xc0; break;
 864         case 192000: i2s_sf = 0xe0; break;
 865         default:
 866                 return -EINVAL;
 867         }
 868
 869         /* Set sampling frequency for I2S audio to 48 kHz */
 870         ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
 871
 872         return 0;
 873 }
 874
 875 static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
 876 {
 877         /* TODO based on input/output/config */
 878         /* TODO See datasheet "Programmers guide" p. 39-40 */
 879
 880         /* Only 2 channels in use for application */
 881         ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
 882         /* Speaker mapping */
 883         ad9389b_wr(sd, 0x51, 0x00);
 884
 885         /* TODO Where should this be placed? */
 886         /* 16 bit audio word length */
 887         ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
 888
 889         return 0;
 890 }
 891
 892 static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
 893         .s_stream = ad9389b_s_audio_stream,
 894         .s_clock_freq = ad9389b_s_clock_freq,
 895         .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
 896         .s_routing = ad9389b_s_routing,
 897 };
 898
 899 /* --------------------- SUBDEV OPS --------------------------------------- */
 900
 901 static const struct v4l2_subdev_ops ad9389b_ops = {
 902         .core  = &ad9389b_core_ops,
 903         .video = &ad9389b_video_ops,
 904         .audio = &ad9389b_audio_ops,
 905         .pad = &ad9389b_pad_ops,
 906 };
 907
 908 /* ----------------------------------------------------------------------- */
 909 static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
 910                                                         int segment, u8 *buf)
 911 {
 912         int i, j;
 913
 914         if (debug < lvl)
 915                 return;
 916
 917         v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
 918         for (i = 0; i < 256; i += 16) {
 919                 u8 b[128];
 920                 u8 *bp = b;
 921
 922                 if (i == 128)
 923                         v4l2_dbg(lvl, debug, sd, "\n");
 924                 for (j = i; j < i + 16; j++) {
 925                         sprintf(bp, "0x%02x, ", buf[j]);
 926                         bp += 6;
 927                 }
 928                 bp[0] = '\0';
 929                 v4l2_dbg(lvl, debug, sd, "%s\n", b);
 930         }
 931 }
 932
 933 static void ad9389b_edid_handler(struct work_struct *work)
 934 {
 935         struct delayed_work *dwork = to_delayed_work(work);
 936         struct ad9389b_state *state = container_of(dwork,
 937                         struct ad9389b_state, edid_handler);
 938         struct v4l2_subdev *sd = &state->sd;
 939         struct ad9389b_edid_detect ed;
 940
 941         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 942
 943         if (ad9389b_check_edid_status(sd)) {
 944                 /* Return if we received the EDID. */
 945                 return;
 946         }
 947
 948         if (ad9389b_have_hotplug(sd)) {
 949                 /* We must retry reading the EDID several times, it is possible
 950                  * that initially the EDID couldn't be read due to i2c errors
 951                  * (DVI connectors are particularly prone to this problem). */
 952                 if (state->edid.read_retries) {
 953                         state->edid.read_retries--;
 954                         /* EDID read failed, trigger a retry */
 955                         ad9389b_wr(sd, 0xc9, 0xf);
 956                         queue_delayed_work(state->work_queue,
 957                                         &state->edid_handler, EDID_DELAY);
 958                         return;
 959                 }
 960         }
 961
 962         /* We failed to read the EDID, so send an event for this. */
 963         ed.present = false;
 964         ed.segment = ad9389b_rd(sd, 0xc4);
 965         v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
 966         v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
 967 }
 968
 969 static void ad9389b_audio_setup(struct v4l2_subdev *sd)
 970 {
 971         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 972
 973         ad9389b_s_i2s_clock_freq(sd, 48000);
 974         ad9389b_s_clock_freq(sd, 48000);
 975         ad9389b_s_routing(sd, 0, 0, 0);
 976 }
 977
 978 /* Initial setup of AD9389b */
 979
 980 /* Configure hdmi transmitter. */
 981 static void ad9389b_setup(struct v4l2_subdev *sd)
 982 {
 983         struct ad9389b_state *state = get_ad9389b_state(sd);
 984
 985         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 986
 987         /* Input format: RGB 4:4:4 */
 988         ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
 989         /* Output format: RGB 4:4:4 */
 990         ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
 991         /* CSC fixed point: +/-2, 1st order interpolation 4:2:2 -> 4:4:4 up
 992            conversion, Aspect ratio: 16:9 */
 993         ad9389b_wr_and_or(sd, 0x17, 0xe1, 0x0e);
 994         /* Disable pixel repetition and CSC */
 995         ad9389b_wr_and_or(sd, 0x3b, 0x9e, 0x0);
 996         /* Output format: RGB 4:4:4, Active Format Information is valid. */
 997         ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
 998         /* Underscanned */
 999         ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
1000         /* Setup video format */
1001         ad9389b_wr(sd, 0x3c, 0x0);
1002         /* Active format aspect ratio: same as picure. */
1003         ad9389b_wr(sd, 0x47, 0x80);
1004         /* No encryption */
1005         ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
1006         /* Positive clk edge capture for input video clock */
1007         ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
1008
1009         ad9389b_audio_setup(sd);
1010
1011         v4l2_ctrl_handler_setup(&state->hdl);
1012
1013         ad9389b_set_IT_content_AVI_InfoFrame(sd);
1014 }
1015
1016 static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
1017 {
1018         struct ad9389b_monitor_detect mdt;
1019         struct ad9389b_state *state = get_ad9389b_state(sd);
1020
1021         mdt.present = state->have_monitor;
1022         v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
1023 }
1024
1025 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
1026 {
1027         struct ad9389b_state *state = get_ad9389b_state(sd);
1028         /* read hotplug and rx-sense state */
1029         u8 status = ad9389b_rd(sd, 0x42);
1030
1031         v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
1032                          __func__,
1033                          status,
1034                          status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
1035                          status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
1036
1037         if ((status & MASK_AD9389B_HPD_DETECT) &&
1038             ((status & MASK_AD9389B_MSEN_DETECT) || state->edid.segments)) {
1039                 v4l2_dbg(1, debug, sd,
1040                                 "%s: hotplug and (rx-sense or edid)\n", __func__);
1041                 if (!state->have_monitor) {
1042                         v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
1043                         state->have_monitor = true;
1044                         ad9389b_set_isr(sd, true);
1045                         if (!ad9389b_s_power(sd, true)) {
1046                                 v4l2_dbg(1, debug, sd,
1047                                         "%s: monitor detected, powerup failed\n", __func__);
1048                                 return;
1049                         }
1050                         ad9389b_setup(sd);
1051                         ad9389b_notify_monitor_detect(sd);
1052                         state->edid.read_retries = EDID_MAX_RETRIES;
1053                         queue_delayed_work(state->work_queue,
1054                                         &state->edid_handler, EDID_DELAY);
1055                 }
1056         } else if (status & MASK_AD9389B_HPD_DETECT) {
1057                 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
1058                 state->edid.read_retries = EDID_MAX_RETRIES;
1059                 queue_delayed_work(state->work_queue,
1060                                 &state->edid_handler, EDID_DELAY);
1061         } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
1062                 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
1063                 if (state->have_monitor) {
1064                         v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
1065                         state->have_monitor = false;
1066                         ad9389b_notify_monitor_detect(sd);
1067                 }
1068                 ad9389b_s_power(sd, false);
1069                 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
1070         }
1071
1072         /* update read only ctrls */
1073         v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
1074         v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
1075         v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1076 }
1077
1078 static bool edid_block_verify_crc(u8 *edid_block)
1079 {
1080         int i;
1081         u8 sum = 0;
1082
1083         for (i = 0; i < 127; i++)
1084                 sum += *(edid_block + i);
1085         return ((255 - sum + 1) == edid_block[127]);
1086 }
1087
1088 static bool edid_segment_verify_crc(struct v4l2_subdev *sd, u32 segment)
1089 {
1090         struct ad9389b_state *state = get_ad9389b_state(sd);
1091         u32 blocks = state->edid.blocks;
1092         u8 *data = state->edid.data;
1093
1094         if (edid_block_verify_crc(&data[segment * 256])) {
1095                 if ((segment + 1) * 2 <= blocks)
1096                         return edid_block_verify_crc(&data[segment * 256 + 128]);
1097                 return true;
1098         }
1099         return false;
1100 }
1101
1102 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1103 {
1104         struct ad9389b_state *state = get_ad9389b_state(sd);
1105         struct ad9389b_edid_detect ed;
1106         int segment;
1107         u8 edidRdy = ad9389b_rd(sd, 0xc5);
1108
1109         v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1110                          __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1111
1112         if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1113                 return false;
1114
1115         segment = ad9389b_rd(sd, 0xc4);
1116         if (segment >= EDID_MAX_SEGM) {
1117                 v4l2_err(sd, "edid segment number too big\n");
1118                 return false;
1119         }
1120         v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1121         ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1122         ad9389b_dbg_dump_edid(2, debug, sd, segment,
1123                         &state->edid.data[segment * 256]);
1124         if (segment == 0) {
1125                 state->edid.blocks = state->edid.data[0x7e] + 1;
1126                 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1127                                 __func__, state->edid.blocks);
1128         }
1129         if (!edid_segment_verify_crc(sd, segment)) {
1130                 /* edid crc error, force reread of edid segment */
1131                 ad9389b_s_power(sd, false);
1132                 ad9389b_s_power(sd, true);
1133                 return false;
1134         }
1135         /* one more segment read ok */
1136         state->edid.segments = segment + 1;
1137         if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1138                 /* Request next EDID segment */
1139                 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1140                                 __func__, state->edid.segments);
1141                 ad9389b_wr(sd, 0xc9, 0xf);
1142                 ad9389b_wr(sd, 0xc4, state->edid.segments);
1143                 state->edid.read_retries = EDID_MAX_RETRIES;
1144                 queue_delayed_work(state->work_queue,
1145                                 &state->edid_handler, EDID_DELAY);
1146                 return false;
1147         }
1148
1149         /* report when we have all segments but report only for segment 0 */
1150         ed.present = true;
1151         ed.segment = 0;
1152         v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1153         state->edid_detect_counter++;
1154         v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1155         return ed.present;
1156 }
1157
1158 /* ----------------------------------------------------------------------- */
1159
1160 static void ad9389b_init_setup(struct v4l2_subdev *sd)
1161 {
1162         struct ad9389b_state *state = get_ad9389b_state(sd);
1163         struct ad9389b_state_edid *edid = &state->edid;
1164
1165         v4l2_dbg(1, debug, sd, "%s\n", __func__);
1166
1167         /* clear all interrupts */
1168         ad9389b_wr(sd, 0x96, 0xff);
1169
1170         memset(edid, 0, sizeof(struct ad9389b_state_edid));
1171         state->have_monitor = false;
1172         ad9389b_set_isr(sd, false);
1173 }
1174
1175 static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1176 {
1177         const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1178         struct ad9389b_state *state;
1179         struct ad9389b_platform_data *pdata = client->dev.platform_data;
1180         struct v4l2_ctrl_handler *hdl;
1181         struct v4l2_subdev *sd;
1182         int err = -EIO;
1183
1184         /* Check if the adapter supports the needed features */
1185         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1186                 return -EIO;
1187
1188         v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1189                         client->addr << 1);
1190
1191         state = kzalloc(sizeof(struct ad9389b_state), GFP_KERNEL);
1192         if (!state)
1193                 return -ENOMEM;
1194
1195         /* Platform data */
1196         if (pdata == NULL) {
1197                 v4l_err(client, "No platform data!\n");
1198                 err = -ENODEV;
1199                 goto err_free;
1200         }
1201         memcpy(&state->pdata, pdata, sizeof(state->pdata));
1202
1203         sd = &state->sd;
1204         v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1205         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1206
1207         hdl = &state->hdl;
1208         v4l2_ctrl_handler_init(hdl, 5);
1209
1210         /* private controls */
1211
1212         state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1213                         V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1214                         0, V4L2_DV_TX_MODE_DVI_D);
1215         state->hdmi_mode_ctrl->is_private = true;
1216         state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1217                         V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1218         state->hotplug_ctrl->is_private = true;
1219         state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1220                         V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1221         state->rx_sense_ctrl->is_private = true;
1222         state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1223                         V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1224         state->have_edid0_ctrl->is_private = true;
1225         state->rgb_quantization_range_ctrl =
1226                 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1227                         V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1228                         0, V4L2_DV_RGB_RANGE_AUTO);
1229         state->rgb_quantization_range_ctrl->is_private = true;
1230         sd->ctrl_handler = hdl;
1231         if (hdl->error) {
1232                 err = hdl->error;
1233
1234                 goto err_hdl;
1235         }
1236
1237         state->pad.flags = MEDIA_PAD_FL_SINK;
1238         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1239         if (err)
1240                 goto err_hdl;
1241
1242         state->chip_revision = ad9389b_rd(sd, 0x0);
1243         if (state->chip_revision != 2) {
1244                 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1245                 err = -EIO;
1246                 goto err_entity;
1247         }
1248         v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1249                         ad9389b_rd(sd, 0x41), state->chip_revision);
1250
1251         state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1252         if (state->edid_i2c_client == NULL) {
1253                 v4l2_err(sd, "failed to register edid i2c client\n");
1254                 goto err_entity;
1255         }
1256
1257         state->work_queue = create_singlethread_workqueue(sd->name);
1258         if (state->work_queue == NULL) {
1259                 v4l2_err(sd, "could not create workqueue\n");
1260                 goto err_unreg;
1261         }
1262
1263         INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1264         state->dv_timings = dv1080p60;
1265
1266         ad9389b_init_setup(sd);
1267         ad9389b_set_isr(sd, true);
1268
1269         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1270                           client->addr << 1, client->adapter->name);
1271         return 0;
1272
1273 err_unreg:
1274         i2c_unregister_device(state->edid_i2c_client);
1275 err_entity:
1276         media_entity_cleanup(&sd->entity);
1277 err_hdl:
1278         v4l2_ctrl_handler_free(&state->hdl);
1279 err_free:
1280         kfree(state);
1281         return err;
1282 }
1283
1284 /* ----------------------------------------------------------------------- */
1285
1286 static int ad9389b_remove(struct i2c_client *client)
1287 {
1288         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1289         struct ad9389b_state *state = get_ad9389b_state(sd);
1290
1291         state->chip_revision = -1;
1292
1293         v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1294                  client->addr << 1, client->adapter->name);
1295
1296         ad9389b_s_stream(sd, false);
1297         ad9389b_s_audio_stream(sd, false);
1298         ad9389b_init_setup(sd);
1299         cancel_delayed_work(&state->edid_handler);
1300         i2c_unregister_device(state->edid_i2c_client);
1301         destroy_workqueue(state->work_queue);
1302         v4l2_device_unregister_subdev(sd);
1303         media_entity_cleanup(&sd->entity);
1304         v4l2_ctrl_handler_free(sd->ctrl_handler);
1305         kfree(get_ad9389b_state(sd));
1306         return 0;
1307 }
1308
1309 /* ----------------------------------------------------------------------- */
1310
1311 static struct i2c_device_id ad9389b_id[] = {
1312         { "ad9389b", V4L2_IDENT_AD9389B },
1313         { "ad9889b", V4L2_IDENT_AD9389B },
1314         { }
1315 };
1316 MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1317
1318 static struct i2c_driver ad9389b_driver = {
1319         .driver = {
1320                 .owner = THIS_MODULE,
1321                 .name = "ad9389b",
1322         },
1323         .probe = ad9389b_probe,
1324         .remove = ad9389b_remove,
1325         .id_table = ad9389b_id,
1326 };
1327
1328 module_i2c_driver(ad9389b_driver);