drivers/media/dvb/frontends/dib3000mc_priv.h

   1 /*
   2  * dib3000mc_priv.h
   3  *
   4  * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License as
   8  *      published by the Free Software Foundation, version 2.
   9  *
  10  * for more information see dib3000mc.c .
  11  */
  12
  13 #ifndef __DIB3000MC_PRIV_H__
  14 #define __DIB3000MC_PRIV_H__
  15
  16 /*
  17  * Demodulator parameters
  18  * reg: 0  1 1  1 11 11 111
  19  *         | |  |  |  |  |
  20  *         | |  |  |  |  +-- alpha (000=0, 001=1, 010=2, 100=4)
  21  *         | |  |  |  +----- constellation (00=QPSK, 01=16QAM, 10=64QAM)
  22  *         | |  |  +-------- guard (00=1/32, 01=1/16, 10=1/8, 11=1/4)
  23  *         | |  +----------- transmission mode (0=2k, 1=8k)
  24  *         | |
  25  *         | +-------------- restart autosearch for parameters
  26  *         +---------------- restart the demodulator
  27  * reg: 181      1 111 1
  28  *               |  |  |
  29  *               |  |  +- FEC applies for HP or LP (0=LP, 1=HP)
  30  *               |  +---- FEC rate (001=1/2, 010=2/3, 011=3/4, 101=5/6, 111=7/8)
  31  *               +------- hierarchy on (0=no, 1=yes)
  32  */
  33
  34 /* demodulator tuning parameter and restart options */
  35 #define DIB3000MC_REG_DEMOD_PARM                (     0)
  36 #define DIB3000MC_DEMOD_PARM(a,c,g,t)   ( \
  37                  (0x7 & a) | \
  38                 ((0x3 & c) << 3) | \
  39                 ((0x3 & g) << 5) | \
  40                 ((0x1 & t) << 7) )
  41 #define DIB3000MC_DEMOD_RST_AUTO_SRCH_ON        (1 << 8)
  42 #define DIB3000MC_DEMOD_RST_AUTO_SRCH_OFF       (0 << 8)
  43 #define DIB3000MC_DEMOD_RST_DEMOD_ON            (1 << 9)
  44 #define DIB3000MC_DEMOD_RST_DEMOD_OFF           (0 << 9)
  45
  46 /* register for hierarchy parameters */
  47 #define DIB3000MC_REG_HRCH_PARM                 (   181)
  48 #define DIB3000MC_HRCH_PARM(s,f,h)              ( \
  49                  (0x1 & s) | \
  50                 ((0x7 & f) << 1) | \
  51                 ((0x1 & h) << 4) )
  52
  53 /* timeout ??? */
  54 #define DIB3000MC_REG_UNK_1                             (     1)
  55 #define DIB3000MC_UNK_1                                 (  0x04)
  56
  57 /* timeout ??? */
  58 #define DIB3000MC_REG_UNK_2                             (     2)
  59 #define DIB3000MC_UNK_2                                 (  0x04)
  60
  61 /* timeout ??? */
  62 #define DIB3000MC_REG_UNK_3                             (     3)
  63 #define DIB3000MC_UNK_3                                 (0x1000)
  64
  65 #define DIB3000MC_REG_UNK_4                             (     4)
  66 #define DIB3000MC_UNK_4                                 (0x0814)
  67
  68 /* timeout ??? */
  69 #define DIB3000MC_REG_SEQ_TPS                   (     5)
  70 #define DIB3000MC_SEQ_TPS_DEFAULT               (     1)
  71 #define DIB3000MC_SEQ_TPS(s,t)                  ( \
  72                 ((s & 0x0f) << 4) | \
  73                 ((t & 0x01) << 8) )
  74 #define DIB3000MC_IS_TPS(v)                             ((v << 8) & 0x1)
  75 #define DIB3000MC_IS_AS(v)                              ((v >> 4) & 0xf)
  76
  77 /* parameters for the bandwidth */
  78 #define DIB3000MC_REG_BW_TIMOUT_MSB             (     6)
  79 #define DIB3000MC_REG_BW_TIMOUT_LSB             (     7)
  80
  81 static u16 dib3000mc_reg_bandwidth[] = { 6,7,8,9,10,11,16,17 };
  82
  83 /*static u16 dib3000mc_bandwidth_5mhz[] =
  84         { 0x28, 0x9380, 0x87, 0x4100, 0x2a4, 0x4500, 0x1, 0xb0d0 };*/
  85
  86 static u16 dib3000mc_bandwidth_6mhz[] =
  87         { 0x21, 0xd040, 0x70, 0xb62b, 0x233, 0x8ed5, 0x1, 0xb0d0 };
  88
  89 static u16 dib3000mc_bandwidth_7mhz[] =
  90         { 0x1c, 0xfba5, 0x60, 0x9c25, 0x1e3, 0x0cb7, 0x1, 0xb0d0 };
  91
  92 static u16 dib3000mc_bandwidth_8mhz[] =
  93         { 0x19, 0x5c30, 0x54, 0x88a0, 0x1a6, 0xab20, 0x1, 0xb0d0 };
  94
  95 static u16 dib3000mc_reg_bandwidth_general[] = { 12,13,14,15 };
  96 static u16 dib3000mc_bandwidth_general[] = { 0x0000, 0x03e8, 0x0000, 0x03f2 };
  97
  98 /* lock mask */
  99 #define DIB3000MC_REG_LOCK_MASK                 (    15)
 100 #define DIB3000MC_ACTIVATE_LOCK_MASK    (0x0800)
 101
 102 /* reset the uncorrected packet count (??? do it 5 times) */
 103 #define DIB3000MC_REG_RST_UNC                   (    18)
 104 #define DIB3000MC_RST_UNC_ON                    (     1)
 105 #define DIB3000MC_RST_UNC_OFF                   (     0)
 106
 107 #define DIB3000MC_REG_UNK_19                    (    19)
 108 #define DIB3000MC_UNK_19                                (     0)
 109
 110 /* DDS frequency value (IF position) and inversion bit */
 111 #define DIB3000MC_REG_INVERSION                 (    21)
 112 #define DIB3000MC_REG_SET_DDS_FREQ_MSB  (    21)
 113 #define DIB3000MC_DDS_FREQ_MSB_INV_OFF  (0x0164)
 114 #define DIB3000MC_DDS_FREQ_MSB_INV_ON   (0x0364)
 115
 116 #define DIB3000MC_REG_SET_DDS_FREQ_LSB  (    22)
 117 #define DIB3000MC_DDS_FREQ_LSB                  (0x463d)
 118
 119 /* timing frequencies setting */
 120 #define DIB3000MC_REG_TIMING_FREQ_MSB   (    23)
 121 #define DIB3000MC_REG_TIMING_FREQ_LSB   (    24)
 122 #define DIB3000MC_CLOCK_REF                             (0x151fd1)
 123
 124 //static u16 dib3000mc_reg_timing_freq[] = { 23,24 };
 125
 126 //static u16 dib3000mc_timing_freq[][2] = {
 127 //      { 0x69, 0x9f18 }, /* 5 MHz */
 128 //      { 0x7e ,0xbee9 }, /* 6 MHz */
 129 //      { 0x93 ,0xdebb }, /* 7 MHz */
 130 //      { 0xa8 ,0xfe8c }, /* 8 MHz */
 131 //};
 132
 133 /* timeout ??? */
 134 static u16 dib3000mc_reg_offset[] = { 26,33 };
 135
 136 static u16 dib3000mc_offset[][2] = {
 137         { 26240, 5 }, /* default */
 138         { 30336, 6 }, /* 8K */
 139         { 38528, 8 }, /* 2K */
 140 };
 141
 142 #define DIB3000MC_REG_ISI                               (    29)
 143 #define DIB3000MC_ISI_DEFAULT                   (0x1073)
 144 #define DIB3000MC_ISI_ACTIVATE                  (0x0000)
 145 #define DIB3000MC_ISI_INHIBIT                   (0x0200)
 146
 147 /* impulse noise control */
 148 static u16 dib3000mc_reg_imp_noise_ctl[] = { 34,35 };
 149
 150 static u16 dib3000mc_imp_noise_ctl[][2] = {
 151         { 0x1294, 0x1ff8 }, /* mode 0 */
 152         { 0x1294, 0x1ff8 }, /* mode 1 */
 153         { 0x1294, 0x1ff8 }, /* mode 2 */
 154         { 0x1294, 0x1ff8 }, /* mode 3 */
 155         { 0x1294, 0x1ff8 }, /* mode 4 */
 156 };
 157
 158 /* AGC registers */
 159 static u16 dib3000mc_reg_agc[] = {
 160         36,37,38,39,42,43,44,45,46,47,48,49
 161 };
 162
 163 static u16 dib3000mc_agc_tuner[][12] = {
 164         {       0x0051, 0x301d, 0x0000, 0x1cc7, 0xcf5c, 0x6666,
 165                 0xbae1, 0xa148, 0x3b5e, 0x3c1c, 0x001a, 0x2019
 166         }, /* TUNER_PANASONIC_ENV77H04D5, */
 167
 168         {       0x0051, 0x301d, 0x0000, 0x1cc7, 0xdc29, 0x570a,
 169                 0xbae1, 0x8ccd, 0x3b6d, 0x551d, 0x000a, 0x951e
 170         }, /* TUNER_PANASONIC_ENV57H13D5, TUNER_PANASONIC_ENV57H12D5 */
 171
 172         {       0x0051, 0x301d, 0x0000, 0x1cc7, 0xffff, 0xffff,
 173                 0xffff, 0x0000, 0xfdfd, 0x4040, 0x00fd, 0x4040
 174         }, /* TUNER_SAMSUNG_DTOS333IH102, TUNER_RFAGCIN_UNKNOWN */
 175
 176         {       0x0196, 0x301d, 0x0000, 0x1cc7, 0xbd71, 0x5c29,
 177                 0xb5c3, 0x6148, 0x6569, 0x5127, 0x0033, 0x3537
 178         }, /* TUNER_PROVIDER_X */
 179         /* TODO TUNER_PANASONIC_ENV57H10D8, TUNER_PANASONIC_ENV57H11D8 */
 180 };
 181
 182 /* AGC loop bandwidth */
 183 static u16 dib3000mc_reg_agc_bandwidth[] = { 40,41 };
 184 static u16 dib3000mc_agc_bandwidth[]  = { 0x119,0x330 };
 185
 186 static u16 dib3000mc_reg_agc_bandwidth_general[] = { 50,51,52,53,54 };
 187 static u16 dib3000mc_agc_bandwidth_general[] =
 188         { 0x8000, 0x91ca, 0x01ba, 0x0087, 0x0087 };
 189
 190 #define DIB3000MC_REG_IMP_NOISE_55              (    55)
 191 #define DIB3000MC_IMP_NEW_ALGO(w)               (w | (1<<10))
 192
 193 /* Impulse noise params */
 194 static u16 dib3000mc_reg_impulse_noise[] = { 55,56,57 };
 195 static u16 dib3000mc_impluse_noise[][3] = {
 196         { 0x489, 0x89, 0x72 }, /* 5 MHz */
 197         { 0x4a5, 0xa5, 0x89 }, /* 6 MHz */
 198         { 0x4c0, 0xc0, 0xa0 }, /* 7 MHz */
 199         { 0x4db, 0xdb, 0xb7 }, /* 8 Mhz */
 200 };
 201
 202 static u16 dib3000mc_reg_fft[] = {
 203         58,59,60,61,62,63,64,65,66,67,68,69,
 204         70,71,72,73,74,75,76,77,78,79,80,81,
 205         82,83,84,85,86
 206 };
 207
 208 static u16 dib3000mc_fft_modes[][29] = {
 209         {       0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c,
 210                 0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d,
 211                 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3,
 212                 0x3feb, 0x7d2, 0x365e, 0x76, 0x48c,
 213                 0x3ffe, 0x5b3, 0x3feb, 0x76,   0x0, 0xd
 214         }, /* fft mode 0 */
 215         {       0x3b, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c,
 216                 0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d,
 217                 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3,
 218                 0x3feb, 0x7d2, 0x365e, 0x76, 0x48c,
 219                 0x3ffe, 0x5b3, 0x3feb, 0x0,  0x8200, 0xd
 220         }, /* fft mode 1 */
 221 };
 222
 223 #define DIB3000MC_REG_UNK_88                    (    88)
 224 #define DIB3000MC_UNK_88                                (0x0410)
 225
 226 static u16 dib3000mc_reg_bw[] = { 93,94,95,96,97,98 };
 227 static u16 dib3000mc_bw[][6] = {
 228         { 0,0,0,0,0,0 }, /* 5 MHz */
 229         { 0,0,0,0,0,0 }, /* 6 MHz */
 230         { 0,0,0,0,0,0 }, /* 7 MHz */
 231         { 0x20, 0x21, 0x20, 0x23, 0x20, 0x27 }, /* 8 MHz */
 232 };
 233
 234
 235 /* phase noise control */
 236 #define DIB3000MC_REG_UNK_99                    (    99)
 237 #define DIB3000MC_UNK_99                                (0x0220)
 238
 239 #define DIB3000MC_REG_SCAN_BOOST                (   100)
 240 #define DIB3000MC_SCAN_BOOST_ON                 ((11 << 6) + 6)
 241 #define DIB3000MC_SCAN_BOOST_OFF                ((16 << 6) + 9)
 242
 243 /* timeout ??? */
 244 #define DIB3000MC_REG_UNK_110                   (   110)
 245 #define DIB3000MC_UNK_110                               (  3277)
 246
 247 #define DIB3000MC_REG_UNK_111                   (   111)
 248 #define DIB3000MC_UNK_111_PH_N_MODE_0   (     0)
 249 #define DIB3000MC_UNK_111_PH_N_MODE_1   (1 << 1)
 250
 251 /* superious rm config */
 252 #define DIB3000MC_REG_UNK_120                   (   120)
 253 #define DIB3000MC_UNK_120                               (  8207)
 254
 255 #define DIB3000MC_REG_UNK_133                   (   133)
 256 #define DIB3000MC_UNK_133                               ( 15564)
 257
 258 #define DIB3000MC_REG_UNK_134                   (   134)
 259 #define DIB3000MC_UNK_134                               (     0)
 260
 261 /* adapter config for constellation */
 262 static u16 dib3000mc_reg_adp_cfg[] = { 129, 130, 131, 132 };
 263
 264 static u16 dib3000mc_adp_cfg[][4] = {
 265         { 0x99a, 0x7fae, 0x333, 0x7ff0 }, /* QPSK  */
 266         { 0x23d, 0x7fdf, 0x0a4, 0x7ff0 }, /* 16-QAM */
 267         { 0x148, 0x7ff0, 0x0a4, 0x7ff8 }, /* 64-QAM */
 268 };
 269
 270 static u16 dib3000mc_reg_mobile_mode[] = { 139, 140, 141, 175, 1032 };
 271
 272 static u16 dib3000mc_mobile_mode[][5] = {
 273         { 0x01, 0x0, 0x0, 0x00, 0x12c }, /* fixed */
 274         { 0x01, 0x0, 0x0, 0x00, 0x12c }, /* portable */
 275         { 0x00, 0x0, 0x0, 0x02, 0x000 }, /* mobile */
 276         { 0x00, 0x0, 0x0, 0x02, 0x000 }, /* auto */
 277 };
 278
 279 #define DIB3000MC_REG_DIVERSITY1                (   177)
 280 #define DIB3000MC_DIVERSITY1_DEFAULT    (     1)
 281
 282 #define DIB3000MC_REG_DIVERSITY2                (   178)
 283 #define DIB3000MC_DIVERSITY2_DEFAULT    (     1)
 284
 285 #define DIB3000MC_REG_DIVERSITY3                (   180)
 286 #define DIB3000MC_DIVERSITY3_IN_OFF             (0xfff0)
 287 #define DIB3000MC_DIVERSITY3_IN_ON              (0xfff6)
 288
 289 #define DIB3000MC_REG_FEC_CFG                   (   195)
 290 #define DIB3000MC_FEC_CFG                               (  0x10)
 291
 292 /*
 293  * reg 206, output mode
 294  *              1111 1111
 295  *              |||| ||||
 296  *              |||| |||+- unk
 297  *              |||| ||+-- unk
 298  *              |||| |+--- unk (on by default)
 299  *              |||| +---- fifo_ctrl (1 = inhibit (flushed), 0 = active (unflushed))
 300  *              |||+------ pid_parse (1 = enabled, 0 = disabled)
 301  *              ||+------- outp_188  (1 = TS packet size 188, 0 = packet size 204)
 302  *              |+-------- unk
 303  *              +--------- unk
 304  */
 305
 306 #define DIB3000MC_REG_SMO_MODE                  (   206)
 307 #define DIB3000MC_SMO_MODE_DEFAULT              (1 << 2)
 308 #define DIB3000MC_SMO_MODE_FIFO_FLUSH   (1 << 3)
 309 #define DIB3000MC_SMO_MODE_FIFO_UNFLUSH (0xfff7)
 310 #define DIB3000MC_SMO_MODE_PID_PARSE    (1 << 4)
 311 #define DIB3000MC_SMO_MODE_NO_PID_PARSE (0xffef)
 312 #define DIB3000MC_SMO_MODE_188                  (1 << 5)
 313 #define DIB3000MC_SMO_MODE_SLAVE                (DIB3000MC_SMO_MODE_DEFAULT | \
 314                         DIB3000MC_SMO_MODE_188 | DIB3000MC_SMO_MODE_PID_PARSE | (1<<1))
 315
 316 #define DIB3000MC_REG_FIFO_THRESHOLD    (   207)
 317 #define DIB3000MC_FIFO_THRESHOLD_DEFAULT        (  1792)
 318 #define DIB3000MC_FIFO_THRESHOLD_SLAVE  (   512)
 319 /*
 320  * pidfilter
 321  * it is not a hardware pidfilter but a filter which drops all pids
 322  * except the ones set. When connected to USB1.1 bandwidth this is important.
 323  * DiB3000P/M-C can filter up to 32 PIDs
 324  */
 325 #define DIB3000MC_REG_FIRST_PID                 (   212)
 326 #define DIB3000MC_NUM_PIDS                              (    32)
 327
 328 #define DIB3000MC_REG_OUTMODE                   (   244)
 329 #define DIB3000MC_OM_PARALLEL_GATED_CLK (     0)
 330 #define DIB3000MC_OM_PAR_CONT_CLK               (1 << 11)
 331 #define DIB3000MC_OM_SERIAL                             (2 << 11)
 332 #define DIB3000MC_OM_DIVOUT_ON                  (4 << 11)
 333 #define DIB3000MC_OM_SLAVE                              (DIB3000MC_OM_DIVOUT_ON | DIB3000MC_OM_PAR_CONT_CLK)
 334
 335 #define DIB3000MC_REG_RF_POWER                  (   392)
 336
 337 #define DIB3000MC_REG_FFT_POSITION              (   407)
 338
 339 #define DIB3000MC_REG_DDS_FREQ_MSB              (   414)
 340 #define DIB3000MC_REG_DDS_FREQ_LSB              (   415)
 341
 342 #define DIB3000MC_REG_TIMING_OFFS_MSB   (   416)
 343 #define DIB3000MC_REG_TIMING_OFFS_LSB   (   417)
 344
 345 #define DIB3000MC_REG_TUNING_PARM               (   458)
 346 #define DIB3000MC_TP_QAM(v)                             ((v >> 13) & 0x03)
 347 #define DIB3000MC_TP_HRCH(v)                    ((v >> 12) & 0x01)
 348 #define DIB3000MC_TP_ALPHA(v)                   ((v >> 9) & 0x07)
 349 #define DIB3000MC_TP_FFT(v)                             ((v >> 8) & 0x01)
 350 #define DIB3000MC_TP_FEC_CR_HP(v)               ((v >> 5) & 0x07)
 351 #define DIB3000MC_TP_FEC_CR_LP(v)               ((v >> 2) & 0x07)
 352 #define DIB3000MC_TP_GUARD(v)                   (v & 0x03)
 353
 354 #define DIB3000MC_REG_SIGNAL_NOISE_MSB  (   483)
 355 #define DIB3000MC_REG_SIGNAL_NOISE_LSB  (   484)
 356
 357 #define DIB3000MC_REG_MER                               (   485)
 358
 359 #define DIB3000MC_REG_BER_MSB                   (   500)
 360 #define DIB3000MC_REG_BER_LSB                   (   501)
 361
 362 #define DIB3000MC_REG_PACKET_ERRORS             (   503)
 363
 364 #define DIB3000MC_REG_PACKET_ERROR_COUNT        (   506)
 365
 366 #define DIB3000MC_REG_LOCK_507                  (   507)
 367 #define DIB3000MC_LOCK_507                              (0x0002) // ? name correct ?
 368
 369 #define DIB3000MC_REG_LOCKING                   (   509)
 370 #define DIB3000MC_AGC_LOCK(v)                   (v & 0x8000)
 371 #define DIB3000MC_CARRIER_LOCK(v)               (v & 0x2000)
 372 #define DIB3000MC_MPEG_SYNC_LOCK(v)             (v & 0x0080)
 373 #define DIB3000MC_MPEG_DATA_LOCK(v)             (v & 0x0040)
 374 #define DIB3000MC_TPS_LOCK(v)                   (v & 0x0004)
 375
 376 #define DIB3000MC_REG_AS_IRQ                    (   511)
 377 #define DIB3000MC_AS_IRQ_SUCCESS                (1 << 1)
 378 #define DIB3000MC_AS_IRQ_FAIL                   (     1)
 379
 380 #define DIB3000MC_REG_TUNER                             (   769)
 381
 382 #define DIB3000MC_REG_RST_I2C_ADDR              (  1024)
 383 #define DIB3000MC_DEMOD_ADDR_ON                 (     1)
 384 #define DIB3000MC_DEMOD_ADDR(a)                 ((a << 4) & 0x03F0)
 385
 386 #define DIB3000MC_REG_RESTART                   (  1027)
 387 #define DIB3000MC_RESTART_OFF                   (0x0000)
 388 #define DIB3000MC_RESTART_AGC                   (0x0800)
 389 #define DIB3000MC_RESTART_CONFIG                (0x8000)
 390
 391 #define DIB3000MC_REG_RESTART_VIT               (  1028)
 392 #define DIB3000MC_RESTART_VIT_OFF               (     0)
 393 #define DIB3000MC_RESTART_VIT_ON                (     1)
 394
 395 #define DIB3000MC_REG_CLK_CFG_1                 (  1031)
 396 #define DIB3000MC_CLK_CFG_1_POWER_UP    (     0)
 397 #define DIB3000MC_CLK_CFG_1_POWER_DOWN  (0xffff)
 398
 399 #define DIB3000MC_REG_CLK_CFG_2                 (  1032)
 400 #define DIB3000MC_CLK_CFG_2_PUP_FIXED   (0x012c)
 401 #define DIB3000MC_CLK_CFG_2_PUP_PORT    (0x0104)
 402 #define DIB3000MC_CLK_CFG_2_PUP_MOBILE  (0x0000)
 403 #define DIB3000MC_CLK_CFG_2_POWER_DOWN  (0xffff)
 404
 405 #define DIB3000MC_REG_CLK_CFG_3                 (  1033)
 406 #define DIB3000MC_CLK_CFG_3_POWER_UP    (     0)
 407 #define DIB3000MC_CLK_CFG_3_POWER_DOWN  (0xfff5)
 408
 409 #define DIB3000MC_REG_CLK_CFG_7                 (  1037)
 410 #define DIB3000MC_CLK_CFG_7_INIT                ( 12592)
 411 #define DIB3000MC_CLK_CFG_7_POWER_UP    (~0x0003)
 412 #define DIB3000MC_CLK_CFG_7_PWR_DOWN    (0x0003)
 413 #define DIB3000MC_CLK_CFG_7_DIV_IN_OFF  (1 << 8)
 414
 415 /* was commented out ??? */
 416 #define DIB3000MC_REG_CLK_CFG_8                 (  1038)
 417 #define DIB3000MC_CLK_CFG_8_POWER_UP    (0x160c)
 418
 419 #define DIB3000MC_REG_CLK_CFG_9                 (  1039)
 420 #define DIB3000MC_CLK_CFG_9_POWER_UP    (     0)
 421
 422 /* also clock ??? */
 423 #define DIB3000MC_REG_ELEC_OUT                  (  1040)
 424 #define DIB3000MC_ELEC_OUT_HIGH_Z               (     0)
 425 #define DIB3000MC_ELEC_OUT_DIV_OUT_ON   (     1)
 426 #define DIB3000MC_ELEC_OUT_SLAVE                (     3)
 427
 428 #endif