drivers/media/dvb-frontends/stv0367.c

   1 /*
   2  * stv0367.c
   3  *
   4  * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
   5  *
   6  * Copyright (C) ST Microelectronics.
   7  * Copyright (C) 2010,2011 NetUP Inc.
   8  * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/string.h>
  25 #include <linux/slab.h>
  26 #include <linux/i2c.h>
  27
  28 #include <media/dvb_math.h>
  29
  30 #include "stv0367.h"
  31 #include "stv0367_defs.h"
  32 #include "stv0367_regs.h"
  33 #include "stv0367_priv.h"
  34
  35 /* Max transfer size done by I2C transfer functions */
  36 #define MAX_XFER_SIZE  64
  37
  38 static int stvdebug;
  39 module_param_named(debug, stvdebug, int, 0644);
  40
  41 static int i2cdebug;
  42 module_param_named(i2c_debug, i2cdebug, int, 0644);
  43
  44 #define dprintk(args...) \
  45         do { \
  46                 if (stvdebug) \
  47                         printk(KERN_DEBUG args); \
  48         } while (0)
  49         /* DVB-C */
  50
  51 enum active_demod_state { demod_none, demod_ter, demod_cab };
  52
  53 struct stv0367cab_state {
  54         enum stv0367_cab_signal_type    state;
  55         u32     mclk;
  56         u32     adc_clk;
  57         s32     search_range;
  58         s32     derot_offset;
  59         /* results */
  60         int locked;                     /* channel found                */
  61         u32 freq_khz;                   /* found frequency (in kHz)     */
  62         u32 symbol_rate;                /* found symbol rate (in Bds)   */
  63         enum fe_spectral_inversion spect_inv; /* Spectrum Inversion     */
  64         u32 qamfec_status_reg;          /* status reg to poll for FEC Lock */
  65 };
  66
  67 struct stv0367ter_state {
  68         /* DVB-T */
  69         enum stv0367_ter_signal_type state;
  70         enum stv0367_ter_if_iq_mode if_iq_mode;
  71         enum stv0367_ter_mode mode;/* mode 2K or 8K */
  72         enum fe_guard_interval guard;
  73         enum stv0367_ter_hierarchy hierarchy;
  74         u32 frequency;
  75         enum fe_spectral_inversion sense; /*  current search spectrum */
  76         u8  force; /* force mode/guard */
  77         u8  bw; /* channel width 6, 7 or 8 in MHz */
  78         u8  pBW; /* channel width used during previous lock */
  79         u32 pBER;
  80         u32 pPER;
  81         u32 ucblocks;
  82         s8  echo_pos; /* echo position */
  83         u8  first_lock;
  84         u8  unlock_counter;
  85         u32 agc_val;
  86 };
  87
  88 struct stv0367_state {
  89         struct dvb_frontend fe;
  90         struct i2c_adapter *i2c;
  91         /* config settings */
  92         const struct stv0367_config *config;
  93         u8 chip_id;
  94         /* DVB-C */
  95         struct stv0367cab_state *cab_state;
  96         /* DVB-T */
  97         struct stv0367ter_state *ter_state;
  98         /* flags for operation control */
  99         u8 use_i2c_gatectrl;
 100         u8 deftabs;
 101         u8 reinit_on_setfrontend;
 102         u8 auto_if_khz;
 103         enum active_demod_state activedemod;
 104 };
 105
 106 #define RF_LOOKUP_TABLE_SIZE  31
 107 #define RF_LOOKUP_TABLE2_SIZE 16
 108 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
 109 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
 110         {/*AGC1*/
 111                 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
 112                 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
 113                 76, 77, 78, 80, 83, 85, 88,
 114         }, {/*RF(dbm)*/
 115                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 116                 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
 117                 49, 50, 52, 53, 54, 55, 56,
 118         }
 119 };
 120 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
 121 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
 122         {/*AGC2*/
 123                 28, 29, 31, 32, 34, 35, 36, 37,
 124                 38, 39, 40, 41, 42, 43, 44, 45,
 125         }, {/*RF(dbm)*/
 126                 57, 58, 59, 60, 61, 62, 63, 64,
 127                 65, 66, 67, 68, 69, 70, 71, 72,
 128         }
 129 };
 130
 131 static
 132 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
 133 {
 134         u8 buf[MAX_XFER_SIZE];
 135         struct i2c_msg msg = {
 136                 .addr = state->config->demod_address,
 137                 .flags = 0,
 138                 .buf = buf,
 139                 .len = len + 2
 140         };
 141         int ret;
 142
 143         if (2 + len > sizeof(buf)) {
 144                 printk(KERN_WARNING
 145                        "%s: i2c wr reg=%04x: len=%d is too big!\n",
 146                        KBUILD_MODNAME, reg, len);
 147                 return -EINVAL;
 148         }
 149
 150
 151         buf[0] = MSB(reg);
 152         buf[1] = LSB(reg);
 153         memcpy(buf + 2, data, len);
 154
 155         if (i2cdebug)
 156                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 157                         state->config->demod_address, reg, buf[2]);
 158
 159         ret = i2c_transfer(state->i2c, &msg, 1);
 160         if (ret != 1)
 161                 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
 162                         __func__, state->config->demod_address, reg, buf[2]);
 163
 164         return (ret != 1) ? -EREMOTEIO : 0;
 165 }
 166
 167 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
 168 {
 169         u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 170
 171         return stv0367_writeregs(state, reg, &tmp, 1);
 172 }
 173
 174 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
 175 {
 176         u8 b0[] = { 0, 0 };
 177         u8 b1[] = { 0 };
 178         struct i2c_msg msg[] = {
 179                 {
 180                         .addr = state->config->demod_address,
 181                         .flags = 0,
 182                         .buf = b0,
 183                         .len = 2
 184                 }, {
 185                         .addr = state->config->demod_address,
 186                         .flags = I2C_M_RD,
 187                         .buf = b1,
 188                         .len = 1
 189                 }
 190         };
 191         int ret;
 192
 193         b0[0] = MSB(reg);
 194         b0[1] = LSB(reg);
 195
 196         ret = i2c_transfer(state->i2c, msg, 2);
 197         if (ret != 2)
 198                 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
 199                         __func__, state->config->demod_address, reg, b1[0]);
 200
 201         if (i2cdebug)
 202                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 203                         state->config->demod_address, reg, b1[0]);
 204
 205         return b1[0];
 206 }
 207
 208 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 209 {
 210         u8 position = 0, i = 0;
 211
 212         (*mask) = label & 0xff;
 213
 214         while ((position == 0) && (i < 8)) {
 215                 position = ((*mask) >> i) & 0x01;
 216                 i++;
 217         }
 218
 219         (*pos) = (i - 1);
 220 }
 221
 222 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
 223 {
 224         u8 reg, mask, pos;
 225
 226         reg = stv0367_readreg(state, (label >> 16) & 0xffff);
 227         extract_mask_pos(label, &mask, &pos);
 228
 229         val = mask & (val << pos);
 230
 231         reg = (reg & (~mask)) | val;
 232         stv0367_writereg(state, (label >> 16) & 0xffff, reg);
 233
 234 }
 235
 236 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
 237 {
 238         u8 mask, pos;
 239
 240         extract_mask_pos(label, &mask, &pos);
 241
 242         val = mask & (val << pos);
 243
 244         (*reg) = ((*reg) & (~mask)) | val;
 245 }
 246
 247 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
 248 {
 249         u8 val = 0xff;
 250         u8 mask, pos;
 251
 252         extract_mask_pos(label, &mask, &pos);
 253
 254         val = stv0367_readreg(state, label >> 16);
 255         val = (val & mask) >> pos;
 256
 257         return val;
 258 }
 259
 260 #if 0 /* Currently, unused */
 261 static u8 stv0367_getbits(u8 reg, u32 label)
 262 {
 263         u8 mask, pos;
 264
 265         extract_mask_pos(label, &mask, &pos);
 266
 267         return (reg & mask) >> pos;
 268 }
 269 #endif
 270
 271 static void stv0367_write_table(struct stv0367_state *state,
 272                                 const struct st_register *deftab)
 273 {
 274         int i = 0;
 275
 276         while (1) {
 277                 if (!deftab[i].addr)
 278                         break;
 279                 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
 280                 i++;
 281         }
 282 }
 283
 284 static void stv0367_pll_setup(struct stv0367_state *state,
 285                                 u32 icspeed, u32 xtal)
 286 {
 287         /* note on regs: R367TER_* and R367CAB_* defines each point to
 288          * 0xf0d8, so just use R367TER_ for both cases
 289          */
 290
 291         switch (icspeed) {
 292         case STV0367_ICSPEED_58000:
 293                 switch (xtal) {
 294                 default:
 295                 case 27000000:
 296                         dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
 297                         /* PLLMDIV: 27, PLLNDIV: 232 */
 298                         stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
 299                         stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
 300                         break;
 301                 }
 302                 break;
 303         default:
 304         case STV0367_ICSPEED_53125:
 305                 switch (xtal) {
 306                         /* set internal freq to 53.125MHz */
 307                 case 16000000:
 308                         stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
 309                         stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
 310                         break;
 311                 case 25000000:
 312                         stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
 313                         stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
 314                         break;
 315                 default:
 316                 case 27000000:
 317                         dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
 318                         stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
 319                         stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
 320                         break;
 321                 case 30000000:
 322                         stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
 323                         stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
 324                         break;
 325                 }
 326         }
 327
 328         stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
 329 }
 330
 331 static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
 332 {
 333         if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
 334                 state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
 335                 *ifkhz = *ifkhz / 1000; /* hz -> khz */
 336         } else
 337                 *ifkhz = state->config->if_khz;
 338
 339         return 0;
 340 }
 341
 342 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
 343 {
 344         struct stv0367_state *state = fe->demodulator_priv;
 345         u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
 346
 347         dprintk("%s:\n", __func__);
 348
 349         if (enable) {
 350                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
 351                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
 352         } else {
 353                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
 354                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
 355         }
 356
 357         stv0367_writereg(state, R367TER_I2CRPT, tmp);
 358
 359         return 0;
 360 }
 361
 362 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
 363 {
 364         struct dvb_frontend_ops *frontend_ops = &fe->ops;
 365         struct dvb_tuner_ops    *tuner_ops = &frontend_ops->tuner_ops;
 366         u32 freq = 0;
 367         int err = 0;
 368
 369         dprintk("%s:\n", __func__);
 370
 371         if (tuner_ops->get_frequency) {
 372                 err = tuner_ops->get_frequency(fe, &freq);
 373                 if (err < 0) {
 374                         printk(KERN_ERR "%s: Invalid parameter\n", __func__);
 375                         return err;
 376                 }
 377
 378                 dprintk("%s: frequency=%d\n", __func__, freq);
 379
 380         } else
 381                 return -1;
 382
 383         return freq;
 384 }
 385
 386 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
 387         {
 388                 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
 389                 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
 390                 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
 391                 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
 392                 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
 393                 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
 394         }, {
 395                 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
 396                 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
 397                 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
 398                 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
 399                 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
 400                 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
 401         }, {
 402                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 403                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 404                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 405                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 406                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 407                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 408         }
 409 };
 410
 411 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
 412         {
 413                 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
 414                 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
 415                 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
 416                 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
 417                 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
 418                 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
 419         }, {
 420                 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
 421                 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
 422                 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
 423                 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
 424                 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
 425                 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
 426         }, {
 427                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 428                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 429                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 430                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 431                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 432                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 433         }
 434 };
 435
 436 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
 437         {
 438                 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
 439                 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
 440                 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
 441                 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
 442                 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
 443                 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
 444         }, {
 445                 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
 446                 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
 447                 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
 448                 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
 449                 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
 450                 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
 451
 452         }, {
 453                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 454                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 455                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 456                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 457                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 458                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 459         }
 460 };
 461
 462 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
 463 {
 464         u32 mclk_Hz = 0; /* master clock frequency (Hz) */
 465         u32 m, n, p;
 466
 467         dprintk("%s:\n", __func__);
 468
 469         if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
 470                 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
 471                 if (n == 0)
 472                         n = n + 1;
 473
 474                 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
 475                 if (m == 0)
 476                         m = m + 1;
 477
 478                 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
 479                 if (p > 5)
 480                         p = 5;
 481
 482                 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
 483
 484                 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
 485                                 n, m, p, mclk_Hz, ExtClk_Hz);
 486         } else
 487                 mclk_Hz = ExtClk_Hz;
 488
 489         dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
 490
 491         return mclk_Hz;
 492 }
 493
 494 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
 495                                 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
 496 {
 497         int i, j, k, freq;
 498
 499         dprintk("%s:\n", __func__);
 500
 501         freq = stv0367ter_get_mclk(state, DemodXtal);
 502
 503         if (freq == 53125000)
 504                 k = 1; /* equivalent to Xtal 25M on 362*/
 505         else if (freq == 54000000)
 506                 k = 0; /* equivalent to Xtal 27M on 362*/
 507         else if (freq == 52500000)
 508                 k = 2; /* equivalent to Xtal 30M on 362*/
 509         else
 510                 return 0;
 511
 512         for (i = 1; i <= 6; i++) {
 513                 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
 514
 515                 for (j = 1; j <= 5; j++) {
 516                         stv0367_writereg(state,
 517                                 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
 518                                 MSB(CellsCoeffs[k][i-1][j-1]));
 519                         stv0367_writereg(state,
 520                                 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
 521                                 LSB(CellsCoeffs[k][i-1][j-1]));
 522                 }
 523         }
 524
 525         return 1;
 526
 527 }
 528
 529 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
 530 {
 531         dprintk("%s:\n", __func__);
 532
 533         stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
 534
 535         /* Lock detect 1 */
 536         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
 537         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
 538         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
 539
 540         /* Lock detect 2 */
 541         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
 542         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
 543         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
 544
 545         /* Lock detect 3 */
 546         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
 547         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
 548         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
 549
 550         /* Lock detect 4 */
 551         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
 552         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
 553         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
 554
 555 }
 556
 557 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
 558                                                         u32 DemodXtalValue)
 559 {
 560         dprintk("%s:\n", __func__);
 561
 562         stv0367_writebits(state, F367TER_NRST_IIR, 0);
 563
 564         switch (Bandwidth) {
 565         case 6:
 566                 if (!stv0367ter_filt_coeff_init(state,
 567                                 CellsCoeffs_6MHz_367cofdm,
 568                                 DemodXtalValue))
 569                         return 0;
 570                 break;
 571         case 7:
 572                 if (!stv0367ter_filt_coeff_init(state,
 573                                 CellsCoeffs_7MHz_367cofdm,
 574                                 DemodXtalValue))
 575                         return 0;
 576                 break;
 577         case 8:
 578                 if (!stv0367ter_filt_coeff_init(state,
 579                                 CellsCoeffs_8MHz_367cofdm,
 580                                 DemodXtalValue))
 581                         return 0;
 582                 break;
 583         default:
 584                 return 0;
 585         }
 586
 587         stv0367_writebits(state, F367TER_NRST_IIR, 1);
 588
 589         return 1;
 590 }
 591
 592 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
 593 {
 594
 595         u8 com_n;
 596
 597         dprintk("%s:\n", __func__);
 598
 599         com_n = stv0367_readbits(state, F367TER_COM_N);
 600
 601         stv0367_writebits(state, F367TER_COM_N, 0x07);
 602
 603         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
 604         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
 605
 606         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
 607         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
 608
 609         stv0367_writebits(state, F367TER_COM_N, com_n);
 610
 611 }
 612
 613 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
 614 {
 615         int local_tempo = 0;
 616         switch (mode) {
 617         case 0:
 618                 local_tempo = tempo1;
 619                 break;
 620         case 1:
 621                 local_tempo = tempo2;
 622                 break ;
 623
 624         case 2:
 625                 local_tempo = tempo3;
 626                 break;
 627
 628         default:
 629                 break;
 630         }
 631         /*      msleep(local_tempo);  */
 632         return local_tempo;
 633 }
 634
 635 static enum
 636 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
 637 {
 638         int wd = 100;
 639         unsigned short int SYR_var;
 640         s32 SYRStatus;
 641
 642         dprintk("%s:\n", __func__);
 643
 644         SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
 645
 646         while ((!SYR_var) && (wd > 0)) {
 647                 usleep_range(2000, 3000);
 648                 wd -= 2;
 649                 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
 650         }
 651
 652         if (!SYR_var)
 653                 SYRStatus = FE_TER_NOSYMBOL;
 654         else
 655                 SYRStatus =  FE_TER_SYMBOLOK;
 656
 657         dprintk("stv0367ter_check_syr SYRStatus %s\n",
 658                                 SYR_var == 0 ? "No Symbol" : "OK");
 659
 660         return SYRStatus;
 661 }
 662
 663 static enum
 664 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
 665                                                                 s32 FFTmode)
 666 {
 667
 668         s32  CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
 669         int wd = 0;
 670
 671         dprintk("%s:\n", __func__);
 672
 673         switch (FFTmode) {
 674         case 0: /*2k mode*/
 675                 CPAMPMin = 20;
 676                 wd = 10;
 677                 break;
 678         case 1: /*8k mode*/
 679                 CPAMPMin = 80;
 680                 wd = 55;
 681                 break;
 682         case 2: /*4k mode*/
 683                 CPAMPMin = 40;
 684                 wd = 30;
 685                 break;
 686         default:
 687                 CPAMPMin = 0xffff;  /*drives to NOCPAMP */
 688                 break;
 689         }
 690
 691         dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
 692
 693         CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
 694         while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
 695                 usleep_range(1000, 2000);
 696                 wd -= 1;
 697                 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
 698                 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
 699         }
 700         dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
 701         if (CPAMPvalue < CPAMPMin) {
 702                 CPAMPStatus = FE_TER_NOCPAMP;
 703                 dprintk("%s: CPAMP failed\n", __func__);
 704         } else {
 705                 dprintk("%s: CPAMP OK !\n", __func__);
 706                 CPAMPStatus = FE_TER_CPAMPOK;
 707         }
 708
 709         return CPAMPStatus;
 710 }
 711
 712 static enum stv0367_ter_signal_type
 713 stv0367ter_lock_algo(struct stv0367_state *state)
 714 {
 715         enum stv0367_ter_signal_type ret_flag;
 716         short int wd, tempo;
 717         u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
 718         u8 tmp, tmp2;
 719
 720         dprintk("%s:\n", __func__);
 721
 722         if (state == NULL)
 723                 return FE_TER_SWNOK;
 724
 725         try = 0;
 726         do {
 727                 ret_flag = FE_TER_LOCKOK;
 728
 729                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
 730
 731                 if (state->config->if_iq_mode != 0)
 732                         stv0367_writebits(state, F367TER_COM_N, 0x07);
 733
 734                 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
 735                 stv0367_writebits(state, F367TER_MODE, 0);
 736                 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
 737                 usleep_range(5000, 10000);
 738
 739                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
 740
 741
 742                 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
 743                         return FE_TER_NOSYMBOL;
 744                 else { /*
 745                         if chip locked on wrong mode first try,
 746                         it must lock correctly second try */
 747                         mode = stv0367_readbits(state, F367TER_SYR_MODE);
 748                         if (stv0367ter_check_cpamp(state, mode) ==
 749                                                         FE_TER_NOCPAMP) {
 750                                 if (try == 0)
 751                                         ret_flag = FE_TER_NOCPAMP;
 752
 753                         }
 754                 }
 755
 756                 try++;
 757         } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
 758
 759         tmp  = stv0367_readreg(state, R367TER_SYR_STAT);
 760         tmp2 = stv0367_readreg(state, R367TER_STATUS);
 761         dprintk("state=%p\n", state);
 762         dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
 763                                                         mode, tmp, tmp2);
 764
 765         tmp  = stv0367_readreg(state, R367TER_PRVIT);
 766         tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
 767         dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
 768
 769         tmp  = stv0367_readreg(state, R367TER_GAIN_SRC1);
 770         dprintk("GAIN_SRC1=0x%x\n", tmp);
 771
 772         if ((mode != 0) && (mode != 1) && (mode != 2))
 773                 return FE_TER_SWNOK;
 774
 775         /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
 776
 777         /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
 778         and set channel predictor in automatic */
 779 #if 0
 780         switch (guard) {
 781
 782         case 0:
 783         case 1:
 784                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
 785                 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
 786                 break;
 787         case 2:
 788         case 3:
 789                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
 790                 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
 791                 break;
 792
 793         default:
 794                 return FE_TER_SWNOK;
 795         }
 796 #endif
 797
 798         /*reset fec an reedsolo FOR 367 only*/
 799         stv0367_writebits(state, F367TER_RST_SFEC, 1);
 800         stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
 801         usleep_range(1000, 2000);
 802         stv0367_writebits(state, F367TER_RST_SFEC, 0);
 803         stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
 804
 805         u_var1 = stv0367_readbits(state, F367TER_LK);
 806         u_var2 = stv0367_readbits(state, F367TER_PRF);
 807         u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
 808         /*      u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
 809
 810         wd = stv0367ter_duration(mode, 125, 500, 250);
 811         tempo = stv0367ter_duration(mode, 4, 16, 8);
 812
 813         /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4))  && (wd>=0)) */
 814         while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
 815                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
 816                 wd -= tempo;
 817                 u_var1 = stv0367_readbits(state, F367TER_LK);
 818                 u_var2 = stv0367_readbits(state, F367TER_PRF);
 819                 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
 820                 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
 821         }
 822
 823         if (!u_var1)
 824                 return FE_TER_NOLOCK;
 825
 826
 827         if (!u_var2)
 828                 return FE_TER_NOPRFOUND;
 829
 830         if (!u_var3)
 831                 return FE_TER_NOTPS;
 832
 833         guard = stv0367_readbits(state, F367TER_SYR_GUARD);
 834         stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
 835         switch (guard) {
 836         case 0:
 837         case 1:
 838                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
 839                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
 840                 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
 841                 break;
 842         case 2:
 843         case 3:
 844                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
 845                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
 846                 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
 847                 break;
 848
 849         default:
 850                 return FE_TER_SWNOK;
 851         }
 852
 853         /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
 854         if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
 855                         (mode == 1) &&
 856                         (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
 857                 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
 858                 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
 859                 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
 860         } else
 861                 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
 862
 863         wd = stv0367ter_duration(mode, 125, 500, 250);
 864         u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
 865
 866         while ((!u_var4) && (wd >= 0)) {
 867                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
 868                 wd -= tempo;
 869                 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
 870         }
 871
 872         if (!u_var4)
 873                 return FE_TER_NOLOCK;
 874
 875         /* for 367 leave COM_N at 0x7 for IQ_mode*/
 876         /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
 877                 tempo=0;
 878                 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
 879                 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
 880                         ChipWaitOrAbort(state,1);
 881                         tempo+=1;
 882                 }
 883
 884                 stv0367_writebits(state,F367TER_COM_N,0x17);
 885         } */
 886
 887         stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
 888
 889         dprintk("FE_TER_LOCKOK !!!\n");
 890
 891         return  FE_TER_LOCKOK;
 892
 893 }
 894
 895 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
 896                                         enum stv0367_ts_mode PathTS)
 897 {
 898
 899         dprintk("%s:\n", __func__);
 900
 901         if (state == NULL)
 902                 return;
 903
 904         stv0367_writebits(state, F367TER_TS_DIS, 0);
 905         switch (PathTS) {
 906         default:
 907                 /*for removing warning :default we can assume in parallel mode*/
 908         case STV0367_PARALLEL_PUNCT_CLOCK:
 909                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
 910                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
 911                 break;
 912         case STV0367_SERIAL_PUNCT_CLOCK:
 913                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
 914                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
 915                 break;
 916         }
 917 }
 918
 919 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
 920                                         enum stv0367_clk_pol clock)
 921 {
 922
 923         dprintk("%s:\n", __func__);
 924
 925         if (state == NULL)
 926                 return;
 927
 928         switch (clock) {
 929         case STV0367_RISINGEDGE_CLOCK:
 930                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
 931                 break;
 932         case STV0367_FALLINGEDGE_CLOCK:
 933                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
 934                 break;
 935                 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
 936         default:
 937                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
 938                 break;
 939         }
 940 }
 941
 942 #if 0
 943 static void stv0367ter_core_sw(struct stv0367_state *state)
 944 {
 945
 946         dprintk("%s:\n", __func__);
 947
 948         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
 949         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
 950         msleep(350);
 951 }
 952 #endif
 953 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
 954 {
 955         struct stv0367_state *state = fe->demodulator_priv;
 956
 957         dprintk("%s:\n", __func__);
 958
 959         if (standby_on) {
 960                 stv0367_writebits(state, F367TER_STDBY, 1);
 961                 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
 962                 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
 963         } else {
 964                 stv0367_writebits(state, F367TER_STDBY, 0);
 965                 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
 966                 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
 967         }
 968
 969         return 0;
 970 }
 971
 972 static int stv0367ter_sleep(struct dvb_frontend *fe)
 973 {
 974         return stv0367ter_standby(fe, 1);
 975 }
 976
 977 static int stv0367ter_init(struct dvb_frontend *fe)
 978 {
 979         struct stv0367_state *state = fe->demodulator_priv;
 980         struct stv0367ter_state *ter_state = state->ter_state;
 981
 982         dprintk("%s:\n", __func__);
 983
 984         ter_state->pBER = 0;
 985
 986         stv0367_write_table(state,
 987                 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
 988
 989         stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
 990
 991         stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
 992         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
 993
 994         /*Set TS1 and TS2 to serial or parallel mode */
 995         stv0367ter_set_ts_mode(state, state->config->ts_mode);
 996         stv0367ter_set_clk_pol(state, state->config->clk_pol);
 997
 998         state->chip_id = stv0367_readreg(state, R367TER_ID);
 999         ter_state->first_lock = 0;
1000         ter_state->unlock_counter = 2;
1001
1002         return 0;
1003 }
1004
1005 static int stv0367ter_algo(struct dvb_frontend *fe)
1006 {
1007         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1008         struct stv0367_state *state = fe->demodulator_priv;
1009         struct stv0367ter_state *ter_state = state->ter_state;
1010         int offset = 0, tempo = 0;
1011         u8 u_var;
1012         u8 /*constell,*/ counter;
1013         s8 step;
1014         s32 timing_offset = 0;
1015         u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
1016
1017         dprintk("%s:\n", __func__);
1018
1019         stv0367_get_if_khz(state, &ifkhz);
1020
1021         ter_state->frequency = p->frequency;
1022         ter_state->force = FE_TER_FORCENONE
1023                         + stv0367_readbits(state, F367TER_FORCE) * 2;
1024         ter_state->if_iq_mode = state->config->if_iq_mode;
1025         switch (state->config->if_iq_mode) {
1026         case FE_TER_NORMAL_IF_TUNER:  /* Normal IF mode */
1027                 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1028                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1029                 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1030                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1031                 break;
1032         case FE_TER_LONGPATH_IF_TUNER:  /* Long IF mode */
1033                 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1034                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1035                 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1036                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1037                 break;
1038         case FE_TER_IQ_TUNER:  /* IQ mode */
1039                 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1040                 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1041                 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1042                 break;
1043         default:
1044                 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1045                 return -EINVAL;
1046         }
1047
1048         usleep_range(5000, 7000);
1049
1050         switch (p->inversion) {
1051         case INVERSION_AUTO:
1052         default:
1053                 dprintk("%s: inversion AUTO\n", __func__);
1054                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1055                         stv0367_writebits(state, F367TER_IQ_INVERT,
1056                                                 ter_state->sense);
1057                 else
1058                         stv0367_writebits(state, F367TER_INV_SPECTR,
1059                                                 ter_state->sense);
1060
1061                 break;
1062         case INVERSION_ON:
1063         case INVERSION_OFF:
1064                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1065                         stv0367_writebits(state, F367TER_IQ_INVERT,
1066                                                 p->inversion);
1067                 else
1068                         stv0367_writebits(state, F367TER_INV_SPECTR,
1069                                                 p->inversion);
1070
1071                 break;
1072         }
1073
1074         if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1075                                 (ter_state->pBW != ter_state->bw)) {
1076                 stv0367ter_agc_iir_lock_detect_set(state);
1077
1078                 /*set fine agc target to 180 for LPIF or IQ mode*/
1079                 /* set Q_AGCTarget */
1080                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1081                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1082                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1083
1084                 /* set Q_AGCTarget */
1085                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1086                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1087                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1088
1089                 if (!stv0367_iir_filt_init(state, ter_state->bw,
1090                                                 state->config->xtal))
1091                         return -EINVAL;
1092                 /*set IIR filter once for 6,7 or 8MHz BW*/
1093                 ter_state->pBW = ter_state->bw;
1094
1095                 stv0367ter_agc_iir_rst(state);
1096         }
1097
1098         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1099                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1100         else
1101                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1102
1103         InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1104         temp = (int)
1105                 ((((ter_state->bw * 64 * (1 << 15) * 100)
1106                                                 / (InternalFreq)) * 10) / 7);
1107
1108         stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1109         temp = temp / 2;
1110         stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1111         stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1112
1113         temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1114                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1115                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1116         temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1117         stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1118         stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1119         temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1120                         stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1121
1122         temp = (int)
1123                 ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
1124
1125         dprintk("DEROT temp=0x%x\n", temp);
1126         stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1127         stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1128
1129         ter_state->echo_pos = 0;
1130         ter_state->ucblocks = 0; /* liplianin */
1131         ter_state->pBER = 0; /* liplianin */
1132         stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1133
1134         if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1135                 return 0;
1136
1137         ter_state->state = FE_TER_LOCKOK;
1138
1139         ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1140         ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1141
1142         ter_state->first_lock = 1; /* we know sense now :) */
1143
1144         ter_state->agc_val =
1145                         (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1146                         (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1147                         stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1148                         (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1149
1150         /* Carrier offset calculation */
1151         stv0367_writebits(state, F367TER_FREEZE, 1);
1152         offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1153         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1154         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1155         stv0367_writebits(state, F367TER_FREEZE, 0);
1156         if (offset > 8388607)
1157                 offset -= 16777216;
1158
1159         offset = offset * 2 / 16384;
1160
1161         if (ter_state->mode == FE_TER_MODE_2K)
1162                 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1163         else if (ter_state->mode == FE_TER_MODE_4K)
1164                 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1165         else  if (ter_state->mode == FE_TER_MODE_8K)
1166                 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1167
1168         if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1169                 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1170                                 (stv0367_readbits(state,
1171                                         F367TER_STATUS_INV_SPECRUM) == 1)))
1172                         offset = offset * -1;
1173         }
1174
1175         if (ter_state->bw == 6)
1176                 offset = (offset * 6) / 8;
1177         else if (ter_state->bw == 7)
1178                 offset = (offset * 7) / 8;
1179
1180         ter_state->frequency += offset;
1181
1182         tempo = 10;  /* exit even if timing_offset stays null */
1183         while ((timing_offset == 0) && (tempo > 0)) {
1184                 usleep_range(10000, 20000);     /*was 20ms  */
1185                 /* fine tuning of timing offset if required */
1186                 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1187                                 + 256 * stv0367_readbits(state,
1188                                                         F367TER_TRL_TOFFSET_HI);
1189                 if (timing_offset >= 32768)
1190                         timing_offset -= 65536;
1191                 trl_nomrate = (512 * stv0367_readbits(state,
1192                                                         F367TER_TRL_NOMRATE_HI)
1193                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1194                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1195
1196                 timing_offset = ((signed)(1000000 / trl_nomrate) *
1197                                                         timing_offset) / 2048;
1198                 tempo--;
1199         }
1200
1201         if (timing_offset <= 0) {
1202                 timing_offset = (timing_offset - 11) / 22;
1203                 step = -1;
1204         } else {
1205                 timing_offset = (timing_offset + 11) / 22;
1206                 step = 1;
1207         }
1208
1209         for (counter = 0; counter < abs(timing_offset); counter++) {
1210                 trl_nomrate += step;
1211                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1212                                                 trl_nomrate % 2);
1213                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1214                                                 trl_nomrate / 2);
1215                 usleep_range(1000, 2000);
1216         }
1217
1218         usleep_range(5000, 6000);
1219         /* unlocks could happen in case of trl centring big step,
1220         then a core off/on restarts demod */
1221         u_var = stv0367_readbits(state, F367TER_LK);
1222
1223         if (!u_var) {
1224                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1225                 msleep(20);
1226                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1233 {
1234         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1235         struct stv0367_state *state = fe->demodulator_priv;
1236         struct stv0367ter_state *ter_state = state->ter_state;
1237
1238         /*u8 trials[2]; */
1239         s8 num_trials, index;
1240         u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1241
1242         if (state->reinit_on_setfrontend)
1243                 stv0367ter_init(fe);
1244
1245         if (fe->ops.tuner_ops.set_params) {
1246                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1247                         fe->ops.i2c_gate_ctrl(fe, 1);
1248                 fe->ops.tuner_ops.set_params(fe);
1249                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1250                         fe->ops.i2c_gate_ctrl(fe, 0);
1251         }
1252
1253         switch (p->transmission_mode) {
1254         default:
1255         case TRANSMISSION_MODE_AUTO:
1256         case TRANSMISSION_MODE_2K:
1257                 ter_state->mode = FE_TER_MODE_2K;
1258                 break;
1259 /*      case TRANSMISSION_MODE_4K:
1260                 pLook.mode = FE_TER_MODE_4K;
1261                 break;*/
1262         case TRANSMISSION_MODE_8K:
1263                 ter_state->mode = FE_TER_MODE_8K;
1264                 break;
1265         }
1266
1267         switch (p->guard_interval) {
1268         default:
1269         case GUARD_INTERVAL_1_32:
1270         case GUARD_INTERVAL_1_16:
1271         case GUARD_INTERVAL_1_8:
1272         case GUARD_INTERVAL_1_4:
1273                 ter_state->guard = p->guard_interval;
1274                 break;
1275         case GUARD_INTERVAL_AUTO:
1276                 ter_state->guard = GUARD_INTERVAL_1_32;
1277                 break;
1278         }
1279
1280         switch (p->bandwidth_hz) {
1281         case 6000000:
1282                 ter_state->bw = FE_TER_CHAN_BW_6M;
1283                 break;
1284         case 7000000:
1285                 ter_state->bw = FE_TER_CHAN_BW_7M;
1286                 break;
1287         case 8000000:
1288         default:
1289                 ter_state->bw = FE_TER_CHAN_BW_8M;
1290         }
1291
1292         ter_state->hierarchy = FE_TER_HIER_NONE;
1293
1294         switch (p->inversion) {
1295         case INVERSION_OFF:
1296         case INVERSION_ON:
1297                 num_trials = 1;
1298                 break;
1299         default:
1300                 num_trials = 2;
1301                 if (ter_state->first_lock)
1302                         num_trials = 1;
1303                 break;
1304         }
1305
1306         ter_state->state = FE_TER_NOLOCK;
1307         index = 0;
1308
1309         while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1310                 if (!ter_state->first_lock) {
1311                         if (p->inversion == INVERSION_AUTO)
1312                                 ter_state->sense = SenseTrials[index];
1313
1314                 }
1315                 stv0367ter_algo(fe);
1316
1317                 if ((ter_state->state == FE_TER_LOCKOK) &&
1318                                 (p->inversion == INVERSION_AUTO) &&
1319                                                                 (index == 1)) {
1320                         /* invert spectrum sense */
1321                         SenseTrials[index] = SenseTrials[0];
1322                         SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1323                 }
1324
1325                 index++;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1332 {
1333         struct stv0367_state *state = fe->demodulator_priv;
1334         struct stv0367ter_state *ter_state = state->ter_state;
1335         u32 errs = 0;
1336
1337         /*wait for counting completion*/
1338         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1339                 errs =
1340                         ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1341                         * (1 << 16))
1342                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1343                         * (1 << 8))
1344                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1345                 ter_state->ucblocks = errs;
1346         }
1347
1348         (*ucblocks) = ter_state->ucblocks;
1349
1350         return 0;
1351 }
1352
1353 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1354                                    struct dtv_frontend_properties *p)
1355 {
1356         struct stv0367_state *state = fe->demodulator_priv;
1357         struct stv0367ter_state *ter_state = state->ter_state;
1358         enum stv0367_ter_mode mode;
1359         int constell = 0,/* snr = 0,*/ Data = 0;
1360
1361         p->frequency = stv0367_get_tuner_freq(fe);
1362         if ((int)p->frequency < 0)
1363                 p->frequency = -p->frequency;
1364
1365         constell = stv0367_readbits(state, F367TER_TPS_CONST);
1366         if (constell == 0)
1367                 p->modulation = QPSK;
1368         else if (constell == 1)
1369                 p->modulation = QAM_16;
1370         else
1371                 p->modulation = QAM_64;
1372
1373         p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1374
1375         /* Get the Hierarchical mode */
1376         Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1377
1378         switch (Data) {
1379         case 0:
1380                 p->hierarchy = HIERARCHY_NONE;
1381                 break;
1382         case 1:
1383                 p->hierarchy = HIERARCHY_1;
1384                 break;
1385         case 2:
1386                 p->hierarchy = HIERARCHY_2;
1387                 break;
1388         case 3:
1389                 p->hierarchy = HIERARCHY_4;
1390                 break;
1391         default:
1392                 p->hierarchy = HIERARCHY_AUTO;
1393                 break; /* error */
1394         }
1395
1396         /* Get the FEC Rate */
1397         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1398                 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1399         else
1400                 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1401
1402         switch (Data) {
1403         case 0:
1404                 p->code_rate_HP = FEC_1_2;
1405                 break;
1406         case 1:
1407                 p->code_rate_HP = FEC_2_3;
1408                 break;
1409         case 2:
1410                 p->code_rate_HP = FEC_3_4;
1411                 break;
1412         case 3:
1413                 p->code_rate_HP = FEC_5_6;
1414                 break;
1415         case 4:
1416                 p->code_rate_HP = FEC_7_8;
1417                 break;
1418         default:
1419                 p->code_rate_HP = FEC_AUTO;
1420                 break; /* error */
1421         }
1422
1423         mode = stv0367_readbits(state, F367TER_SYR_MODE);
1424
1425         switch (mode) {
1426         case FE_TER_MODE_2K:
1427                 p->transmission_mode = TRANSMISSION_MODE_2K;
1428                 break;
1429 /*      case FE_TER_MODE_4K:
1430                 p->transmission_mode = TRANSMISSION_MODE_4K;
1431                 break;*/
1432         case FE_TER_MODE_8K:
1433                 p->transmission_mode = TRANSMISSION_MODE_8K;
1434                 break;
1435         default:
1436                 p->transmission_mode = TRANSMISSION_MODE_AUTO;
1437         }
1438
1439         p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
1440
1441         return 0;
1442 }
1443
1444 static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
1445 {
1446         struct stv0367_state *state = fe->demodulator_priv;
1447         u32 snru32 = 0;
1448         int cpt = 0;
1449         u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1450
1451         while (cpt < 10) {
1452                 usleep_range(2000, 3000);
1453                 if (cut == 0x50) /*cut 1.0 cut 1.1*/
1454                         snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1455                 else /*cu2.0*/
1456                         snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1457
1458                 cpt++;
1459         }
1460         snru32 /= 10;/*average on 10 values*/
1461
1462         return snru32;
1463 }
1464
1465 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
1466 {
1467         u32 snrval = stv0367ter_snr_readreg(fe);
1468
1469         *snr = snrval / 1000;
1470
1471         return 0;
1472 }
1473
1474 #if 0
1475 static int stv0367ter_status(struct dvb_frontend *fe)
1476 {
1477
1478         struct stv0367_state *state = fe->demodulator_priv;
1479         struct stv0367ter_state *ter_state = state->ter_state;
1480         int locked = FALSE;
1481
1482         locked = (stv0367_readbits(state, F367TER_LK));
1483         if (!locked)
1484                 ter_state->unlock_counter += 1;
1485         else
1486                 ter_state->unlock_counter = 0;
1487
1488         if (ter_state->unlock_counter > 2) {
1489                 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1490                                 (!stv0367_readbits(state, F367TER_LK))) {
1491                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1492                         usleep_range(2000, 3000);
1493                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1494                         msleep(350);
1495                         locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1496                                         (stv0367_readbits(state, F367TER_LK));
1497                 }
1498
1499         }
1500
1501         return locked;
1502 }
1503 #endif
1504 static int stv0367ter_read_status(struct dvb_frontend *fe,
1505                                   enum fe_status *status)
1506 {
1507         struct stv0367_state *state = fe->demodulator_priv;
1508
1509         dprintk("%s:\n", __func__);
1510
1511         *status = 0;
1512
1513         if (stv0367_readbits(state, F367TER_LK)) {
1514                 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
1515                           | FE_HAS_SYNC | FE_HAS_LOCK;
1516                 dprintk("%s: stv0367 has locked\n", __func__);
1517         }
1518
1519         return 0;
1520 }
1521
1522 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
1523 {
1524         struct stv0367_state *state = fe->demodulator_priv;
1525         struct stv0367ter_state *ter_state = state->ter_state;
1526         u32 Errors = 0, tber = 0, temporary = 0;
1527         int abc = 0, def = 0;
1528
1529
1530         /*wait for counting completion*/
1531         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1532                 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1533                         * (1 << 16))
1534                         + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1535                         * (1 << 8))
1536                         + ((u32)stv0367_readbits(state,
1537                                                 F367TER_SFEC_ERR_CNT_LO));
1538         /*measurement not completed, load previous value*/
1539         else {
1540                 tber = ter_state->pBER;
1541                 return 0;
1542         }
1543
1544         abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1545         def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1546
1547         if (Errors == 0) {
1548                 tber = 0;
1549         } else if (abc == 0x7) {
1550                 if (Errors <= 4) {
1551                         temporary = (Errors * 1000000000) / (8 * (1 << 14));
1552                 } else if (Errors <= 42) {
1553                         temporary = (Errors * 100000000) / (8 * (1 << 14));
1554                         temporary = temporary * 10;
1555                 } else if (Errors <= 429) {
1556                         temporary = (Errors * 10000000) / (8 * (1 << 14));
1557                         temporary = temporary * 100;
1558                 } else if (Errors <= 4294) {
1559                         temporary = (Errors * 1000000) / (8 * (1 << 14));
1560                         temporary = temporary * 1000;
1561                 } else if (Errors <= 42949) {
1562                         temporary = (Errors * 100000) / (8 * (1 << 14));
1563                         temporary = temporary * 10000;
1564                 } else if (Errors <= 429496) {
1565                         temporary = (Errors * 10000) / (8 * (1 << 14));
1566                         temporary = temporary * 100000;
1567                 } else { /*if (Errors<4294967) 2^22 max error*/
1568                         temporary = (Errors * 1000) / (8 * (1 << 14));
1569                         temporary = temporary * 100000; /* still to *10 */
1570                 }
1571
1572                 /* Byte error*/
1573                 if (def == 2)
1574                         /*tber=Errors/(8*(1 <<14));*/
1575                         tber = temporary;
1576                 else if (def == 3)
1577                         /*tber=Errors/(8*(1 <<16));*/
1578                         tber = temporary / 4;
1579                 else if (def == 4)
1580                         /*tber=Errors/(8*(1 <<18));*/
1581                         tber = temporary / 16;
1582                 else if (def == 5)
1583                         /*tber=Errors/(8*(1 <<20));*/
1584                         tber = temporary / 64;
1585                 else if (def == 6)
1586                         /*tber=Errors/(8*(1 <<22));*/
1587                         tber = temporary / 256;
1588                 else
1589                         /* should not pass here*/
1590                         tber = 0;
1591
1592                 if ((Errors < 4294967) && (Errors > 429496))
1593                         tber *= 10;
1594
1595         }
1596
1597         /* save actual value */
1598         ter_state->pBER = tber;
1599
1600         (*ber) = tber;
1601
1602         return 0;
1603 }
1604 #if 0
1605 static u32 stv0367ter_get_per(struct stv0367_state *state)
1606 {
1607         struct stv0367ter_state *ter_state = state->ter_state;
1608         u32 Errors = 0, Per = 0, temporary = 0;
1609         int abc = 0, def = 0, cpt = 0;
1610
1611         while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1612                         (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1613                 usleep_range(1000, 2000);
1614                 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1615                         * (1 << 16))
1616                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1617                         * (1 << 8))
1618                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1619                 cpt++;
1620         }
1621         abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1622         def = stv0367_readbits(state, F367TER_NUM_EVT1);
1623
1624         if (Errors == 0)
1625                 Per = 0;
1626         else if (abc == 0x9) {
1627                 if (Errors <= 4) {
1628                         temporary = (Errors * 1000000000) / (8 * (1 << 8));
1629                 } else if (Errors <= 42) {
1630                         temporary = (Errors * 100000000) / (8 * (1 << 8));
1631                         temporary = temporary * 10;
1632                 } else if (Errors <= 429) {
1633                         temporary = (Errors * 10000000) / (8 * (1 << 8));
1634                         temporary = temporary * 100;
1635                 } else if (Errors <= 4294) {
1636                         temporary = (Errors * 1000000) / (8 * (1 << 8));
1637                         temporary = temporary * 1000;
1638                 } else if (Errors <= 42949) {
1639                         temporary = (Errors * 100000) / (8 * (1 << 8));
1640                         temporary = temporary * 10000;
1641                 } else { /*if(Errors<=429496)  2^16 errors max*/
1642                         temporary = (Errors * 10000) / (8 * (1 << 8));
1643                         temporary = temporary * 100000;
1644                 }
1645
1646                 /* pkt error*/
1647                 if (def == 2)
1648                         /*Per=Errors/(1 << 8);*/
1649                         Per = temporary;
1650                 else if (def == 3)
1651                         /*Per=Errors/(1 << 10);*/
1652                         Per = temporary / 4;
1653                 else if (def == 4)
1654                         /*Per=Errors/(1 << 12);*/
1655                         Per = temporary / 16;
1656                 else if (def == 5)
1657                         /*Per=Errors/(1 << 14);*/
1658                         Per = temporary / 64;
1659                 else if (def == 6)
1660                         /*Per=Errors/(1 << 16);*/
1661                         Per = temporary / 256;
1662                 else
1663                         Per = 0;
1664
1665         }
1666         /* save actual value */
1667         ter_state->pPER = Per;
1668
1669         return Per;
1670 }
1671 #endif
1672 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
1673                                         struct dvb_frontend_tune_settings
1674                                         *fe_tune_settings)
1675 {
1676         fe_tune_settings->min_delay_ms = 1000;
1677         fe_tune_settings->step_size = 0;
1678         fe_tune_settings->max_drift = 0;
1679
1680         return 0;
1681 }
1682
1683 static void stv0367_release(struct dvb_frontend *fe)
1684 {
1685         struct stv0367_state *state = fe->demodulator_priv;
1686
1687         kfree(state->ter_state);
1688         kfree(state->cab_state);
1689         kfree(state);
1690 }
1691
1692 static const struct dvb_frontend_ops stv0367ter_ops = {
1693         .delsys = { SYS_DVBT },
1694         .info = {
1695                 .name                   = "ST STV0367 DVB-T",
1696                 .frequency_min_hz       =  47 * MHz,
1697                 .frequency_max_hz       = 862 * MHz,
1698                 .frequency_stepsize_hz  = 15625,
1699                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1700                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
1701                         FE_CAN_FEC_AUTO |
1702                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1703                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
1704                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
1705                         FE_CAN_INVERSION_AUTO |
1706                         FE_CAN_MUTE_TS
1707         },
1708         .release = stv0367_release,
1709         .init = stv0367ter_init,
1710         .sleep = stv0367ter_sleep,
1711         .i2c_gate_ctrl = stv0367ter_gate_ctrl,
1712         .set_frontend = stv0367ter_set_frontend,
1713         .get_frontend = stv0367ter_get_frontend,
1714         .get_tune_settings = stv0367_get_tune_settings,
1715         .read_status = stv0367ter_read_status,
1716         .read_ber = stv0367ter_read_ber,/* too slow */
1717 /*      .read_signal_strength = stv0367_read_signal_strength,*/
1718         .read_snr = stv0367ter_read_snr,
1719         .read_ucblocks = stv0367ter_read_ucblocks,
1720 };
1721
1722 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
1723                                    struct i2c_adapter *i2c)
1724 {
1725         struct stv0367_state *state = NULL;
1726         struct stv0367ter_state *ter_state = NULL;
1727
1728         /* allocate memory for the internal state */
1729         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1730         if (state == NULL)
1731                 goto error;
1732         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
1733         if (ter_state == NULL)
1734                 goto error;
1735
1736         /* setup the state */
1737         state->i2c = i2c;
1738         state->config = config;
1739         state->ter_state = ter_state;
1740         state->fe.ops = stv0367ter_ops;
1741         state->fe.demodulator_priv = state;
1742         state->chip_id = stv0367_readreg(state, 0xf000);
1743
1744         /* demod operation options */
1745         state->use_i2c_gatectrl = 1;
1746         state->deftabs = STV0367_DEFTAB_GENERIC;
1747         state->reinit_on_setfrontend = 1;
1748         state->auto_if_khz = 0;
1749
1750         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1751
1752         /* check if the demod is there */
1753         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1754                 goto error;
1755
1756         return &state->fe;
1757
1758 error:
1759         kfree(ter_state);
1760         kfree(state);
1761         return NULL;
1762 }
1763 EXPORT_SYMBOL(stv0367ter_attach);
1764
1765 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
1766 {
1767         struct stv0367_state *state = fe->demodulator_priv;
1768
1769         dprintk("%s:\n", __func__);
1770
1771         stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1772
1773         return 0;
1774 }
1775
1776 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
1777 {
1778         struct stv0367_state *state = fe->demodulator_priv;
1779         u32 mclk_Hz = 0;/* master clock frequency (Hz) */
1780         u32 M, N, P;
1781
1782
1783         if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1784                 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1785                 if (N == 0)
1786                         N = N + 1;
1787
1788                 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1789                 if (M == 0)
1790                         M = M + 1;
1791
1792                 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1793
1794                 if (P > 5)
1795                         P = 5;
1796
1797                 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
1798                 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
1799                                                                 mclk_Hz);
1800         } else
1801                 mclk_Hz = ExtClk_Hz;
1802
1803         dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
1804
1805         return mclk_Hz;
1806 }
1807
1808 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
1809 {
1810         u32 ADCClk_Hz = ExtClk_Hz;
1811
1812         ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
1813
1814         return ADCClk_Hz;
1815 }
1816
1817 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1818                                                  u32 SymbolRate,
1819                                                  enum stv0367cab_mod QAMSize)
1820 {
1821         /* Set QAM size */
1822         stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1823
1824         /* Set Registers settings specific to the QAM size */
1825         switch (QAMSize) {
1826         case FE_CAB_MOD_QAM4:
1827                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1828                 break;
1829         case FE_CAB_MOD_QAM16:
1830                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1831                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1832                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1833                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1834                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1835                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1836                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1837                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1838                 break;
1839         case FE_CAB_MOD_QAM32:
1840                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1841                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1842                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1843                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1844                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1845                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1846                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1847                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1848                 break;
1849         case FE_CAB_MOD_QAM64:
1850                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1851                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1852                 if (SymbolRate > 4500000) {
1853                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1854                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1855                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1856                 } else if (SymbolRate > 2500000) {
1857                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1858                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1859                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1860                 } else {
1861                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1862                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1863                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1864                 }
1865                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1866                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1867                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1868                 break;
1869         case FE_CAB_MOD_QAM128:
1870                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1871                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1872                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1873                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1874                 if (SymbolRate > 4500000)
1875                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1876                 else if (SymbolRate > 2500000)
1877                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1878                 else
1879                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1880
1881                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1882                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1883                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1884                 break;
1885         case FE_CAB_MOD_QAM256:
1886                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1887                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1888                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1889                 if (SymbolRate > 4500000)
1890                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1891                 else if (SymbolRate > 2500000)
1892                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1893                 else
1894                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1895
1896                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1897                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1898                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1899                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1900                 break;
1901         case FE_CAB_MOD_QAM512:
1902                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1903                 break;
1904         case FE_CAB_MOD_QAM1024:
1905                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1906                 break;
1907         default:
1908                 break;
1909         }
1910
1911         return QAMSize;
1912 }
1913
1914 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1915                                         u32 adc_hz, s32 derot_hz)
1916 {
1917         u32 sampled_if = 0;
1918         u32 adc_khz;
1919
1920         adc_khz = adc_hz / 1000;
1921
1922         dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
1923
1924         if (adc_khz != 0) {
1925                 if (derot_hz < 1000000)
1926                         derot_hz = adc_hz / 4; /* ZIF operation */
1927                 if (derot_hz > adc_hz)
1928                         derot_hz = derot_hz - adc_hz;
1929                 sampled_if = (u32)derot_hz / 1000;
1930                 sampled_if *= 32768;
1931                 sampled_if /= adc_khz;
1932                 sampled_if *= 256;
1933         }
1934
1935         if (sampled_if > 8388607)
1936                 sampled_if = 8388607;
1937
1938         dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
1939
1940         stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1941         stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1942         stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1943
1944         return derot_hz;
1945 }
1946
1947 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1948 {
1949         u32 sampled_if;
1950
1951         sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1952                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1953                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1954
1955         sampled_if /= 256;
1956         sampled_if *= (adc_hz / 1000);
1957         sampled_if += 1;
1958         sampled_if /= 32768;
1959
1960         return sampled_if;
1961 }
1962
1963 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1964                         u32 mclk_hz, u32 SymbolRate,
1965                         enum stv0367cab_mod QAMSize)
1966 {
1967         u32 QamSizeCorr = 0;
1968         u32 u32_tmp = 0, u32_tmp1 = 0;
1969         u32 adp_khz;
1970
1971         dprintk("%s:\n", __func__);
1972
1973         /* Set Correction factor of SRC gain */
1974         switch (QAMSize) {
1975         case FE_CAB_MOD_QAM4:
1976                 QamSizeCorr = 1110;
1977                 break;
1978         case FE_CAB_MOD_QAM16:
1979                 QamSizeCorr = 1032;
1980                 break;
1981         case FE_CAB_MOD_QAM32:
1982                 QamSizeCorr =  954;
1983                 break;
1984         case FE_CAB_MOD_QAM64:
1985                 QamSizeCorr =  983;
1986                 break;
1987         case FE_CAB_MOD_QAM128:
1988                 QamSizeCorr =  957;
1989                 break;
1990         case FE_CAB_MOD_QAM256:
1991                 QamSizeCorr =  948;
1992                 break;
1993         case FE_CAB_MOD_QAM512:
1994                 QamSizeCorr =    0;
1995                 break;
1996         case FE_CAB_MOD_QAM1024:
1997                 QamSizeCorr =  944;
1998                 break;
1999         default:
2000                 break;
2001         }
2002
2003         /* Transfer ratio calculation */
2004         if (adc_hz != 0) {
2005                 u32_tmp = 256 * SymbolRate;
2006                 u32_tmp = u32_tmp / adc_hz;
2007         }
2008         stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2009
2010         /* Symbol rate and SRC gain calculation */
2011         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2012         if (adp_khz != 0) {
2013                 u32_tmp = SymbolRate;
2014                 u32_tmp1 = SymbolRate;
2015
2016                 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2017                         /* Symbol rate calculation */
2018                         u32_tmp *= 2048; /* 2048 = 2^11 */
2019                         u32_tmp = u32_tmp / adp_khz;
2020                         u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2021                         u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2022                         u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2023
2024                         /* SRC Gain Calculation */
2025                         u32_tmp1 *= 2048; /* *2*2^10 */
2026                         u32_tmp1 /= 439; /* *2/878 */
2027                         u32_tmp1 *= 256; /* *2^8 */
2028                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2029                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2030                         u32_tmp1 = u32_tmp1 / 10000000;
2031
2032                 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2033                         /* Symbol rate calculation */
2034                         u32_tmp *= 1024 ; /* 1024 = 2**10 */
2035                         u32_tmp = u32_tmp / adp_khz;
2036                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2037                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2038                         u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2039
2040                         /* SRC Gain Calculation */
2041                         u32_tmp1 *= 1024; /* *2*2^9 */
2042                         u32_tmp1 /= 439; /* *2/878 */
2043                         u32_tmp1 *= 256; /* *2^8 */
2044                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2045                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2046                         u32_tmp1 = u32_tmp1 / 5000000;
2047                 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2048                         /* Symbol rate calculation */
2049                         u32_tmp *= 512 ; /* 512 = 2**9 */
2050                         u32_tmp = u32_tmp / adp_khz;
2051                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2052                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2053                         u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2054
2055                         /* SRC Gain Calculation */
2056                         u32_tmp1 *= 512; /* *2*2^8 */
2057                         u32_tmp1 /= 439; /* *2/878 */
2058                         u32_tmp1 *= 256; /* *2^8 */
2059                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2060                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2061                         u32_tmp1 = u32_tmp1 / 2500000;
2062                 } else {
2063                         /* Symbol rate calculation */
2064                         u32_tmp *= 256 ; /* 256 = 2**8 */
2065                         u32_tmp = u32_tmp / adp_khz;
2066                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2067                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2068                         u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2069
2070                         /* SRC Gain Calculation */
2071                         u32_tmp1 *= 256; /* 2*2^7 */
2072                         u32_tmp1 /= 439; /* *2/878 */
2073                         u32_tmp1 *= 256; /* *2^8 */
2074                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2075                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2076                         u32_tmp1 = u32_tmp1 / 1250000;
2077                 }
2078         }
2079 #if 0
2080         /* Filters' coefficients are calculated and written
2081         into registers only if the filters are enabled */
2082         if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2083                 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2084                                                                 SymbolRate);
2085                 /* AllPass filter must be enabled
2086                 when the adjacents filter is used */
2087                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2088                 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2089         } else
2090                 /* AllPass filter must be disabled
2091                 when the adjacents filter is not used */
2092 #endif
2093         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2094
2095         stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2096         stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2097         stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2098         stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2099
2100         stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2101         stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2102
2103         return SymbolRate ;
2104 }
2105
2106 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2107 {
2108         u32 regsym;
2109         u32 adp_khz;
2110
2111         regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2112                 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2113                 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2114                 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2115
2116         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2117
2118         if (regsym < 134217728) {               /* 134217728L = 2**27*/
2119                 regsym = regsym * 32;           /* 32 = 2**5 */
2120                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2121                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2122                 regsym = regsym / 128;          /* 128 = 2**7 */
2123                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2124                 regsym /= 2048 ;                /* 2048 = 2**11 */
2125         } else if (regsym < 268435456) {        /* 268435456L = 2**28 */
2126                 regsym = regsym * 16;           /* 16 = 2**4 */
2127                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2128                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2129                 regsym = regsym / 128;          /* 128 = 2**7 */
2130                 regsym *= 125 ;                 /* 125 = 1000/2**3*/
2131                 regsym /= 1024 ;                /* 256 = 2**10*/
2132         } else if (regsym < 536870912) {        /* 536870912L = 2**29*/
2133                 regsym = regsym * 8;            /* 8 = 2**3 */
2134                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2135                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2136                 regsym = regsym / 128;          /* 128 = 2**7 */
2137                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2138                 regsym /= 512 ;                 /* 128 = 2**9 */
2139         } else {
2140                 regsym = regsym * 4;            /* 4 = 2**2 */
2141                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2142                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2143                 regsym = regsym / 128;          /* 128 = 2**7 */
2144                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2145                 regsym /= 256 ;                 /* 64 = 2**8 */
2146         }
2147
2148         return regsym;
2149 }
2150
2151 static u32 stv0367cab_fsm_status(struct stv0367_state *state)
2152 {
2153         return stv0367_readbits(state, F367CAB_FSM_STATUS);
2154 }
2155
2156 static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
2157 {
2158         return stv0367_readbits(state,
2159                 (state->cab_state->qamfec_status_reg ?
2160                  state->cab_state->qamfec_status_reg :
2161                  F367CAB_QAMFEC_LOCK));
2162 }
2163
2164 static
2165 enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
2166 {
2167         enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
2168
2169         switch (qam_fsm_status) {
2170         case 1:
2171                 signaltype = FE_CAB_NOAGC;
2172                 break;
2173         case 2:
2174                 signaltype = FE_CAB_NOTIMING;
2175                 break;
2176         case 3:
2177                 signaltype = FE_CAB_TIMINGOK;
2178                 break;
2179         case 4:
2180                 signaltype = FE_CAB_NOCARRIER;
2181                 break;
2182         case 5:
2183                 signaltype = FE_CAB_CARRIEROK;
2184                 break;
2185         case 7:
2186                 signaltype = FE_CAB_NOBLIND;
2187                 break;
2188         case 8:
2189                 signaltype = FE_CAB_BLINDOK;
2190                 break;
2191         case 10:
2192                 signaltype = FE_CAB_NODEMOD;
2193                 break;
2194         case 11:
2195                 signaltype = FE_CAB_DEMODOK;
2196                 break;
2197         case 12:
2198                 signaltype = FE_CAB_DEMODOK;
2199                 break;
2200         case 13:
2201                 signaltype = FE_CAB_NODEMOD;
2202                 break;
2203         case 14:
2204                 signaltype = FE_CAB_NOBLIND;
2205                 break;
2206         case 15:
2207                 signaltype = FE_CAB_NOSIGNAL;
2208                 break;
2209         default:
2210                 break;
2211         }
2212
2213         return signaltype;
2214 }
2215
2216 static int stv0367cab_read_status(struct dvb_frontend *fe,
2217                                   enum fe_status *status)
2218 {
2219         struct stv0367_state *state = fe->demodulator_priv;
2220
2221         dprintk("%s:\n", __func__);
2222
2223         *status = 0;
2224
2225         /* update cab_state->state from QAM_FSM_STATUS */
2226         state->cab_state->state = stv0367cab_fsm_signaltype(
2227                 stv0367cab_fsm_status(state));
2228
2229         if (stv0367cab_qamfec_lock(state)) {
2230                 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
2231                           | FE_HAS_SYNC | FE_HAS_LOCK;
2232                 dprintk("%s: stv0367 has locked\n", __func__);
2233         } else {
2234                 if (state->cab_state->state > FE_CAB_NOSIGNAL)
2235                         *status |= FE_HAS_SIGNAL;
2236
2237                 if (state->cab_state->state > FE_CAB_NOCARRIER)
2238                         *status |= FE_HAS_CARRIER;
2239
2240                 if (state->cab_state->state >= FE_CAB_DEMODOK)
2241                         *status |= FE_HAS_VITERBI;
2242
2243                 if (state->cab_state->state >= FE_CAB_DATAOK)
2244                         *status |= FE_HAS_SYNC;
2245         }
2246
2247         return 0;
2248 }
2249
2250 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2251 {
2252         struct stv0367_state *state = fe->demodulator_priv;
2253
2254         dprintk("%s:\n", __func__);
2255
2256         if (standby_on) {
2257                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2258                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2259                 stv0367_writebits(state, F367CAB_STDBY, 1);
2260                 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2261                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2262                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2263                 stv0367_writebits(state, F367CAB_POFFQ, 1);
2264                 stv0367_writebits(state, F367CAB_POFFI, 1);
2265         } else {
2266                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2267                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2268                 stv0367_writebits(state, F367CAB_STDBY, 0);
2269                 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2270                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2271                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2272                 stv0367_writebits(state, F367CAB_POFFQ, 0);
2273                 stv0367_writebits(state, F367CAB_POFFI, 0);
2274         }
2275
2276         return 0;
2277 }
2278
2279 static int stv0367cab_sleep(struct dvb_frontend *fe)
2280 {
2281         return stv0367cab_standby(fe, 1);
2282 }
2283
2284 static int stv0367cab_init(struct dvb_frontend *fe)
2285 {
2286         struct stv0367_state *state = fe->demodulator_priv;
2287         struct stv0367cab_state *cab_state = state->cab_state;
2288
2289         dprintk("%s:\n", __func__);
2290
2291         stv0367_write_table(state,
2292                 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
2293
2294         switch (state->config->ts_mode) {
2295         case STV0367_DVBCI_CLOCK:
2296                 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2297                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2298                 break;
2299         case STV0367_SERIAL_PUNCT_CLOCK:
2300         case STV0367_SERIAL_CONT_CLOCK:
2301                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2302                 break;
2303         case STV0367_PARALLEL_PUNCT_CLOCK:
2304         case STV0367_OUTPUTMODE_DEFAULT:
2305                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2306                 break;
2307         }
2308
2309         switch (state->config->clk_pol) {
2310         case STV0367_RISINGEDGE_CLOCK:
2311                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2312                 break;
2313         case STV0367_FALLINGEDGE_CLOCK:
2314         case STV0367_CLOCKPOLARITY_DEFAULT:
2315                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2316                 break;
2317         }
2318
2319         stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2320
2321         stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2322
2323         stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2324
2325         stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2326
2327         stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2328
2329         cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2330         cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2331
2332         return 0;
2333 }
2334 static
2335 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2336                                              struct dtv_frontend_properties *p)
2337 {
2338         struct stv0367cab_state *cab_state = state->cab_state;
2339         enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2340         u32     QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
2341                 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2342                 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2343         u8      TrackAGCAccum;
2344         s32     tmp;
2345
2346         dprintk("%s:\n", __func__);
2347
2348         stv0367_get_if_khz(state, &ifkhz);
2349
2350         /* Timeouts calculation */
2351         /* A max lock time of 25 ms is allowed for delayed AGC */
2352         AGCTimeOut = 25;
2353         /* 100000 symbols needed by the TRL as a maximum value */
2354         TRLTimeOut = 100000000 / p->symbol_rate;
2355         /* CRLSymbols is the needed number of symbols to achieve a lock
2356            within [-4%, +4%] of the symbol rate.
2357            CRL timeout is calculated
2358            for a lock within [-search_range, +search_range].
2359            EQL timeout can be changed depending on
2360            the micro-reflections we want to handle.
2361            A characterization must be performed
2362            with these echoes to get new timeout values.
2363         */
2364         switch (p->modulation) {
2365         case QAM_16:
2366                 CRLSymbols = 150000;
2367                 EQLTimeOut = 100;
2368                 break;
2369         case QAM_32:
2370                 CRLSymbols = 250000;
2371                 EQLTimeOut = 100;
2372                 break;
2373         case QAM_64:
2374                 CRLSymbols = 200000;
2375                 EQLTimeOut = 100;
2376                 break;
2377         case QAM_128:
2378                 CRLSymbols = 250000;
2379                 EQLTimeOut = 100;
2380                 break;
2381         case QAM_256:
2382                 CRLSymbols = 250000;
2383                 EQLTimeOut = 100;
2384                 break;
2385         default:
2386                 CRLSymbols = 200000;
2387                 EQLTimeOut = 100;
2388                 break;
2389         }
2390 #if 0
2391         if (pIntParams->search_range < 0) {
2392                 CRLTimeOut = (25 * CRLSymbols *
2393                                 (-pIntParams->search_range / 1000)) /
2394                                         (pIntParams->symbol_rate / 1000);
2395         } else
2396 #endif
2397         CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2398                                         (p->symbol_rate / 1000);
2399
2400         CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2401         /* Timeouts below 50ms are coerced */
2402         if (CRLTimeOut < 50)
2403                 CRLTimeOut = 50;
2404         /* A maximum of 100 TS packets is needed to get FEC lock even in case
2405         the spectrum inversion needs to be changed.
2406            This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2407         */
2408         FECTimeOut = 20;
2409         DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2410
2411         dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2412
2413         /* Reset the TRL to ensure nothing starts until the
2414            AGC is stable which ensures a better lock time
2415         */
2416         stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2417         /* Set AGC accumulation time to minimum and lock threshold to maximum
2418         in order to speed up the AGC lock */
2419         TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2420         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2421         /* Modulus Mapper is disabled */
2422         stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2423         /* Disable the sweep function */
2424         stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2425         /* The sweep function is never used, Sweep rate must be set to 0 */
2426         /* Set the derotator frequency in Hz */
2427         stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2428                 (1000 * (s32)ifkhz + cab_state->derot_offset));
2429         /* Disable the Allpass Filter when the symbol rate is out of range */
2430         if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2431                 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2432                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2433         }
2434 #if 0
2435         /* Check if the tuner is locked */
2436         tuner_lock = stv0367cab_tuner_get_status(fe);
2437         if (tuner_lock == 0)
2438                 return FE_367CAB_NOTUNER;
2439 #endif
2440         /* Release the TRL to start demodulator acquisition */
2441         /* Wait for QAM lock */
2442         LockTime = 0;
2443         stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2444         do {
2445                 QAM_Lock = stv0367cab_fsm_status(state);
2446                 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2447                                                         (QAM_Lock == 0x04))
2448                         /*
2449                          * We don't wait longer, the frequency/phase offset
2450                          * must be too big
2451                          */
2452                         LockTime = DemodTimeOut;
2453                 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2454                                                         (QAM_Lock == 0x02))
2455                         /*
2456                          * We don't wait longer, either there is no signal or
2457                          * it is not the right symbol rate or it is an analog
2458                          * carrier
2459                          */
2460                 {
2461                         LockTime = DemodTimeOut;
2462                         u32_tmp = stv0367_readbits(state,
2463                                                 F367CAB_AGC_PWR_WORD_LO) +
2464                                         (stv0367_readbits(state,
2465                                                 F367CAB_AGC_PWR_WORD_ME) << 8) +
2466                                         (stv0367_readbits(state,
2467                                                 F367CAB_AGC_PWR_WORD_HI) << 16);
2468                         if (u32_tmp >= 131072)
2469                                 u32_tmp = 262144 - u32_tmp;
2470                         u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2471                                                         F367CAB_AGC_IF_BWSEL)));
2472
2473                         if (u32_tmp < stv0367_readbits(state,
2474                                                 F367CAB_AGC_PWRREF_LO) +
2475                                         256 * stv0367_readbits(state,
2476                                                 F367CAB_AGC_PWRREF_HI) - 10)
2477                                 QAM_Lock = 0x0f;
2478                 } else {
2479                         usleep_range(10000, 20000);
2480                         LockTime += 10;
2481                 }
2482                 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2483                 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2484
2485                 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2486
2487         } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2488                                                 (LockTime < DemodTimeOut));
2489
2490         dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2491
2492         tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2493         dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2494         tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2495         dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2496
2497         tmp  = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2498         dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2499
2500         if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2501                 /* Wait for FEC lock */
2502                 LockTime = 0;
2503                 do {
2504                         usleep_range(5000, 7000);
2505                         LockTime += 5;
2506                         QAMFEC_Lock = stv0367cab_qamfec_lock(state);
2507                 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2508         } else
2509                 QAMFEC_Lock = 0;
2510
2511         if (QAMFEC_Lock) {
2512                 signalType = FE_CAB_DATAOK;
2513                 cab_state->spect_inv = stv0367_readbits(state,
2514                                                         F367CAB_QUAD_INV);
2515 #if 0
2516 /* not clear for me */
2517                 if (ifkhz != 0) {
2518                         if (ifkhz > cab_state->adc_clk / 1000) {
2519                                 cab_state->freq_khz =
2520                                         FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2521                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2522                                 - cab_state->adc_clk / 1000 + ifkhz;
2523                         } else {
2524                                 cab_state->freq_khz =
2525                                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2526                                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2527                                                 + ifkhz;
2528                         }
2529                 } else {
2530                         cab_state->freq_khz =
2531                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
2532                                 stv0367cab_get_derot_freq(state,
2533                                                         cab_state->adc_clk) -
2534                                 cab_state->adc_clk / 4000;
2535                 }
2536 #endif
2537                 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2538                                                         cab_state->mclk);
2539                 cab_state->locked = 1;
2540
2541                 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2542         } else
2543                 signalType = stv0367cab_fsm_signaltype(QAM_Lock);
2544
2545         /* Set the AGC control values to tracking values */
2546         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2547         return signalType;
2548 }
2549
2550 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
2551 {
2552         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2553         struct stv0367_state *state = fe->demodulator_priv;
2554         struct stv0367cab_state *cab_state = state->cab_state;
2555         enum stv0367cab_mod QAMSize = 0;
2556
2557         dprintk("%s: freq = %d, srate = %d\n", __func__,
2558                                         p->frequency, p->symbol_rate);
2559
2560         cab_state->derot_offset = 0;
2561
2562         switch (p->modulation) {
2563         case QAM_16:
2564                 QAMSize = FE_CAB_MOD_QAM16;
2565                 break;
2566         case QAM_32:
2567                 QAMSize = FE_CAB_MOD_QAM32;
2568                 break;
2569         case QAM_64:
2570                 QAMSize = FE_CAB_MOD_QAM64;
2571                 break;
2572         case QAM_128:
2573                 QAMSize = FE_CAB_MOD_QAM128;
2574                 break;
2575         case QAM_256:
2576                 QAMSize = FE_CAB_MOD_QAM256;
2577                 break;
2578         default:
2579                 break;
2580         }
2581
2582         if (state->reinit_on_setfrontend)
2583                 stv0367cab_init(fe);
2584
2585         /* Tuner Frequency Setting */
2586         if (fe->ops.tuner_ops.set_params) {
2587                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2588                         fe->ops.i2c_gate_ctrl(fe, 1);
2589                 fe->ops.tuner_ops.set_params(fe);
2590                 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2591                         fe->ops.i2c_gate_ctrl(fe, 0);
2592         }
2593
2594         stv0367cab_SetQamSize(
2595                         state,
2596                         p->symbol_rate,
2597                         QAMSize);
2598
2599         stv0367cab_set_srate(state,
2600                         cab_state->adc_clk,
2601                         cab_state->mclk,
2602                         p->symbol_rate,
2603                         QAMSize);
2604         /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
2605         cab_state->state = stv0367cab_algo(state, p);
2606         return 0;
2607 }
2608
2609 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
2610                                    struct dtv_frontend_properties *p)
2611 {
2612         struct stv0367_state *state = fe->demodulator_priv;
2613         struct stv0367cab_state *cab_state = state->cab_state;
2614         u32 ifkhz = 0;
2615
2616         enum stv0367cab_mod QAMSize;
2617
2618         dprintk("%s:\n", __func__);
2619
2620         stv0367_get_if_khz(state, &ifkhz);
2621         p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
2622
2623         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2624         switch (QAMSize) {
2625         case FE_CAB_MOD_QAM16:
2626                 p->modulation = QAM_16;
2627                 break;
2628         case FE_CAB_MOD_QAM32:
2629                 p->modulation = QAM_32;
2630                 break;
2631         case FE_CAB_MOD_QAM64:
2632                 p->modulation = QAM_64;
2633                 break;
2634         case FE_CAB_MOD_QAM128:
2635                 p->modulation = QAM_128;
2636                 break;
2637         case FE_CAB_MOD_QAM256:
2638                 p->modulation = QAM_256;
2639                 break;
2640         default:
2641                 break;
2642         }
2643
2644         p->frequency = stv0367_get_tuner_freq(fe);
2645
2646         dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
2647
2648         if (ifkhz == 0) {
2649                 p->frequency +=
2650                         (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2651                         cab_state->adc_clk / 4000);
2652                 return 0;
2653         }
2654
2655         if (ifkhz > cab_state->adc_clk / 1000)
2656                 p->frequency += (ifkhz
2657                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2658                         - cab_state->adc_clk / 1000);
2659         else
2660                 p->frequency += (ifkhz
2661                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2662
2663         return 0;
2664 }
2665
2666 #if 0
2667 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2668                         u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
2669 {
2670         stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2671         stv0367cab_GetPacketsCount(state, Monitor_results);
2672
2673         return;
2674 }
2675
2676 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
2677 {
2678         struct stv0367_state *state = fe->demodulator_priv;
2679
2680         return 0;
2681 }
2682 #endif
2683 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2684 {
2685         s32 rfLevel = 0;
2686         s32 RfAgcPwm = 0, IfAgcPwm = 0;
2687         u8 i;
2688
2689         stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2690
2691         RfAgcPwm =
2692                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2693                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2694         RfAgcPwm = 100 * RfAgcPwm / 1023;
2695
2696         IfAgcPwm =
2697                 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2698                 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2699         if (IfAgcPwm >= 2048)
2700                 IfAgcPwm -= 2048;
2701         else
2702                 IfAgcPwm += 2048;
2703
2704         IfAgcPwm = 100 * IfAgcPwm / 4095;
2705
2706         /* For DTT75467 on NIM */
2707         if (RfAgcPwm < 90  && IfAgcPwm < 28) {
2708                 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
2709                         if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
2710                                 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
2711                                 break;
2712                         }
2713                 }
2714                 if (i == RF_LOOKUP_TABLE_SIZE)
2715                         rfLevel = -56;
2716         } else { /*if IF AGC>10*/
2717                 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
2718                         if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
2719                                 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
2720                                 break;
2721                         }
2722                 }
2723                 if (i == RF_LOOKUP_TABLE2_SIZE)
2724                         rfLevel = -72;
2725         }
2726         return rfLevel;
2727 }
2728
2729 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
2730 {
2731         struct stv0367_state *state = fe->demodulator_priv;
2732
2733         s32 signal =  stv0367cab_get_rf_lvl(state);
2734
2735         dprintk("%s: signal=%d dBm\n", __func__, signal);
2736
2737         if (signal <= -72)
2738                 *strength = 65535;
2739         else
2740                 *strength = (22 + signal) * (-1311);
2741
2742         dprintk("%s: strength=%d\n", __func__, (*strength));
2743
2744         return 0;
2745 }
2746
2747 static int stv0367cab_snr_power(struct dvb_frontend *fe)
2748 {
2749         struct stv0367_state *state = fe->demodulator_priv;
2750         enum stv0367cab_mod QAMSize;
2751
2752         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2753         switch (QAMSize) {
2754         case FE_CAB_MOD_QAM4:
2755                 return 21904;
2756         case FE_CAB_MOD_QAM16:
2757                 return 20480;
2758         case FE_CAB_MOD_QAM32:
2759                 return 23040;
2760         case FE_CAB_MOD_QAM64:
2761                 return 21504;
2762         case FE_CAB_MOD_QAM128:
2763                 return 23616;
2764         case FE_CAB_MOD_QAM256:
2765                 return 21760;
2766         case FE_CAB_MOD_QAM1024:
2767                 return 21280;
2768         default:
2769                 break;
2770         }
2771
2772         return 1;
2773 }
2774
2775 static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
2776 {
2777         struct stv0367_state *state = fe->demodulator_priv;
2778         u32 regval = 0;
2779         int i;
2780
2781         for (i = 0; i < 10; i++) {
2782                 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2783                         + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2784         }
2785
2786         if (avgdiv)
2787                 regval /= 10;
2788
2789         return regval;
2790 }
2791
2792 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
2793 {
2794         struct stv0367_state *state = fe->demodulator_priv;
2795         u32 noisepercentage;
2796         u32 regval = 0, temp = 0;
2797         int power;
2798
2799         power = stv0367cab_snr_power(fe);
2800         regval = stv0367cab_snr_readreg(fe, 1);
2801
2802         if (regval != 0) {
2803                 temp = power
2804                         * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2805                 temp /= regval;
2806         }
2807
2808         /* table values, not needed to calculate logarithms */
2809         if (temp >= 5012)
2810                 noisepercentage = 100;
2811         else if (temp >= 3981)
2812                 noisepercentage = 93;
2813         else if (temp >= 3162)
2814                 noisepercentage = 86;
2815         else if (temp >= 2512)
2816                 noisepercentage = 79;
2817         else if (temp >= 1995)
2818                 noisepercentage = 72;
2819         else if (temp >= 1585)
2820                 noisepercentage = 65;
2821         else if (temp >= 1259)
2822                 noisepercentage = 58;
2823         else if (temp >= 1000)
2824                 noisepercentage = 50;
2825         else if (temp >= 794)
2826                 noisepercentage = 43;
2827         else if (temp >= 501)
2828                 noisepercentage = 36;
2829         else if (temp >= 316)
2830                 noisepercentage = 29;
2831         else if (temp >= 200)
2832                 noisepercentage = 22;
2833         else if (temp >= 158)
2834                 noisepercentage = 14;
2835         else if (temp >= 126)
2836                 noisepercentage = 7;
2837         else
2838                 noisepercentage = 0;
2839
2840         dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
2841
2842         *snr = (noisepercentage * 65535) / 100;
2843
2844         return 0;
2845 }
2846
2847 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
2848 {
2849         struct stv0367_state *state = fe->demodulator_priv;
2850         int corrected, tscount;
2851
2852         *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2853                         | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2854         corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2855                         | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2856         tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2857                         | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2858
2859         dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
2860                                 __func__, *ucblocks, corrected, tscount);
2861
2862         return 0;
2863 };
2864
2865 static const struct dvb_frontend_ops stv0367cab_ops = {
2866         .delsys = { SYS_DVBC_ANNEX_A },
2867         .info = {
2868                 .name = "ST STV0367 DVB-C",
2869                 .frequency_min_hz =  47 * MHz,
2870                 .frequency_max_hz = 862 * MHz,
2871                 .frequency_stepsize_hz = 62500,
2872                 .symbol_rate_min = 870000,
2873                 .symbol_rate_max = 11700000,
2874                 .caps = 0x400 |/* FE_CAN_QAM_4 */
2875                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
2876                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
2877                         FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
2878         },
2879         .release                                = stv0367_release,
2880         .init                                   = stv0367cab_init,
2881         .sleep                                  = stv0367cab_sleep,
2882         .i2c_gate_ctrl                          = stv0367cab_gate_ctrl,
2883         .set_frontend                           = stv0367cab_set_frontend,
2884         .get_frontend                           = stv0367cab_get_frontend,
2885         .read_status                            = stv0367cab_read_status,
2886 /*      .read_ber                               = stv0367cab_read_ber, */
2887         .read_signal_strength                   = stv0367cab_read_strength,
2888         .read_snr                               = stv0367cab_read_snr,
2889         .read_ucblocks                          = stv0367cab_read_ucblcks,
2890         .get_tune_settings                      = stv0367_get_tune_settings,
2891 };
2892
2893 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
2894                                    struct i2c_adapter *i2c)
2895 {
2896         struct stv0367_state *state = NULL;
2897         struct stv0367cab_state *cab_state = NULL;
2898
2899         /* allocate memory for the internal state */
2900         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2901         if (state == NULL)
2902                 goto error;
2903         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
2904         if (cab_state == NULL)
2905                 goto error;
2906
2907         /* setup the state */
2908         state->i2c = i2c;
2909         state->config = config;
2910         cab_state->search_range = 280000;
2911         cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
2912         state->cab_state = cab_state;
2913         state->fe.ops = stv0367cab_ops;
2914         state->fe.demodulator_priv = state;
2915         state->chip_id = stv0367_readreg(state, 0xf000);
2916
2917         /* demod operation options */
2918         state->use_i2c_gatectrl = 1;
2919         state->deftabs = STV0367_DEFTAB_GENERIC;
2920         state->reinit_on_setfrontend = 1;
2921         state->auto_if_khz = 0;
2922
2923         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2924
2925         /* check if the demod is there */
2926         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2927                 goto error;
2928
2929         return &state->fe;
2930
2931 error:
2932         kfree(cab_state);
2933         kfree(state);
2934         return NULL;
2935 }
2936 EXPORT_SYMBOL(stv0367cab_attach);
2937
2938 /*
2939  * Functions for operation on Digital Devices hardware
2940  */
2941
2942 static void stv0367ddb_setup_ter(struct stv0367_state *state)
2943 {
2944         stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2945         stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2946         stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2947         stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2948         stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2949         stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2950
2951         /* Tuner Setup */
2952         /* Buffer Q disabled, I Enabled, unsigned ADC */
2953         stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2954         stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2955
2956         /* Clock setup */
2957         /* PLL bypassed and disabled */
2958         stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2959         stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2960
2961         /* IC runs at 54 MHz with a 27 MHz crystal */
2962         stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2963
2964         msleep(50);
2965         /* PLL enabled and used */
2966         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2967
2968         state->activedemod = demod_ter;
2969 }
2970
2971 static void stv0367ddb_setup_cab(struct stv0367_state *state)
2972 {
2973         stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2974         stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2975         stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2976         stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2977         stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2978         stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2979
2980         /* Tuner Setup */
2981         /* Buffer Q disabled, I Enabled, signed ADC */
2982         stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2983         /* ADCQ disabled */
2984         stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2985
2986         /* Clock setup */
2987         /* PLL bypassed and disabled */
2988         stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2989         /* Set QAM */
2990         stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2991
2992         /* IC runs at 58 MHz with a 27 MHz crystal */
2993         stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2994
2995         msleep(50);
2996         /* PLL enabled and used */
2997         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2998
2999         state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
3000                 state->config->xtal);
3001         state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
3002                 state->config->xtal);
3003
3004         state->activedemod = demod_cab;
3005 }
3006
3007 static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
3008 {
3009         struct stv0367_state *state = fe->demodulator_priv;
3010
3011         switch (fe->dtv_property_cache.delivery_system) {
3012         case SYS_DVBT:
3013                 if (state->activedemod != demod_ter)
3014                         stv0367ddb_setup_ter(state);
3015
3016                 return stv0367ter_set_frontend(fe);
3017         case SYS_DVBC_ANNEX_A:
3018                 if (state->activedemod != demod_cab)
3019                         stv0367ddb_setup_cab(state);
3020
3021                 /* protect against division error oopses */
3022                 if (fe->dtv_property_cache.symbol_rate == 0) {
3023                         printk(KERN_ERR "Invalid symbol rate\n");
3024                         return -EINVAL;
3025                 }
3026
3027                 return stv0367cab_set_frontend(fe);
3028         default:
3029                 break;
3030         }
3031
3032         return -EINVAL;
3033 }
3034
3035 static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
3036 {
3037         struct stv0367_state *state = fe->demodulator_priv;
3038         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3039         s32 signalstrength;
3040
3041         switch (state->activedemod) {
3042         case demod_cab:
3043                 signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
3044                 break;
3045         default:
3046                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3047                 return;
3048         }
3049
3050         p->strength.stat[0].scale = FE_SCALE_DECIBEL;
3051         p->strength.stat[0].uvalue = signalstrength;
3052 }
3053
3054 static void stv0367ddb_read_snr(struct dvb_frontend *fe)
3055 {
3056         struct stv0367_state *state = fe->demodulator_priv;
3057         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3058         int cab_pwr;
3059         u32 regval, tmpval, snrval = 0;
3060
3061         switch (state->activedemod) {
3062         case demod_ter:
3063                 snrval = stv0367ter_snr_readreg(fe);
3064                 break;
3065         case demod_cab:
3066                 cab_pwr = stv0367cab_snr_power(fe);
3067                 regval = stv0367cab_snr_readreg(fe, 0);
3068
3069                 /* prevent division by zero */
3070                 if (!regval) {
3071                         snrval = 0;
3072                         break;
3073                 }
3074
3075                 tmpval = (cab_pwr * 320) / regval;
3076                 snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
3077                 break;
3078         default:
3079                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3080                 return;
3081         }
3082
3083         p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
3084         p->cnr.stat[0].uvalue = snrval;
3085 }
3086
3087 static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
3088 {
3089         struct stv0367_state *state = fe->demodulator_priv;
3090         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3091         u32 ucblocks = 0;
3092
3093         switch (state->activedemod) {
3094         case demod_ter:
3095                 stv0367ter_read_ucblocks(fe, &ucblocks);
3096                 break;
3097         case demod_cab:
3098                 stv0367cab_read_ucblcks(fe, &ucblocks);
3099                 break;
3100         default:
3101                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3102                 return;
3103         }
3104
3105         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
3106         p->block_error.stat[0].uvalue = ucblocks;
3107 }
3108
3109 static int stv0367ddb_read_status(struct dvb_frontend *fe,
3110                                   enum fe_status *status)
3111 {
3112         struct stv0367_state *state = fe->demodulator_priv;
3113         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3114         int ret = 0;
3115
3116         switch (state->activedemod) {
3117         case demod_ter:
3118                 ret = stv0367ter_read_status(fe, status);
3119                 break;
3120         case demod_cab:
3121                 ret = stv0367cab_read_status(fe, status);
3122                 break;
3123         default:
3124                 break;
3125         }
3126
3127         /* stop and report on *_read_status failure */
3128         if (ret)
3129                 return ret;
3130
3131         stv0367ddb_read_signal_strength(fe);
3132
3133         /* read carrier/noise when a carrier is detected */
3134         if (*status & FE_HAS_CARRIER)
3135                 stv0367ddb_read_snr(fe);
3136         else
3137                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3138
3139         /* read uncorrected blocks on FE_HAS_LOCK */
3140         if (*status & FE_HAS_LOCK)
3141                 stv0367ddb_read_ucblocks(fe);
3142         else
3143                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3144
3145         return 0;
3146 }
3147
3148 static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
3149                                    struct dtv_frontend_properties *p)
3150 {
3151         struct stv0367_state *state = fe->demodulator_priv;
3152
3153         switch (state->activedemod) {
3154         case demod_ter:
3155                 return stv0367ter_get_frontend(fe, p);
3156         case demod_cab:
3157                 return stv0367cab_get_frontend(fe, p);
3158         default:
3159                 break;
3160         }
3161
3162         return 0;
3163 }
3164
3165 static int stv0367ddb_sleep(struct dvb_frontend *fe)
3166 {
3167         struct stv0367_state *state = fe->demodulator_priv;
3168
3169         switch (state->activedemod) {
3170         case demod_ter:
3171                 state->activedemod = demod_none;
3172                 return stv0367ter_sleep(fe);
3173         case demod_cab:
3174                 state->activedemod = demod_none;
3175                 return stv0367cab_sleep(fe);
3176         default:
3177                 break;
3178         }
3179
3180         return -EINVAL;
3181 }
3182
3183 static int stv0367ddb_init(struct stv0367_state *state)
3184 {
3185         struct stv0367ter_state *ter_state = state->ter_state;
3186         struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
3187
3188         stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3189
3190         if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3191                 stv0367_write_table(state,
3192                         stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3193
3194         stv0367_write_table(state,
3195                 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3196
3197         stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3198         stv0367_write_table(state,
3199                 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3200
3201         stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3202         stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3203         stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3204         stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3205         stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3206         stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3207         stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3208         stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3209
3210         /* OFDM TS Setup */
3211
3212         stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3213         stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3214         stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3215         stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3216
3217         stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3218         stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3219
3220         stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3221
3222         /* Also needed for QAM */
3223         stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3224
3225         stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3226
3227         /* QAM TS setup, note exact format also depends on descrambler */
3228         /* settings */
3229         /* Inverted Clock, Swap, serial */
3230         stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3231
3232         /* Clock setup (PLL bypassed and disabled) */
3233         stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3234
3235         /* IC runs at 58 MHz with a 27 MHz crystal */
3236         stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3237
3238         /* Tuner setup */
3239         /* Buffer Q disabled, I Enabled, signed ADC */
3240         stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3241         stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3242
3243         /* Improves the C/N lock limit */
3244         stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3245         /* ZIF/IF Automatic mode */
3246         stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3247         /* Improving burst noise performances */
3248         stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3249         /* Improving ACI performances */
3250         stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3251
3252         /* PLL enabled and used */
3253         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3254
3255         stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3256
3257         ter_state->pBER = 0;
3258         ter_state->first_lock = 0;
3259         ter_state->unlock_counter = 2;
3260
3261         p->strength.len = 1;
3262         p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3263         p->cnr.len = 1;
3264         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3265         p->block_error.len = 1;
3266         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3267
3268         return 0;
3269 }
3270
3271 static const struct dvb_frontend_ops stv0367ddb_ops = {
3272         .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
3273         .info = {
3274                 .name                   = "ST STV0367 DDB DVB-C/T",
3275                 .frequency_min_hz       =  47 * MHz,
3276                 .frequency_max_hz       = 865 * MHz,
3277                 .frequency_stepsize_hz  = 166667,
3278                 .symbol_rate_min        = 870000,
3279                 .symbol_rate_max        = 11700000,
3280                 .caps = /* DVB-C */
3281                         0x400 |/* FE_CAN_QAM_4 */
3282                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
3283                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3284                         FE_CAN_QAM_256 |
3285                         /* DVB-T */
3286                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
3287                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
3288                         FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
3289                         FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
3290                         FE_CAN_MUTE_TS
3291         },
3292         .release = stv0367_release,
3293         .sleep = stv0367ddb_sleep,
3294         .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
3295         .set_frontend = stv0367ddb_set_frontend,
3296         .get_frontend = stv0367ddb_get_frontend,
3297         .get_tune_settings = stv0367_get_tune_settings,
3298         .read_status = stv0367ddb_read_status,
3299 };
3300
3301 struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
3302                                    struct i2c_adapter *i2c)
3303 {
3304         struct stv0367_state *state = NULL;
3305         struct stv0367ter_state *ter_state = NULL;
3306         struct stv0367cab_state *cab_state = NULL;
3307
3308         /* allocate memory for the internal state */
3309         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3310         if (state == NULL)
3311                 goto error;
3312         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
3313         if (ter_state == NULL)
3314                 goto error;
3315         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3316         if (cab_state == NULL)
3317                 goto error;
3318
3319         /* setup the state */
3320         state->i2c = i2c;
3321         state->config = config;
3322         state->ter_state = ter_state;
3323         cab_state->search_range = 280000;
3324         cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
3325         state->cab_state = cab_state;
3326         state->fe.ops = stv0367ddb_ops;
3327         state->fe.demodulator_priv = state;
3328         state->chip_id = stv0367_readreg(state, R367TER_ID);
3329
3330         /* demod operation options */
3331         state->use_i2c_gatectrl = 0;
3332         state->deftabs = STV0367_DEFTAB_DDB;
3333         state->reinit_on_setfrontend = 0;
3334         state->auto_if_khz = 1;
3335         state->activedemod = demod_none;
3336
3337         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3338
3339         /* check if the demod is there */
3340         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3341                 goto error;
3342
3343         dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
3344                 state->fe.ops.info.name, state->chip_id,
3345                 config->demod_address);
3346
3347         stv0367ddb_init(state);
3348
3349         return &state->fe;
3350
3351 error:
3352         kfree(cab_state);
3353         kfree(ter_state);
3354         kfree(state);
3355         return NULL;
3356 }
3357 EXPORT_SYMBOL(stv0367ddb_attach);
3358
3359 MODULE_PARM_DESC(debug, "Set debug");
3360 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3361
3362 MODULE_AUTHOR("Igor M. Liplianin");
3363 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3364 MODULE_LICENSE("GPL");