drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony digital demodulator driver for
   5  *      CXD2841ER - DVB-S/S2/T/T2/C/C2
   6  *      CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   7  *
   8  * Copyright 2012 Sony Corporation
   9  * Copyright (C) 2014 NetUP Inc.
  10  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  11  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22   */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/bitops.h>
  29 #include <linux/math64.h>
  30 #include <linux/log2.h>
  31 #include <linux/dynamic_debug.h>
  32 #include <linux/kernel.h>
  33
  34 #include <media/dvb_math.h>
  35 #include <media/dvb_frontend.h>
  36 #include "cxd2841er.h"
  37 #include "cxd2841er_priv.h"
  38
  39 #define MAX_WRITE_REGSIZE       16
  40 #define LOG2_E_100X 144
  41
  42 #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
  43
  44 /* DVB-C constellation */
  45 enum sony_dvbc_constellation_t {
  46         SONY_DVBC_CONSTELLATION_16QAM,
  47         SONY_DVBC_CONSTELLATION_32QAM,
  48         SONY_DVBC_CONSTELLATION_64QAM,
  49         SONY_DVBC_CONSTELLATION_128QAM,
  50         SONY_DVBC_CONSTELLATION_256QAM
  51 };
  52
  53 enum cxd2841er_state {
  54         STATE_SHUTDOWN = 0,
  55         STATE_SLEEP_S,
  56         STATE_ACTIVE_S,
  57         STATE_SLEEP_TC,
  58         STATE_ACTIVE_TC
  59 };
  60
  61 struct cxd2841er_priv {
  62         struct dvb_frontend             frontend;
  63         struct i2c_adapter              *i2c;
  64         u8                              i2c_addr_slvx;
  65         u8                              i2c_addr_slvt;
  66         const struct cxd2841er_config   *config;
  67         enum cxd2841er_state            state;
  68         u8                              system;
  69         enum cxd2841er_xtal             xtal;
  70         enum fe_caps caps;
  71         u32                             flags;
  72 };
  73
  74 static const struct cxd2841er_cnr_data s_cn_data[] = {
  75         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  76         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  77         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  78         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  79         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  80         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  81         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  82         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  83         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  84         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  85         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  86         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  87         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  88         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  89         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  90         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  91         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  92         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  93         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  94         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  95         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  96         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  97         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  98         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  99         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
 100         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
 101         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
 102         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
 103         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
 104         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
 105         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
 106         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
 107         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
 108         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
 109         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
 110         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
 111         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
 112         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
 113         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
 114         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 115         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 116         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 117         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 118         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 119         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 120         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 121         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 122         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 123         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 124         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 125         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 126         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 127         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 128         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 129         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 130         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 131         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 132         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 133         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 134         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 135         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 136         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 137         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 138         { 0x0015, 19900 }, { 0x0014, 20000 },
 139 };
 140
 141 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 142         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 143         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 144         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 145         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 146         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 147         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 148         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 149         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 150         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 151         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 152         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 153         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 154         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 155         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 156         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 157         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 158         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 159         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 160         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 161         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 162         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 163         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 164         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 165         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 166         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 167         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 168         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 169         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 170         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 171         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 172         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 173         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 174         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 175         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 176         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 177         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 178         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 179         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 180         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 181         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 182         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 183         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 184         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 185         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 186         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 187         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 188         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 189         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 190         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 191         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 192         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 193         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 194         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 195         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 196         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 197         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 198         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 199         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 200         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 201         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 202         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 203         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 204         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 205         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 206 };
 207
 208 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
 209 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
 210
 211 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 212                                 u8 addr, u8 reg, u8 write,
 213                                 const u8 *data, u32 len)
 214 {
 215         dev_dbg(&priv->i2c->dev,
 216                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
 217                 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
 218 }
 219
 220 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 221                                 u8 addr, u8 reg, const u8 *data, u32 len)
 222 {
 223         int ret;
 224         u8 buf[MAX_WRITE_REGSIZE + 1];
 225         u8 i2c_addr = (addr == I2C_SLVX ?
 226                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 227         struct i2c_msg msg[1] = {
 228                 {
 229                         .addr = i2c_addr,
 230                         .flags = 0,
 231                         .len = len + 1,
 232                         .buf = buf,
 233                 }
 234         };
 235
 236         if (len + 1 >= sizeof(buf)) {
 237                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 238                          reg, len + 1);
 239                 return -E2BIG;
 240         }
 241
 242         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 243         buf[0] = reg;
 244         memcpy(&buf[1], data, len);
 245
 246         ret = i2c_transfer(priv->i2c, msg, 1);
 247         if (ret >= 0 && ret != 1)
 248                 ret = -EIO;
 249         if (ret < 0) {
 250                 dev_warn(&priv->i2c->dev,
 251                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 252                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 253                 return ret;
 254         }
 255         return 0;
 256 }
 257
 258 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 259                                u8 addr, u8 reg, u8 val)
 260 {
 261         u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 262
 263         return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
 264 }
 265
 266 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 267                                u8 addr, u8 reg, u8 *val, u32 len)
 268 {
 269         int ret;
 270         u8 i2c_addr = (addr == I2C_SLVX ?
 271                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 272         struct i2c_msg msg[2] = {
 273                 {
 274                         .addr = i2c_addr,
 275                         .flags = 0,
 276                         .len = 1,
 277                         .buf = &reg,
 278                 }, {
 279                         .addr = i2c_addr,
 280                         .flags = I2C_M_RD,
 281                         .len = len,
 282                         .buf = val,
 283                 }
 284         };
 285
 286         ret = i2c_transfer(priv->i2c, msg, 2);
 287         if (ret >= 0 && ret != 2)
 288                 ret = -EIO;
 289         if (ret < 0) {
 290                 dev_warn(&priv->i2c->dev,
 291                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 292                         KBUILD_MODNAME, ret, i2c_addr, reg);
 293                 return ret;
 294         }
 295         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 296         return 0;
 297 }
 298
 299 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 300                               u8 addr, u8 reg, u8 *val)
 301 {
 302         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 303 }
 304
 305 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 306                                   u8 addr, u8 reg, u8 data, u8 mask)
 307 {
 308         int res;
 309         u8 rdata;
 310
 311         if (mask != 0xff) {
 312                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 313                 if (res)
 314                         return res;
 315                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 316         }
 317         return cxd2841er_write_reg(priv, addr, reg, data);
 318 }
 319
 320 static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
 321 {
 322         u64 tmp;
 323
 324         tmp = (u64) ifhz * 16777216;
 325         do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
 326
 327         return (u32) tmp;
 328 }
 329
 330 static u32 cxd2841er_calc_iffreq(u32 ifhz)
 331 {
 332         return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
 333 }
 334
 335 static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
 336 {
 337         u32 hz;
 338
 339         if (priv->frontend.ops.tuner_ops.get_if_frequency
 340                         && (priv->flags & CXD2841ER_AUTO_IFHZ))
 341                 priv->frontend.ops.tuner_ops.get_if_frequency(
 342                         &priv->frontend, &hz);
 343         else
 344                 hz = def_hz;
 345
 346         return hz;
 347 }
 348
 349 static int cxd2841er_tuner_set(struct dvb_frontend *fe)
 350 {
 351         struct cxd2841er_priv *priv = fe->demodulator_priv;
 352
 353         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 354                 fe->ops.i2c_gate_ctrl(fe, 1);
 355         if (fe->ops.tuner_ops.set_params)
 356                 fe->ops.tuner_ops.set_params(fe);
 357         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 358                 fe->ops.i2c_gate_ctrl(fe, 0);
 359
 360         return 0;
 361 }
 362
 363 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 364                                            u32 symbol_rate)
 365 {
 366         u32 reg_value = 0;
 367         u8 data[3] = {0, 0, 0};
 368
 369         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 370         /*
 371          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 372          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 373          *          = ((symbolRateKSps * 16384) + 500) / 1000
 374          */
 375         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 376         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 377                 dev_err(&priv->i2c->dev,
 378                         "%s(): reg_value is out of range\n", __func__);
 379                 return -EINVAL;
 380         }
 381         data[0] = (u8)((reg_value >> 16) & 0x0F);
 382         data[1] = (u8)((reg_value >>  8) & 0xFF);
 383         data[2] = (u8)(reg_value & 0xFF);
 384         /* Set SLV-T Bank : 0xAE */
 385         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 386         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 387         return 0;
 388 }
 389
 390 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 391                                         u8 system);
 392
 393 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 394                                          u8 system, u32 symbol_rate)
 395 {
 396         int ret;
 397         u8 data[4] = { 0, 0, 0, 0 };
 398
 399         if (priv->state != STATE_SLEEP_S) {
 400                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 401                         __func__, (int)priv->state);
 402                 return -EINVAL;
 403         }
 404         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 405         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 406         /* Set demod mode */
 407         if (system == SYS_DVBS) {
 408                 data[0] = 0x0A;
 409         } else if (system == SYS_DVBS2) {
 410                 data[0] = 0x0B;
 411         } else {
 412                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 413                         __func__, system);
 414                 return -EINVAL;
 415         }
 416         /* Set SLV-X Bank : 0x00 */
 417         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 418         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 419         /* DVB-S/S2 */
 420         data[0] = 0x00;
 421         /* Set SLV-T Bank : 0x00 */
 422         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 423         /* Enable S/S2 auto detection 1 */
 424         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 425         /* Set SLV-T Bank : 0xAE */
 426         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 427         /* Enable S/S2 auto detection 2 */
 428         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 429         /* Set SLV-T Bank : 0x00 */
 430         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 431         /* Enable demod clock */
 432         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 433         /* Enable ADC clock */
 434         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 435         /* Enable ADC 1 */
 436         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 437         /* Enable ADC 2 */
 438         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 439         /* Set SLV-X Bank : 0x00 */
 440         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 441         /* Enable ADC 3 */
 442         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 443         /* Set SLV-T Bank : 0xA3 */
 444         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 445         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 446         data[0] = 0x07;
 447         data[1] = 0x3B;
 448         data[2] = 0x08;
 449         data[3] = 0xC5;
 450         /* Set SLV-T Bank : 0xAB */
 451         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 452         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 453         data[0] = 0x05;
 454         data[1] = 0x80;
 455         data[2] = 0x0A;
 456         data[3] = 0x80;
 457         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 458         data[0] = 0x0C;
 459         data[1] = 0xCC;
 460         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 461         /* Set demod parameter */
 462         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 463         if (ret != 0)
 464                 return ret;
 465         /* Set SLV-T Bank : 0x00 */
 466         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 467         /* disable Hi-Z setting 1 */
 468         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 469         /* disable Hi-Z setting 2 */
 470         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 471         priv->state = STATE_ACTIVE_S;
 472         return 0;
 473 }
 474
 475 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 476                                                u32 bandwidth);
 477
 478 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 479                                                 u32 bandwidth);
 480
 481 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 482                                                u32 bandwidth);
 483
 484 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 485                 u32 bandwidth);
 486
 487 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 488
 489 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 490
 491 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 492
 493 static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
 494
 495 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 496                                    struct dtv_frontend_properties *p)
 497 {
 498         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 499         if (priv->state != STATE_ACTIVE_S &&
 500                         priv->state != STATE_ACTIVE_TC) {
 501                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 502                         __func__, priv->state);
 503                 return -EINVAL;
 504         }
 505         /* Set SLV-T Bank : 0x00 */
 506         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 507         /* disable TS output */
 508         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 509         if (priv->state == STATE_ACTIVE_S)
 510                 return cxd2841er_dvbs2_set_symbol_rate(
 511                                 priv, p->symbol_rate / 1000);
 512         else if (priv->state == STATE_ACTIVE_TC) {
 513                 switch (priv->system) {
 514                 case SYS_DVBT:
 515                         return cxd2841er_sleep_tc_to_active_t_band(
 516                                         priv, p->bandwidth_hz);
 517                 case SYS_DVBT2:
 518                         return cxd2841er_sleep_tc_to_active_t2_band(
 519                                         priv, p->bandwidth_hz);
 520                 case SYS_DVBC_ANNEX_A:
 521                         return cxd2841er_sleep_tc_to_active_c_band(
 522                                         priv, p->bandwidth_hz);
 523                 case SYS_ISDBT:
 524                         cxd2841er_active_i_to_sleep_tc(priv);
 525                         cxd2841er_sleep_tc_to_shutdown(priv);
 526                         cxd2841er_shutdown_to_sleep_tc(priv);
 527                         return cxd2841er_sleep_tc_to_active_i(
 528                                         priv, p->bandwidth_hz);
 529                 }
 530         }
 531         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 532                 __func__, priv->system);
 533         return -EINVAL;
 534 }
 535
 536 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 537 {
 538         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 539         if (priv->state != STATE_ACTIVE_S) {
 540                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 541                         __func__, priv->state);
 542                 return -EINVAL;
 543         }
 544         /* Set SLV-T Bank : 0x00 */
 545         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 546         /* disable TS output */
 547         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 548         /* enable Hi-Z setting 1 */
 549         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 550         /* enable Hi-Z setting 2 */
 551         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 552         /* Set SLV-X Bank : 0x00 */
 553         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 554         /* disable ADC 1 */
 555         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 556         /* Set SLV-T Bank : 0x00 */
 557         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 558         /* disable ADC clock */
 559         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 560         /* disable ADC 2 */
 561         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 562         /* disable ADC 3 */
 563         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 564         /* SADC Bias ON */
 565         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 566         /* disable demod clock */
 567         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 568         /* Set SLV-T Bank : 0xAE */
 569         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 570         /* disable S/S2 auto detection1 */
 571         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 572         /* Set SLV-T Bank : 0x00 */
 573         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 574         /* disable S/S2 auto detection2 */
 575         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 576         priv->state = STATE_SLEEP_S;
 577         return 0;
 578 }
 579
 580 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 581 {
 582         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 583         if (priv->state != STATE_SLEEP_S) {
 584                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 585                         __func__, priv->state);
 586                 return -EINVAL;
 587         }
 588         /* Set SLV-T Bank : 0x00 */
 589         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 590         /* Disable DSQOUT */
 591         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 592         /* Disable DSQIN */
 593         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 594         /* Set SLV-X Bank : 0x00 */
 595         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 596         /* Disable oscillator */
 597         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 598         /* Set demod mode */
 599         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 600         priv->state = STATE_SHUTDOWN;
 601         return 0;
 602 }
 603
 604 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 605 {
 606         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 607         if (priv->state != STATE_SLEEP_TC) {
 608                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 609                         __func__, priv->state);
 610                 return -EINVAL;
 611         }
 612         /* Set SLV-X Bank : 0x00 */
 613         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 614         /* Disable oscillator */
 615         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 616         /* Set demod mode */
 617         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 618         priv->state = STATE_SHUTDOWN;
 619         return 0;
 620 }
 621
 622 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 623 {
 624         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 625         if (priv->state != STATE_ACTIVE_TC) {
 626                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 627                         __func__, priv->state);
 628                 return -EINVAL;
 629         }
 630         /* Set SLV-T Bank : 0x00 */
 631         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 632         /* disable TS output */
 633         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 634         /* enable Hi-Z setting 1 */
 635         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 636         /* enable Hi-Z setting 2 */
 637         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 638         /* Set SLV-X Bank : 0x00 */
 639         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 640         /* disable ADC 1 */
 641         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 642         /* Set SLV-T Bank : 0x00 */
 643         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 644         /* Disable ADC 2 */
 645         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 646         /* Disable ADC 3 */
 647         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 648         /* Disable ADC clock */
 649         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 650         /* Disable RF level monitor */
 651         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 652         /* Disable demod clock */
 653         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 654         priv->state = STATE_SLEEP_TC;
 655         return 0;
 656 }
 657
 658 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 659 {
 660         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 661         if (priv->state != STATE_ACTIVE_TC) {
 662                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 663                         __func__, priv->state);
 664                 return -EINVAL;
 665         }
 666         /* Set SLV-T Bank : 0x00 */
 667         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 668         /* disable TS output */
 669         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 670         /* enable Hi-Z setting 1 */
 671         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 672         /* enable Hi-Z setting 2 */
 673         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 674         /* Cancel DVB-T2 setting */
 675         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 676         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 677         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 678         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 679         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 680         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 681         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 682         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 683         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 684         /* Set SLV-X Bank : 0x00 */
 685         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 686         /* disable ADC 1 */
 687         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 688         /* Set SLV-T Bank : 0x00 */
 689         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 690         /* Disable ADC 2 */
 691         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 692         /* Disable ADC 3 */
 693         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 694         /* Disable ADC clock */
 695         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 696         /* Disable RF level monitor */
 697         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 698         /* Disable demod clock */
 699         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 700         priv->state = STATE_SLEEP_TC;
 701         return 0;
 702 }
 703
 704 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 705 {
 706         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 707         if (priv->state != STATE_ACTIVE_TC) {
 708                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 709                         __func__, priv->state);
 710                 return -EINVAL;
 711         }
 712         /* Set SLV-T Bank : 0x00 */
 713         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 714         /* disable TS output */
 715         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 716         /* enable Hi-Z setting 1 */
 717         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 718         /* enable Hi-Z setting 2 */
 719         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 720         /* Cancel DVB-C setting */
 721         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 722         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 723         /* Set SLV-X Bank : 0x00 */
 724         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 725         /* disable ADC 1 */
 726         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 727         /* Set SLV-T Bank : 0x00 */
 728         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 729         /* Disable ADC 2 */
 730         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 731         /* Disable ADC 3 */
 732         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 733         /* Disable ADC clock */
 734         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 735         /* Disable RF level monitor */
 736         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 737         /* Disable demod clock */
 738         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 739         priv->state = STATE_SLEEP_TC;
 740         return 0;
 741 }
 742
 743 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 744 {
 745         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 746         if (priv->state != STATE_ACTIVE_TC) {
 747                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 748                                 __func__, priv->state);
 749                 return -EINVAL;
 750         }
 751         /* Set SLV-T Bank : 0x00 */
 752         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 753         /* disable TS output */
 754         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 755         /* enable Hi-Z setting 1 */
 756         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 757         /* enable Hi-Z setting 2 */
 758         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 759
 760         /* TODO: Cancel demod parameter */
 761
 762         /* Set SLV-X Bank : 0x00 */
 763         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 764         /* disable ADC 1 */
 765         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 766         /* Set SLV-T Bank : 0x00 */
 767         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 768         /* Disable ADC 2 */
 769         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 770         /* Disable ADC 3 */
 771         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 772         /* Disable ADC clock */
 773         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 774         /* Disable RF level monitor */
 775         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 776         /* Disable demod clock */
 777         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 778         priv->state = STATE_SLEEP_TC;
 779         return 0;
 780 }
 781
 782 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 783 {
 784         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 785         if (priv->state != STATE_SHUTDOWN) {
 786                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 787                         __func__, priv->state);
 788                 return -EINVAL;
 789         }
 790         /* Set SLV-X Bank : 0x00 */
 791         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 792         /* Clear all demodulator registers */
 793         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 794         usleep_range(3000, 5000);
 795         /* Set SLV-X Bank : 0x00 */
 796         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 797         /* Set demod SW reset */
 798         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 799
 800         switch (priv->xtal) {
 801         case SONY_XTAL_20500:
 802                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 803                 break;
 804         case SONY_XTAL_24000:
 805                 /* Select demod frequency */
 806                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 807                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 808                 break;
 809         case SONY_XTAL_41000:
 810                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 811                 break;
 812         default:
 813                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 814                                 __func__, priv->xtal);
 815                 return -EINVAL;
 816         }
 817
 818         /* Set demod mode */
 819         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 820         /* Clear demod SW reset */
 821         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 822         usleep_range(1000, 2000);
 823         /* Set SLV-T Bank : 0x00 */
 824         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 825         /* enable DSQOUT */
 826         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 827         /* enable DSQIN */
 828         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 829         /* TADC Bias On */
 830         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 831         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 832         /* SADC Bias On */
 833         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 834         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 835         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 836         priv->state = STATE_SLEEP_S;
 837         return 0;
 838 }
 839
 840 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 841 {
 842         u8 data = 0;
 843
 844         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 845         if (priv->state != STATE_SHUTDOWN) {
 846                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 847                         __func__, priv->state);
 848                 return -EINVAL;
 849         }
 850         /* Set SLV-X Bank : 0x00 */
 851         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 852         /* Clear all demodulator registers */
 853         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 854         usleep_range(3000, 5000);
 855         /* Set SLV-X Bank : 0x00 */
 856         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 857         /* Set demod SW reset */
 858         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 859   /* Select ADC clock mode */
 860         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 861
 862         switch (priv->xtal) {
 863         case SONY_XTAL_20500:
 864                 data = 0x0;
 865                 break;
 866         case SONY_XTAL_24000:
 867                 /* Select demod frequency */
 868                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 869                 data = 0x3;
 870                 break;
 871         case SONY_XTAL_41000:
 872                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 873                 data = 0x1;
 874                 break;
 875         }
 876         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 877         /* Clear demod SW reset */
 878         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 879         usleep_range(1000, 2000);
 880         /* Set SLV-T Bank : 0x00 */
 881         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 882         /* TADC Bias On */
 883         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 884         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 885         /* SADC Bias On */
 886         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 887         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 888         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 889         priv->state = STATE_SLEEP_TC;
 890         return 0;
 891 }
 892
 893 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 894 {
 895         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 896         /* Set SLV-T Bank : 0x00 */
 897         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 898         /* SW Reset */
 899         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 900         /* Enable TS output */
 901         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 902         return 0;
 903 }
 904
 905 /* Set TS parallel mode */
 906 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 907                                         u8 system)
 908 {
 909         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 910
 911         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 912         /* Set SLV-T Bank : 0x00 */
 913         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 914         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 915         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 916         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 917         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 918                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 919
 920         /*
 921          * slave    Bank    Addr    Bit    default    Name
 922          * <SLV-T>  00h     C4h     [1:0]  2'b??      OSERCKMODE
 923          */
 924         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
 925                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 926         /*
 927          * slave    Bank    Addr    Bit    default    Name
 928          * <SLV-T>  00h     D1h     [1:0]  2'b??      OSERDUTYMODE
 929          */
 930         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
 931                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 932         /*
 933          * slave    Bank    Addr    Bit    default    Name
 934          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 935          */
 936         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 937         /*
 938          * Disable TS IF Clock
 939          * slave    Bank    Addr    Bit    default    Name
 940          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 941          */
 942         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 943         /*
 944          * slave    Bank    Addr    Bit    default    Name
 945          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 946          */
 947         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
 948                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 949         /*
 950          * Enable TS IF Clock
 951          * slave    Bank    Addr    Bit    default    Name
 952          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 953          */
 954         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 955
 956         if (system == SYS_DVBT) {
 957                 /* Enable parity period for DVB-T */
 958                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 959                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 960         } else if (system == SYS_DVBC_ANNEX_A) {
 961                 /* Enable parity period for DVB-C */
 962                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 963                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 964         }
 965 }
 966
 967 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 968 {
 969         u8 chip_id = 0;
 970
 971         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 972         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 973                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 974         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 975                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 976
 977         return chip_id;
 978 }
 979
 980 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 981                                    enum fe_status *status)
 982 {
 983         u8 reg = 0;
 984         struct cxd2841er_priv *priv = fe->demodulator_priv;
 985
 986         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 987         *status = 0;
 988         if (priv->state != STATE_ACTIVE_S) {
 989                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 990                         __func__, priv->state);
 991                 return -EINVAL;
 992         }
 993         /* Set SLV-T Bank : 0xA0 */
 994         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 995         /*
 996          *  slave     Bank      Addr      Bit      Signal name
 997          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 998          */
 999         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
1000         if (reg & 0x04) {
1001                 *status = FE_HAS_SIGNAL
1002                         | FE_HAS_CARRIER
1003                         | FE_HAS_VITERBI
1004                         | FE_HAS_SYNC
1005                         | FE_HAS_LOCK;
1006         }
1007         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
1008         return 0;
1009 }
1010
1011 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1012                                       u8 *sync, u8 *tslock, u8 *unlock)
1013 {
1014         u8 data = 0;
1015
1016         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1017         if (priv->state != STATE_ACTIVE_TC)
1018                 return -EINVAL;
1019         if (priv->system == SYS_DVBT) {
1020                 /* Set SLV-T Bank : 0x10 */
1021                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1022         } else {
1023                 /* Set SLV-T Bank : 0x20 */
1024                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1025         }
1026         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1027         if ((data & 0x07) == 0x07) {
1028                 dev_dbg(&priv->i2c->dev,
1029                         "%s(): invalid hardware state detected\n", __func__);
1030                 *sync = 0;
1031                 *tslock = 0;
1032                 *unlock = 0;
1033         } else {
1034                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1035                 *tslock = ((data & 0x20) ? 1 : 0);
1036                 *unlock = ((data & 0x10) ? 1 : 0);
1037         }
1038         return 0;
1039 }
1040
1041 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1042 {
1043         u8 data;
1044
1045         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1046         if (priv->state != STATE_ACTIVE_TC)
1047                 return -EINVAL;
1048         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1049         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1050         if ((data & 0x01) == 0) {
1051                 *tslock = 0;
1052         } else {
1053                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1054                 *tslock = ((data & 0x20) ? 1 : 0);
1055         }
1056         return 0;
1057 }
1058
1059 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1060                 u8 *sync, u8 *tslock, u8 *unlock)
1061 {
1062         u8 data = 0;
1063
1064         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1065         if (priv->state != STATE_ACTIVE_TC)
1066                 return -EINVAL;
1067         /* Set SLV-T Bank : 0x60 */
1068         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1069         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1070         dev_dbg(&priv->i2c->dev,
1071                         "%s(): lock=0x%x\n", __func__, data);
1072         *sync = ((data & 0x02) ? 1 : 0);
1073         *tslock = ((data & 0x01) ? 1 : 0);
1074         *unlock = ((data & 0x10) ? 1 : 0);
1075         return 0;
1076 }
1077
1078 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1079                                     enum fe_status *status)
1080 {
1081         int ret = 0;
1082         u8 sync = 0;
1083         u8 tslock = 0;
1084         u8 unlock = 0;
1085         struct cxd2841er_priv *priv = fe->demodulator_priv;
1086
1087         *status = 0;
1088         if (priv->state == STATE_ACTIVE_TC) {
1089                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1090                         ret = cxd2841er_read_status_t_t2(
1091                                 priv, &sync, &tslock, &unlock);
1092                         if (ret)
1093                                 goto done;
1094                         if (unlock)
1095                                 goto done;
1096                         if (sync)
1097                                 *status = FE_HAS_SIGNAL |
1098                                         FE_HAS_CARRIER |
1099                                         FE_HAS_VITERBI |
1100                                         FE_HAS_SYNC;
1101                         if (tslock)
1102                                 *status |= FE_HAS_LOCK;
1103                 } else if (priv->system == SYS_ISDBT) {
1104                         ret = cxd2841er_read_status_i(
1105                                         priv, &sync, &tslock, &unlock);
1106                         if (ret)
1107                                 goto done;
1108                         if (unlock)
1109                                 goto done;
1110                         if (sync)
1111                                 *status = FE_HAS_SIGNAL |
1112                                         FE_HAS_CARRIER |
1113                                         FE_HAS_VITERBI |
1114                                         FE_HAS_SYNC;
1115                         if (tslock)
1116                                 *status |= FE_HAS_LOCK;
1117                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1118                         ret = cxd2841er_read_status_c(priv, &tslock);
1119                         if (ret)
1120                                 goto done;
1121                         if (tslock)
1122                                 *status = FE_HAS_SIGNAL |
1123                                         FE_HAS_CARRIER |
1124                                         FE_HAS_VITERBI |
1125                                         FE_HAS_SYNC |
1126                                         FE_HAS_LOCK;
1127                 }
1128         }
1129 done:
1130         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1131         return ret;
1132 }
1133
1134 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1135                                              int *offset)
1136 {
1137         u8 data[3];
1138         u8 is_hs_mode;
1139         s32 cfrl_ctrlval;
1140         s32 temp_div, temp_q, temp_r;
1141
1142         if (priv->state != STATE_ACTIVE_S) {
1143                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1144                         __func__, priv->state);
1145                 return -EINVAL;
1146         }
1147         /*
1148          * Get High Sampling Rate mode
1149          *  slave     Bank      Addr      Bit      Signal name
1150          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1151          */
1152         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1153         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1154         if (data[0] & 0x01) {
1155                 /*
1156                  *  slave     Bank      Addr      Bit      Signal name
1157                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1158                  */
1159                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1160                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1161         } else {
1162                 dev_dbg(&priv->i2c->dev,
1163                         "%s(): unable to detect sampling rate mode\n",
1164                         __func__);
1165                 return -EINVAL;
1166         }
1167         /*
1168          *  slave     Bank      Addr      Bit      Signal name
1169          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1170          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1171          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1172          */
1173         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1174         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1175                                 (((u32)data[1] & 0xFF) <<  8) |
1176                                 ((u32)data[2] & 0xFF), 20);
1177         temp_div = (is_hs_mode ? 1048576 : 1572864);
1178         if (cfrl_ctrlval > 0) {
1179                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1180                         temp_div, &temp_r);
1181         } else {
1182                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1183                         temp_div, &temp_r);
1184         }
1185         if (temp_r >= temp_div / 2)
1186                 temp_q++;
1187         if (cfrl_ctrlval > 0)
1188                 temp_q *= -1;
1189         *offset = temp_q;
1190         return 0;
1191 }
1192
1193 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1194                                            u32 bandwidth, int *offset)
1195 {
1196         u8 data[4];
1197
1198         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1199         if (priv->state != STATE_ACTIVE_TC) {
1200                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1201                         __func__, priv->state);
1202                 return -EINVAL;
1203         }
1204         if (priv->system != SYS_ISDBT) {
1205                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1206                         __func__, priv->system);
1207                 return -EINVAL;
1208         }
1209         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1210         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1211         *offset = -1 * sign_extend32(
1212                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1213                 ((u32)data[2] << 8) | (u32)data[3], 29);
1214
1215         switch (bandwidth) {
1216         case 6000000:
1217                 *offset = -1 * ((*offset) * 8/264);
1218                 break;
1219         case 7000000:
1220                 *offset = -1 * ((*offset) * 8/231);
1221                 break;
1222         case 8000000:
1223                 *offset = -1 * ((*offset) * 8/198);
1224                 break;
1225         default:
1226                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1227                                 __func__, bandwidth);
1228                 return -EINVAL;
1229         }
1230
1231         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1232                         __func__, bandwidth, *offset);
1233
1234         return 0;
1235 }
1236
1237 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1238                                            u32 bandwidth, int *offset)
1239 {
1240         u8 data[4];
1241
1242         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1243         if (priv->state != STATE_ACTIVE_TC) {
1244                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1245                         __func__, priv->state);
1246                 return -EINVAL;
1247         }
1248         if (priv->system != SYS_DVBT) {
1249                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1250                         __func__, priv->system);
1251                 return -EINVAL;
1252         }
1253         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1254         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1255         *offset = -1 * sign_extend32(
1256                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1257                 ((u32)data[2] << 8) | (u32)data[3], 29);
1258         *offset *= (bandwidth / 1000000);
1259         *offset /= 235;
1260         return 0;
1261 }
1262
1263 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1264                                            u32 bandwidth, int *offset)
1265 {
1266         u8 data[4];
1267
1268         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1269         if (priv->state != STATE_ACTIVE_TC) {
1270                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1271                         __func__, priv->state);
1272                 return -EINVAL;
1273         }
1274         if (priv->system != SYS_DVBT2) {
1275                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1276                         __func__, priv->system);
1277                 return -EINVAL;
1278         }
1279         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1280         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1281         *offset = -1 * sign_extend32(
1282                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1283                 ((u32)data[2] << 8) | (u32)data[3], 27);
1284         switch (bandwidth) {
1285         case 1712000:
1286                 *offset /= 582;
1287                 break;
1288         case 5000000:
1289         case 6000000:
1290         case 7000000:
1291         case 8000000:
1292                 *offset *= (bandwidth / 1000000);
1293                 *offset /= 940;
1294                 break;
1295         default:
1296                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1297                         __func__, bandwidth);
1298                 return -EINVAL;
1299         }
1300         return 0;
1301 }
1302
1303 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1304                                           int *offset)
1305 {
1306         u8 data[2];
1307
1308         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1309         if (priv->state != STATE_ACTIVE_TC) {
1310                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1311                         __func__, priv->state);
1312                 return -EINVAL;
1313         }
1314         if (priv->system != SYS_DVBC_ANNEX_A) {
1315                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1316                         __func__, priv->system);
1317                 return -EINVAL;
1318         }
1319         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1320         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1321         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1322                                                 | (u32)data[1], 13), 16384);
1323         return 0;
1324 }
1325
1326 static int cxd2841er_read_packet_errors_c(
1327                 struct cxd2841er_priv *priv, u32 *penum)
1328 {
1329         u8 data[3];
1330
1331         *penum = 0;
1332         if (priv->state != STATE_ACTIVE_TC) {
1333                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1334                                 __func__, priv->state);
1335                 return -EINVAL;
1336         }
1337         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1338         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1339         if (data[2] & 0x01)
1340                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1341         return 0;
1342 }
1343
1344 static int cxd2841er_read_packet_errors_t(
1345                 struct cxd2841er_priv *priv, u32 *penum)
1346 {
1347         u8 data[3];
1348
1349         *penum = 0;
1350         if (priv->state != STATE_ACTIVE_TC) {
1351                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1352                         __func__, priv->state);
1353                 return -EINVAL;
1354         }
1355         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1356         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1357         if (data[2] & 0x01)
1358                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1359         return 0;
1360 }
1361
1362 static int cxd2841er_read_packet_errors_t2(
1363                 struct cxd2841er_priv *priv, u32 *penum)
1364 {
1365         u8 data[3];
1366
1367         *penum = 0;
1368         if (priv->state != STATE_ACTIVE_TC) {
1369                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1370                         __func__, priv->state);
1371                 return -EINVAL;
1372         }
1373         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1374         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1375         if (data[0] & 0x01)
1376                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1377         return 0;
1378 }
1379
1380 static int cxd2841er_read_packet_errors_i(
1381                 struct cxd2841er_priv *priv, u32 *penum)
1382 {
1383         u8 data[2];
1384
1385         *penum = 0;
1386         if (priv->state != STATE_ACTIVE_TC) {
1387                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1388                                 __func__, priv->state);
1389                 return -EINVAL;
1390         }
1391         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1392         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1393
1394         if (!(data[0] & 0x01))
1395                 return 0;
1396
1397         /* Layer A */
1398         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1399         *penum = ((u32)data[0] << 8) | (u32)data[1];
1400
1401         /* Layer B */
1402         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1403         *penum += ((u32)data[0] << 8) | (u32)data[1];
1404
1405         /* Layer C */
1406         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1407         *penum += ((u32)data[0] << 8) | (u32)data[1];
1408
1409         return 0;
1410 }
1411
1412 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1413                 u32 *bit_error, u32 *bit_count)
1414 {
1415         u8 data[3];
1416         u32 bit_err, period_exp;
1417
1418         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1419         if (priv->state != STATE_ACTIVE_TC) {
1420                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1421                                 __func__, priv->state);
1422                 return -EINVAL;
1423         }
1424         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1425         cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1426         if (!(data[0] & 0x80)) {
1427                 dev_dbg(&priv->i2c->dev,
1428                                 "%s(): no valid BER data\n", __func__);
1429                 return -EINVAL;
1430         }
1431         bit_err = ((u32)(data[0] & 0x3f) << 16) |
1432                 ((u32)data[1] << 8) |
1433                 (u32)data[2];
1434         cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1435         period_exp = data[0] & 0x1f;
1436
1437         if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1438                 dev_dbg(&priv->i2c->dev,
1439                                 "%s(): period_exp(%u) or bit_err(%u)  not in range. no valid BER data\n",
1440                                 __func__, period_exp, bit_err);
1441                 return -EINVAL;
1442         }
1443
1444         dev_dbg(&priv->i2c->dev,
1445                         "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1446                         __func__, period_exp, bit_err,
1447                         ((1 << period_exp) * 204 * 8));
1448
1449         *bit_error = bit_err;
1450         *bit_count = ((1 << period_exp) * 204 * 8);
1451
1452         return 0;
1453 }
1454
1455 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1456                 u32 *bit_error, u32 *bit_count)
1457 {
1458         u8 data[3];
1459         u8 pktnum[2];
1460
1461         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1462         if (priv->state != STATE_ACTIVE_TC) {
1463                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1464                                 __func__, priv->state);
1465                 return -EINVAL;
1466         }
1467
1468         cxd2841er_freeze_regs(priv);
1469         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1470         cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1471         cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1472         cxd2841er_unfreeze_regs(priv);
1473
1474         if (!pktnum[0] && !pktnum[1]) {
1475                 dev_dbg(&priv->i2c->dev,
1476                                 "%s(): no valid BER data\n", __func__);
1477                 return -EINVAL;
1478         }
1479
1480         *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1481                 ((u32)data[1] << 8) | data[2];
1482         *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1483         dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1484                         __func__, *bit_error, *bit_count);
1485
1486         return 0;
1487 }
1488
1489 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1490                                     u32 *bit_error, u32 *bit_count)
1491 {
1492         u8 data[11];
1493
1494         /* Set SLV-T Bank : 0xA0 */
1495         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1496         /*
1497          *  slave     Bank      Addr      Bit      Signal name
1498          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1499          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1500          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1501          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1502          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1503          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1504          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1505          */
1506         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1507         if (data[0] & 0x01) {
1508                 *bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1509                              ((u32)(data[2]  & 0xFF) <<  8) |
1510                              (u32)(data[3]  & 0xFF);
1511                 *bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1512                              ((u32)(data[9]  & 0xFF) <<  8) |
1513                              (u32)(data[10] & 0xFF);
1514                 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1515                         dev_dbg(&priv->i2c->dev,
1516                                 "%s(): invalid bit_error %d, bit_count %d\n",
1517                                 __func__, *bit_error, *bit_count);
1518                         return -EINVAL;
1519                 }
1520                 return 0;
1521         }
1522         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1523         return -EINVAL;
1524 }
1525
1526
1527 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1528                                      u32 *bit_error, u32 *bit_count)
1529 {
1530         u8 data[5];
1531         u32 period;
1532
1533         /* Set SLV-T Bank : 0xB2 */
1534         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1535         /*
1536          *  slave     Bank      Addr      Bit      Signal name
1537          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1538          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1539          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1540          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1541          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1542          */
1543         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1544         if (data[0] & 0x01) {
1545                 /* Bit error count */
1546                 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1547                              ((u32)(data[2] & 0xFF) << 16) |
1548                              ((u32)(data[3] & 0xFF) <<  8) |
1549                              (u32)(data[4] & 0xFF);
1550
1551                 /* Set SLV-T Bank : 0xA0 */
1552                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1553                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1554                 /* Measurement period */
1555                 period = (u32)(1 << (data[0] & 0x0F));
1556                 if (period == 0) {
1557                         dev_dbg(&priv->i2c->dev,
1558                                 "%s(): period is 0\n", __func__);
1559                         return -EINVAL;
1560                 }
1561                 if (*bit_error > (period * 64800)) {
1562                         dev_dbg(&priv->i2c->dev,
1563                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1564                                 __func__, *bit_error, period);
1565                         return -EINVAL;
1566                 }
1567                 *bit_count = period * 64800;
1568
1569                 return 0;
1570         } else {
1571                 dev_dbg(&priv->i2c->dev,
1572                         "%s(): no data available\n", __func__);
1573         }
1574         return -EINVAL;
1575 }
1576
1577 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1578                                  u32 *bit_error, u32 *bit_count)
1579 {
1580         u8 data[4];
1581         u32 period_exp, n_ldpc;
1582
1583         if (priv->state != STATE_ACTIVE_TC) {
1584                 dev_dbg(&priv->i2c->dev,
1585                         "%s(): invalid state %d\n", __func__, priv->state);
1586                 return -EINVAL;
1587         }
1588         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1589         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1590         if (!(data[0] & 0x10)) {
1591                 dev_dbg(&priv->i2c->dev,
1592                         "%s(): no valid BER data\n", __func__);
1593                 return -EINVAL;
1594         }
1595         *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1596                      ((u32)data[1] << 16) |
1597                      ((u32)data[2] << 8) |
1598                      (u32)data[3];
1599         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1600         period_exp = data[0] & 0x0f;
1601         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1602         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1603         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1604         if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1605                 dev_dbg(&priv->i2c->dev,
1606                         "%s(): invalid BER value\n", __func__);
1607                 return -EINVAL;
1608         }
1609
1610         /*
1611          * FIXME: the right thing would be to return bit_error untouched,
1612          * but, as we don't know the scale returned by the counters, let's
1613          * at least preserver BER = bit_error/bit_count.
1614          */
1615         if (period_exp >= 4) {
1616                 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1617                 *bit_error *= 3125ULL;
1618         } else {
1619                 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1620                 *bit_error *= 50000ULL;
1621         }
1622         return 0;
1623 }
1624
1625 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1626                                 u32 *bit_error, u32 *bit_count)
1627 {
1628         u8 data[2];
1629         u32 period;
1630
1631         if (priv->state != STATE_ACTIVE_TC) {
1632                 dev_dbg(&priv->i2c->dev,
1633                         "%s(): invalid state %d\n", __func__, priv->state);
1634                 return -EINVAL;
1635         }
1636         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1637         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1638         if (!(data[0] & 0x01)) {
1639                 dev_dbg(&priv->i2c->dev,
1640                         "%s(): no valid BER data\n", __func__);
1641                 return 0;
1642         }
1643         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1644         *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1645         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1646         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1647
1648         /*
1649          * FIXME: the right thing would be to return bit_error untouched,
1650          * but, as we don't know the scale returned by the counters, let's
1651          * at least preserver BER = bit_error/bit_count.
1652          */
1653         *bit_count = period / 128;
1654         *bit_error *= 78125ULL;
1655         return 0;
1656 }
1657
1658 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1659 {
1660         /*
1661          * Freeze registers: ensure multiple separate register reads
1662          * are from the same snapshot
1663          */
1664         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1665         return 0;
1666 }
1667
1668 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1669 {
1670         /*
1671          * un-freeze registers
1672          */
1673         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1674         return 0;
1675 }
1676
1677 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1678                 u8 delsys, u32 *snr)
1679 {
1680         u8 data[3];
1681         u32 res = 0, value;
1682         int min_index, max_index, index;
1683         static const struct cxd2841er_cnr_data *cn_data;
1684
1685         cxd2841er_freeze_regs(priv);
1686         /* Set SLV-T Bank : 0xA1 */
1687         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1688         /*
1689          *  slave     Bank      Addr      Bit     Signal name
1690          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1691          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1692          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1693          */
1694         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1695         cxd2841er_unfreeze_regs(priv);
1696
1697         if (data[0] & 0x01) {
1698                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1699                 min_index = 0;
1700                 if (delsys == SYS_DVBS) {
1701                         cn_data = s_cn_data;
1702                         max_index = ARRAY_SIZE(s_cn_data) - 1;
1703                 } else {
1704                         cn_data = s2_cn_data;
1705                         max_index = ARRAY_SIZE(s2_cn_data) - 1;
1706                 }
1707                 if (value >= cn_data[min_index].value) {
1708                         res = cn_data[min_index].cnr_x1000;
1709                         goto done;
1710                 }
1711                 if (value <= cn_data[max_index].value) {
1712                         res = cn_data[max_index].cnr_x1000;
1713                         goto done;
1714                 }
1715                 while ((max_index - min_index) > 1) {
1716                         index = (max_index + min_index) / 2;
1717                         if (value == cn_data[index].value) {
1718                                 res = cn_data[index].cnr_x1000;
1719                                 goto done;
1720                         } else if (value > cn_data[index].value)
1721                                 max_index = index;
1722                         else
1723                                 min_index = index;
1724                         if ((max_index - min_index) <= 1) {
1725                                 if (value == cn_data[max_index].value) {
1726                                         res = cn_data[max_index].cnr_x1000;
1727                                         goto done;
1728                                 } else {
1729                                         res = cn_data[min_index].cnr_x1000;
1730                                         goto done;
1731                                 }
1732                         }
1733                 }
1734         } else {
1735                 dev_dbg(&priv->i2c->dev,
1736                         "%s(): no data available\n", __func__);
1737                 return -EINVAL;
1738         }
1739 done:
1740         *snr = res;
1741         return 0;
1742 }
1743
1744 static uint32_t sony_log(uint32_t x)
1745 {
1746         return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1747 }
1748
1749 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1750 {
1751         u32 reg;
1752         u8 data[2];
1753         enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1754
1755         *snr = 0;
1756         if (priv->state != STATE_ACTIVE_TC) {
1757                 dev_dbg(&priv->i2c->dev,
1758                                 "%s(): invalid state %d\n",
1759                                 __func__, priv->state);
1760                 return -EINVAL;
1761         }
1762
1763         cxd2841er_freeze_regs(priv);
1764         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1765         cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1766         qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1767         cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1768         cxd2841er_unfreeze_regs(priv);
1769
1770         reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1771         if (reg == 0) {
1772                 dev_dbg(&priv->i2c->dev,
1773                                 "%s(): reg value out of range\n", __func__);
1774                 return 0;
1775         }
1776
1777         switch (qam) {
1778         case SONY_DVBC_CONSTELLATION_16QAM:
1779         case SONY_DVBC_CONSTELLATION_64QAM:
1780         case SONY_DVBC_CONSTELLATION_256QAM:
1781                 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1782                 if (reg < 126)
1783                         reg = 126;
1784                 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1785                 break;
1786         case SONY_DVBC_CONSTELLATION_32QAM:
1787         case SONY_DVBC_CONSTELLATION_128QAM:
1788                 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1789                 if (reg < 69)
1790                         reg = 69;
1791                 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1792                 break;
1793         default:
1794                 return -EINVAL;
1795         }
1796
1797         return 0;
1798 }
1799
1800 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1801 {
1802         u32 reg;
1803         u8 data[2];
1804
1805         *snr = 0;
1806         if (priv->state != STATE_ACTIVE_TC) {
1807                 dev_dbg(&priv->i2c->dev,
1808                         "%s(): invalid state %d\n", __func__, priv->state);
1809                 return -EINVAL;
1810         }
1811
1812         cxd2841er_freeze_regs(priv);
1813         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1814         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1815         cxd2841er_unfreeze_regs(priv);
1816
1817         reg = ((u32)data[0] << 8) | (u32)data[1];
1818         if (reg == 0) {
1819                 dev_dbg(&priv->i2c->dev,
1820                         "%s(): reg value out of range\n", __func__);
1821                 return 0;
1822         }
1823         if (reg > 4996)
1824                 reg = 4996;
1825         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
1826         return 0;
1827 }
1828
1829 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1830 {
1831         u32 reg;
1832         u8 data[2];
1833
1834         *snr = 0;
1835         if (priv->state != STATE_ACTIVE_TC) {
1836                 dev_dbg(&priv->i2c->dev,
1837                         "%s(): invalid state %d\n", __func__, priv->state);
1838                 return -EINVAL;
1839         }
1840
1841         cxd2841er_freeze_regs(priv);
1842         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1843         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1844         cxd2841er_unfreeze_regs(priv);
1845
1846         reg = ((u32)data[0] << 8) | (u32)data[1];
1847         if (reg == 0) {
1848                 dev_dbg(&priv->i2c->dev,
1849                         "%s(): reg value out of range\n", __func__);
1850                 return 0;
1851         }
1852         if (reg > 10876)
1853                 reg = 10876;
1854         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
1855         return 0;
1856 }
1857
1858 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1859 {
1860         u32 reg;
1861         u8 data[2];
1862
1863         *snr = 0;
1864         if (priv->state != STATE_ACTIVE_TC) {
1865                 dev_dbg(&priv->i2c->dev,
1866                                 "%s(): invalid state %d\n", __func__,
1867                                 priv->state);
1868                 return -EINVAL;
1869         }
1870
1871         cxd2841er_freeze_regs(priv);
1872         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1873         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1874         cxd2841er_unfreeze_regs(priv);
1875
1876         reg = ((u32)data[0] << 8) | (u32)data[1];
1877         if (reg == 0) {
1878                 dev_dbg(&priv->i2c->dev,
1879                                 "%s(): reg value out of range\n", __func__);
1880                 return 0;
1881         }
1882         *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1883         return 0;
1884 }
1885
1886 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1887                                         u8 delsys)
1888 {
1889         u8 data[2];
1890
1891         cxd2841er_write_reg(
1892                 priv, I2C_SLVT, 0x00, 0x40);
1893         cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1894         dev_dbg(&priv->i2c->dev,
1895                         "%s(): AGC value=%u\n",
1896                         __func__, (((u16)data[0] & 0x0F) << 8) |
1897                         (u16)(data[1] & 0xFF));
1898         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1899 }
1900
1901 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1902                                         u8 delsys)
1903 {
1904         u8 data[2];
1905
1906         cxd2841er_write_reg(
1907                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1908         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1909         dev_dbg(&priv->i2c->dev,
1910                         "%s(): AGC value=%u\n",
1911                         __func__, (((u16)data[0] & 0x0F) << 8) |
1912                         (u16)(data[1] & 0xFF));
1913         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1914 }
1915
1916 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1917                 u8 delsys)
1918 {
1919         u8 data[2];
1920
1921         cxd2841er_write_reg(
1922                         priv, I2C_SLVT, 0x00, 0x60);
1923         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1924
1925         dev_dbg(&priv->i2c->dev,
1926                         "%s(): AGC value=%u\n",
1927                         __func__, (((u16)data[0] & 0x0F) << 8) |
1928                         (u16)(data[1] & 0xFF));
1929         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1930 }
1931
1932 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1933 {
1934         u8 data[2];
1935
1936         /* Set SLV-T Bank : 0xA0 */
1937         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1938         /*
1939          *  slave     Bank      Addr      Bit       Signal name
1940          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1941          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1942          */
1943         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1944         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1945 }
1946
1947 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1948 {
1949         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1950         struct cxd2841er_priv *priv = fe->demodulator_priv;
1951         u32 ret, bit_error = 0, bit_count = 0;
1952
1953         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1954         switch (p->delivery_system) {
1955         case SYS_DVBC_ANNEX_A:
1956         case SYS_DVBC_ANNEX_B:
1957         case SYS_DVBC_ANNEX_C:
1958                 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1959                 break;
1960         case SYS_ISDBT:
1961                 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1962                 break;
1963         case SYS_DVBS:
1964                 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1965                 break;
1966         case SYS_DVBS2:
1967                 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1968                 break;
1969         case SYS_DVBT:
1970                 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1971                 break;
1972         case SYS_DVBT2:
1973                 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1974                 break;
1975         default:
1976                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1977                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1978                 return;
1979         }
1980
1981         if (!ret) {
1982                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1983                 p->post_bit_error.stat[0].uvalue += bit_error;
1984                 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1985                 p->post_bit_count.stat[0].uvalue += bit_count;
1986         } else {
1987                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1988                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1989         }
1990 }
1991
1992 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1993 {
1994         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1995         struct cxd2841er_priv *priv = fe->demodulator_priv;
1996         s32 strength;
1997
1998         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1999         switch (p->delivery_system) {
2000         case SYS_DVBT:
2001         case SYS_DVBT2:
2002                 strength = cxd2841er_read_agc_gain_t_t2(priv,
2003                                                         p->delivery_system);
2004                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2005                 /* Formula was empirically determinated @ 410 MHz */
2006                 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
2007                 break;  /* Code moved out of the function */
2008         case SYS_DVBC_ANNEX_A:
2009         case SYS_DVBC_ANNEX_B:
2010         case SYS_DVBC_ANNEX_C:
2011                 strength = cxd2841er_read_agc_gain_c(priv,
2012                                                         p->delivery_system);
2013                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2014                 /*
2015                  * Formula was empirically determinated via linear regression,
2016                  * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2017                  * stream modulated with QAM64
2018                  */
2019                 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
2020                 break;
2021         case SYS_ISDBT:
2022                 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2023                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2024                 /*
2025                  * Formula was empirically determinated via linear regression,
2026                  * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2027                  */
2028                 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
2029                 break;
2030         case SYS_DVBS:
2031         case SYS_DVBS2:
2032                 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2033                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2034                 p->strength.stat[0].uvalue = strength;
2035                 break;
2036         default:
2037                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2038                 break;
2039         }
2040 }
2041
2042 static void cxd2841er_read_snr(struct dvb_frontend *fe)
2043 {
2044         u32 tmp = 0;
2045         int ret = 0;
2046         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2047         struct cxd2841er_priv *priv = fe->demodulator_priv;
2048
2049         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2050         switch (p->delivery_system) {
2051         case SYS_DVBC_ANNEX_A:
2052         case SYS_DVBC_ANNEX_B:
2053         case SYS_DVBC_ANNEX_C:
2054                 ret = cxd2841er_read_snr_c(priv, &tmp);
2055                 break;
2056         case SYS_DVBT:
2057                 ret = cxd2841er_read_snr_t(priv, &tmp);
2058                 break;
2059         case SYS_DVBT2:
2060                 ret = cxd2841er_read_snr_t2(priv, &tmp);
2061                 break;
2062         case SYS_ISDBT:
2063                 ret = cxd2841er_read_snr_i(priv, &tmp);
2064                 break;
2065         case SYS_DVBS:
2066         case SYS_DVBS2:
2067                 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2068                 break;
2069         default:
2070                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2071                         __func__, p->delivery_system);
2072                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2073                 return;
2074         }
2075
2076         dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2077                         __func__, (int32_t)tmp);
2078
2079         if (!ret) {
2080                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2081                 p->cnr.stat[0].svalue = tmp;
2082         } else {
2083                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2084         }
2085 }
2086
2087 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2088 {
2089         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2090         struct cxd2841er_priv *priv = fe->demodulator_priv;
2091         u32 ucblocks = 0;
2092
2093         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2094         switch (p->delivery_system) {
2095         case SYS_DVBC_ANNEX_A:
2096         case SYS_DVBC_ANNEX_B:
2097         case SYS_DVBC_ANNEX_C:
2098                 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2099                 break;
2100         case SYS_DVBT:
2101                 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2102                 break;
2103         case SYS_DVBT2:
2104                 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2105                 break;
2106         case SYS_ISDBT:
2107                 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2108                 break;
2109         default:
2110                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2111                 return;
2112         }
2113         dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2114
2115         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2116         p->block_error.stat[0].uvalue = ucblocks;
2117 }
2118
2119 static int cxd2841er_dvbt2_set_profile(
2120         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2121 {
2122         u8 tune_mode;
2123         u8 seq_not2d_time;
2124
2125         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2126         switch (profile) {
2127         case DVBT2_PROFILE_BASE:
2128                 tune_mode = 0x01;
2129                 /* Set early unlock time */
2130                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2131                 break;
2132         case DVBT2_PROFILE_LITE:
2133                 tune_mode = 0x05;
2134                 /* Set early unlock time */
2135                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2136                 break;
2137         case DVBT2_PROFILE_ANY:
2138                 tune_mode = 0x00;
2139                 /* Set early unlock time */
2140                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2141                 break;
2142         default:
2143                 return -EINVAL;
2144         }
2145         /* Set SLV-T Bank : 0x2E */
2146         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2147         /* Set profile and tune mode */
2148         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2149         /* Set SLV-T Bank : 0x2B */
2150         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2151         /* Set early unlock detection time */
2152         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2153         return 0;
2154 }
2155
2156 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2157                                           u8 is_auto, u8 plp_id)
2158 {
2159         if (is_auto) {
2160                 dev_dbg(&priv->i2c->dev,
2161                         "%s() using auto PLP selection\n", __func__);
2162         } else {
2163                 dev_dbg(&priv->i2c->dev,
2164                         "%s() using manual PLP selection, ID %d\n",
2165                         __func__, plp_id);
2166         }
2167         /* Set SLV-T Bank : 0x23 */
2168         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2169         if (!is_auto) {
2170                 /* Manual PLP selection mode. Set the data PLP Id. */
2171                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2172         }
2173         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2174         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2175         return 0;
2176 }
2177
2178 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2179                                                 u32 bandwidth)
2180 {
2181         u32 iffreq, ifhz;
2182         u8 data[MAX_WRITE_REGSIZE];
2183
2184         static const uint8_t nominalRate8bw[3][5] = {
2185                 /* TRCG Nominal Rate [37:0] */
2186                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2187                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2188                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2189         };
2190
2191         static const uint8_t nominalRate7bw[3][5] = {
2192                 /* TRCG Nominal Rate [37:0] */
2193                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2194                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2195                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2196         };
2197
2198         static const uint8_t nominalRate6bw[3][5] = {
2199                 /* TRCG Nominal Rate [37:0] */
2200                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2201                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2202                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2203         };
2204
2205         static const uint8_t nominalRate5bw[3][5] = {
2206                 /* TRCG Nominal Rate [37:0] */
2207                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2208                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2209                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2210         };
2211
2212         static const uint8_t nominalRate17bw[3][5] = {
2213                 /* TRCG Nominal Rate [37:0] */
2214                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2215                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2216                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
2217         };
2218
2219         static const uint8_t itbCoef8bw[3][14] = {
2220                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2221                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2222                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2223                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2224                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2225                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2226         };
2227
2228         static const uint8_t itbCoef7bw[3][14] = {
2229                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2230                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2231                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2232                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2233                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2234                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2235         };
2236
2237         static const uint8_t itbCoef6bw[3][14] = {
2238                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2239                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2240                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2241                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2242                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2243                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2244         };
2245
2246         static const uint8_t itbCoef5bw[3][14] = {
2247                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2248                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2249                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2250                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2251                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2252                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2253         };
2254
2255         static const uint8_t itbCoef17bw[3][14] = {
2256                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2257                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2258                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2259                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
2260                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2261                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
2262         };
2263
2264         /* Set SLV-T Bank : 0x20 */
2265         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2266
2267         switch (bandwidth) {
2268         case 8000000:
2269                 /* <Timing Recovery setting> */
2270                 cxd2841er_write_regs(priv, I2C_SLVT,
2271                                 0x9F, nominalRate8bw[priv->xtal], 5);
2272
2273                 /* Set SLV-T Bank : 0x27 */
2274                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2275                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2276                                 0x7a, 0x00, 0x0f);
2277
2278                 /* Set SLV-T Bank : 0x10 */
2279                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2280
2281                 /* Group delay equaliser settings for
2282                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2283                  */
2284                 if (priv->flags & CXD2841ER_ASCOT)
2285                         cxd2841er_write_regs(priv, I2C_SLVT,
2286                                 0xA6, itbCoef8bw[priv->xtal], 14);
2287                 /* <IF freq setting> */
2288                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2289                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2290                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2291                 data[1] = (u8)((iffreq >> 8) & 0xff);
2292                 data[2] = (u8)(iffreq & 0xff);
2293                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2294                 /* System bandwidth setting */
2295                 cxd2841er_set_reg_bits(
2296                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2297                 break;
2298         case 7000000:
2299                 /* <Timing Recovery setting> */
2300                 cxd2841er_write_regs(priv, I2C_SLVT,
2301                                 0x9F, nominalRate7bw[priv->xtal], 5);
2302
2303                 /* Set SLV-T Bank : 0x27 */
2304                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2305                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2306                                 0x7a, 0x00, 0x0f);
2307
2308                 /* Set SLV-T Bank : 0x10 */
2309                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2310
2311                 /* Group delay equaliser settings for
2312                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2313                  */
2314                 if (priv->flags & CXD2841ER_ASCOT)
2315                         cxd2841er_write_regs(priv, I2C_SLVT,
2316                                 0xA6, itbCoef7bw[priv->xtal], 14);
2317                 /* <IF freq setting> */
2318                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2319                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2320                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2321                 data[1] = (u8)((iffreq >> 8) & 0xff);
2322                 data[2] = (u8)(iffreq & 0xff);
2323                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2324                 /* System bandwidth setting */
2325                 cxd2841er_set_reg_bits(
2326                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2327                 break;
2328         case 6000000:
2329                 /* <Timing Recovery setting> */
2330                 cxd2841er_write_regs(priv, I2C_SLVT,
2331                                 0x9F, nominalRate6bw[priv->xtal], 5);
2332
2333                 /* Set SLV-T Bank : 0x27 */
2334                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2335                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2336                                 0x7a, 0x00, 0x0f);
2337
2338                 /* Set SLV-T Bank : 0x10 */
2339                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2340
2341                 /* Group delay equaliser settings for
2342                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2343                  */
2344                 if (priv->flags & CXD2841ER_ASCOT)
2345                         cxd2841er_write_regs(priv, I2C_SLVT,
2346                                 0xA6, itbCoef6bw[priv->xtal], 14);
2347                 /* <IF freq setting> */
2348                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2349                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2350                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2351                 data[1] = (u8)((iffreq >> 8) & 0xff);
2352                 data[2] = (u8)(iffreq & 0xff);
2353                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2354                 /* System bandwidth setting */
2355                 cxd2841er_set_reg_bits(
2356                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2357                 break;
2358         case 5000000:
2359                 /* <Timing Recovery setting> */
2360                 cxd2841er_write_regs(priv, I2C_SLVT,
2361                                 0x9F, nominalRate5bw[priv->xtal], 5);
2362
2363                 /* Set SLV-T Bank : 0x27 */
2364                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2365                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2366                                 0x7a, 0x00, 0x0f);
2367
2368                 /* Set SLV-T Bank : 0x10 */
2369                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2370
2371                 /* Group delay equaliser settings for
2372                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2373                  */
2374                 if (priv->flags & CXD2841ER_ASCOT)
2375                         cxd2841er_write_regs(priv, I2C_SLVT,
2376                                 0xA6, itbCoef5bw[priv->xtal], 14);
2377                 /* <IF freq setting> */
2378                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2379                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2380                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2381                 data[1] = (u8)((iffreq >> 8) & 0xff);
2382                 data[2] = (u8)(iffreq & 0xff);
2383                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2384                 /* System bandwidth setting */
2385                 cxd2841er_set_reg_bits(
2386                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2387                 break;
2388         case 1712000:
2389                 /* <Timing Recovery setting> */
2390                 cxd2841er_write_regs(priv, I2C_SLVT,
2391                                 0x9F, nominalRate17bw[priv->xtal], 5);
2392
2393                 /* Set SLV-T Bank : 0x27 */
2394                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2395                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2396                                 0x7a, 0x03, 0x0f);
2397
2398                 /* Set SLV-T Bank : 0x10 */
2399                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2400
2401                 /* Group delay equaliser settings for
2402                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2403                  */
2404                 if (priv->flags & CXD2841ER_ASCOT)
2405                         cxd2841er_write_regs(priv, I2C_SLVT,
2406                                 0xA6, itbCoef17bw[priv->xtal], 14);
2407                 /* <IF freq setting> */
2408                 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2409                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2410                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2411                 data[1] = (u8)((iffreq >> 8) & 0xff);
2412                 data[2] = (u8)(iffreq & 0xff);
2413                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2414                 /* System bandwidth setting */
2415                 cxd2841er_set_reg_bits(
2416                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2417                 break;
2418         default:
2419                 return -EINVAL;
2420         }
2421         return 0;
2422 }
2423
2424 static int cxd2841er_sleep_tc_to_active_t_band(
2425                 struct cxd2841er_priv *priv, u32 bandwidth)
2426 {
2427         u8 data[MAX_WRITE_REGSIZE];
2428         u32 iffreq, ifhz;
2429         static const u8 nominalRate8bw[3][5] = {
2430                 /* TRCG Nominal Rate [37:0] */
2431                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2432                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2433                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2434         };
2435         static const u8 nominalRate7bw[3][5] = {
2436                 /* TRCG Nominal Rate [37:0] */
2437                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2438                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2439                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2440         };
2441         static const u8 nominalRate6bw[3][5] = {
2442                 /* TRCG Nominal Rate [37:0] */
2443                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2444                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2445                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2446         };
2447         static const u8 nominalRate5bw[3][5] = {
2448                 /* TRCG Nominal Rate [37:0] */
2449                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2450                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2451                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2452         };
2453
2454         static const u8 itbCoef8bw[3][14] = {
2455                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2456                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2457                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2458                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2459                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2460                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2461         };
2462         static const u8 itbCoef7bw[3][14] = {
2463                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2464                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2465                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2466                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2467                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2468                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2469         };
2470         static const u8 itbCoef6bw[3][14] = {
2471                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2472                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2473                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2474                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2475                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2476                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2477         };
2478         static const u8 itbCoef5bw[3][14] = {
2479                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2480                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2481                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2482                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2483                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2484                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2485         };
2486
2487         /* Set SLV-T Bank : 0x13 */
2488         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2489         /* Echo performance optimization setting */
2490         data[0] = 0x01;
2491         data[1] = 0x14;
2492         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2493
2494         /* Set SLV-T Bank : 0x10 */
2495         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2496
2497         switch (bandwidth) {
2498         case 8000000:
2499                 /* <Timing Recovery setting> */
2500                 cxd2841er_write_regs(priv, I2C_SLVT,
2501                                 0x9F, nominalRate8bw[priv->xtal], 5);
2502                 /* Group delay equaliser settings for
2503                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2504                 */
2505                 if (priv->flags & CXD2841ER_ASCOT)
2506                         cxd2841er_write_regs(priv, I2C_SLVT,
2507                                 0xA6, itbCoef8bw[priv->xtal], 14);
2508                 /* <IF freq setting> */
2509                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2510                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2511                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2512                 data[1] = (u8)((iffreq >> 8) & 0xff);
2513                 data[2] = (u8)(iffreq & 0xff);
2514                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2515                 /* System bandwidth setting */
2516                 cxd2841er_set_reg_bits(
2517                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2518
2519                 /* Demod core latency setting */
2520                 if (priv->xtal == SONY_XTAL_24000) {
2521                         data[0] = 0x15;
2522                         data[1] = 0x28;
2523                 } else {
2524                         data[0] = 0x01;
2525                         data[1] = 0xE0;
2526                 }
2527                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2528
2529                 /* Notch filter setting */
2530                 data[0] = 0x01;
2531                 data[1] = 0x02;
2532                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2533                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2534                 break;
2535         case 7000000:
2536                 /* <Timing Recovery setting> */
2537                 cxd2841er_write_regs(priv, I2C_SLVT,
2538                                 0x9F, nominalRate7bw[priv->xtal], 5);
2539                 /* Group delay equaliser settings for
2540                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2541                 */
2542                 if (priv->flags & CXD2841ER_ASCOT)
2543                         cxd2841er_write_regs(priv, I2C_SLVT,
2544                                 0xA6, itbCoef7bw[priv->xtal], 14);
2545                 /* <IF freq setting> */
2546                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2547                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2548                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2549                 data[1] = (u8)((iffreq >> 8) & 0xff);
2550                 data[2] = (u8)(iffreq & 0xff);
2551                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2552                 /* System bandwidth setting */
2553                 cxd2841er_set_reg_bits(
2554                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2555
2556                 /* Demod core latency setting */
2557                 if (priv->xtal == SONY_XTAL_24000) {
2558                         data[0] = 0x1F;
2559                         data[1] = 0xF8;
2560                 } else {
2561                         data[0] = 0x12;
2562                         data[1] = 0xF8;
2563                 }
2564                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2565
2566                 /* Notch filter setting */
2567                 data[0] = 0x00;
2568                 data[1] = 0x03;
2569                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2570                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2571                 break;
2572         case 6000000:
2573                 /* <Timing Recovery setting> */
2574                 cxd2841er_write_regs(priv, I2C_SLVT,
2575                                 0x9F, nominalRate6bw[priv->xtal], 5);
2576                 /* Group delay equaliser settings for
2577                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2578                 */
2579                 if (priv->flags & CXD2841ER_ASCOT)
2580                         cxd2841er_write_regs(priv, I2C_SLVT,
2581                                 0xA6, itbCoef6bw[priv->xtal], 14);
2582                 /* <IF freq setting> */
2583                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2584                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2585                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2586                 data[1] = (u8)((iffreq >> 8) & 0xff);
2587                 data[2] = (u8)(iffreq & 0xff);
2588                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2589                 /* System bandwidth setting */
2590                 cxd2841er_set_reg_bits(
2591                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2592
2593                 /* Demod core latency setting */
2594                 if (priv->xtal == SONY_XTAL_24000) {
2595                         data[0] = 0x25;
2596                         data[1] = 0x4C;
2597                 } else {
2598                         data[0] = 0x1F;
2599                         data[1] = 0xDC;
2600                 }
2601                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2602
2603                 /* Notch filter setting */
2604                 data[0] = 0x00;
2605                 data[1] = 0x03;
2606                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2607                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2608                 break;
2609         case 5000000:
2610                 /* <Timing Recovery setting> */
2611                 cxd2841er_write_regs(priv, I2C_SLVT,
2612                                 0x9F, nominalRate5bw[priv->xtal], 5);
2613                 /* Group delay equaliser settings for
2614                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2615                 */
2616                 if (priv->flags & CXD2841ER_ASCOT)
2617                         cxd2841er_write_regs(priv, I2C_SLVT,
2618                                 0xA6, itbCoef5bw[priv->xtal], 14);
2619                 /* <IF freq setting> */
2620                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2621                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2622                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2623                 data[1] = (u8)((iffreq >> 8) & 0xff);
2624                 data[2] = (u8)(iffreq & 0xff);
2625                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2626                 /* System bandwidth setting */
2627                 cxd2841er_set_reg_bits(
2628                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2629
2630                 /* Demod core latency setting */
2631                 if (priv->xtal == SONY_XTAL_24000) {
2632                         data[0] = 0x2C;
2633                         data[1] = 0xC2;
2634                 } else {
2635                         data[0] = 0x26;
2636                         data[1] = 0x3C;
2637                 }
2638                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2639
2640                 /* Notch filter setting */
2641                 data[0] = 0x00;
2642                 data[1] = 0x03;
2643                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2644                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2645                 break;
2646         }
2647
2648         return 0;
2649 }
2650
2651 static int cxd2841er_sleep_tc_to_active_i_band(
2652                 struct cxd2841er_priv *priv, u32 bandwidth)
2653 {
2654         u32 iffreq, ifhz;
2655         u8 data[3];
2656
2657         /* TRCG Nominal Rate */
2658         static const u8 nominalRate8bw[3][5] = {
2659                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2660                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2661                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2662         };
2663
2664         static const u8 nominalRate7bw[3][5] = {
2665                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2666                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2667                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2668         };
2669
2670         static const u8 nominalRate6bw[3][5] = {
2671                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2672                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2673                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2674         };
2675
2676         static const u8 itbCoef8bw[3][14] = {
2677                 {0x00}, /* 20.5MHz XTal */
2678                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2679                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2680                 {0x0}, /* 41MHz XTal   */
2681         };
2682
2683         static const u8 itbCoef7bw[3][14] = {
2684                 {0x00}, /* 20.5MHz XTal */
2685                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2686                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2687                 {0x00}, /* 41MHz XTal   */
2688         };
2689
2690         static const u8 itbCoef6bw[3][14] = {
2691                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2692                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2693                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2694                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2695                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2696                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2697         };
2698
2699         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2700         /* Set SLV-T Bank : 0x10 */
2701         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2702
2703         /*  20.5/41MHz Xtal support is not available
2704          *  on ISDB-T 7MHzBW and 8MHzBW
2705         */
2706         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2707                 dev_err(&priv->i2c->dev,
2708                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2709                         __func__, bandwidth);
2710                 return -EINVAL;
2711         }
2712
2713         switch (bandwidth) {
2714         case 8000000:
2715                 /* TRCG Nominal Rate */
2716                 cxd2841er_write_regs(priv, I2C_SLVT,
2717                                 0x9F, nominalRate8bw[priv->xtal], 5);
2718                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2719                 if (priv->flags & CXD2841ER_ASCOT)
2720                         cxd2841er_write_regs(priv, I2C_SLVT,
2721                                 0xA6, itbCoef8bw[priv->xtal], 14);
2722
2723                 /* IF freq setting */
2724                 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2725                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2726                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2727                 data[1] = (u8)((iffreq >> 8) & 0xff);
2728                 data[2] = (u8)(iffreq & 0xff);
2729                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2730
2731                 /* System bandwidth setting */
2732                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2733
2734                 /* Demod core latency setting */
2735                 data[0] = 0x13;
2736                 data[1] = 0xFC;
2737                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2738
2739                 /* Acquisition optimization setting */
2740                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2741                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2742                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2743                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2744                 break;
2745         case 7000000:
2746                 /* TRCG Nominal Rate */
2747                 cxd2841er_write_regs(priv, I2C_SLVT,
2748                                 0x9F, nominalRate7bw[priv->xtal], 5);
2749                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2750                 if (priv->flags & CXD2841ER_ASCOT)
2751                         cxd2841er_write_regs(priv, I2C_SLVT,
2752                                 0xA6, itbCoef7bw[priv->xtal], 14);
2753
2754                 /* IF freq setting */
2755                 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2756                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2757                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2758                 data[1] = (u8)((iffreq >> 8) & 0xff);
2759                 data[2] = (u8)(iffreq & 0xff);
2760                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2761
2762                 /* System bandwidth setting */
2763                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2764
2765                 /* Demod core latency setting */
2766                 data[0] = 0x1A;
2767                 data[1] = 0xFA;
2768                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2769
2770                 /* Acquisition optimization setting */
2771                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2772                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2773                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2774                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2775                 break;
2776         case 6000000:
2777                 /* TRCG Nominal Rate */
2778                 cxd2841er_write_regs(priv, I2C_SLVT,
2779                                 0x9F, nominalRate6bw[priv->xtal], 5);
2780                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2781                 if (priv->flags & CXD2841ER_ASCOT)
2782                         cxd2841er_write_regs(priv, I2C_SLVT,
2783                                 0xA6, itbCoef6bw[priv->xtal], 14);
2784
2785                 /* IF freq setting */
2786                 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2787                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2788                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2789                 data[1] = (u8)((iffreq >> 8) & 0xff);
2790                 data[2] = (u8)(iffreq & 0xff);
2791                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2792
2793                 /* System bandwidth setting */
2794                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2795
2796                 /* Demod core latency setting */
2797                 if (priv->xtal == SONY_XTAL_24000) {
2798                         data[0] = 0x1F;
2799                         data[1] = 0x79;
2800                 } else {
2801                         data[0] = 0x1A;
2802                         data[1] = 0xE2;
2803                 }
2804                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2805
2806                 /* Acquisition optimization setting */
2807                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2808                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2809                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2810                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2811                 break;
2812         default:
2813                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2814                                 __func__, bandwidth);
2815                 return -EINVAL;
2816         }
2817         return 0;
2818 }
2819
2820 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2821                                                u32 bandwidth)
2822 {
2823         u8 bw7_8mhz_b10_a6[] = {
2824                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2825                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2826         u8 bw6mhz_b10_a6[] = {
2827                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2828                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2829         u8 b10_b6[3];
2830         u32 iffreq, ifhz;
2831
2832         if (bandwidth != 6000000 &&
2833                         bandwidth != 7000000 &&
2834                         bandwidth != 8000000) {
2835                 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2836                                 __func__, bandwidth);
2837                 bandwidth = 8000000;
2838         }
2839
2840         dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2841         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2842         switch (bandwidth) {
2843         case 8000000:
2844         case 7000000:
2845                 if (priv->flags & CXD2841ER_ASCOT)
2846                         cxd2841er_write_regs(
2847                                 priv, I2C_SLVT, 0xa6,
2848                                 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2849                 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2850                 iffreq = cxd2841er_calc_iffreq(ifhz);
2851                 break;
2852         case 6000000:
2853                 if (priv->flags & CXD2841ER_ASCOT)
2854                         cxd2841er_write_regs(
2855                                 priv, I2C_SLVT, 0xa6,
2856                                 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2857                 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2858                 iffreq = cxd2841er_calc_iffreq(ifhz);
2859                 break;
2860         default:
2861                 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2862                         __func__, bandwidth);
2863                 return -EINVAL;
2864         }
2865         /* <IF freq setting> */
2866         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2867         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2868         b10_b6[2] = (u8)(iffreq & 0xff);
2869         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2870         /* Set SLV-T Bank : 0x11 */
2871         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2872         switch (bandwidth) {
2873         case 8000000:
2874         case 7000000:
2875                 cxd2841er_set_reg_bits(
2876                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2877                 break;
2878         case 6000000:
2879                 cxd2841er_set_reg_bits(
2880                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2881                 break;
2882         }
2883         /* Set SLV-T Bank : 0x40 */
2884         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2885         switch (bandwidth) {
2886         case 8000000:
2887                 cxd2841er_set_reg_bits(
2888                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2889                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2890                 break;
2891         case 7000000:
2892                 cxd2841er_set_reg_bits(
2893                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2894                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2895                 break;
2896         case 6000000:
2897                 cxd2841er_set_reg_bits(
2898                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2899                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2900                 break;
2901         }
2902         return 0;
2903 }
2904
2905 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2906                                           u32 bandwidth)
2907 {
2908         u8 data[2] = { 0x09, 0x54 };
2909         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2910
2911         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2912         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2913         /* Set SLV-X Bank : 0x00 */
2914         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2915         /* Set demod mode */
2916         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2917         /* Set SLV-T Bank : 0x00 */
2918         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2919         /* Enable demod clock */
2920         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2921         /* Disable RF level monitor */
2922         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2923         /* Enable ADC clock */
2924         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2925         /* Enable ADC 1 */
2926         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2927         /* Enable ADC 2 & 3 */
2928         if (priv->xtal == SONY_XTAL_41000) {
2929                 data[0] = 0x0A;
2930                 data[1] = 0xD4;
2931         }
2932         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2933         /* Enable ADC 4 */
2934         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2935         /* Set SLV-T Bank : 0x10 */
2936         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2937         /* IFAGC gain settings */
2938         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2939         /* Set SLV-T Bank : 0x11 */
2940         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2941         /* BBAGC TARGET level setting */
2942         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2943         /* Set SLV-T Bank : 0x10 */
2944         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2945         /* ASCOT setting */
2946         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2947                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
2948         /* Set SLV-T Bank : 0x18 */
2949         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2950         /* Pre-RS BER moniter setting */
2951         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2952         /* FEC Auto Recovery setting */
2953         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2954         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2955         /* Set SLV-T Bank : 0x00 */
2956         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2957         /* TSIF setting */
2958         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2959         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2960
2961         if (priv->xtal == SONY_XTAL_24000) {
2962                 /* Set SLV-T Bank : 0x10 */
2963                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2964                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2965                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2966                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2967         }
2968
2969         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2970         /* Set SLV-T Bank : 0x00 */
2971         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2972         /* Disable HiZ Setting 1 */
2973         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2974         /* Disable HiZ Setting 2 */
2975         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2976         priv->state = STATE_ACTIVE_TC;
2977         return 0;
2978 }
2979
2980 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2981                                            u32 bandwidth)
2982 {
2983         u8 data[MAX_WRITE_REGSIZE];
2984
2985         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2986         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2987         /* Set SLV-X Bank : 0x00 */
2988         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2989         /* Set demod mode */
2990         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2991         /* Set SLV-T Bank : 0x00 */
2992         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2993         /* Enable demod clock */
2994         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2995         /* Disable RF level monitor */
2996         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2997         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2998         /* Enable ADC clock */
2999         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3000         /* Enable ADC 1 */
3001         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3002
3003         if (priv->xtal == SONY_XTAL_41000) {
3004                 data[0] = 0x0A;
3005                 data[1] = 0xD4;
3006         } else {
3007                 data[0] = 0x09;
3008                 data[1] = 0x54;
3009         }
3010
3011         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3012         /* Enable ADC 4 */
3013         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3014         /* Set SLV-T Bank : 0x10 */
3015         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3016         /* IFAGC gain settings */
3017         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3018         /* Set SLV-T Bank : 0x11 */
3019         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3020         /* BBAGC TARGET level setting */
3021         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3022         /* Set SLV-T Bank : 0x10 */
3023         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3024         /* ASCOT setting */
3025         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3026                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3027         /* Set SLV-T Bank : 0x20 */
3028         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3029         /* Acquisition optimization setting */
3030         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3031         /* Set SLV-T Bank : 0x2b */
3032         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3033         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
3034         /* Set SLV-T Bank : 0x23 */
3035         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3036         /* L1 Control setting */
3037         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
3038         /* Set SLV-T Bank : 0x00 */
3039         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3040         /* TSIF setting */
3041         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3042         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3043         /* DVB-T2 initial setting */
3044         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3045         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3046         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3047         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3048         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3049         /* Set SLV-T Bank : 0x2a */
3050         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3051         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3052         /* Set SLV-T Bank : 0x2b */
3053         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3054         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3055
3056         /* 24MHz Xtal setting */
3057         if (priv->xtal == SONY_XTAL_24000) {
3058                 /* Set SLV-T Bank : 0x11 */
3059                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3060                 data[0] = 0xEB;
3061                 data[1] = 0x03;
3062                 data[2] = 0x3B;
3063                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3064
3065                 /* Set SLV-T Bank : 0x20 */
3066                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3067                 data[0] = 0x5E;
3068                 data[1] = 0x5E;
3069                 data[2] = 0x47;
3070                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3071
3072                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3073
3074                 data[0] = 0x3F;
3075                 data[1] = 0xFF;
3076                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3077
3078                 /* Set SLV-T Bank : 0x24 */
3079                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3080                 data[0] = 0x0B;
3081                 data[1] = 0x72;
3082                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3083
3084                 data[0] = 0x93;
3085                 data[1] = 0xF3;
3086                 data[2] = 0x00;
3087                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3088
3089                 data[0] = 0x05;
3090                 data[1] = 0xB8;
3091                 data[2] = 0xD8;
3092                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3093
3094                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3095
3096                 /* Set SLV-T Bank : 0x25 */
3097                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3098                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3099
3100                 /* Set SLV-T Bank : 0x27 */
3101                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3102                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3103
3104                 /* Set SLV-T Bank : 0x2B */
3105                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3106                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3107                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3108
3109                 /* Set SLV-T Bank : 0x2D */
3110                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3111                 data[0] = 0x89;
3112                 data[1] = 0x89;
3113                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3114
3115                 /* Set SLV-T Bank : 0x5E */
3116                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3117                 data[0] = 0x24;
3118                 data[1] = 0x95;
3119                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3120         }
3121
3122         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3123
3124         /* Set SLV-T Bank : 0x00 */
3125         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3126         /* Disable HiZ Setting 1 */
3127         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3128         /* Disable HiZ Setting 2 */
3129         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3130         priv->state = STATE_ACTIVE_TC;
3131         return 0;
3132 }
3133
3134 /* ISDB-Tb part */
3135 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3136                 u32 bandwidth)
3137 {
3138         u8 data[2] = { 0x09, 0x54 };
3139         u8 data24m[2] = {0x60, 0x00};
3140         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3141
3142         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3143         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3144         /* Set SLV-X Bank : 0x00 */
3145         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3146         /* Set demod mode */
3147         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3148         /* Set SLV-T Bank : 0x00 */
3149         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3150         /* Enable demod clock */
3151         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3152         /* Enable RF level monitor */
3153         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3154         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3155         /* Enable ADC clock */
3156         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3157         /* Enable ADC 1 */
3158         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3159         /* xtal freq 20.5MHz or 24M */
3160         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3161         /* Enable ADC 4 */
3162         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3163         /* ASCOT setting */
3164         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3165                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3166         /* FEC Auto Recovery setting */
3167         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3168         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3169         /* ISDB-T initial setting */
3170         /* Set SLV-T Bank : 0x00 */
3171         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3172         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3173         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3174         /* Set SLV-T Bank : 0x10 */
3175         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3176         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3177         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3178         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3179         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3180         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3181         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3182         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3183         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3184         /* Set SLV-T Bank : 0x15 */
3185         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3186         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3187         /* Set SLV-T Bank : 0x1E */
3188         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3189         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3190         /* Set SLV-T Bank : 0x63 */
3191         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3192         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3193
3194         /* for xtal 24MHz */
3195         /* Set SLV-T Bank : 0x10 */
3196         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3197         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3198         /* Set SLV-T Bank : 0x60 */
3199         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3200         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3201
3202         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3203         /* Set SLV-T Bank : 0x00 */
3204         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3205         /* Disable HiZ Setting 1 */
3206         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3207         /* Disable HiZ Setting 2 */
3208         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3209         priv->state = STATE_ACTIVE_TC;
3210         return 0;
3211 }
3212
3213 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3214                                           u32 bandwidth)
3215 {
3216         u8 data[2] = { 0x09, 0x54 };
3217
3218         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3219         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3220         /* Set SLV-X Bank : 0x00 */
3221         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3222         /* Set demod mode */
3223         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3224         /* Set SLV-T Bank : 0x00 */
3225         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3226         /* Enable demod clock */
3227         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3228         /* Disable RF level monitor */
3229         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3230         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3231         /* Enable ADC clock */
3232         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3233         /* Enable ADC 1 */
3234         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3235         /* xtal freq 20.5MHz */
3236         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3237         /* Enable ADC 4 */
3238         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3239         /* Set SLV-T Bank : 0x10 */
3240         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3241         /* IFAGC gain settings */
3242         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3243         /* Set SLV-T Bank : 0x11 */
3244         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3245         /* BBAGC TARGET level setting */
3246         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3247         /* Set SLV-T Bank : 0x10 */
3248         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3249         /* ASCOT setting */
3250         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3251                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3252         /* Set SLV-T Bank : 0x40 */
3253         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3254         /* Demod setting */
3255         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3256         /* Set SLV-T Bank : 0x00 */
3257         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3258         /* TSIF setting */
3259         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3260         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3261
3262         cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3263         /* Set SLV-T Bank : 0x00 */
3264         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3265         /* Disable HiZ Setting 1 */
3266         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3267         /* Disable HiZ Setting 2 */
3268         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3269         priv->state = STATE_ACTIVE_TC;
3270         return 0;
3271 }
3272
3273 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3274                                   struct dtv_frontend_properties *p)
3275 {
3276         enum fe_status status = 0;
3277         struct cxd2841er_priv *priv = fe->demodulator_priv;
3278
3279         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3280         if (priv->state == STATE_ACTIVE_S)
3281                 cxd2841er_read_status_s(fe, &status);
3282         else if (priv->state == STATE_ACTIVE_TC)
3283                 cxd2841er_read_status_tc(fe, &status);
3284
3285         if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
3286                 cxd2841er_read_signal_strength(fe);
3287         else
3288                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3289
3290         if (status & FE_HAS_LOCK) {
3291                 cxd2841er_read_snr(fe);
3292                 cxd2841er_read_ucblocks(fe);
3293
3294                 cxd2841er_read_ber(fe);
3295         } else {
3296                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3297                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3298                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3299                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3300         }
3301         return 0;
3302 }
3303
3304 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3305 {
3306         int ret = 0, i, timeout, carr_offset;
3307         enum fe_status status;
3308         struct cxd2841er_priv *priv = fe->demodulator_priv;
3309         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3310         u32 symbol_rate = p->symbol_rate/1000;
3311
3312         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3313                 __func__,
3314                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3315                  p->frequency, symbol_rate, priv->xtal);
3316
3317         if (priv->flags & CXD2841ER_EARLY_TUNE)
3318                 cxd2841er_tuner_set(fe);
3319
3320         switch (priv->state) {
3321         case STATE_SLEEP_S:
3322                 ret = cxd2841er_sleep_s_to_active_s(
3323                         priv, p->delivery_system, symbol_rate);
3324                 break;
3325         case STATE_ACTIVE_S:
3326                 ret = cxd2841er_retune_active(priv, p);
3327                 break;
3328         default:
3329                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3330                         __func__, priv->state);
3331                 ret = -EINVAL;
3332                 goto done;
3333         }
3334         if (ret) {
3335                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3336                 goto done;
3337         }
3338
3339         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3340                 cxd2841er_tuner_set(fe);
3341
3342         cxd2841er_tune_done(priv);
3343         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3344
3345         i = 0;
3346         do {
3347                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3348                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3349                 cxd2841er_read_status_s(fe, &status);
3350                 if (status & FE_HAS_LOCK)
3351                         break;
3352                 i++;
3353         } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL);
3354
3355         if (status & FE_HAS_LOCK) {
3356                 if (cxd2841er_get_carrier_offset_s_s2(
3357                                 priv, &carr_offset)) {
3358                         ret = -EINVAL;
3359                         goto done;
3360                 }
3361                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3362                         __func__, carr_offset);
3363         }
3364 done:
3365         /* Reset stats */
3366         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3367         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3368         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3369         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3370         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3371
3372         return ret;
3373 }
3374
3375 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3376 {
3377         int ret = 0, timeout;
3378         enum fe_status status;
3379         struct cxd2841er_priv *priv = fe->demodulator_priv;
3380         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3381
3382         dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3383                  __func__, p->delivery_system, p->bandwidth_hz);
3384
3385         if (priv->flags & CXD2841ER_EARLY_TUNE)
3386                 cxd2841er_tuner_set(fe);
3387
3388         /* deconfigure/put demod to sleep on delsys switch if active */
3389         if (priv->state == STATE_ACTIVE_TC &&
3390             priv->system != p->delivery_system) {
3391                 dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
3392                          __func__, priv->system, p->delivery_system);
3393                 cxd2841er_sleep_tc(fe);
3394         }
3395
3396         if (p->delivery_system == SYS_DVBT) {
3397                 priv->system = SYS_DVBT;
3398                 switch (priv->state) {
3399                 case STATE_SLEEP_TC:
3400                         ret = cxd2841er_sleep_tc_to_active_t(
3401                                 priv, p->bandwidth_hz);
3402                         break;
3403                 case STATE_ACTIVE_TC:
3404                         ret = cxd2841er_retune_active(priv, p);
3405                         break;
3406                 default:
3407                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3408                                 __func__, priv->state);
3409                         ret = -EINVAL;
3410                 }
3411         } else if (p->delivery_system == SYS_DVBT2) {
3412                 priv->system = SYS_DVBT2;
3413                 cxd2841er_dvbt2_set_plp_config(priv,
3414                         (int)(p->stream_id > 255), p->stream_id);
3415                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3416                 switch (priv->state) {
3417                 case STATE_SLEEP_TC:
3418                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3419                                 p->bandwidth_hz);
3420                         break;
3421                 case STATE_ACTIVE_TC:
3422                         ret = cxd2841er_retune_active(priv, p);
3423                         break;
3424                 default:
3425                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3426                                 __func__, priv->state);
3427                         ret = -EINVAL;
3428                 }
3429         } else if (p->delivery_system == SYS_ISDBT) {
3430                 priv->system = SYS_ISDBT;
3431                 switch (priv->state) {
3432                 case STATE_SLEEP_TC:
3433                         ret = cxd2841er_sleep_tc_to_active_i(
3434                                         priv, p->bandwidth_hz);
3435                         break;
3436                 case STATE_ACTIVE_TC:
3437                         ret = cxd2841er_retune_active(priv, p);
3438                         break;
3439                 default:
3440                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3441                                         __func__, priv->state);
3442                         ret = -EINVAL;
3443                 }
3444         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3445                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3446                 priv->system = SYS_DVBC_ANNEX_A;
3447                 /* correct bandwidth */
3448                 if (p->bandwidth_hz != 6000000 &&
3449                                 p->bandwidth_hz != 7000000 &&
3450                                 p->bandwidth_hz != 8000000) {
3451                         p->bandwidth_hz = 8000000;
3452                         dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3453                                         __func__, p->bandwidth_hz);
3454                 }
3455
3456                 switch (priv->state) {
3457                 case STATE_SLEEP_TC:
3458                         ret = cxd2841er_sleep_tc_to_active_c(
3459                                 priv, p->bandwidth_hz);
3460                         break;
3461                 case STATE_ACTIVE_TC:
3462                         ret = cxd2841er_retune_active(priv, p);
3463                         break;
3464                 default:
3465                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3466                                 __func__, priv->state);
3467                         ret = -EINVAL;
3468                 }
3469         } else {
3470                 dev_dbg(&priv->i2c->dev,
3471                         "%s(): invalid delivery system %d\n",
3472                         __func__, p->delivery_system);
3473                 ret = -EINVAL;
3474         }
3475         if (ret)
3476                 goto done;
3477
3478         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3479                 cxd2841er_tuner_set(fe);
3480
3481         cxd2841er_tune_done(priv);
3482
3483         if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3484                 goto done;
3485
3486         timeout = 2500;
3487         while (timeout > 0) {
3488                 ret = cxd2841er_read_status_tc(fe, &status);
3489                 if (ret)
3490                         goto done;
3491                 if (status & FE_HAS_LOCK)
3492                         break;
3493                 msleep(20);
3494                 timeout -= 20;
3495         }
3496         if (timeout < 0)
3497                 dev_dbg(&priv->i2c->dev,
3498                         "%s(): LOCK wait timeout\n", __func__);
3499 done:
3500         return ret;
3501 }
3502
3503 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3504                             bool re_tune,
3505                             unsigned int mode_flags,
3506                             unsigned int *delay,
3507                             enum fe_status *status)
3508 {
3509         int ret, carrier_offset;
3510         struct cxd2841er_priv *priv = fe->demodulator_priv;
3511         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3512
3513         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3514         if (re_tune) {
3515                 ret = cxd2841er_set_frontend_s(fe);
3516                 if (ret)
3517                         return ret;
3518                 cxd2841er_read_status_s(fe, status);
3519                 if (*status & FE_HAS_LOCK) {
3520                         if (cxd2841er_get_carrier_offset_s_s2(
3521                                         priv, &carrier_offset))
3522                                 return -EINVAL;
3523                         p->frequency += carrier_offset;
3524                         ret = cxd2841er_set_frontend_s(fe);
3525                         if (ret)
3526                                 return ret;
3527                 }
3528         }
3529         *delay = HZ / 5;
3530         return cxd2841er_read_status_s(fe, status);
3531 }
3532
3533 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3534                              bool re_tune,
3535                              unsigned int mode_flags,
3536                              unsigned int *delay,
3537                              enum fe_status *status)
3538 {
3539         int ret, carrier_offset;
3540         struct cxd2841er_priv *priv = fe->demodulator_priv;
3541         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3542
3543         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3544                         re_tune, p->bandwidth_hz);
3545         if (re_tune) {
3546                 ret = cxd2841er_set_frontend_tc(fe);
3547                 if (ret)
3548                         return ret;
3549                 cxd2841er_read_status_tc(fe, status);
3550                 if (*status & FE_HAS_LOCK) {
3551                         switch (priv->system) {
3552                         case SYS_ISDBT:
3553                                 ret = cxd2841er_get_carrier_offset_i(
3554                                                 priv, p->bandwidth_hz,
3555                                                 &carrier_offset);
3556                                 if (ret)
3557                                         return ret;
3558                                 break;
3559                         case SYS_DVBT:
3560                                 ret = cxd2841er_get_carrier_offset_t(
3561                                         priv, p->bandwidth_hz,
3562                                         &carrier_offset);
3563                                 if (ret)
3564                                         return ret;
3565                                 break;
3566                         case SYS_DVBT2:
3567                                 ret = cxd2841er_get_carrier_offset_t2(
3568                                         priv, p->bandwidth_hz,
3569                                         &carrier_offset);
3570                                 if (ret)
3571                                         return ret;
3572                                 break;
3573                         case SYS_DVBC_ANNEX_A:
3574                                 ret = cxd2841er_get_carrier_offset_c(
3575                                         priv, &carrier_offset);
3576                                 if (ret)
3577                                         return ret;
3578                                 break;
3579                         default:
3580                                 dev_dbg(&priv->i2c->dev,
3581                                         "%s(): invalid delivery system %d\n",
3582                                         __func__, priv->system);
3583                                 return -EINVAL;
3584                         }
3585                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3586                                 __func__, carrier_offset);
3587                         p->frequency += carrier_offset;
3588                         ret = cxd2841er_set_frontend_tc(fe);
3589                         if (ret)
3590                                 return ret;
3591                 }
3592         }
3593         *delay = HZ / 5;
3594         return cxd2841er_read_status_tc(fe, status);
3595 }
3596
3597 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3598 {
3599         struct cxd2841er_priv *priv = fe->demodulator_priv;
3600
3601         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3602         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3603         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3604         return 0;
3605 }
3606
3607 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3608 {
3609         struct cxd2841er_priv *priv = fe->demodulator_priv;
3610
3611         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3612
3613         if (priv->state == STATE_ACTIVE_TC) {
3614                 switch (priv->system) {
3615                 case SYS_DVBT:
3616                         cxd2841er_active_t_to_sleep_tc(priv);
3617                         break;
3618                 case SYS_DVBT2:
3619                         cxd2841er_active_t2_to_sleep_tc(priv);
3620                         break;
3621                 case SYS_ISDBT:
3622                         cxd2841er_active_i_to_sleep_tc(priv);
3623                         break;
3624                 case SYS_DVBC_ANNEX_A:
3625                         cxd2841er_active_c_to_sleep_tc(priv);
3626                         break;
3627                 default:
3628                         dev_warn(&priv->i2c->dev,
3629                                 "%s(): unknown delivery system %d\n",
3630                                 __func__, priv->system);
3631                 }
3632         }
3633         if (priv->state != STATE_SLEEP_TC) {
3634                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3635                         __func__, priv->state);
3636                 return -EINVAL;
3637         }
3638         return 0;
3639 }
3640
3641 static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
3642 {
3643         struct cxd2841er_priv *priv = fe->demodulator_priv;
3644
3645         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3646
3647         if (!cxd2841er_sleep_tc(fe))
3648                 cxd2841er_sleep_tc_to_shutdown(priv);
3649         return 0;
3650 }
3651
3652 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3653                                 enum fe_sec_mini_cmd burst)
3654 {
3655         u8 data;
3656         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3657
3658         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3659                 (burst == SEC_MINI_A ? "A" : "B"));
3660         if (priv->state != STATE_SLEEP_S &&
3661                         priv->state != STATE_ACTIVE_S) {
3662                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3663                         __func__, priv->state);
3664                 return -EINVAL;
3665         }
3666         data = (burst == SEC_MINI_A ? 0 : 1);
3667         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3668         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3669         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3670         return 0;
3671 }
3672
3673 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3674                               enum fe_sec_tone_mode tone)
3675 {
3676         u8 data;
3677         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3678
3679         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3680                 (tone == SEC_TONE_ON ? "On" : "Off"));
3681         if (priv->state != STATE_SLEEP_S &&
3682                         priv->state != STATE_ACTIVE_S) {
3683                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3684                         __func__, priv->state);
3685                 return -EINVAL;
3686         }
3687         data = (tone == SEC_TONE_ON ? 1 : 0);
3688         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3689         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3690         return 0;
3691 }
3692
3693 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3694                                      struct dvb_diseqc_master_cmd *cmd)
3695 {
3696         int i;
3697         u8 data[12];
3698         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3699
3700         if (priv->state != STATE_SLEEP_S &&
3701                         priv->state != STATE_ACTIVE_S) {
3702                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3703                         __func__, priv->state);
3704                 return -EINVAL;
3705         }
3706         dev_dbg(&priv->i2c->dev,
3707                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3708         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3709         /* DiDEqC enable */
3710         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3711         /* cmd1 length & data */
3712         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3713         memset(data, 0, sizeof(data));
3714         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3715                 data[i] = cmd->msg[i];
3716         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3717         /* repeat count for cmd1 */
3718         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3719         /* repeat count for cmd2: always 0 */
3720         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3721         /* start transmit */
3722         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3723         /* wait for 1 sec timeout */
3724         for (i = 0; i < 50; i++) {
3725                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3726                 if (!data[0]) {
3727                         dev_dbg(&priv->i2c->dev,
3728                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3729                         return 0;
3730                 }
3731                 msleep(20);
3732         }
3733         dev_dbg(&priv->i2c->dev,
3734                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3735         return -ETIMEDOUT;
3736 }
3737
3738 static void cxd2841er_release(struct dvb_frontend *fe)
3739 {
3740         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3741
3742         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3743         kfree(priv);
3744 }
3745
3746 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3747 {
3748         struct cxd2841er_priv *priv = fe->demodulator_priv;
3749
3750         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3751         cxd2841er_set_reg_bits(
3752                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3753         return 0;
3754 }
3755
3756 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3757 {
3758         struct cxd2841er_priv *priv = fe->demodulator_priv;
3759
3760         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3761         return DVBFE_ALGO_HW;
3762 }
3763
3764 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3765 {
3766         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3767
3768         p->strength.len = 1;
3769         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3770         p->cnr.len = 1;
3771         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3772         p->block_error.len = 1;
3773         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3774         p->post_bit_error.len = 1;
3775         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3776         p->post_bit_count.len = 1;
3777         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3778 }
3779
3780
3781 static int cxd2841er_init_s(struct dvb_frontend *fe)
3782 {
3783         struct cxd2841er_priv *priv = fe->demodulator_priv;
3784
3785         /* sanity. force demod to SHUTDOWN state */
3786         if (priv->state == STATE_SLEEP_S) {
3787                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3788                                 __func__);
3789                 cxd2841er_sleep_s_to_shutdown(priv);
3790         } else if (priv->state == STATE_ACTIVE_S) {
3791                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3792                                 __func__);
3793                 cxd2841er_active_s_to_sleep_s(priv);
3794                 cxd2841er_sleep_s_to_shutdown(priv);
3795         }
3796
3797         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3798         cxd2841er_shutdown_to_sleep_s(priv);
3799         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3800         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3801         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3802
3803         cxd2841er_init_stats(fe);
3804
3805         return 0;
3806 }
3807
3808 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3809 {
3810         struct cxd2841er_priv *priv = fe->demodulator_priv;
3811         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3812
3813         dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3814                         __func__, p->bandwidth_hz);
3815         cxd2841er_shutdown_to_sleep_tc(priv);
3816         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
3817         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3818         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
3819                 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
3820         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3821         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3822         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3823         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3824         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3825                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
3826
3827         /* clear TSCFG bits 3+4 */
3828         if (priv->flags & CXD2841ER_TSBITS)
3829                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3830
3831         cxd2841er_init_stats(fe);
3832
3833         return 0;
3834 }
3835
3836 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3837 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3838
3839 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3840                                              struct i2c_adapter *i2c,
3841                                              u8 system)
3842 {
3843         u8 chip_id = 0;
3844         const char *type;
3845         const char *name;
3846         struct cxd2841er_priv *priv = NULL;
3847
3848         /* allocate memory for the internal state */
3849         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3850         if (!priv)
3851                 return NULL;
3852         priv->i2c = i2c;
3853         priv->config = cfg;
3854         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3855         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3856         priv->xtal = cfg->xtal;
3857         priv->flags = cfg->flags;
3858         priv->frontend.demodulator_priv = priv;
3859         dev_info(&priv->i2c->dev,
3860                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3861                 __func__, priv->i2c,
3862                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3863         chip_id = cxd2841er_chip_id(priv);
3864         switch (chip_id) {
3865         case CXD2837ER_CHIP_ID:
3866                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3867                                 "Sony CXD2837ER DVB-T/T2/C demodulator");
3868                 name = "CXD2837ER";
3869                 type = "C/T/T2";
3870                 break;
3871         case CXD2838ER_CHIP_ID:
3872                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3873                                 "Sony CXD2838ER ISDB-T demodulator");
3874                 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3875                 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3876                 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3877                 name = "CXD2838ER";
3878                 type = "ISDB-T";
3879                 break;
3880         case CXD2841ER_CHIP_ID:
3881                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3882                                 "Sony CXD2841ER DVB-T/T2/C demodulator");
3883                 name = "CXD2841ER";
3884                 type = "T/T2/C/ISDB-T";
3885                 break;
3886         case CXD2843ER_CHIP_ID:
3887                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3888                                 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3889                 name = "CXD2843ER";
3890                 type = "C/C2/T/T2";
3891                 break;
3892         case CXD2854ER_CHIP_ID:
3893                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3894                                 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3895                 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3896                 name = "CXD2854ER";
3897                 type = "C/C2/T/T2/ISDB-T";
3898                 break;
3899         default:
3900                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3901                                 __func__, chip_id);
3902                 priv->frontend.demodulator_priv = NULL;
3903                 kfree(priv);
3904                 return NULL;
3905         }
3906
3907         /* create dvb_frontend */
3908         if (system == SYS_DVBS) {
3909                 memcpy(&priv->frontend.ops,
3910                         &cxd2841er_dvbs_s2_ops,
3911                         sizeof(struct dvb_frontend_ops));
3912                 type = "S/S2";
3913         } else {
3914                 memcpy(&priv->frontend.ops,
3915                         &cxd2841er_t_c_ops,
3916                         sizeof(struct dvb_frontend_ops));
3917         }
3918
3919         dev_info(&priv->i2c->dev,
3920                 "%s(): attaching %s DVB-%s frontend\n",
3921                 __func__, name, type);
3922         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3923                 __func__, chip_id);
3924         return &priv->frontend;
3925 }
3926
3927 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3928                                         struct i2c_adapter *i2c)
3929 {
3930         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3931 }
3932 EXPORT_SYMBOL(cxd2841er_attach_s);
3933
3934 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3935                                         struct i2c_adapter *i2c)
3936 {
3937         return cxd2841er_attach(cfg, i2c, 0);
3938 }
3939 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3940
3941 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3942         .delsys = { SYS_DVBS, SYS_DVBS2 },
3943         .info = {
3944                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3945                 .frequency_min  = 500000,
3946                 .frequency_max  = 2500000,
3947                 .frequency_stepsize     = 0,
3948                 .symbol_rate_min = 1000000,
3949                 .symbol_rate_max = 45000000,
3950                 .symbol_rate_tolerance = 500,
3951                 .caps = FE_CAN_INVERSION_AUTO |
3952                         FE_CAN_FEC_AUTO |
3953                         FE_CAN_QPSK,
3954         },
3955         .init = cxd2841er_init_s,
3956         .sleep = cxd2841er_sleep_s,
3957         .release = cxd2841er_release,
3958         .set_frontend = cxd2841er_set_frontend_s,
3959         .get_frontend = cxd2841er_get_frontend,
3960         .read_status = cxd2841er_read_status_s,
3961         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3962         .get_frontend_algo = cxd2841er_get_algo,
3963         .set_tone = cxd2841er_set_tone,
3964         .diseqc_send_burst = cxd2841er_send_burst,
3965         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3966         .tune = cxd2841er_tune_s
3967 };
3968
3969 static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3970         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3971         .info = {
3972                 .name   = "", /* will set in attach function */
3973                 .caps = FE_CAN_FEC_1_2 |
3974                         FE_CAN_FEC_2_3 |
3975                         FE_CAN_FEC_3_4 |
3976                         FE_CAN_FEC_5_6 |
3977                         FE_CAN_FEC_7_8 |
3978                         FE_CAN_FEC_AUTO |
3979                         FE_CAN_QPSK |
3980                         FE_CAN_QAM_16 |
3981                         FE_CAN_QAM_32 |
3982                         FE_CAN_QAM_64 |
3983                         FE_CAN_QAM_128 |
3984                         FE_CAN_QAM_256 |
3985                         FE_CAN_QAM_AUTO |
3986                         FE_CAN_TRANSMISSION_MODE_AUTO |
3987                         FE_CAN_GUARD_INTERVAL_AUTO |
3988                         FE_CAN_HIERARCHY_AUTO |
3989                         FE_CAN_MUTE_TS |
3990                         FE_CAN_2G_MODULATION,
3991                 .frequency_min = 42000000,
3992                 .frequency_max = 1002000000,
3993                 .symbol_rate_min = 870000,
3994                 .symbol_rate_max = 11700000
3995         },
3996         .init = cxd2841er_init_tc,
3997         .sleep = cxd2841er_shutdown_tc,
3998         .release = cxd2841er_release,
3999         .set_frontend = cxd2841er_set_frontend_tc,
4000         .get_frontend = cxd2841er_get_frontend,
4001         .read_status = cxd2841er_read_status_tc,
4002         .tune = cxd2841er_tune_tc,
4003         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
4004         .get_frontend_algo = cxd2841er_get_algo
4005 };
4006
4007 MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
4008 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
4009 MODULE_LICENSE("GPL");