drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony digital demodulator driver for
   5  *      CXD2841ER - DVB-S/S2/T/T2/C/C2
   6  *      CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   7  *
   8  * Copyright 2012 Sony Corporation
   9  * Copyright (C) 2014 NetUP Inc.
  10  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  11  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22   */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/bitops.h>
  29 #include <linux/math64.h>
  30 #include <linux/log2.h>
  31 #include <linux/dynamic_debug.h>
  32
  33 #include "dvb_math.h"
  34 #include "dvb_frontend.h"
  35 #include "cxd2841er.h"
  36 #include "cxd2841er_priv.h"
  37
  38 #define MAX_WRITE_REGSIZE       16
  39 #define LOG2_E_100X 144
  40
  41 /* DVB-C constellation */
  42 enum sony_dvbc_constellation_t {
  43         SONY_DVBC_CONSTELLATION_16QAM,
  44         SONY_DVBC_CONSTELLATION_32QAM,
  45         SONY_DVBC_CONSTELLATION_64QAM,
  46         SONY_DVBC_CONSTELLATION_128QAM,
  47         SONY_DVBC_CONSTELLATION_256QAM
  48 };
  49
  50 enum cxd2841er_state {
  51         STATE_SHUTDOWN = 0,
  52         STATE_SLEEP_S,
  53         STATE_ACTIVE_S,
  54         STATE_SLEEP_TC,
  55         STATE_ACTIVE_TC
  56 };
  57
  58 struct cxd2841er_priv {
  59         struct dvb_frontend             frontend;
  60         struct i2c_adapter              *i2c;
  61         u8                              i2c_addr_slvx;
  62         u8                              i2c_addr_slvt;
  63         const struct cxd2841er_config   *config;
  64         enum cxd2841er_state            state;
  65         u8                              system;
  66         enum cxd2841er_xtal             xtal;
  67         enum fe_caps caps;
  68 };
  69
  70 static const struct cxd2841er_cnr_data s_cn_data[] = {
  71         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  72         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  73         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  74         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  75         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  76         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  77         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  78         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  79         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  80         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  81         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  82         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  83         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  84         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  85         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  86         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  87         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  88         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  89         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  90         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  91         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  92         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  93         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  94         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  95         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  96         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  97         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  98         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  99         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
 100         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
 101         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
 102         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
 103         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
 104         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
 105         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
 106         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
 107         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
 108         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
 109         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
 110         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 111         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 112         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 113         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 114         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 115         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 116         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 117         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 118         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 119         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 120         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 121         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 122         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 123         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 124         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 125         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 126         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 127         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 128         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 129         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 130         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 131         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 132         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 133         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 134         { 0x0015, 19900 }, { 0x0014, 20000 },
 135 };
 136
 137 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 138         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 139         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 140         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 141         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 142         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 143         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 144         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 145         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 146         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 147         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 148         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 149         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 150         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 151         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 152         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 153         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 154         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 155         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 156         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 157         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 158         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 159         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 160         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 161         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 162         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 163         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 164         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 165         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 166         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 167         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 168         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 169         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 170         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 171         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 172         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 173         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 174         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 175         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 176         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 177         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 178         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 179         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 180         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 181         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 182         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 183         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 184         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 185         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 186         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 187         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 188         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 189         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 190         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 191         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 192         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 193         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 194         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 195         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 196         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 197         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 198         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 199         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 200         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 201         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 202 };
 203
 204 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 205 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
 206                 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
 207                 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 208
 209 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 210                                 u8 addr, u8 reg, u8 write,
 211                                 const u8 *data, u32 len)
 212 {
 213         dev_dbg(&priv->i2c->dev,
 214                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
 215                 (write == 0 ? "read" : "write"), addr, reg, len);
 216         print_hex_dump_bytes("cxd2841er: I2C data: ",
 217                 DUMP_PREFIX_OFFSET, data, len);
 218 }
 219
 220 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 221                                 u8 addr, u8 reg, const u8 *data, u32 len)
 222 {
 223         int ret;
 224         u8 buf[MAX_WRITE_REGSIZE + 1];
 225         u8 i2c_addr = (addr == I2C_SLVX ?
 226                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 227         struct i2c_msg msg[1] = {
 228                 {
 229                         .addr = i2c_addr,
 230                         .flags = 0,
 231                         .len = len + 1,
 232                         .buf = buf,
 233                 }
 234         };
 235
 236         if (len + 1 >= sizeof(buf)) {
 237                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 238                          reg, len + 1);
 239                 return -E2BIG;
 240         }
 241
 242         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 243         buf[0] = reg;
 244         memcpy(&buf[1], data, len);
 245
 246         ret = i2c_transfer(priv->i2c, msg, 1);
 247         if (ret >= 0 && ret != 1)
 248                 ret = -EIO;
 249         if (ret < 0) {
 250                 dev_warn(&priv->i2c->dev,
 251                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 252                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 253                 return ret;
 254         }
 255         return 0;
 256 }
 257
 258 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 259                                u8 addr, u8 reg, u8 val)
 260 {
 261         return cxd2841er_write_regs(priv, addr, reg, &val, 1);
 262 }
 263
 264 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 265                                u8 addr, u8 reg, u8 *val, u32 len)
 266 {
 267         int ret;
 268         u8 i2c_addr = (addr == I2C_SLVX ?
 269                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 270         struct i2c_msg msg[2] = {
 271                 {
 272                         .addr = i2c_addr,
 273                         .flags = 0,
 274                         .len = 1,
 275                         .buf = &reg,
 276                 }, {
 277                         .addr = i2c_addr,
 278                         .flags = I2C_M_RD,
 279                         .len = len,
 280                         .buf = val,
 281                 }
 282         };
 283
 284         ret = i2c_transfer(priv->i2c, &msg[0], 1);
 285         if (ret >= 0 && ret != 1)
 286                 ret = -EIO;
 287         if (ret < 0) {
 288                 dev_warn(&priv->i2c->dev,
 289                         "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
 290                         KBUILD_MODNAME, ret, i2c_addr, reg);
 291                 return ret;
 292         }
 293         ret = i2c_transfer(priv->i2c, &msg[1], 1);
 294         if (ret >= 0 && ret != 1)
 295                 ret = -EIO;
 296         if (ret < 0) {
 297                 dev_warn(&priv->i2c->dev,
 298                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 299                         KBUILD_MODNAME, ret, i2c_addr, reg);
 300                 return ret;
 301         }
 302         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 303         return 0;
 304 }
 305
 306 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 307                               u8 addr, u8 reg, u8 *val)
 308 {
 309         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 310 }
 311
 312 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 313                                   u8 addr, u8 reg, u8 data, u8 mask)
 314 {
 315         int res;
 316         u8 rdata;
 317
 318         if (mask != 0xff) {
 319                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 320                 if (res)
 321                         return res;
 322                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 323         }
 324         return cxd2841er_write_reg(priv, addr, reg, data);
 325 }
 326
 327 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 328                                            u32 symbol_rate)
 329 {
 330         u32 reg_value = 0;
 331         u8 data[3] = {0, 0, 0};
 332
 333         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 334         /*
 335          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 336          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 337          *          = ((symbolRateKSps * 16384) + 500) / 1000
 338          */
 339         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 340         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 341                 dev_err(&priv->i2c->dev,
 342                         "%s(): reg_value is out of range\n", __func__);
 343                 return -EINVAL;
 344         }
 345         data[0] = (u8)((reg_value >> 16) & 0x0F);
 346         data[1] = (u8)((reg_value >>  8) & 0xFF);
 347         data[2] = (u8)(reg_value & 0xFF);
 348         /* Set SLV-T Bank : 0xAE */
 349         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 350         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 351         return 0;
 352 }
 353
 354 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 355                                         u8 system);
 356
 357 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 358                                          u8 system, u32 symbol_rate)
 359 {
 360         int ret;
 361         u8 data[4] = { 0, 0, 0, 0 };
 362
 363         if (priv->state != STATE_SLEEP_S) {
 364                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 365                         __func__, (int)priv->state);
 366                 return -EINVAL;
 367         }
 368         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 369         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 370         /* Set demod mode */
 371         if (system == SYS_DVBS) {
 372                 data[0] = 0x0A;
 373         } else if (system == SYS_DVBS2) {
 374                 data[0] = 0x0B;
 375         } else {
 376                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 377                         __func__, system);
 378                 return -EINVAL;
 379         }
 380         /* Set SLV-X Bank : 0x00 */
 381         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 382         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 383         /* DVB-S/S2 */
 384         data[0] = 0x00;
 385         /* Set SLV-T Bank : 0x00 */
 386         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 387         /* Enable S/S2 auto detection 1 */
 388         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 389         /* Set SLV-T Bank : 0xAE */
 390         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 391         /* Enable S/S2 auto detection 2 */
 392         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 393         /* Set SLV-T Bank : 0x00 */
 394         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 395         /* Enable demod clock */
 396         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 397         /* Enable ADC clock */
 398         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 399         /* Enable ADC 1 */
 400         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 401         /* Enable ADC 2 */
 402         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 403         /* Set SLV-X Bank : 0x00 */
 404         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 405         /* Enable ADC 3 */
 406         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 407         /* Set SLV-T Bank : 0xA3 */
 408         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 409         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 410         data[0] = 0x07;
 411         data[1] = 0x3B;
 412         data[2] = 0x08;
 413         data[3] = 0xC5;
 414         /* Set SLV-T Bank : 0xAB */
 415         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 416         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 417         data[0] = 0x05;
 418         data[1] = 0x80;
 419         data[2] = 0x0A;
 420         data[3] = 0x80;
 421         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 422         data[0] = 0x0C;
 423         data[1] = 0xCC;
 424         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 425         /* Set demod parameter */
 426         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 427         if (ret != 0)
 428                 return ret;
 429         /* Set SLV-T Bank : 0x00 */
 430         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 431         /* disable Hi-Z setting 1 */
 432         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 433         /* disable Hi-Z setting 2 */
 434         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 435         priv->state = STATE_ACTIVE_S;
 436         return 0;
 437 }
 438
 439 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 440                                                u32 bandwidth);
 441
 442 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 443                                                 u32 bandwidth);
 444
 445 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 446                                                u32 bandwidth);
 447
 448 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 449                 u32 bandwidth);
 450
 451 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 452
 453 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 454
 455 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 456
 457 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 458                                    struct dtv_frontend_properties *p)
 459 {
 460         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 461         if (priv->state != STATE_ACTIVE_S &&
 462                         priv->state != STATE_ACTIVE_TC) {
 463                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 464                         __func__, priv->state);
 465                 return -EINVAL;
 466         }
 467         /* Set SLV-T Bank : 0x00 */
 468         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 469         /* disable TS output */
 470         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 471         if (priv->state == STATE_ACTIVE_S)
 472                 return cxd2841er_dvbs2_set_symbol_rate(
 473                                 priv, p->symbol_rate / 1000);
 474         else if (priv->state == STATE_ACTIVE_TC) {
 475                 switch (priv->system) {
 476                 case SYS_DVBT:
 477                         return cxd2841er_sleep_tc_to_active_t_band(
 478                                         priv, p->bandwidth_hz);
 479                 case SYS_DVBT2:
 480                         return cxd2841er_sleep_tc_to_active_t2_band(
 481                                         priv, p->bandwidth_hz);
 482                 case SYS_DVBC_ANNEX_A:
 483                         return cxd2841er_sleep_tc_to_active_c_band(
 484                                         priv, p->bandwidth_hz);
 485                 case SYS_ISDBT:
 486                         cxd2841er_active_i_to_sleep_tc(priv);
 487                         cxd2841er_sleep_tc_to_shutdown(priv);
 488                         cxd2841er_shutdown_to_sleep_tc(priv);
 489                         return cxd2841er_sleep_tc_to_active_i(
 490                                         priv, p->bandwidth_hz);
 491                 }
 492         }
 493         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 494                 __func__, priv->system);
 495         return -EINVAL;
 496 }
 497
 498 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 499 {
 500         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 501         if (priv->state != STATE_ACTIVE_S) {
 502                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 503                         __func__, priv->state);
 504                 return -EINVAL;
 505         }
 506         /* Set SLV-T Bank : 0x00 */
 507         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 508         /* disable TS output */
 509         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 510         /* enable Hi-Z setting 1 */
 511         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 512         /* enable Hi-Z setting 2 */
 513         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 514         /* Set SLV-X Bank : 0x00 */
 515         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 516         /* disable ADC 1 */
 517         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 518         /* Set SLV-T Bank : 0x00 */
 519         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 520         /* disable ADC clock */
 521         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 522         /* disable ADC 2 */
 523         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 524         /* disable ADC 3 */
 525         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 526         /* SADC Bias ON */
 527         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 528         /* disable demod clock */
 529         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 530         /* Set SLV-T Bank : 0xAE */
 531         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 532         /* disable S/S2 auto detection1 */
 533         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 534         /* Set SLV-T Bank : 0x00 */
 535         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 536         /* disable S/S2 auto detection2 */
 537         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 538         priv->state = STATE_SLEEP_S;
 539         return 0;
 540 }
 541
 542 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 543 {
 544         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 545         if (priv->state != STATE_SLEEP_S) {
 546                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 547                         __func__, priv->state);
 548                 return -EINVAL;
 549         }
 550         /* Set SLV-T Bank : 0x00 */
 551         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 552         /* Disable DSQOUT */
 553         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 554         /* Disable DSQIN */
 555         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 556         /* Set SLV-X Bank : 0x00 */
 557         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 558         /* Disable oscillator */
 559         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 560         /* Set demod mode */
 561         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 562         priv->state = STATE_SHUTDOWN;
 563         return 0;
 564 }
 565
 566 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 567 {
 568         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 569         if (priv->state != STATE_SLEEP_TC) {
 570                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 571                         __func__, priv->state);
 572                 return -EINVAL;
 573         }
 574         /* Set SLV-X Bank : 0x00 */
 575         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 576         /* Disable oscillator */
 577         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 578         /* Set demod mode */
 579         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 580         priv->state = STATE_SHUTDOWN;
 581         return 0;
 582 }
 583
 584 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 585 {
 586         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 587         if (priv->state != STATE_ACTIVE_TC) {
 588                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 589                         __func__, priv->state);
 590                 return -EINVAL;
 591         }
 592         /* Set SLV-T Bank : 0x00 */
 593         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 594         /* disable TS output */
 595         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 596         /* enable Hi-Z setting 1 */
 597         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 598         /* enable Hi-Z setting 2 */
 599         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 600         /* Set SLV-X Bank : 0x00 */
 601         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 602         /* disable ADC 1 */
 603         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 604         /* Set SLV-T Bank : 0x00 */
 605         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 606         /* Disable ADC 2 */
 607         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 608         /* Disable ADC 3 */
 609         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 610         /* Disable ADC clock */
 611         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 612         /* Disable RF level monitor */
 613         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 614         /* Disable demod clock */
 615         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 616         priv->state = STATE_SLEEP_TC;
 617         return 0;
 618 }
 619
 620 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 621 {
 622         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 623         if (priv->state != STATE_ACTIVE_TC) {
 624                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 625                         __func__, priv->state);
 626                 return -EINVAL;
 627         }
 628         /* Set SLV-T Bank : 0x00 */
 629         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 630         /* disable TS output */
 631         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 632         /* enable Hi-Z setting 1 */
 633         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 634         /* enable Hi-Z setting 2 */
 635         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 636         /* Cancel DVB-T2 setting */
 637         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 638         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 639         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 640         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 641         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 642         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 643         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 644         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 645         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 646         /* Set SLV-X Bank : 0x00 */
 647         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 648         /* disable ADC 1 */
 649         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 650         /* Set SLV-T Bank : 0x00 */
 651         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 652         /* Disable ADC 2 */
 653         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 654         /* Disable ADC 3 */
 655         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 656         /* Disable ADC clock */
 657         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 658         /* Disable RF level monitor */
 659         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 660         /* Disable demod clock */
 661         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 662         priv->state = STATE_SLEEP_TC;
 663         return 0;
 664 }
 665
 666 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 667 {
 668         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 669         if (priv->state != STATE_ACTIVE_TC) {
 670                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 671                         __func__, priv->state);
 672                 return -EINVAL;
 673         }
 674         /* Set SLV-T Bank : 0x00 */
 675         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 676         /* disable TS output */
 677         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 678         /* enable Hi-Z setting 1 */
 679         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 680         /* enable Hi-Z setting 2 */
 681         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 682         /* Cancel DVB-C setting */
 683         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 684         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 685         /* Set SLV-X Bank : 0x00 */
 686         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 687         /* disable ADC 1 */
 688         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 689         /* Set SLV-T Bank : 0x00 */
 690         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 691         /* Disable ADC 2 */
 692         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 693         /* Disable ADC 3 */
 694         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 695         /* Disable ADC clock */
 696         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 697         /* Disable RF level monitor */
 698         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 699         /* Disable demod clock */
 700         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 701         priv->state = STATE_SLEEP_TC;
 702         return 0;
 703 }
 704
 705 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 706 {
 707         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 708         if (priv->state != STATE_ACTIVE_TC) {
 709                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 710                                 __func__, priv->state);
 711                 return -EINVAL;
 712         }
 713         /* Set SLV-T Bank : 0x00 */
 714         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 715         /* disable TS output */
 716         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 717         /* enable Hi-Z setting 1 */
 718         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 719         /* enable Hi-Z setting 2 */
 720         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 721
 722         /* TODO: Cancel demod parameter */
 723
 724         /* Set SLV-X Bank : 0x00 */
 725         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 726         /* disable ADC 1 */
 727         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 728         /* Set SLV-T Bank : 0x00 */
 729         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 730         /* Disable ADC 2 */
 731         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 732         /* Disable ADC 3 */
 733         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 734         /* Disable ADC clock */
 735         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 736         /* Disable RF level monitor */
 737         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 738         /* Disable demod clock */
 739         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 740         priv->state = STATE_SLEEP_TC;
 741         return 0;
 742 }
 743
 744 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 745 {
 746         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 747         if (priv->state != STATE_SHUTDOWN) {
 748                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 749                         __func__, priv->state);
 750                 return -EINVAL;
 751         }
 752         /* Set SLV-X Bank : 0x00 */
 753         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 754         /* Clear all demodulator registers */
 755         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 756         usleep_range(3000, 5000);
 757         /* Set SLV-X Bank : 0x00 */
 758         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 759         /* Set demod SW reset */
 760         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 761
 762         switch (priv->xtal) {
 763         case SONY_XTAL_20500:
 764                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 765                 break;
 766         case SONY_XTAL_24000:
 767                 /* Select demod frequency */
 768                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 769                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 770                 break;
 771         case SONY_XTAL_41000:
 772                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 773                 break;
 774         default:
 775                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 776                                 __func__, priv->xtal);
 777                 return -EINVAL;
 778         }
 779
 780         /* Set demod mode */
 781         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 782         /* Clear demod SW reset */
 783         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 784         usleep_range(1000, 2000);
 785         /* Set SLV-T Bank : 0x00 */
 786         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 787         /* enable DSQOUT */
 788         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 789         /* enable DSQIN */
 790         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 791         /* TADC Bias On */
 792         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 793         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 794         /* SADC Bias On */
 795         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 796         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 797         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 798         priv->state = STATE_SLEEP_S;
 799         return 0;
 800 }
 801
 802 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 803 {
 804         u8 data = 0;
 805
 806         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 807         if (priv->state != STATE_SHUTDOWN) {
 808                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 809                         __func__, priv->state);
 810                 return -EINVAL;
 811         }
 812         /* Set SLV-X Bank : 0x00 */
 813         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 814         /* Clear all demodulator registers */
 815         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 816         usleep_range(3000, 5000);
 817         /* Set SLV-X Bank : 0x00 */
 818         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 819         /* Set demod SW reset */
 820         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 821   /* Select ADC clock mode */
 822         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 823
 824         switch (priv->xtal) {
 825         case SONY_XTAL_20500:
 826                 data = 0x0;
 827                 break;
 828         case SONY_XTAL_24000:
 829                 /* Select demod frequency */
 830                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 831                 data = 0x3;
 832                 break;
 833         case SONY_XTAL_41000:
 834                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 835                 data = 0x1;
 836                 break;
 837         }
 838         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 839         /* Clear demod SW reset */
 840         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 841         usleep_range(1000, 2000);
 842         /* Set SLV-T Bank : 0x00 */
 843         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 844         /* TADC Bias On */
 845         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 846         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 847         /* SADC Bias On */
 848         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 849         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 850         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 851         priv->state = STATE_SLEEP_TC;
 852         return 0;
 853 }
 854
 855 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 856 {
 857         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 858         /* Set SLV-T Bank : 0x00 */
 859         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 860         /* SW Reset */
 861         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 862         /* Enable TS output */
 863         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 864         return 0;
 865 }
 866
 867 /* Set TS parallel mode */
 868 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 869                                         u8 system)
 870 {
 871         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 872
 873         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 874         /* Set SLV-T Bank : 0x00 */
 875         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 876         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 877         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 878         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 879         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 880                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 881
 882         /*
 883          * slave    Bank    Addr    Bit    default    Name
 884          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 885          */
 886         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 887         /*
 888          * Disable TS IF Clock
 889          * slave    Bank    Addr    Bit    default    Name
 890          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 891          */
 892         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 893         /*
 894          * slave    Bank    Addr    Bit    default    Name
 895          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 896          */
 897         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
 898         /*
 899          * Enable TS IF Clock
 900          * slave    Bank    Addr    Bit    default    Name
 901          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 902          */
 903         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 904
 905         if (system == SYS_DVBT) {
 906                 /* Enable parity period for DVB-T */
 907                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 908                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 909         } else if (system == SYS_DVBC_ANNEX_A) {
 910                 /* Enable parity period for DVB-C */
 911                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 912                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 913         }
 914 }
 915
 916 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 917 {
 918         u8 chip_id = 0;
 919
 920         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 921         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 922                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 923         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 924                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 925
 926         return chip_id;
 927 }
 928
 929 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 930                                    enum fe_status *status)
 931 {
 932         u8 reg = 0;
 933         struct cxd2841er_priv *priv = fe->demodulator_priv;
 934
 935         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 936         *status = 0;
 937         if (priv->state != STATE_ACTIVE_S) {
 938                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 939                         __func__, priv->state);
 940                 return -EINVAL;
 941         }
 942         /* Set SLV-T Bank : 0xA0 */
 943         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 944         /*
 945          *  slave     Bank      Addr      Bit      Signal name
 946          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 947          */
 948         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 949         if (reg & 0x04) {
 950                 *status = FE_HAS_SIGNAL
 951                         | FE_HAS_CARRIER
 952                         | FE_HAS_VITERBI
 953                         | FE_HAS_SYNC
 954                         | FE_HAS_LOCK;
 955         }
 956         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
 957         return 0;
 958 }
 959
 960 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
 961                                       u8 *sync, u8 *tslock, u8 *unlock)
 962 {
 963         u8 data = 0;
 964
 965         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 966         if (priv->state != STATE_ACTIVE_TC)
 967                 return -EINVAL;
 968         if (priv->system == SYS_DVBT) {
 969                 /* Set SLV-T Bank : 0x10 */
 970                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 971         } else {
 972                 /* Set SLV-T Bank : 0x20 */
 973                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
 974         }
 975         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 976         if ((data & 0x07) == 0x07) {
 977                 dev_dbg(&priv->i2c->dev,
 978                         "%s(): invalid hardware state detected\n", __func__);
 979                 *sync = 0;
 980                 *tslock = 0;
 981                 *unlock = 0;
 982         } else {
 983                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
 984                 *tslock = ((data & 0x20) ? 1 : 0);
 985                 *unlock = ((data & 0x10) ? 1 : 0);
 986         }
 987         return 0;
 988 }
 989
 990 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
 991 {
 992         u8 data;
 993
 994         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 995         if (priv->state != STATE_ACTIVE_TC)
 996                 return -EINVAL;
 997         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 998         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
 999         if ((data & 0x01) == 0) {
1000                 *tslock = 0;
1001         } else {
1002                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1003                 *tslock = ((data & 0x20) ? 1 : 0);
1004         }
1005         return 0;
1006 }
1007
1008 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1009                 u8 *sync, u8 *tslock, u8 *unlock)
1010 {
1011         u8 data = 0;
1012
1013         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1014         if (priv->state != STATE_ACTIVE_TC)
1015                 return -EINVAL;
1016         /* Set SLV-T Bank : 0x60 */
1017         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1018         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1019         dev_dbg(&priv->i2c->dev,
1020                         "%s(): lock=0x%x\n", __func__, data);
1021         *sync = ((data & 0x02) ? 1 : 0);
1022         *tslock = ((data & 0x01) ? 1 : 0);
1023         *unlock = ((data & 0x10) ? 1 : 0);
1024         return 0;
1025 }
1026
1027 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1028                                     enum fe_status *status)
1029 {
1030         int ret = 0;
1031         u8 sync = 0;
1032         u8 tslock = 0;
1033         u8 unlock = 0;
1034         struct cxd2841er_priv *priv = fe->demodulator_priv;
1035
1036         *status = 0;
1037         if (priv->state == STATE_ACTIVE_TC) {
1038                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1039                         ret = cxd2841er_read_status_t_t2(
1040                                 priv, &sync, &tslock, &unlock);
1041                         if (ret)
1042                                 goto done;
1043                         if (unlock)
1044                                 goto done;
1045                         if (sync)
1046                                 *status = FE_HAS_SIGNAL |
1047                                         FE_HAS_CARRIER |
1048                                         FE_HAS_VITERBI |
1049                                         FE_HAS_SYNC;
1050                         if (tslock)
1051                                 *status |= FE_HAS_LOCK;
1052                 } else if (priv->system == SYS_ISDBT) {
1053                         ret = cxd2841er_read_status_i(
1054                                         priv, &sync, &tslock, &unlock);
1055                         if (ret)
1056                                 goto done;
1057                         if (unlock)
1058                                 goto done;
1059                         if (sync)
1060                                 *status = FE_HAS_SIGNAL |
1061                                         FE_HAS_CARRIER |
1062                                         FE_HAS_VITERBI |
1063                                         FE_HAS_SYNC;
1064                         if (tslock)
1065                                 *status |= FE_HAS_LOCK;
1066                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1067                         ret = cxd2841er_read_status_c(priv, &tslock);
1068                         if (ret)
1069                                 goto done;
1070                         if (tslock)
1071                                 *status = FE_HAS_SIGNAL |
1072                                         FE_HAS_CARRIER |
1073                                         FE_HAS_VITERBI |
1074                                         FE_HAS_SYNC |
1075                                         FE_HAS_LOCK;
1076                 }
1077         }
1078 done:
1079         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1080         return ret;
1081 }
1082
1083 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1084                                              int *offset)
1085 {
1086         u8 data[3];
1087         u8 is_hs_mode;
1088         s32 cfrl_ctrlval;
1089         s32 temp_div, temp_q, temp_r;
1090
1091         if (priv->state != STATE_ACTIVE_S) {
1092                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1093                         __func__, priv->state);
1094                 return -EINVAL;
1095         }
1096         /*
1097          * Get High Sampling Rate mode
1098          *  slave     Bank      Addr      Bit      Signal name
1099          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1100          */
1101         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1102         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1103         if (data[0] & 0x01) {
1104                 /*
1105                  *  slave     Bank      Addr      Bit      Signal name
1106                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1107                  */
1108                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1109                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1110         } else {
1111                 dev_dbg(&priv->i2c->dev,
1112                         "%s(): unable to detect sampling rate mode\n",
1113                         __func__);
1114                 return -EINVAL;
1115         }
1116         /*
1117          *  slave     Bank      Addr      Bit      Signal name
1118          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1119          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1120          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1121          */
1122         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1123         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1124                                 (((u32)data[1] & 0xFF) <<  8) |
1125                                 ((u32)data[2] & 0xFF), 20);
1126         temp_div = (is_hs_mode ? 1048576 : 1572864);
1127         if (cfrl_ctrlval > 0) {
1128                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1129                         temp_div, &temp_r);
1130         } else {
1131                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1132                         temp_div, &temp_r);
1133         }
1134         if (temp_r >= temp_div / 2)
1135                 temp_q++;
1136         if (cfrl_ctrlval > 0)
1137                 temp_q *= -1;
1138         *offset = temp_q;
1139         return 0;
1140 }
1141
1142 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1143                                            u32 bandwidth, int *offset)
1144 {
1145         u8 data[4];
1146
1147         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1148         if (priv->state != STATE_ACTIVE_TC) {
1149                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1150                         __func__, priv->state);
1151                 return -EINVAL;
1152         }
1153         if (priv->system != SYS_ISDBT) {
1154                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1155                         __func__, priv->system);
1156                 return -EINVAL;
1157         }
1158         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1159         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1160         *offset = -1 * sign_extend32(
1161                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1162                 ((u32)data[2] << 8) | (u32)data[3], 29);
1163
1164         switch (bandwidth) {
1165         case 6000000:
1166                 *offset = -1 * ((*offset) * 8/264);
1167                 break;
1168         case 7000000:
1169                 *offset = -1 * ((*offset) * 8/231);
1170                 break;
1171         case 8000000:
1172                 *offset = -1 * ((*offset) * 8/198);
1173                 break;
1174         default:
1175                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1176                                 __func__, bandwidth);
1177                 return -EINVAL;
1178         }
1179
1180         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1181                         __func__, bandwidth, *offset);
1182
1183         return 0;
1184 }
1185
1186 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1187                                            u32 bandwidth, int *offset)
1188 {
1189         u8 data[4];
1190
1191         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1192         if (priv->state != STATE_ACTIVE_TC) {
1193                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1194                         __func__, priv->state);
1195                 return -EINVAL;
1196         }
1197         if (priv->system != SYS_DVBT) {
1198                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1199                         __func__, priv->system);
1200                 return -EINVAL;
1201         }
1202         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1203         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1204         *offset = -1 * sign_extend32(
1205                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1206                 ((u32)data[2] << 8) | (u32)data[3], 29);
1207         *offset *= (bandwidth / 1000000);
1208         *offset /= 235;
1209         return 0;
1210 }
1211
1212 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1213                                            u32 bandwidth, int *offset)
1214 {
1215         u8 data[4];
1216
1217         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1218         if (priv->state != STATE_ACTIVE_TC) {
1219                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1220                         __func__, priv->state);
1221                 return -EINVAL;
1222         }
1223         if (priv->system != SYS_DVBT2) {
1224                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1225                         __func__, priv->system);
1226                 return -EINVAL;
1227         }
1228         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1229         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1230         *offset = -1 * sign_extend32(
1231                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1232                 ((u32)data[2] << 8) | (u32)data[3], 27);
1233         switch (bandwidth) {
1234         case 1712000:
1235                 *offset /= 582;
1236                 break;
1237         case 5000000:
1238         case 6000000:
1239         case 7000000:
1240         case 8000000:
1241                 *offset *= (bandwidth / 1000000);
1242                 *offset /= 940;
1243                 break;
1244         default:
1245                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1246                         __func__, bandwidth);
1247                 return -EINVAL;
1248         }
1249         return 0;
1250 }
1251
1252 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1253                                           int *offset)
1254 {
1255         u8 data[2];
1256
1257         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1258         if (priv->state != STATE_ACTIVE_TC) {
1259                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1260                         __func__, priv->state);
1261                 return -EINVAL;
1262         }
1263         if (priv->system != SYS_DVBC_ANNEX_A) {
1264                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1265                         __func__, priv->system);
1266                 return -EINVAL;
1267         }
1268         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1269         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1270         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1271                                                 | (u32)data[1], 13), 16384);
1272         return 0;
1273 }
1274
1275 static int cxd2841er_read_packet_errors_c(
1276                 struct cxd2841er_priv *priv, u32 *penum)
1277 {
1278         u8 data[3];
1279
1280         *penum = 0;
1281         if (priv->state != STATE_ACTIVE_TC) {
1282                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1283                                 __func__, priv->state);
1284                 return -EINVAL;
1285         }
1286         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1287         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1288         if (data[2] & 0x01)
1289                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1290         return 0;
1291 }
1292
1293 static int cxd2841er_read_packet_errors_t(
1294                 struct cxd2841er_priv *priv, u32 *penum)
1295 {
1296         u8 data[3];
1297
1298         *penum = 0;
1299         if (priv->state != STATE_ACTIVE_TC) {
1300                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1301                         __func__, priv->state);
1302                 return -EINVAL;
1303         }
1304         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1305         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1306         if (data[2] & 0x01)
1307                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1308         return 0;
1309 }
1310
1311 static int cxd2841er_read_packet_errors_t2(
1312                 struct cxd2841er_priv *priv, u32 *penum)
1313 {
1314         u8 data[3];
1315
1316         *penum = 0;
1317         if (priv->state != STATE_ACTIVE_TC) {
1318                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1319                         __func__, priv->state);
1320                 return -EINVAL;
1321         }
1322         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1323         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1324         if (data[0] & 0x01)
1325                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1326         return 0;
1327 }
1328
1329 static int cxd2841er_read_packet_errors_i(
1330                 struct cxd2841er_priv *priv, u32 *penum)
1331 {
1332         u8 data[2];
1333
1334         *penum = 0;
1335         if (priv->state != STATE_ACTIVE_TC) {
1336                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1337                                 __func__, priv->state);
1338                 return -EINVAL;
1339         }
1340         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1341         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1342
1343         if (!(data[0] & 0x01))
1344                 return 0;
1345
1346         /* Layer A */
1347         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1348         *penum = ((u32)data[0] << 8) | (u32)data[1];
1349
1350         /* Layer B */
1351         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1352         *penum += ((u32)data[0] << 8) | (u32)data[1];
1353
1354         /* Layer C */
1355         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1356         *penum += ((u32)data[0] << 8) | (u32)data[1];
1357
1358         return 0;
1359 }
1360
1361 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1362                 u32 *bit_error, u32 *bit_count)
1363 {
1364         u8 data[3];
1365         u32 bit_err, period_exp;
1366
1367         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1368         if (priv->state != STATE_ACTIVE_TC) {
1369                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1370                                 __func__, priv->state);
1371                 return -EINVAL;
1372         }
1373         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1374         cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1375         if (!(data[0] & 0x80)) {
1376                 dev_dbg(&priv->i2c->dev,
1377                                 "%s(): no valid BER data\n", __func__);
1378                 return -EINVAL;
1379         }
1380         bit_err = ((u32)(data[0] & 0x3f) << 16) |
1381                 ((u32)data[1] << 8) |
1382                 (u32)data[2];
1383         cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1384         period_exp = data[0] & 0x1f;
1385
1386         if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1387                 dev_dbg(&priv->i2c->dev,
1388                                 "%s(): period_exp(%u) or bit_err(%u)  not in range. no valid BER data\n",
1389                                 __func__, period_exp, bit_err);
1390                 return -EINVAL;
1391         }
1392
1393         dev_dbg(&priv->i2c->dev,
1394                         "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1395                         __func__, period_exp, bit_err,
1396                         ((1 << period_exp) * 204 * 8));
1397
1398         *bit_error = bit_err;
1399         *bit_count = ((1 << period_exp) * 204 * 8);
1400
1401         return 0;
1402 }
1403
1404 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1405                                     u32 *bit_error, u32 *bit_count)
1406 {
1407         u8 data[11];
1408
1409         /* Set SLV-T Bank : 0xA0 */
1410         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1411         /*
1412          *  slave     Bank      Addr      Bit      Signal name
1413          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1414          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1415          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1416          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1417          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1418          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1419          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1420          */
1421         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1422         if (data[0] & 0x01) {
1423                 *bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1424                              ((u32)(data[2]  & 0xFF) <<  8) |
1425                              (u32)(data[3]  & 0xFF);
1426                 *bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1427                              ((u32)(data[9]  & 0xFF) <<  8) |
1428                              (u32)(data[10] & 0xFF);
1429                 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1430                         dev_dbg(&priv->i2c->dev,
1431                                 "%s(): invalid bit_error %d, bit_count %d\n",
1432                                 __func__, *bit_error, *bit_count);
1433                         return -EINVAL;
1434                 }
1435                 return 0;
1436         }
1437         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1438         return -EINVAL;
1439 }
1440
1441
1442 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1443                                      u32 *bit_error, u32 *bit_count)
1444 {
1445         u8 data[5];
1446         u32 period;
1447
1448         /* Set SLV-T Bank : 0xB2 */
1449         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1450         /*
1451          *  slave     Bank      Addr      Bit      Signal name
1452          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1453          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1454          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1455          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1456          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1457          */
1458         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1459         if (data[0] & 0x01) {
1460                 /* Bit error count */
1461                 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1462                              ((u32)(data[2] & 0xFF) << 16) |
1463                              ((u32)(data[3] & 0xFF) <<  8) |
1464                              (u32)(data[4] & 0xFF);
1465
1466                 /* Set SLV-T Bank : 0xA0 */
1467                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1468                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1469                 /* Measurement period */
1470                 period = (u32)(1 << (data[0] & 0x0F));
1471                 if (period == 0) {
1472                         dev_dbg(&priv->i2c->dev,
1473                                 "%s(): period is 0\n", __func__);
1474                         return -EINVAL;
1475                 }
1476                 if (*bit_error > (period * 64800)) {
1477                         dev_dbg(&priv->i2c->dev,
1478                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1479                                 __func__, *bit_error, period);
1480                         return -EINVAL;
1481                 }
1482                 *bit_count = period * 64800;
1483
1484                 return 0;
1485         } else {
1486                 dev_dbg(&priv->i2c->dev,
1487                         "%s(): no data available\n", __func__);
1488         }
1489         return -EINVAL;
1490 }
1491
1492 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1493                                  u32 *bit_error, u32 *bit_count)
1494 {
1495         u8 data[4];
1496         u32 period_exp, n_ldpc;
1497
1498         if (priv->state != STATE_ACTIVE_TC) {
1499                 dev_dbg(&priv->i2c->dev,
1500                         "%s(): invalid state %d\n", __func__, priv->state);
1501                 return -EINVAL;
1502         }
1503         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1504         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1505         if (!(data[0] & 0x10)) {
1506                 dev_dbg(&priv->i2c->dev,
1507                         "%s(): no valid BER data\n", __func__);
1508                 return -EINVAL;
1509         }
1510         *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1511                      ((u32)data[1] << 16) |
1512                      ((u32)data[2] << 8) |
1513                      (u32)data[3];
1514         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1515         period_exp = data[0] & 0x0f;
1516         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1517         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1518         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1519         if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1520                 dev_dbg(&priv->i2c->dev,
1521                         "%s(): invalid BER value\n", __func__);
1522                 return -EINVAL;
1523         }
1524
1525         /*
1526          * FIXME: the right thing would be to return bit_error untouched,
1527          * but, as we don't know the scale returned by the counters, let's
1528          * at least preserver BER = bit_error/bit_count.
1529          */
1530         if (period_exp >= 4) {
1531                 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1532                 *bit_error *= 3125ULL;
1533         } else {
1534                 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1535                 *bit_error *= 50000ULL;
1536         }
1537         return 0;
1538 }
1539
1540 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1541                                 u32 *bit_error, u32 *bit_count)
1542 {
1543         u8 data[2];
1544         u32 period;
1545
1546         if (priv->state != STATE_ACTIVE_TC) {
1547                 dev_dbg(&priv->i2c->dev,
1548                         "%s(): invalid state %d\n", __func__, priv->state);
1549                 return -EINVAL;
1550         }
1551         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1552         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1553         if (!(data[0] & 0x01)) {
1554                 dev_dbg(&priv->i2c->dev,
1555                         "%s(): no valid BER data\n", __func__);
1556                 return 0;
1557         }
1558         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1559         *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1560         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1561         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1562
1563         /*
1564          * FIXME: the right thing would be to return bit_error untouched,
1565          * but, as we don't know the scale returned by the counters, let's
1566          * at least preserver BER = bit_error/bit_count.
1567          */
1568         *bit_count = period / 128;
1569         *bit_error *= 78125ULL;
1570         return 0;
1571 }
1572
1573 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1574                 u8 delsys, u32 *snr)
1575 {
1576         u8 data[3];
1577         u32 res = 0, value;
1578         int min_index, max_index, index;
1579         static const struct cxd2841er_cnr_data *cn_data;
1580
1581         /* Set SLV-T Bank : 0xA1 */
1582         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1583         /*
1584          *  slave     Bank      Addr      Bit     Signal name
1585          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1586          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1587          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1588          */
1589         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1590         if (data[0] & 0x01) {
1591                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1592                 min_index = 0;
1593                 if (delsys == SYS_DVBS) {
1594                         cn_data = s_cn_data;
1595                         max_index = sizeof(s_cn_data) /
1596                                 sizeof(s_cn_data[0]) - 1;
1597                 } else {
1598                         cn_data = s2_cn_data;
1599                         max_index = sizeof(s2_cn_data) /
1600                                 sizeof(s2_cn_data[0]) - 1;
1601                 }
1602                 if (value >= cn_data[min_index].value) {
1603                         res = cn_data[min_index].cnr_x1000;
1604                         goto done;
1605                 }
1606                 if (value <= cn_data[max_index].value) {
1607                         res = cn_data[max_index].cnr_x1000;
1608                         goto done;
1609                 }
1610                 while ((max_index - min_index) > 1) {
1611                         index = (max_index + min_index) / 2;
1612                         if (value == cn_data[index].value) {
1613                                 res = cn_data[index].cnr_x1000;
1614                                 goto done;
1615                         } else if (value > cn_data[index].value)
1616                                 max_index = index;
1617                         else
1618                                 min_index = index;
1619                         if ((max_index - min_index) <= 1) {
1620                                 if (value == cn_data[max_index].value) {
1621                                         res = cn_data[max_index].cnr_x1000;
1622                                         goto done;
1623                                 } else {
1624                                         res = cn_data[min_index].cnr_x1000;
1625                                         goto done;
1626                                 }
1627                         }
1628                 }
1629         } else {
1630                 dev_dbg(&priv->i2c->dev,
1631                         "%s(): no data available\n", __func__);
1632                 return -EINVAL;
1633         }
1634 done:
1635         *snr = res;
1636         return 0;
1637 }
1638
1639 static uint32_t sony_log(uint32_t x)
1640 {
1641         return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1642 }
1643
1644 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1645 {
1646         u32 reg;
1647         u8 data[2];
1648         enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1649
1650         *snr = 0;
1651         if (priv->state != STATE_ACTIVE_TC) {
1652                 dev_dbg(&priv->i2c->dev,
1653                                 "%s(): invalid state %d\n",
1654                                 __func__, priv->state);
1655                 return -EINVAL;
1656         }
1657
1658         /*
1659          * Freeze registers: ensure multiple separate register reads
1660          * are from the same snapshot
1661          */
1662         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1663
1664         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1665         cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1666         qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1667         cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1668
1669         reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1670         if (reg == 0) {
1671                 dev_dbg(&priv->i2c->dev,
1672                                 "%s(): reg value out of range\n", __func__);
1673                 return 0;
1674         }
1675
1676         switch (qam) {
1677         case SONY_DVBC_CONSTELLATION_16QAM:
1678         case SONY_DVBC_CONSTELLATION_64QAM:
1679         case SONY_DVBC_CONSTELLATION_256QAM:
1680                 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1681                 if (reg < 126)
1682                         reg = 126;
1683                 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1684                 break;
1685         case SONY_DVBC_CONSTELLATION_32QAM:
1686         case SONY_DVBC_CONSTELLATION_128QAM:
1687                 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1688                 if (reg < 69)
1689                         reg = 69;
1690                 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1691                 break;
1692         default:
1693                 return -EINVAL;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1700 {
1701         u32 reg;
1702         u8 data[2];
1703
1704         *snr = 0;
1705         if (priv->state != STATE_ACTIVE_TC) {
1706                 dev_dbg(&priv->i2c->dev,
1707                         "%s(): invalid state %d\n", __func__, priv->state);
1708                 return -EINVAL;
1709         }
1710         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1711         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1712         reg = ((u32)data[0] << 8) | (u32)data[1];
1713         if (reg == 0) {
1714                 dev_dbg(&priv->i2c->dev,
1715                         "%s(): reg value out of range\n", __func__);
1716                 return 0;
1717         }
1718         if (reg > 4996)
1719                 reg = 4996;
1720         *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1721         return 0;
1722 }
1723
1724 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1725 {
1726         u32 reg;
1727         u8 data[2];
1728
1729         *snr = 0;
1730         if (priv->state != STATE_ACTIVE_TC) {
1731                 dev_dbg(&priv->i2c->dev,
1732                         "%s(): invalid state %d\n", __func__, priv->state);
1733                 return -EINVAL;
1734         }
1735         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1736         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1737         reg = ((u32)data[0] << 8) | (u32)data[1];
1738         if (reg == 0) {
1739                 dev_dbg(&priv->i2c->dev,
1740                         "%s(): reg value out of range\n", __func__);
1741                 return 0;
1742         }
1743         if (reg > 10876)
1744                 reg = 10876;
1745         *snr = 10000 * ((intlog10(reg) -
1746                 intlog10(12600 - reg)) >> 24) + 32000;
1747         return 0;
1748 }
1749
1750 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1751 {
1752         u32 reg;
1753         u8 data[2];
1754
1755         *snr = 0;
1756         if (priv->state != STATE_ACTIVE_TC) {
1757                 dev_dbg(&priv->i2c->dev,
1758                                 "%s(): invalid state %d\n", __func__,
1759                                 priv->state);
1760                 return -EINVAL;
1761         }
1762
1763         /* Freeze all registers */
1764         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1765
1766
1767         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1768         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1769         reg = ((u32)data[0] << 8) | (u32)data[1];
1770         if (reg == 0) {
1771                 dev_dbg(&priv->i2c->dev,
1772                                 "%s(): reg value out of range\n", __func__);
1773                 return 0;
1774         }
1775         if (reg > 4996)
1776                 reg = 4996;
1777         *snr = 100 * intlog10(reg) - 9031;
1778         return 0;
1779 }
1780
1781 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1782                                         u8 delsys)
1783 {
1784         u8 data[2];
1785
1786         cxd2841er_write_reg(
1787                 priv, I2C_SLVT, 0x00, 0x40);
1788         cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1789         dev_dbg(&priv->i2c->dev,
1790                         "%s(): AGC value=%u\n",
1791                         __func__, (((u16)data[0] & 0x0F) << 8) |
1792                         (u16)(data[1] & 0xFF));
1793         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1794 }
1795
1796 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1797                                         u8 delsys)
1798 {
1799         u8 data[2];
1800
1801         cxd2841er_write_reg(
1802                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1803         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1804         dev_dbg(&priv->i2c->dev,
1805                         "%s(): AGC value=%u\n",
1806                         __func__, (((u16)data[0] & 0x0F) << 8) |
1807                         (u16)(data[1] & 0xFF));
1808         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1809 }
1810
1811 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1812                 u8 delsys)
1813 {
1814         u8 data[2];
1815
1816         cxd2841er_write_reg(
1817                         priv, I2C_SLVT, 0x00, 0x60);
1818         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1819
1820         dev_dbg(&priv->i2c->dev,
1821                         "%s(): AGC value=%u\n",
1822                         __func__, (((u16)data[0] & 0x0F) << 8) |
1823                         (u16)(data[1] & 0xFF));
1824         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1825 }
1826
1827 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1828 {
1829         u8 data[2];
1830
1831         /* Set SLV-T Bank : 0xA0 */
1832         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1833         /*
1834          *  slave     Bank      Addr      Bit       Signal name
1835          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1836          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1837          */
1838         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1839         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1840 }
1841
1842 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1843 {
1844         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1845         struct cxd2841er_priv *priv = fe->demodulator_priv;
1846         u32 ret, bit_error = 0, bit_count = 0;
1847
1848         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1849         switch (p->delivery_system) {
1850         case SYS_DVBC_ANNEX_A:
1851         case SYS_DVBC_ANNEX_B:
1852         case SYS_DVBC_ANNEX_C:
1853                 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1854                 break;
1855         case SYS_DVBS:
1856                 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1857                 break;
1858         case SYS_DVBS2:
1859                 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1860                 break;
1861         case SYS_DVBT:
1862                 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1863                 break;
1864         case SYS_DVBT2:
1865                 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1866                 break;
1867         default:
1868                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1869                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1870                 return;
1871         }
1872
1873         if (!ret) {
1874                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1875                 p->post_bit_error.stat[0].uvalue += bit_error;
1876                 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1877                 p->post_bit_count.stat[0].uvalue += bit_count;
1878         } else {
1879                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1880                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1881         }
1882 }
1883
1884 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1885 {
1886         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1887         struct cxd2841er_priv *priv = fe->demodulator_priv;
1888         s32 strength;
1889
1890         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1891         switch (p->delivery_system) {
1892         case SYS_DVBT:
1893         case SYS_DVBT2:
1894                 strength = cxd2841er_read_agc_gain_t_t2(priv,
1895                                                         p->delivery_system);
1896                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1897                 /* Formula was empirically determinated @ 410 MHz */
1898                 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
1899                 break;  /* Code moved out of the function */
1900         case SYS_DVBC_ANNEX_A:
1901         case SYS_DVBC_ANNEX_B:
1902         case SYS_DVBC_ANNEX_C:
1903                 strength = cxd2841er_read_agc_gain_c(priv,
1904                                                         p->delivery_system);
1905                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1906                 /*
1907                  * Formula was empirically determinated via linear regression,
1908                  * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
1909                  * stream modulated with QAM64
1910                  */
1911                 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
1912                 break;
1913         case SYS_ISDBT:
1914                 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
1915                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1916                 /*
1917                  * Formula was empirically determinated via linear regression,
1918                  * using frequencies: 175 MHz, 410 MHz and 800 MHz.
1919                  */
1920                 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
1921                 break;
1922         case SYS_DVBS:
1923         case SYS_DVBS2:
1924                 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1925                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1926                 p->strength.stat[0].uvalue = strength;
1927                 break;
1928         default:
1929                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1930                 break;
1931         }
1932 }
1933
1934 static void cxd2841er_read_snr(struct dvb_frontend *fe)
1935 {
1936         u32 tmp = 0;
1937         int ret = 0;
1938         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1939         struct cxd2841er_priv *priv = fe->demodulator_priv;
1940
1941         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1942         switch (p->delivery_system) {
1943         case SYS_DVBC_ANNEX_A:
1944         case SYS_DVBC_ANNEX_B:
1945         case SYS_DVBC_ANNEX_C:
1946                 ret = cxd2841er_read_snr_c(priv, &tmp);
1947                 break;
1948         case SYS_DVBT:
1949                 ret = cxd2841er_read_snr_t(priv, &tmp);
1950                 break;
1951         case SYS_DVBT2:
1952                 ret = cxd2841er_read_snr_t2(priv, &tmp);
1953                 break;
1954         case SYS_ISDBT:
1955                 ret = cxd2841er_read_snr_i(priv, &tmp);
1956                 break;
1957         case SYS_DVBS:
1958         case SYS_DVBS2:
1959                 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
1960                 break;
1961         default:
1962                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1963                         __func__, p->delivery_system);
1964                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1965                 return;
1966         }
1967
1968         if (!ret) {
1969                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1970                 p->cnr.stat[0].svalue = tmp;
1971         } else {
1972                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1973         }
1974 }
1975
1976 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
1977 {
1978         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1979         struct cxd2841er_priv *priv = fe->demodulator_priv;
1980         u32 ucblocks;
1981
1982         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1983         switch (p->delivery_system) {
1984         case SYS_DVBC_ANNEX_A:
1985         case SYS_DVBC_ANNEX_B:
1986         case SYS_DVBC_ANNEX_C:
1987                 cxd2841er_read_packet_errors_c(priv, &ucblocks);
1988                 break;
1989         case SYS_DVBT:
1990                 cxd2841er_read_packet_errors_t(priv, &ucblocks);
1991                 break;
1992         case SYS_DVBT2:
1993                 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
1994                 break;
1995         case SYS_ISDBT:
1996                 cxd2841er_read_packet_errors_i(priv, &ucblocks);
1997                 break;
1998         default:
1999                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2000                 return;
2001         }
2002         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2003
2004         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2005         p->block_error.stat[0].uvalue = ucblocks;
2006 }
2007
2008 static int cxd2841er_dvbt2_set_profile(
2009         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2010 {
2011         u8 tune_mode;
2012         u8 seq_not2d_time;
2013
2014         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2015         switch (profile) {
2016         case DVBT2_PROFILE_BASE:
2017                 tune_mode = 0x01;
2018                 /* Set early unlock time */
2019                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2020                 break;
2021         case DVBT2_PROFILE_LITE:
2022                 tune_mode = 0x05;
2023                 /* Set early unlock time */
2024                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2025                 break;
2026         case DVBT2_PROFILE_ANY:
2027                 tune_mode = 0x00;
2028                 /* Set early unlock time */
2029                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2030                 break;
2031         default:
2032                 return -EINVAL;
2033         }
2034         /* Set SLV-T Bank : 0x2E */
2035         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2036         /* Set profile and tune mode */
2037         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2038         /* Set SLV-T Bank : 0x2B */
2039         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2040         /* Set early unlock detection time */
2041         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2042         return 0;
2043 }
2044
2045 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2046                                           u8 is_auto, u8 plp_id)
2047 {
2048         if (is_auto) {
2049                 dev_dbg(&priv->i2c->dev,
2050                         "%s() using auto PLP selection\n", __func__);
2051         } else {
2052                 dev_dbg(&priv->i2c->dev,
2053                         "%s() using manual PLP selection, ID %d\n",
2054                         __func__, plp_id);
2055         }
2056         /* Set SLV-T Bank : 0x23 */
2057         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2058         if (!is_auto) {
2059                 /* Manual PLP selection mode. Set the data PLP Id. */
2060                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2061         }
2062         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2063         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2064         return 0;
2065 }
2066
2067 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2068                                                 u32 bandwidth)
2069 {
2070         u32 iffreq;
2071         u8 data[MAX_WRITE_REGSIZE];
2072
2073         const uint8_t nominalRate8bw[3][5] = {
2074                 /* TRCG Nominal Rate [37:0] */
2075                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2076                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2077                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2078         };
2079
2080         const uint8_t nominalRate7bw[3][5] = {
2081                 /* TRCG Nominal Rate [37:0] */
2082                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2083                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2084                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2085         };
2086
2087         const uint8_t nominalRate6bw[3][5] = {
2088                 /* TRCG Nominal Rate [37:0] */
2089                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2090                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2091                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2092         };
2093
2094         const uint8_t nominalRate5bw[3][5] = {
2095                 /* TRCG Nominal Rate [37:0] */
2096                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2097                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2098                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2099         };
2100
2101         const uint8_t nominalRate17bw[3][5] = {
2102                 /* TRCG Nominal Rate [37:0] */
2103                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2104                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2105                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
2106         };
2107
2108         const uint8_t itbCoef8bw[3][14] = {
2109                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2110                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2111                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2112                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2113                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2114                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2115         };
2116
2117         const uint8_t itbCoef7bw[3][14] = {
2118                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2119                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2120                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2121                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2122                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2123                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2124         };
2125
2126         const uint8_t itbCoef6bw[3][14] = {
2127                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2128                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2129                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2130                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2131                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2132                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2133         };
2134
2135         const uint8_t itbCoef5bw[3][14] = {
2136                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2137                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2138                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2139                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2140                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2141                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2142         };
2143
2144         const uint8_t itbCoef17bw[3][14] = {
2145                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2146                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2147                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2148                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
2149                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2150                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
2151         };
2152
2153         /* Set SLV-T Bank : 0x20 */
2154         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2155
2156         switch (bandwidth) {
2157         case 8000000:
2158                 /* <Timing Recovery setting> */
2159                 cxd2841er_write_regs(priv, I2C_SLVT,
2160                                 0x9F, nominalRate8bw[priv->xtal], 5);
2161
2162                 /* Set SLV-T Bank : 0x27 */
2163                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2164                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2165                                 0x7a, 0x00, 0x0f);
2166
2167                 /* Set SLV-T Bank : 0x10 */
2168                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2169
2170                 /* Group delay equaliser settings for
2171                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2172                  */
2173                 cxd2841er_write_regs(priv, I2C_SLVT,
2174                                 0xA6, itbCoef8bw[priv->xtal], 14);
2175                 /* <IF freq setting> */
2176                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2177                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2178                 data[1] = (u8)((iffreq >> 8) & 0xff);
2179                 data[2] = (u8)(iffreq & 0xff);
2180                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2181                 /* System bandwidth setting */
2182                 cxd2841er_set_reg_bits(
2183                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2184                 break;
2185         case 7000000:
2186                 /* <Timing Recovery setting> */
2187                 cxd2841er_write_regs(priv, I2C_SLVT,
2188                                 0x9F, nominalRate7bw[priv->xtal], 5);
2189
2190                 /* Set SLV-T Bank : 0x27 */
2191                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2192                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2193                                 0x7a, 0x00, 0x0f);
2194
2195                 /* Set SLV-T Bank : 0x10 */
2196                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2197
2198                 /* Group delay equaliser settings for
2199                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2200                  */
2201                 cxd2841er_write_regs(priv, I2C_SLVT,
2202                                 0xA6, itbCoef7bw[priv->xtal], 14);
2203                 /* <IF freq setting> */
2204                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2205                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2206                 data[1] = (u8)((iffreq >> 8) & 0xff);
2207                 data[2] = (u8)(iffreq & 0xff);
2208                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2209                 /* System bandwidth setting */
2210                 cxd2841er_set_reg_bits(
2211                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2212                 break;
2213         case 6000000:
2214                 /* <Timing Recovery setting> */
2215                 cxd2841er_write_regs(priv, I2C_SLVT,
2216                                 0x9F, nominalRate6bw[priv->xtal], 5);
2217
2218                 /* Set SLV-T Bank : 0x27 */
2219                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2220                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2221                                 0x7a, 0x00, 0x0f);
2222
2223                 /* Set SLV-T Bank : 0x10 */
2224                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2225
2226                 /* Group delay equaliser settings for
2227                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2228                  */
2229                 cxd2841er_write_regs(priv, I2C_SLVT,
2230                                 0xA6, itbCoef6bw[priv->xtal], 14);
2231                 /* <IF freq setting> */
2232                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2233                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2234                 data[1] = (u8)((iffreq >> 8) & 0xff);
2235                 data[2] = (u8)(iffreq & 0xff);
2236                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2237                 /* System bandwidth setting */
2238                 cxd2841er_set_reg_bits(
2239                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2240                 break;
2241         case 5000000:
2242                 /* <Timing Recovery setting> */
2243                 cxd2841er_write_regs(priv, I2C_SLVT,
2244                                 0x9F, nominalRate5bw[priv->xtal], 5);
2245
2246                 /* Set SLV-T Bank : 0x27 */
2247                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2248                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2249                                 0x7a, 0x00, 0x0f);
2250
2251                 /* Set SLV-T Bank : 0x10 */
2252                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2253
2254                 /* Group delay equaliser settings for
2255                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2256                  */
2257                 cxd2841er_write_regs(priv, I2C_SLVT,
2258                                 0xA6, itbCoef5bw[priv->xtal], 14);
2259                 /* <IF freq setting> */
2260                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2261                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2262                 data[1] = (u8)((iffreq >> 8) & 0xff);
2263                 data[2] = (u8)(iffreq & 0xff);
2264                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2265                 /* System bandwidth setting */
2266                 cxd2841er_set_reg_bits(
2267                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2268                 break;
2269         case 1712000:
2270                 /* <Timing Recovery setting> */
2271                 cxd2841er_write_regs(priv, I2C_SLVT,
2272                                 0x9F, nominalRate17bw[priv->xtal], 5);
2273
2274                 /* Set SLV-T Bank : 0x27 */
2275                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2276                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2277                                 0x7a, 0x03, 0x0f);
2278
2279                 /* Set SLV-T Bank : 0x10 */
2280                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2281
2282                 /* Group delay equaliser settings for
2283                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2284                  */
2285                 cxd2841er_write_regs(priv, I2C_SLVT,
2286                                 0xA6, itbCoef17bw[priv->xtal], 14);
2287                 /* <IF freq setting> */
2288                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2289                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2290                 data[1] = (u8)((iffreq >> 8) & 0xff);
2291                 data[2] = (u8)(iffreq & 0xff);
2292                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2293                 /* System bandwidth setting */
2294                 cxd2841er_set_reg_bits(
2295                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2296                 break;
2297         default:
2298                 return -EINVAL;
2299         }
2300         return 0;
2301 }
2302
2303 static int cxd2841er_sleep_tc_to_active_t_band(
2304                 struct cxd2841er_priv *priv, u32 bandwidth)
2305 {
2306         u8 data[MAX_WRITE_REGSIZE];
2307         u32 iffreq;
2308         u8 nominalRate8bw[3][5] = {
2309                 /* TRCG Nominal Rate [37:0] */
2310                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2311                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2312                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2313         };
2314         u8 nominalRate7bw[3][5] = {
2315                 /* TRCG Nominal Rate [37:0] */
2316                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2317                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2318                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2319         };
2320         u8 nominalRate6bw[3][5] = {
2321                 /* TRCG Nominal Rate [37:0] */
2322                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2323                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2324                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2325         };
2326         u8 nominalRate5bw[3][5] = {
2327                 /* TRCG Nominal Rate [37:0] */
2328                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2329                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2330                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2331         };
2332
2333         u8 itbCoef8bw[3][14] = {
2334                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2335                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2336                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2337                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2338                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2339                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2340         };
2341         u8 itbCoef7bw[3][14] = {
2342                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2343                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2344                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2345                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2346                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2347                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2348         };
2349         u8 itbCoef6bw[3][14] = {
2350                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2351                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2352                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2353                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2354                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2355                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2356         };
2357         u8 itbCoef5bw[3][14] = {
2358                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2359                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2360                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2361                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2362                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2363                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2364         };
2365
2366         /* Set SLV-T Bank : 0x13 */
2367         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2368         /* Echo performance optimization setting */
2369         data[0] = 0x01;
2370         data[1] = 0x14;
2371         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2372
2373         /* Set SLV-T Bank : 0x10 */
2374         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2375
2376         switch (bandwidth) {
2377         case 8000000:
2378                 /* <Timing Recovery setting> */
2379                 cxd2841er_write_regs(priv, I2C_SLVT,
2380                                 0x9F, nominalRate8bw[priv->xtal], 5);
2381                 /* Group delay equaliser settings for
2382                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2383                 */
2384                 cxd2841er_write_regs(priv, I2C_SLVT,
2385                                 0xA6, itbCoef8bw[priv->xtal], 14);
2386                 /* <IF freq setting> */
2387                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2388                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2389                 data[1] = (u8)((iffreq >> 8) & 0xff);
2390                 data[2] = (u8)(iffreq & 0xff);
2391                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2392                 /* System bandwidth setting */
2393                 cxd2841er_set_reg_bits(
2394                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2395
2396                 /* Demod core latency setting */
2397                 if (priv->xtal == SONY_XTAL_24000) {
2398                         data[0] = 0x15;
2399                         data[1] = 0x28;
2400                 } else {
2401                         data[0] = 0x01;
2402                         data[1] = 0xE0;
2403                 }
2404                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2405
2406                 /* Notch filter setting */
2407                 data[0] = 0x01;
2408                 data[1] = 0x02;
2409                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2410                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2411                 break;
2412         case 7000000:
2413                 /* <Timing Recovery setting> */
2414                 cxd2841er_write_regs(priv, I2C_SLVT,
2415                                 0x9F, nominalRate7bw[priv->xtal], 5);
2416                 /* Group delay equaliser settings for
2417                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2418                 */
2419                 cxd2841er_write_regs(priv, I2C_SLVT,
2420                                 0xA6, itbCoef7bw[priv->xtal], 14);
2421                 /* <IF freq setting> */
2422                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2423                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2424                 data[1] = (u8)((iffreq >> 8) & 0xff);
2425                 data[2] = (u8)(iffreq & 0xff);
2426                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2427                 /* System bandwidth setting */
2428                 cxd2841er_set_reg_bits(
2429                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2430
2431                 /* Demod core latency setting */
2432                 if (priv->xtal == SONY_XTAL_24000) {
2433                         data[0] = 0x1F;
2434                         data[1] = 0xF8;
2435                 } else {
2436                         data[0] = 0x12;
2437                         data[1] = 0xF8;
2438                 }
2439                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2440
2441                 /* Notch filter setting */
2442                 data[0] = 0x00;
2443                 data[1] = 0x03;
2444                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2445                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2446                 break;
2447         case 6000000:
2448                 /* <Timing Recovery setting> */
2449                 cxd2841er_write_regs(priv, I2C_SLVT,
2450                                 0x9F, nominalRate6bw[priv->xtal], 5);
2451                 /* Group delay equaliser settings for
2452                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2453                 */
2454                 cxd2841er_write_regs(priv, I2C_SLVT,
2455                                 0xA6, itbCoef6bw[priv->xtal], 14);
2456                 /* <IF freq setting> */
2457                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2458                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2459                 data[1] = (u8)((iffreq >> 8) & 0xff);
2460                 data[2] = (u8)(iffreq & 0xff);
2461                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2462                 /* System bandwidth setting */
2463                 cxd2841er_set_reg_bits(
2464                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2465
2466                 /* Demod core latency setting */
2467                 if (priv->xtal == SONY_XTAL_24000) {
2468                         data[0] = 0x25;
2469                         data[1] = 0x4C;
2470                 } else {
2471                         data[0] = 0x1F;
2472                         data[1] = 0xDC;
2473                 }
2474                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2475
2476                 /* Notch filter setting */
2477                 data[0] = 0x00;
2478                 data[1] = 0x03;
2479                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2480                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2481                 break;
2482         case 5000000:
2483                 /* <Timing Recovery setting> */
2484                 cxd2841er_write_regs(priv, I2C_SLVT,
2485                                 0x9F, nominalRate5bw[priv->xtal], 5);
2486                 /* Group delay equaliser settings for
2487                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2488                 */
2489                 cxd2841er_write_regs(priv, I2C_SLVT,
2490                                 0xA6, itbCoef5bw[priv->xtal], 14);
2491                 /* <IF freq setting> */
2492                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2493                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2494                 data[1] = (u8)((iffreq >> 8) & 0xff);
2495                 data[2] = (u8)(iffreq & 0xff);
2496                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2497                 /* System bandwidth setting */
2498                 cxd2841er_set_reg_bits(
2499                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2500
2501                 /* Demod core latency setting */
2502                 if (priv->xtal == SONY_XTAL_24000) {
2503                         data[0] = 0x2C;
2504                         data[1] = 0xC2;
2505                 } else {
2506                         data[0] = 0x26;
2507                         data[1] = 0x3C;
2508                 }
2509                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2510
2511                 /* Notch filter setting */
2512                 data[0] = 0x00;
2513                 data[1] = 0x03;
2514                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2515                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2516                 break;
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int cxd2841er_sleep_tc_to_active_i_band(
2523                 struct cxd2841er_priv *priv, u32 bandwidth)
2524 {
2525         u32 iffreq;
2526         u8 data[3];
2527
2528         /* TRCG Nominal Rate */
2529         u8 nominalRate8bw[3][5] = {
2530                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2531                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2532                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2533         };
2534
2535         u8 nominalRate7bw[3][5] = {
2536                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2537                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2538                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2539         };
2540
2541         u8 nominalRate6bw[3][5] = {
2542                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2543                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2544                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2545         };
2546
2547         u8 itbCoef8bw[3][14] = {
2548                 {0x00}, /* 20.5MHz XTal */
2549                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2550                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2551                 {0x0}, /* 41MHz XTal   */
2552         };
2553
2554         u8 itbCoef7bw[3][14] = {
2555                 {0x00}, /* 20.5MHz XTal */
2556                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2557                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2558                 {0x00}, /* 41MHz XTal   */
2559         };
2560
2561         u8 itbCoef6bw[3][14] = {
2562                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2563                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2564                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2565                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2566                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2567                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2568         };
2569
2570         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2571         /* Set SLV-T Bank : 0x10 */
2572         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2573
2574         /*  20.5/41MHz Xtal support is not available
2575          *  on ISDB-T 7MHzBW and 8MHzBW
2576         */
2577         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2578                 dev_err(&priv->i2c->dev,
2579                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2580                         __func__, bandwidth);
2581                 return -EINVAL;
2582         }
2583
2584         switch (bandwidth) {
2585         case 8000000:
2586                 /* TRCG Nominal Rate */
2587                 cxd2841er_write_regs(priv, I2C_SLVT,
2588                                 0x9F, nominalRate8bw[priv->xtal], 5);
2589                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2590                 cxd2841er_write_regs(priv, I2C_SLVT,
2591                                 0xA6, itbCoef8bw[priv->xtal], 14);
2592
2593                 /* IF freq setting */
2594                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2595                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2596                 data[1] = (u8)((iffreq >> 8) & 0xff);
2597                 data[2] = (u8)(iffreq & 0xff);
2598                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2599
2600                 /* System bandwidth setting */
2601                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2602
2603                 /* Demod core latency setting */
2604                 data[0] = 0x13;
2605                 data[1] = 0xFC;
2606                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2607
2608                 /* Acquisition optimization setting */
2609                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2610                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2611                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2612                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2613                 break;
2614         case 7000000:
2615                 /* TRCG Nominal Rate */
2616                 cxd2841er_write_regs(priv, I2C_SLVT,
2617                                 0x9F, nominalRate7bw[priv->xtal], 5);
2618                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2619                 cxd2841er_write_regs(priv, I2C_SLVT,
2620                                 0xA6, itbCoef7bw[priv->xtal], 14);
2621
2622                 /* IF freq setting */
2623                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2624                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2625                 data[1] = (u8)((iffreq >> 8) & 0xff);
2626                 data[2] = (u8)(iffreq & 0xff);
2627                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2628
2629                 /* System bandwidth setting */
2630                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2631
2632                 /* Demod core latency setting */
2633                 data[0] = 0x1A;
2634                 data[1] = 0xFA;
2635                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2636
2637                 /* Acquisition optimization setting */
2638                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2639                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2640                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2641                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2642                 break;
2643         case 6000000:
2644                 /* TRCG Nominal Rate */
2645                 cxd2841er_write_regs(priv, I2C_SLVT,
2646                                 0x9F, nominalRate6bw[priv->xtal], 5);
2647                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2648                 cxd2841er_write_regs(priv, I2C_SLVT,
2649                                 0xA6, itbCoef6bw[priv->xtal], 14);
2650
2651                 /* IF freq setting */
2652                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2653                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2654                 data[1] = (u8)((iffreq >> 8) & 0xff);
2655                 data[2] = (u8)(iffreq & 0xff);
2656                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2657
2658                 /* System bandwidth setting */
2659                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2660
2661                 /* Demod core latency setting */
2662                 if (priv->xtal == SONY_XTAL_24000) {
2663                         data[0] = 0x1F;
2664                         data[1] = 0x79;
2665                 } else {
2666                         data[0] = 0x1A;
2667                         data[1] = 0xE2;
2668                 }
2669                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2670
2671                 /* Acquisition optimization setting */
2672                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2673                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2674                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2675                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2676                 break;
2677         default:
2678                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2679                                 __func__, bandwidth);
2680                 return -EINVAL;
2681         }
2682         return 0;
2683 }
2684
2685 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2686                                                u32 bandwidth)
2687 {
2688         u8 bw7_8mhz_b10_a6[] = {
2689                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2690                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2691         u8 bw6mhz_b10_a6[] = {
2692                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2693                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2694         u8 b10_b6[3];
2695         u32 iffreq;
2696
2697         dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2698         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2699         switch (bandwidth) {
2700         case 8000000:
2701         case 7000000:
2702                 cxd2841er_write_regs(
2703                         priv, I2C_SLVT, 0xa6,
2704                         bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2705                 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2706                 break;
2707         case 6000000:
2708                 cxd2841er_write_regs(
2709                         priv, I2C_SLVT, 0xa6,
2710                         bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2711                 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2712                 break;
2713         default:
2714                 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2715                         __func__, bandwidth);
2716                 return -EINVAL;
2717         }
2718         /* <IF freq setting> */
2719         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2720         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2721         b10_b6[2] = (u8)(iffreq & 0xff);
2722         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2723         /* Set SLV-T Bank : 0x11 */
2724         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2725         switch (bandwidth) {
2726         case 8000000:
2727         case 7000000:
2728                 cxd2841er_set_reg_bits(
2729                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2730                 break;
2731         case 6000000:
2732                 cxd2841er_set_reg_bits(
2733                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2734                 break;
2735         }
2736         /* Set SLV-T Bank : 0x40 */
2737         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2738         switch (bandwidth) {
2739         case 8000000:
2740                 cxd2841er_set_reg_bits(
2741                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2742                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2743                 break;
2744         case 7000000:
2745                 cxd2841er_set_reg_bits(
2746                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2747                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2748                 break;
2749         case 6000000:
2750                 cxd2841er_set_reg_bits(
2751                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2752                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2753                 break;
2754         }
2755         return 0;
2756 }
2757
2758 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2759                                           u32 bandwidth)
2760 {
2761         u8 data[2] = { 0x09, 0x54 };
2762         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2763
2764         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2765         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2766         /* Set SLV-X Bank : 0x00 */
2767         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2768         /* Set demod mode */
2769         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2770         /* Set SLV-T Bank : 0x00 */
2771         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2772         /* Enable demod clock */
2773         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2774         /* Disable RF level monitor */
2775         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2776         /* Enable ADC clock */
2777         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2778         /* Enable ADC 1 */
2779         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2780         /* Enable ADC 2 & 3 */
2781         if (priv->xtal == SONY_XTAL_41000) {
2782                 data[0] = 0x0A;
2783                 data[1] = 0xD4;
2784         }
2785         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2786         /* Enable ADC 4 */
2787         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2788         /* Set SLV-T Bank : 0x10 */
2789         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2790         /* IFAGC gain settings */
2791         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2792         /* Set SLV-T Bank : 0x11 */
2793         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2794         /* BBAGC TARGET level setting */
2795         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2796         /* Set SLV-T Bank : 0x10 */
2797         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2798         /* ASCOT setting ON */
2799         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2800         /* Set SLV-T Bank : 0x18 */
2801         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2802         /* Pre-RS BER moniter setting */
2803         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2804         /* FEC Auto Recovery setting */
2805         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2806         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2807         /* Set SLV-T Bank : 0x00 */
2808         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2809         /* TSIF setting */
2810         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2811         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2812
2813         if (priv->xtal == SONY_XTAL_24000) {
2814                 /* Set SLV-T Bank : 0x10 */
2815                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2816                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2817                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2818                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2819         }
2820
2821         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2822         /* Set SLV-T Bank : 0x00 */
2823         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2824         /* Disable HiZ Setting 1 */
2825         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2826         /* Disable HiZ Setting 2 */
2827         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2828         priv->state = STATE_ACTIVE_TC;
2829         return 0;
2830 }
2831
2832 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2833                                            u32 bandwidth)
2834 {
2835         u8 data[MAX_WRITE_REGSIZE];
2836
2837         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2838         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2839         /* Set SLV-X Bank : 0x00 */
2840         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2841         /* Set demod mode */
2842         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2843         /* Set SLV-T Bank : 0x00 */
2844         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2845         /* Enable demod clock */
2846         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2847         /* Disable RF level monitor */
2848         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2849         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2850         /* Enable ADC clock */
2851         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2852         /* Enable ADC 1 */
2853         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2854
2855         if (priv->xtal == SONY_XTAL_41000) {
2856                 data[0] = 0x0A;
2857                 data[1] = 0xD4;
2858         } else {
2859                 data[0] = 0x09;
2860                 data[1] = 0x54;
2861         }
2862
2863         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2864         /* Enable ADC 4 */
2865         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2866         /* Set SLV-T Bank : 0x10 */
2867         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2868         /* IFAGC gain settings */
2869         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2870         /* Set SLV-T Bank : 0x11 */
2871         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2872         /* BBAGC TARGET level setting */
2873         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2874         /* Set SLV-T Bank : 0x10 */
2875         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2876         /* ASCOT setting ON */
2877         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2878         /* Set SLV-T Bank : 0x20 */
2879         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2880         /* Acquisition optimization setting */
2881         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2882         /* Set SLV-T Bank : 0x2b */
2883         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2884         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2885         /* Set SLV-T Bank : 0x23 */
2886         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2887         /* L1 Control setting */
2888         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
2889         /* Set SLV-T Bank : 0x00 */
2890         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2891         /* TSIF setting */
2892         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2893         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2894         /* DVB-T2 initial setting */
2895         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2896         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2897         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2898         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2899         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2900         /* Set SLV-T Bank : 0x2a */
2901         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2902         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2903         /* Set SLV-T Bank : 0x2b */
2904         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2905         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2906
2907         /* 24MHz Xtal setting */
2908         if (priv->xtal == SONY_XTAL_24000) {
2909                 /* Set SLV-T Bank : 0x11 */
2910                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2911                 data[0] = 0xEB;
2912                 data[1] = 0x03;
2913                 data[2] = 0x3B;
2914                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2915
2916                 /* Set SLV-T Bank : 0x20 */
2917                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2918                 data[0] = 0x5E;
2919                 data[1] = 0x5E;
2920                 data[2] = 0x47;
2921                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2922
2923                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
2924
2925                 data[0] = 0x3F;
2926                 data[1] = 0xFF;
2927                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2928
2929                 /* Set SLV-T Bank : 0x24 */
2930                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
2931                 data[0] = 0x0B;
2932                 data[1] = 0x72;
2933                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
2934
2935                 data[0] = 0x93;
2936                 data[1] = 0xF3;
2937                 data[2] = 0x00;
2938                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
2939
2940                 data[0] = 0x05;
2941                 data[1] = 0xB8;
2942                 data[2] = 0xD8;
2943                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
2944
2945                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
2946
2947                 /* Set SLV-T Bank : 0x25 */
2948                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
2949                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
2950
2951                 /* Set SLV-T Bank : 0x27 */
2952                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2953                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
2954
2955                 /* Set SLV-T Bank : 0x2B */
2956                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
2957                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
2958                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
2959
2960                 /* Set SLV-T Bank : 0x2D */
2961                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
2962                 data[0] = 0x89;
2963                 data[1] = 0x89;
2964                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
2965
2966                 /* Set SLV-T Bank : 0x5E */
2967                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
2968                 data[0] = 0x24;
2969                 data[1] = 0x95;
2970                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
2971         }
2972
2973         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2974
2975         /* Set SLV-T Bank : 0x00 */
2976         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2977         /* Disable HiZ Setting 1 */
2978         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2979         /* Disable HiZ Setting 2 */
2980         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2981         priv->state = STATE_ACTIVE_TC;
2982         return 0;
2983 }
2984
2985 /* ISDB-Tb part */
2986 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2987                 u32 bandwidth)
2988 {
2989         u8 data[2] = { 0x09, 0x54 };
2990         u8 data24m[2] = {0x60, 0x00};
2991         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2992
2993         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2994         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2995         /* Set SLV-X Bank : 0x00 */
2996         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2997         /* Set demod mode */
2998         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2999         /* Set SLV-T Bank : 0x00 */
3000         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3001         /* Enable demod clock */
3002         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3003         /* Enable RF level monitor */
3004         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3005         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3006         /* Enable ADC clock */
3007         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3008         /* Enable ADC 1 */
3009         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3010         /* xtal freq 20.5MHz or 24M */
3011         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3012         /* Enable ADC 4 */
3013         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3014         /* ASCOT setting ON */
3015         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
3016         /* FEC Auto Recovery setting */
3017         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3018         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3019         /* ISDB-T initial setting */
3020         /* Set SLV-T Bank : 0x00 */
3021         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3022         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3023         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3024         /* Set SLV-T Bank : 0x10 */
3025         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3026         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3027         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3028         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3029         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3030         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3031         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3032         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3033         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3034         /* Set SLV-T Bank : 0x15 */
3035         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3036         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3037         /* Set SLV-T Bank : 0x1E */
3038         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3039         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3040         /* Set SLV-T Bank : 0x63 */
3041         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3042         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3043
3044         /* for xtal 24MHz */
3045         /* Set SLV-T Bank : 0x10 */
3046         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3047         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3048         /* Set SLV-T Bank : 0x60 */
3049         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3050         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3051
3052         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3053         /* Set SLV-T Bank : 0x00 */
3054         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3055         /* Disable HiZ Setting 1 */
3056         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3057         /* Disable HiZ Setting 2 */
3058         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3059         priv->state = STATE_ACTIVE_TC;
3060         return 0;
3061 }
3062
3063 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3064                                           u32 bandwidth)
3065 {
3066         u8 data[2] = { 0x09, 0x54 };
3067
3068         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3069         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3070         /* Set SLV-X Bank : 0x00 */
3071         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3072         /* Set demod mode */
3073         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3074         /* Set SLV-T Bank : 0x00 */
3075         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3076         /* Enable demod clock */
3077         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3078         /* Disable RF level monitor */
3079         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3080         /* Enable ADC clock */
3081         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3082         /* Enable ADC 1 */
3083         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3084         /* xtal freq 20.5MHz */
3085         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3086         /* Enable ADC 4 */
3087         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3088         /* Set SLV-T Bank : 0x10 */
3089         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3090         /* IFAGC gain settings */
3091         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3092         /* Set SLV-T Bank : 0x11 */
3093         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3094         /* BBAGC TARGET level setting */
3095         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3096         /* Set SLV-T Bank : 0x10 */
3097         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3098         /* ASCOT setting ON */
3099         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
3100         /* Set SLV-T Bank : 0x40 */
3101         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3102         /* Demod setting */
3103         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3104         /* Set SLV-T Bank : 0x00 */
3105         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3106         /* TSIF setting */
3107         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3108         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3109
3110         cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3111         /* Set SLV-T Bank : 0x00 */
3112         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3113         /* Disable HiZ Setting 1 */
3114         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3115         /* Disable HiZ Setting 2 */
3116         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3117         priv->state = STATE_ACTIVE_TC;
3118         return 0;
3119 }
3120
3121 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3122                                   struct dtv_frontend_properties *p)
3123 {
3124         enum fe_status status = 0;
3125         struct cxd2841er_priv *priv = fe->demodulator_priv;
3126
3127         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3128         if (priv->state == STATE_ACTIVE_S)
3129                 cxd2841er_read_status_s(fe, &status);
3130         else if (priv->state == STATE_ACTIVE_TC)
3131                 cxd2841er_read_status_tc(fe, &status);
3132
3133         cxd2841er_read_signal_strength(fe);
3134
3135         if (status & FE_HAS_LOCK) {
3136                 cxd2841er_read_snr(fe);
3137                 cxd2841er_read_ucblocks(fe);
3138
3139                 cxd2841er_read_ber(fe);
3140         } else {
3141                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3142                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3143                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3144                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3145         }
3146         return 0;
3147 }
3148
3149 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3150 {
3151         int ret = 0, i, timeout, carr_offset;
3152         enum fe_status status;
3153         struct cxd2841er_priv *priv = fe->demodulator_priv;
3154         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3155         u32 symbol_rate = p->symbol_rate/1000;
3156
3157         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3158                 __func__,
3159                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3160                  p->frequency, symbol_rate, priv->xtal);
3161         switch (priv->state) {
3162         case STATE_SLEEP_S:
3163                 ret = cxd2841er_sleep_s_to_active_s(
3164                         priv, p->delivery_system, symbol_rate);
3165                 break;
3166         case STATE_ACTIVE_S:
3167                 ret = cxd2841er_retune_active(priv, p);
3168                 break;
3169         default:
3170                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3171                         __func__, priv->state);
3172                 ret = -EINVAL;
3173                 goto done;
3174         }
3175         if (ret) {
3176                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3177                 goto done;
3178         }
3179         if (fe->ops.i2c_gate_ctrl)
3180                 fe->ops.i2c_gate_ctrl(fe, 1);
3181         if (fe->ops.tuner_ops.set_params)
3182                 fe->ops.tuner_ops.set_params(fe);
3183         if (fe->ops.i2c_gate_ctrl)
3184                 fe->ops.i2c_gate_ctrl(fe, 0);
3185         cxd2841er_tune_done(priv);
3186         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3187         for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3188                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3189                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3190                 cxd2841er_read_status_s(fe, &status);
3191                 if (status & FE_HAS_LOCK)
3192                         break;
3193         }
3194         if (status & FE_HAS_LOCK) {
3195                 if (cxd2841er_get_carrier_offset_s_s2(
3196                                 priv, &carr_offset)) {
3197                         ret = -EINVAL;
3198                         goto done;
3199                 }
3200                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3201                         __func__, carr_offset);
3202         }
3203 done:
3204         /* Reset stats */
3205         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3206         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3207         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3208         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3209         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3210
3211         return ret;
3212 }
3213
3214 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3215 {
3216         int ret = 0, timeout;
3217         enum fe_status status;
3218         struct cxd2841er_priv *priv = fe->demodulator_priv;
3219         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3220
3221         dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3222                  __func__, p->delivery_system, p->bandwidth_hz);
3223         if (p->delivery_system == SYS_DVBT) {
3224                 priv->system = SYS_DVBT;
3225                 switch (priv->state) {
3226                 case STATE_SLEEP_TC:
3227                         ret = cxd2841er_sleep_tc_to_active_t(
3228                                 priv, p->bandwidth_hz);
3229                         break;
3230                 case STATE_ACTIVE_TC:
3231                         ret = cxd2841er_retune_active(priv, p);
3232                         break;
3233                 default:
3234                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3235                                 __func__, priv->state);
3236                         ret = -EINVAL;
3237                 }
3238         } else if (p->delivery_system == SYS_DVBT2) {
3239                 priv->system = SYS_DVBT2;
3240                 cxd2841er_dvbt2_set_plp_config(priv,
3241                         (int)(p->stream_id > 255), p->stream_id);
3242                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3243                 switch (priv->state) {
3244                 case STATE_SLEEP_TC:
3245                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3246                                 p->bandwidth_hz);
3247                         break;
3248                 case STATE_ACTIVE_TC:
3249                         ret = cxd2841er_retune_active(priv, p);
3250                         break;
3251                 default:
3252                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3253                                 __func__, priv->state);
3254                         ret = -EINVAL;
3255                 }
3256         } else if (p->delivery_system == SYS_ISDBT) {
3257                 priv->system = SYS_ISDBT;
3258                 switch (priv->state) {
3259                 case STATE_SLEEP_TC:
3260                         ret = cxd2841er_sleep_tc_to_active_i(
3261                                         priv, p->bandwidth_hz);
3262                         break;
3263                 case STATE_ACTIVE_TC:
3264                         ret = cxd2841er_retune_active(priv, p);
3265                         break;
3266                 default:
3267                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3268                                         __func__, priv->state);
3269                         ret = -EINVAL;
3270                 }
3271         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3272                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3273                 priv->system = SYS_DVBC_ANNEX_A;
3274                 /* correct bandwidth */
3275                 if (p->bandwidth_hz != 6000000 &&
3276                                 p->bandwidth_hz != 7000000 &&
3277                                 p->bandwidth_hz != 8000000) {
3278                         p->bandwidth_hz = 8000000;
3279                         dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3280                                         __func__, p->bandwidth_hz);
3281                 }
3282
3283                 switch (priv->state) {
3284                 case STATE_SLEEP_TC:
3285                         ret = cxd2841er_sleep_tc_to_active_c(
3286                                 priv, p->bandwidth_hz);
3287                         break;
3288                 case STATE_ACTIVE_TC:
3289                         ret = cxd2841er_retune_active(priv, p);
3290                         break;
3291                 default:
3292                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3293                                 __func__, priv->state);
3294                         ret = -EINVAL;
3295                 }
3296         } else {
3297                 dev_dbg(&priv->i2c->dev,
3298                         "%s(): invalid delivery system %d\n",
3299                         __func__, p->delivery_system);
3300                 ret = -EINVAL;
3301         }
3302         if (ret)
3303                 goto done;
3304         if (fe->ops.i2c_gate_ctrl)
3305                 fe->ops.i2c_gate_ctrl(fe, 1);
3306         if (fe->ops.tuner_ops.set_params)
3307                 fe->ops.tuner_ops.set_params(fe);
3308         if (fe->ops.i2c_gate_ctrl)
3309                 fe->ops.i2c_gate_ctrl(fe, 0);
3310         cxd2841er_tune_done(priv);
3311         timeout = 2500;
3312         while (timeout > 0) {
3313                 ret = cxd2841er_read_status_tc(fe, &status);
3314                 if (ret)
3315                         goto done;
3316                 if (status & FE_HAS_LOCK)
3317                         break;
3318                 msleep(20);
3319                 timeout -= 20;
3320         }
3321         if (timeout < 0)
3322                 dev_dbg(&priv->i2c->dev,
3323                         "%s(): LOCK wait timeout\n", __func__);
3324 done:
3325         return ret;
3326 }
3327
3328 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3329                             bool re_tune,
3330                             unsigned int mode_flags,
3331                             unsigned int *delay,
3332                             enum fe_status *status)
3333 {
3334         int ret, carrier_offset;
3335         struct cxd2841er_priv *priv = fe->demodulator_priv;
3336         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3337
3338         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3339         if (re_tune) {
3340                 ret = cxd2841er_set_frontend_s(fe);
3341                 if (ret)
3342                         return ret;
3343                 cxd2841er_read_status_s(fe, status);
3344                 if (*status & FE_HAS_LOCK) {
3345                         if (cxd2841er_get_carrier_offset_s_s2(
3346                                         priv, &carrier_offset))
3347                                 return -EINVAL;
3348                         p->frequency += carrier_offset;
3349                         ret = cxd2841er_set_frontend_s(fe);
3350                         if (ret)
3351                                 return ret;
3352                 }
3353         }
3354         *delay = HZ / 5;
3355         return cxd2841er_read_status_s(fe, status);
3356 }
3357
3358 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3359                              bool re_tune,
3360                              unsigned int mode_flags,
3361                              unsigned int *delay,
3362                              enum fe_status *status)
3363 {
3364         int ret, carrier_offset;
3365         struct cxd2841er_priv *priv = fe->demodulator_priv;
3366         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3367
3368         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3369                         re_tune, p->bandwidth_hz);
3370         if (re_tune) {
3371                 ret = cxd2841er_set_frontend_tc(fe);
3372                 if (ret)
3373                         return ret;
3374                 cxd2841er_read_status_tc(fe, status);
3375                 if (*status & FE_HAS_LOCK) {
3376                         switch (priv->system) {
3377                         case SYS_ISDBT:
3378                                 ret = cxd2841er_get_carrier_offset_i(
3379                                                 priv, p->bandwidth_hz,
3380                                                 &carrier_offset);
3381                                 break;
3382                         case SYS_DVBT:
3383                                 ret = cxd2841er_get_carrier_offset_t(
3384                                         priv, p->bandwidth_hz,
3385                                         &carrier_offset);
3386                                 break;
3387                         case SYS_DVBT2:
3388                                 ret = cxd2841er_get_carrier_offset_t2(
3389                                         priv, p->bandwidth_hz,
3390                                         &carrier_offset);
3391                                 break;
3392                         case SYS_DVBC_ANNEX_A:
3393                                 ret = cxd2841er_get_carrier_offset_c(
3394                                         priv, &carrier_offset);
3395                                 break;
3396                         default:
3397                                 dev_dbg(&priv->i2c->dev,
3398                                         "%s(): invalid delivery system %d\n",
3399                                         __func__, priv->system);
3400                                 return -EINVAL;
3401                         }
3402                         if (ret)
3403                                 return ret;
3404                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3405                                 __func__, carrier_offset);
3406                         p->frequency += carrier_offset;
3407                         ret = cxd2841er_set_frontend_tc(fe);
3408                         if (ret)
3409                                 return ret;
3410                 }
3411         }
3412         *delay = HZ / 5;
3413         return cxd2841er_read_status_tc(fe, status);
3414 }
3415
3416 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3417 {
3418         struct cxd2841er_priv *priv = fe->demodulator_priv;
3419
3420         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3421         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3422         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3423         return 0;
3424 }
3425
3426 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3427 {
3428         struct cxd2841er_priv *priv = fe->demodulator_priv;
3429
3430         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3431         if (priv->state == STATE_ACTIVE_TC) {
3432                 switch (priv->system) {
3433                 case SYS_DVBT:
3434                         cxd2841er_active_t_to_sleep_tc(priv);
3435                         break;
3436                 case SYS_DVBT2:
3437                         cxd2841er_active_t2_to_sleep_tc(priv);
3438                         break;
3439                 case SYS_ISDBT:
3440                         cxd2841er_active_i_to_sleep_tc(priv);
3441                         break;
3442                 case SYS_DVBC_ANNEX_A:
3443                         cxd2841er_active_c_to_sleep_tc(priv);
3444                         break;
3445                 default:
3446                         dev_warn(&priv->i2c->dev,
3447                                 "%s(): unknown delivery system %d\n",
3448                                 __func__, priv->system);
3449                 }
3450         }
3451         if (priv->state != STATE_SLEEP_TC) {
3452                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3453                         __func__, priv->state);
3454                 return -EINVAL;
3455         }
3456         cxd2841er_sleep_tc_to_shutdown(priv);
3457         return 0;
3458 }
3459
3460 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3461                                 enum fe_sec_mini_cmd burst)
3462 {
3463         u8 data;
3464         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3465
3466         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3467                 (burst == SEC_MINI_A ? "A" : "B"));
3468         if (priv->state != STATE_SLEEP_S &&
3469                         priv->state != STATE_ACTIVE_S) {
3470                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3471                         __func__, priv->state);
3472                 return -EINVAL;
3473         }
3474         data = (burst == SEC_MINI_A ? 0 : 1);
3475         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3476         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3477         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3478         return 0;
3479 }
3480
3481 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3482                               enum fe_sec_tone_mode tone)
3483 {
3484         u8 data;
3485         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3486
3487         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3488                 (tone == SEC_TONE_ON ? "On" : "Off"));
3489         if (priv->state != STATE_SLEEP_S &&
3490                         priv->state != STATE_ACTIVE_S) {
3491                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3492                         __func__, priv->state);
3493                 return -EINVAL;
3494         }
3495         data = (tone == SEC_TONE_ON ? 1 : 0);
3496         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3497         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3498         return 0;
3499 }
3500
3501 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3502                                      struct dvb_diseqc_master_cmd *cmd)
3503 {
3504         int i;
3505         u8 data[12];
3506         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3507
3508         if (priv->state != STATE_SLEEP_S &&
3509                         priv->state != STATE_ACTIVE_S) {
3510                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3511                         __func__, priv->state);
3512                 return -EINVAL;
3513         }
3514         dev_dbg(&priv->i2c->dev,
3515                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3516         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3517         /* DiDEqC enable */
3518         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3519         /* cmd1 length & data */
3520         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3521         memset(data, 0, sizeof(data));
3522         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3523                 data[i] = cmd->msg[i];
3524         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3525         /* repeat count for cmd1 */
3526         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3527         /* repeat count for cmd2: always 0 */
3528         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3529         /* start transmit */
3530         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3531         /* wait for 1 sec timeout */
3532         for (i = 0; i < 50; i++) {
3533                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3534                 if (!data[0]) {
3535                         dev_dbg(&priv->i2c->dev,
3536                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3537                         return 0;
3538                 }
3539                 msleep(20);
3540         }
3541         dev_dbg(&priv->i2c->dev,
3542                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3543         return -ETIMEDOUT;
3544 }
3545
3546 static void cxd2841er_release(struct dvb_frontend *fe)
3547 {
3548         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3549
3550         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3551         kfree(priv);
3552 }
3553
3554 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3555 {
3556         struct cxd2841er_priv *priv = fe->demodulator_priv;
3557
3558         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3559         cxd2841er_set_reg_bits(
3560                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3561         return 0;
3562 }
3563
3564 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3565 {
3566         struct cxd2841er_priv *priv = fe->demodulator_priv;
3567
3568         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3569         return DVBFE_ALGO_HW;
3570 }
3571
3572 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3573 {
3574         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3575
3576         p->strength.len = 1;
3577         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3578         p->cnr.len = 1;
3579         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3580         p->block_error.len = 1;
3581         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3582         p->post_bit_error.len = 1;
3583         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3584         p->post_bit_count.len = 1;
3585         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3586 }
3587
3588
3589 static int cxd2841er_init_s(struct dvb_frontend *fe)
3590 {
3591         struct cxd2841er_priv *priv = fe->demodulator_priv;
3592
3593         /* sanity. force demod to SHUTDOWN state */
3594         if (priv->state == STATE_SLEEP_S) {
3595                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3596                                 __func__);
3597                 cxd2841er_sleep_s_to_shutdown(priv);
3598         } else if (priv->state == STATE_ACTIVE_S) {
3599                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3600                                 __func__);
3601                 cxd2841er_active_s_to_sleep_s(priv);
3602                 cxd2841er_sleep_s_to_shutdown(priv);
3603         }
3604
3605         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3606         cxd2841er_shutdown_to_sleep_s(priv);
3607         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3608         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3609         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3610
3611         cxd2841er_init_stats(fe);
3612
3613         return 0;
3614 }
3615
3616 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3617 {
3618         struct cxd2841er_priv *priv = fe->demodulator_priv;
3619         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3620
3621         dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3622                         __func__, p->bandwidth_hz);
3623         cxd2841er_shutdown_to_sleep_tc(priv);
3624         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3625         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3626         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3627         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3628         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3629         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3630         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3631         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3632
3633         cxd2841er_init_stats(fe);
3634
3635         return 0;
3636 }
3637
3638 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3639 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3640
3641 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3642                                              struct i2c_adapter *i2c,
3643                                              u8 system)
3644 {
3645         u8 chip_id = 0;
3646         const char *type;
3647         const char *name;
3648         struct cxd2841er_priv *priv = NULL;
3649
3650         /* allocate memory for the internal state */
3651         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3652         if (!priv)
3653                 return NULL;
3654         priv->i2c = i2c;
3655         priv->config = cfg;
3656         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3657         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3658         priv->xtal = cfg->xtal;
3659         priv->frontend.demodulator_priv = priv;
3660         dev_info(&priv->i2c->dev,
3661                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3662                 __func__, priv->i2c,
3663                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3664         chip_id = cxd2841er_chip_id(priv);
3665         switch (chip_id) {
3666         case CXD2841ER_CHIP_ID:
3667                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3668                                 "Sony CXD2841ER DVB-T/T2/C demodulator");
3669                 name = "CXD2841ER";
3670                 break;
3671         case CXD2854ER_CHIP_ID:
3672                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3673                                 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3674                 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3675                 name = "CXD2854ER";
3676                 break;
3677         default:
3678                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3679                                 __func__, chip_id);
3680                 priv->frontend.demodulator_priv = NULL;
3681                 kfree(priv);
3682                 return NULL;
3683         }
3684
3685         /* create dvb_frontend */
3686         if (system == SYS_DVBS) {
3687                 memcpy(&priv->frontend.ops,
3688                         &cxd2841er_dvbs_s2_ops,
3689                         sizeof(struct dvb_frontend_ops));
3690                 type = "S/S2";
3691         } else {
3692                 memcpy(&priv->frontend.ops,
3693                         &cxd2841er_t_c_ops,
3694                         sizeof(struct dvb_frontend_ops));
3695                 type = "T/T2/C/ISDB-T";
3696         }
3697
3698         dev_info(&priv->i2c->dev,
3699                 "%s(): attaching %s DVB-%s frontend\n",
3700                 __func__, name, type);
3701         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3702                 __func__, chip_id);
3703         return &priv->frontend;
3704 }
3705
3706 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3707                                         struct i2c_adapter *i2c)
3708 {
3709         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3710 }
3711 EXPORT_SYMBOL(cxd2841er_attach_s);
3712
3713 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3714                                         struct i2c_adapter *i2c)
3715 {
3716         return cxd2841er_attach(cfg, i2c, 0);
3717 }
3718 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3719
3720 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3721         .delsys = { SYS_DVBS, SYS_DVBS2 },
3722         .info = {
3723                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3724                 .frequency_min  = 500000,
3725                 .frequency_max  = 2500000,
3726                 .frequency_stepsize     = 0,
3727                 .symbol_rate_min = 1000000,
3728                 .symbol_rate_max = 45000000,
3729                 .symbol_rate_tolerance = 500,
3730                 .caps = FE_CAN_INVERSION_AUTO |
3731                         FE_CAN_FEC_AUTO |
3732                         FE_CAN_QPSK,
3733         },
3734         .init = cxd2841er_init_s,
3735         .sleep = cxd2841er_sleep_s,
3736         .release = cxd2841er_release,
3737         .set_frontend = cxd2841er_set_frontend_s,
3738         .get_frontend = cxd2841er_get_frontend,
3739         .read_status = cxd2841er_read_status_s,
3740         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3741         .get_frontend_algo = cxd2841er_get_algo,
3742         .set_tone = cxd2841er_set_tone,
3743         .diseqc_send_burst = cxd2841er_send_burst,
3744         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3745         .tune = cxd2841er_tune_s
3746 };
3747
3748 static struct  dvb_frontend_ops cxd2841er_t_c_ops = {
3749         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3750         .info = {
3751                 .name   = "", /* will set in attach function */
3752                 .caps = FE_CAN_FEC_1_2 |
3753                         FE_CAN_FEC_2_3 |
3754                         FE_CAN_FEC_3_4 |
3755                         FE_CAN_FEC_5_6 |
3756                         FE_CAN_FEC_7_8 |
3757                         FE_CAN_FEC_AUTO |
3758                         FE_CAN_QPSK |
3759                         FE_CAN_QAM_16 |
3760                         FE_CAN_QAM_32 |
3761                         FE_CAN_QAM_64 |
3762                         FE_CAN_QAM_128 |
3763                         FE_CAN_QAM_256 |
3764                         FE_CAN_QAM_AUTO |
3765                         FE_CAN_TRANSMISSION_MODE_AUTO |
3766                         FE_CAN_GUARD_INTERVAL_AUTO |
3767                         FE_CAN_HIERARCHY_AUTO |
3768                         FE_CAN_MUTE_TS |
3769                         FE_CAN_2G_MODULATION,
3770                 .frequency_min = 42000000,
3771                 .frequency_max = 1002000000
3772         },
3773         .init = cxd2841er_init_tc,
3774         .sleep = cxd2841er_sleep_tc,
3775         .release = cxd2841er_release,
3776         .set_frontend = cxd2841er_set_frontend_tc,
3777         .get_frontend = cxd2841er_get_frontend,
3778         .read_status = cxd2841er_read_status_tc,
3779         .tune = cxd2841er_tune_tc,
3780         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3781         .get_frontend_algo = cxd2841er_get_algo
3782 };
3783
3784 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3785 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
3786 MODULE_LICENSE("GPL");