drivers/mailbox/mtk-cmdq-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2018 MediaTek Inc.
   4
   5 #include <linux/bitops.h>
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/errno.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/mailbox_controller.h>
  16 #include <linux/mailbox/mtk-cmdq-mailbox.h>
  17 #include <linux/of_device.h>
  18
  19 #define CMDQ_OP_CODE_MASK               (0xff << CMDQ_OP_CODE_SHIFT)
  20 #define CMDQ_IRQ_MASK                   0xffff
  21 #define CMDQ_NUM_CMD(t)                 (t->cmd_buf_size / CMDQ_INST_SIZE)
  22
  23 #define CMDQ_CURR_IRQ_STATUS            0x10
  24 #define CMDQ_THR_SLOT_CYCLES            0x30
  25 #define CMDQ_THR_BASE                   0x100
  26 #define CMDQ_THR_SIZE                   0x80
  27 #define CMDQ_THR_WARM_RESET             0x00
  28 #define CMDQ_THR_ENABLE_TASK            0x04
  29 #define CMDQ_THR_SUSPEND_TASK           0x08
  30 #define CMDQ_THR_CURR_STATUS            0x0c
  31 #define CMDQ_THR_IRQ_STATUS             0x10
  32 #define CMDQ_THR_IRQ_ENABLE             0x14
  33 #define CMDQ_THR_CURR_ADDR              0x20
  34 #define CMDQ_THR_END_ADDR               0x24
  35 #define CMDQ_THR_WAIT_TOKEN             0x30
  36 #define CMDQ_THR_PRIORITY               0x40
  37
  38 #define CMDQ_THR_ACTIVE_SLOT_CYCLES     0x3200
  39 #define CMDQ_THR_ENABLED                0x1
  40 #define CMDQ_THR_DISABLED               0x0
  41 #define CMDQ_THR_SUSPEND                0x1
  42 #define CMDQ_THR_RESUME                 0x0
  43 #define CMDQ_THR_STATUS_SUSPENDED       BIT(1)
  44 #define CMDQ_THR_DO_WARM_RESET          BIT(0)
  45 #define CMDQ_THR_IRQ_DONE               0x1
  46 #define CMDQ_THR_IRQ_ERROR              0x12
  47 #define CMDQ_THR_IRQ_EN                 (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
  48 #define CMDQ_THR_IS_WAITING             BIT(31)
  49
  50 #define CMDQ_JUMP_BY_OFFSET             0x10000000
  51 #define CMDQ_JUMP_BY_PA                 0x10000001
  52
  53 struct cmdq_thread {
  54         struct mbox_chan        *chan;
  55         void __iomem            *base;
  56         struct list_head        task_busy_list;
  57         u32                     priority;
  58         bool                    atomic_exec;
  59 };
  60
  61 struct cmdq_task {
  62         struct cmdq             *cmdq;
  63         struct list_head        list_entry;
  64         dma_addr_t              pa_base;
  65         struct cmdq_thread      *thread;
  66         struct cmdq_pkt         *pkt; /* the packet sent from mailbox client */
  67 };
  68
  69 struct cmdq {
  70         struct mbox_controller  mbox;
  71         void __iomem            *base;
  72         u32                     irq;
  73         u32                     thread_nr;
  74         struct cmdq_thread      *thread;
  75         struct clk              *clock;
  76         bool                    suspended;
  77 };
  78
  79 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
  80 {
  81         u32 status;
  82
  83         writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
  84
  85         /* If already disabled, treat as suspended successful. */
  86         if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
  87                 return 0;
  88
  89         if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
  90                         status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
  91                 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
  92                         (u32)(thread->base - cmdq->base));
  93                 return -EFAULT;
  94         }
  95
  96         return 0;
  97 }
  98
  99 static void cmdq_thread_resume(struct cmdq_thread *thread)
 100 {
 101         writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
 102 }
 103
 104 static void cmdq_init(struct cmdq *cmdq)
 105 {
 106         WARN_ON(clk_enable(cmdq->clock) < 0);
 107         writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 108         clk_disable(cmdq->clock);
 109 }
 110
 111 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
 112 {
 113         u32 warm_reset;
 114
 115         writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
 116         if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
 117                         warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
 118                         0, 10)) {
 119                 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
 120                         (u32)(thread->base - cmdq->base));
 121                 return -EFAULT;
 122         }
 123
 124         return 0;
 125 }
 126
 127 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
 128 {
 129         cmdq_thread_reset(cmdq, thread);
 130         writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
 131 }
 132
 133 /* notify GCE to re-fetch commands by setting GCE thread PC */
 134 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
 135 {
 136         writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
 137                thread->base + CMDQ_THR_CURR_ADDR);
 138 }
 139
 140 static void cmdq_task_insert_into_thread(struct cmdq_task *task)
 141 {
 142         struct device *dev = task->cmdq->mbox.dev;
 143         struct cmdq_thread *thread = task->thread;
 144         struct cmdq_task *prev_task = list_last_entry(
 145                         &thread->task_busy_list, typeof(*task), list_entry);
 146         u64 *prev_task_base = prev_task->pkt->va_base;
 147
 148         /* let previous task jump to this task */
 149         dma_sync_single_for_cpu(dev, prev_task->pa_base,
 150                                 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 151         prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
 152                 (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
 153         dma_sync_single_for_device(dev, prev_task->pa_base,
 154                                    prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 155
 156         cmdq_thread_invalidate_fetched_data(thread);
 157 }
 158
 159 static bool cmdq_command_is_wfe(u64 cmd)
 160 {
 161         u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
 162         u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
 163         u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0xffffffff;
 164
 165         return ((cmd & wfe_mask) == (wfe_op | wfe_option));
 166 }
 167
 168 /* we assume tasks in the same display GCE thread are waiting the same event. */
 169 static void cmdq_task_remove_wfe(struct cmdq_task *task)
 170 {
 171         struct device *dev = task->cmdq->mbox.dev;
 172         u64 *base = task->pkt->va_base;
 173         int i;
 174
 175         dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
 176                                 DMA_TO_DEVICE);
 177         for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
 178                 if (cmdq_command_is_wfe(base[i]))
 179                         base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
 180                                   CMDQ_JUMP_PASS;
 181         dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
 182                                    DMA_TO_DEVICE);
 183 }
 184
 185 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
 186 {
 187         return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
 188 }
 189
 190 static void cmdq_thread_wait_end(struct cmdq_thread *thread,
 191                                  unsigned long end_pa)
 192 {
 193         struct device *dev = thread->chan->mbox->dev;
 194         unsigned long curr_pa;
 195
 196         if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
 197                         curr_pa, curr_pa == end_pa, 1, 20))
 198                 dev_err(dev, "GCE thread cannot run to end.\n");
 199 }
 200
 201 static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta)
 202 {
 203         struct cmdq_task_cb *cb = &task->pkt->async_cb;
 204         struct cmdq_cb_data data;
 205
 206         WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL);
 207         data.sta = sta;
 208         data.data = cb->data;
 209         cb->cb(data);
 210
 211         list_del(&task->list_entry);
 212 }
 213
 214 static void cmdq_task_handle_error(struct cmdq_task *task)
 215 {
 216         struct cmdq_thread *thread = task->thread;
 217         struct cmdq_task *next_task;
 218
 219         dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
 220         WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
 221         next_task = list_first_entry_or_null(&thread->task_busy_list,
 222                         struct cmdq_task, list_entry);
 223         if (next_task)
 224                 writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
 225         cmdq_thread_resume(thread);
 226 }
 227
 228 static void cmdq_thread_irq_handler(struct cmdq *cmdq,
 229                                     struct cmdq_thread *thread)
 230 {
 231         struct cmdq_task *task, *tmp, *curr_task = NULL;
 232         u32 curr_pa, irq_flag, task_end_pa;
 233         bool err;
 234
 235         irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
 236         writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
 237
 238         /*
 239          * When ISR call this function, another CPU core could run
 240          * "release task" right before we acquire the spin lock, and thus
 241          * reset / disable this GCE thread, so we need to check the enable
 242          * bit of this GCE thread.
 243          */
 244         if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
 245                 return;
 246
 247         if (irq_flag & CMDQ_THR_IRQ_ERROR)
 248                 err = true;
 249         else if (irq_flag & CMDQ_THR_IRQ_DONE)
 250                 err = false;
 251         else
 252                 return;
 253
 254         curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
 255
 256         list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
 257                                  list_entry) {
 258                 task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
 259                 if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
 260                         curr_task = task;
 261
 262                 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
 263                         cmdq_task_exec_done(task, CMDQ_CB_NORMAL);
 264                         kfree(task);
 265                 } else if (err) {
 266                         cmdq_task_exec_done(task, CMDQ_CB_ERROR);
 267                         cmdq_task_handle_error(curr_task);
 268                         kfree(task);
 269                 }
 270
 271                 if (curr_task)
 272                         break;
 273         }
 274
 275         if (list_empty(&thread->task_busy_list)) {
 276                 cmdq_thread_disable(cmdq, thread);
 277                 clk_disable(cmdq->clock);
 278         }
 279 }
 280
 281 static irqreturn_t cmdq_irq_handler(int irq, void *dev)
 282 {
 283         struct cmdq *cmdq = dev;
 284         unsigned long irq_status, flags = 0L;
 285         int bit;
 286
 287         irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
 288         if (!(irq_status ^ CMDQ_IRQ_MASK))
 289                 return IRQ_NONE;
 290
 291         for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {
 292                 struct cmdq_thread *thread = &cmdq->thread[bit];
 293
 294                 spin_lock_irqsave(&thread->chan->lock, flags);
 295                 cmdq_thread_irq_handler(cmdq, thread);
 296                 spin_unlock_irqrestore(&thread->chan->lock, flags);
 297         }
 298
 299         return IRQ_HANDLED;
 300 }
 301
 302 static int cmdq_suspend(struct device *dev)
 303 {
 304         struct cmdq *cmdq = dev_get_drvdata(dev);
 305         struct cmdq_thread *thread;
 306         int i;
 307         bool task_running = false;
 308
 309         cmdq->suspended = true;
 310
 311         for (i = 0; i < cmdq->thread_nr; i++) {
 312                 thread = &cmdq->thread[i];
 313                 if (!list_empty(&thread->task_busy_list)) {
 314                         task_running = true;
 315                         break;
 316                 }
 317         }
 318
 319         if (task_running)
 320                 dev_warn(dev, "exist running task(s) in suspend\n");
 321
 322         clk_unprepare(cmdq->clock);
 323
 324         return 0;
 325 }
 326
 327 static int cmdq_resume(struct device *dev)
 328 {
 329         struct cmdq *cmdq = dev_get_drvdata(dev);
 330
 331         WARN_ON(clk_prepare(cmdq->clock) < 0);
 332         cmdq->suspended = false;
 333         return 0;
 334 }
 335
 336 static int cmdq_remove(struct platform_device *pdev)
 337 {
 338         struct cmdq *cmdq = platform_get_drvdata(pdev);
 339
 340         mbox_controller_unregister(&cmdq->mbox);
 341         clk_unprepare(cmdq->clock);
 342
 343         if (cmdq->mbox.chans)
 344                 devm_kfree(&pdev->dev, cmdq->mbox.chans);
 345
 346         if (cmdq->thread)
 347                 devm_kfree(&pdev->dev, cmdq->thread);
 348
 349         devm_kfree(&pdev->dev, cmdq);
 350
 351         return 0;
 352 }
 353
 354 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 355 {
 356         struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
 357         struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
 358         struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
 359         struct cmdq_task *task;
 360         unsigned long curr_pa, end_pa;
 361
 362         /* Client should not flush new tasks if suspended. */
 363         WARN_ON(cmdq->suspended);
 364
 365         task = kzalloc(sizeof(*task), GFP_ATOMIC);
 366         if (!task)
 367                 return -ENOMEM;
 368
 369         task->cmdq = cmdq;
 370         INIT_LIST_HEAD(&task->list_entry);
 371         task->pa_base = pkt->pa_base;
 372         task->thread = thread;
 373         task->pkt = pkt;
 374
 375         if (list_empty(&thread->task_busy_list)) {
 376                 WARN_ON(clk_enable(cmdq->clock) < 0);
 377                 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
 378
 379                 writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
 380                 writel(task->pa_base + pkt->cmd_buf_size,
 381                        thread->base + CMDQ_THR_END_ADDR);
 382                 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
 383                 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
 384                 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
 385         } else {
 386                 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 387                 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
 388                 end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
 389
 390                 /*
 391                  * Atomic execution should remove the following wfe, i.e. only
 392                  * wait event at first task, and prevent to pause when running.
 393                  */
 394                 if (thread->atomic_exec) {
 395                         /* GCE is executing if command is not WFE */
 396                         if (!cmdq_thread_is_in_wfe(thread)) {
 397                                 cmdq_thread_resume(thread);
 398                                 cmdq_thread_wait_end(thread, end_pa);
 399                                 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 400                                 /* set to this task directly */
 401                                 writel(task->pa_base,
 402                                        thread->base + CMDQ_THR_CURR_ADDR);
 403                         } else {
 404                                 cmdq_task_insert_into_thread(task);
 405                                 cmdq_task_remove_wfe(task);
 406                                 smp_mb(); /* modify jump before enable thread */
 407                         }
 408                 } else {
 409                         /* check boundary */
 410                         if (curr_pa == end_pa - CMDQ_INST_SIZE ||
 411                             curr_pa == end_pa) {
 412                                 /* set to this task directly */
 413                                 writel(task->pa_base,
 414                                        thread->base + CMDQ_THR_CURR_ADDR);
 415                         } else {
 416                                 cmdq_task_insert_into_thread(task);
 417                                 smp_mb(); /* modify jump before enable thread */
 418                         }
 419                 }
 420                 writel(task->pa_base + pkt->cmd_buf_size,
 421                        thread->base + CMDQ_THR_END_ADDR);
 422                 cmdq_thread_resume(thread);
 423         }
 424         list_move_tail(&task->list_entry, &thread->task_busy_list);
 425
 426         return 0;
 427 }
 428
 429 static int cmdq_mbox_startup(struct mbox_chan *chan)
 430 {
 431         return 0;
 432 }
 433
 434 static void cmdq_mbox_shutdown(struct mbox_chan *chan)
 435 {
 436 }
 437
 438 static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
 439         .send_data = cmdq_mbox_send_data,
 440         .startup = cmdq_mbox_startup,
 441         .shutdown = cmdq_mbox_shutdown,
 442 };
 443
 444 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
 445                 const struct of_phandle_args *sp)
 446 {
 447         int ind = sp->args[0];
 448         struct cmdq_thread *thread;
 449
 450         if (ind >= mbox->num_chans)
 451                 return ERR_PTR(-EINVAL);
 452
 453         thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
 454         thread->priority = sp->args[1];
 455         thread->atomic_exec = (sp->args[2] != 0);
 456         thread->chan = &mbox->chans[ind];
 457
 458         return &mbox->chans[ind];
 459 }
 460
 461 static int cmdq_probe(struct platform_device *pdev)
 462 {
 463         struct device *dev = &pdev->dev;
 464         struct resource *res;
 465         struct cmdq *cmdq;
 466         int err, i;
 467
 468         cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
 469         if (!cmdq)
 470                 return -ENOMEM;
 471
 472         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 473         cmdq->base = devm_ioremap_resource(dev, res);
 474         if (IS_ERR(cmdq->base)) {
 475                 dev_err(dev, "failed to ioremap gce\n");
 476                 return PTR_ERR(cmdq->base);
 477         }
 478
 479         cmdq->irq = platform_get_irq(pdev, 0);
 480         if (!cmdq->irq) {
 481                 dev_err(dev, "failed to get irq\n");
 482                 return -EINVAL;
 483         }
 484         err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
 485                                "mtk_cmdq", cmdq);
 486         if (err < 0) {
 487                 dev_err(dev, "failed to register ISR (%d)\n", err);
 488                 return err;
 489         }
 490
 491         dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
 492                 dev, cmdq->base, cmdq->irq);
 493
 494         cmdq->clock = devm_clk_get(dev, "gce");
 495         if (IS_ERR(cmdq->clock)) {
 496                 dev_err(dev, "failed to get gce clk\n");
 497                 return PTR_ERR(cmdq->clock);
 498         }
 499
 500         cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
 501         cmdq->mbox.dev = dev;
 502         cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
 503                                         sizeof(*cmdq->mbox.chans), GFP_KERNEL);
 504         if (!cmdq->mbox.chans)
 505                 return -ENOMEM;
 506
 507         cmdq->mbox.num_chans = cmdq->thread_nr;
 508         cmdq->mbox.ops = &cmdq_mbox_chan_ops;
 509         cmdq->mbox.of_xlate = cmdq_xlate;
 510
 511         /* make use of TXDONE_BY_ACK */
 512         cmdq->mbox.txdone_irq = false;
 513         cmdq->mbox.txdone_poll = false;
 514
 515         cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
 516                                         sizeof(*cmdq->thread), GFP_KERNEL);
 517         if (!cmdq->thread)
 518                 return -ENOMEM;
 519
 520         for (i = 0; i < cmdq->thread_nr; i++) {
 521                 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
 522                                 CMDQ_THR_SIZE * i;
 523                 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
 524                 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
 525         }
 526
 527         err = mbox_controller_register(&cmdq->mbox);
 528         if (err < 0) {
 529                 dev_err(dev, "failed to register mailbox: %d\n", err);
 530                 return err;
 531         }
 532
 533         platform_set_drvdata(pdev, cmdq);
 534         WARN_ON(clk_prepare(cmdq->clock) < 0);
 535
 536         cmdq_init(cmdq);
 537
 538         return 0;
 539 }
 540
 541 static const struct dev_pm_ops cmdq_pm_ops = {
 542         .suspend = cmdq_suspend,
 543         .resume = cmdq_resume,
 544 };
 545
 546 static const struct of_device_id cmdq_of_ids[] = {
 547         {.compatible = "mediatek,mt8173-gce", .data = (void *)16},
 548         {}
 549 };
 550
 551 static struct platform_driver cmdq_drv = {
 552         .probe = cmdq_probe,
 553         .remove = cmdq_remove,
 554         .driver = {
 555                 .name = "mtk_cmdq",
 556                 .pm = &cmdq_pm_ops,
 557                 .of_match_table = cmdq_of_ids,
 558         }
 559 };
 560
 561 static int __init cmdq_drv_init(void)
 562 {
 563         return platform_driver_register(&cmdq_drv);
 564 }
 565
 566 static void __exit cmdq_drv_exit(void)
 567 {
 568         platform_driver_unregister(&cmdq_drv);
 569 }
 570
 571 subsys_initcall(cmdq_drv_init);
 572 module_exit(cmdq_drv_exit);
 573
 574 MODULE_LICENSE("GPL v2");