2 * linux/arch/arm/common/gic.c
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Interrupt architecture for the GIC:
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/err.h>
28 #include <linux/module.h>
29 #include <linux/list.h>
30 #include <linux/smp.h>
31 #include <linux/cpu.h>
32 #include <linux/cpu_pm.h>
33 #include <linux/cpumask.h>
36 #include <linux/of_address.h>
37 #include <linux/of_irq.h>
38 #include <linux/irqdomain.h>
39 #include <linux/interrupt.h>
40 #include <linux/percpu.h>
41 #include <linux/slab.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
45 #include <asm/cputype.h>
47 #include <asm/exception.h>
48 #include <asm/smp_plat.h>
50 #include "irq-gic-common.h"
54 void __iomem *common_base;
55 void __percpu * __iomem *percpu_base;
58 struct gic_chip_data {
59 union gic_base dist_base;
60 union gic_base cpu_base;
62 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
63 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
64 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
65 u32 __percpu *saved_ppi_enable;
66 u32 __percpu *saved_ppi_conf;
68 struct irq_domain *domain;
69 unsigned int gic_irqs;
70 #ifdef CONFIG_GIC_NON_BANKED
71 void __iomem *(*get_base)(union gic_base *);
75 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
78 * The GIC mapping of CPU interfaces does not necessarily match
79 * the logical CPU numbering. Let's use a mapping as returned
82 #define NR_GIC_CPU_IF 8
83 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
86 * Supported arch specific GIC irq extension.
87 * Default make them NULL.
89 struct irq_chip gic_arch_extn = {
93 .irq_retrigger = NULL,
102 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
104 #ifdef CONFIG_GIC_NON_BANKED
105 static void __iomem *gic_get_percpu_base(union gic_base *base)
107 return *__this_cpu_ptr(base->percpu_base);
110 static void __iomem *gic_get_common_base(union gic_base *base)
112 return base->common_base;
115 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
117 return data->get_base(&data->dist_base);
120 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
122 return data->get_base(&data->cpu_base);
125 static inline void gic_set_base_accessor(struct gic_chip_data *data,
126 void __iomem *(*f)(union gic_base *))
131 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
132 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
133 #define gic_set_base_accessor(d, f)
136 static inline void __iomem *gic_dist_base(struct irq_data *d)
138 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
139 return gic_data_dist_base(gic_data);
142 static inline void __iomem *gic_cpu_base(struct irq_data *d)
144 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
145 return gic_data_cpu_base(gic_data);
148 static inline unsigned int gic_irq(struct irq_data *d)
154 * Routines to acknowledge, disable and enable interrupts
156 static void gic_mask_irq(struct irq_data *d)
158 u32 mask = 1 << (gic_irq(d) % 32);
160 raw_spin_lock(&irq_controller_lock);
161 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
162 if (gic_arch_extn.irq_mask)
163 gic_arch_extn.irq_mask(d);
164 raw_spin_unlock(&irq_controller_lock);
167 static void gic_unmask_irq(struct irq_data *d)
169 u32 mask = 1 << (gic_irq(d) % 32);
171 raw_spin_lock(&irq_controller_lock);
172 if (gic_arch_extn.irq_unmask)
173 gic_arch_extn.irq_unmask(d);
174 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
175 raw_spin_unlock(&irq_controller_lock);
178 static void gic_eoi_irq(struct irq_data *d)
180 if (gic_arch_extn.irq_eoi) {
181 raw_spin_lock(&irq_controller_lock);
182 gic_arch_extn.irq_eoi(d);
183 raw_spin_unlock(&irq_controller_lock);
186 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
189 static int gic_set_type(struct irq_data *d, unsigned int type)
191 void __iomem *base = gic_dist_base(d);
192 unsigned int gicirq = gic_irq(d);
194 /* Interrupt configuration for SGIs can't be changed */
198 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
201 raw_spin_lock(&irq_controller_lock);
203 if (gic_arch_extn.irq_set_type)
204 gic_arch_extn.irq_set_type(d, type);
206 gic_configure_irq(gicirq, type, base, NULL);
208 raw_spin_unlock(&irq_controller_lock);
213 static int gic_retrigger(struct irq_data *d)
215 if (gic_arch_extn.irq_retrigger)
216 return gic_arch_extn.irq_retrigger(d);
218 /* the genirq layer expects 0 if we can't retrigger in hardware */
223 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
226 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
227 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
231 cpu = cpumask_any_and(mask_val, cpu_online_mask);
233 cpu = cpumask_first(mask_val);
235 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
238 raw_spin_lock(&irq_controller_lock);
239 mask = 0xff << shift;
240 bit = gic_cpu_map[cpu] << shift;
241 val = readl_relaxed(reg) & ~mask;
242 writel_relaxed(val | bit, reg);
243 raw_spin_unlock(&irq_controller_lock);
245 return IRQ_SET_MASK_OK;
250 static int gic_set_wake(struct irq_data *d, unsigned int on)
254 if (gic_arch_extn.irq_set_wake)
255 ret = gic_arch_extn.irq_set_wake(d, on);
261 #define gic_set_wake NULL
264 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
267 struct gic_chip_data *gic = &gic_data[0];
268 void __iomem *cpu_base = gic_data_cpu_base(gic);
271 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
272 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
274 if (likely(irqnr > 15 && irqnr < 1021)) {
275 irqnr = irq_find_mapping(gic->domain, irqnr);
276 handle_IRQ(irqnr, regs);
280 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
282 handle_IPI(irqnr, regs);
290 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
292 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
293 struct irq_chip *chip = irq_get_chip(irq);
294 unsigned int cascade_irq, gic_irq;
295 unsigned long status;
297 chained_irq_enter(chip, desc);
299 raw_spin_lock(&irq_controller_lock);
300 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
301 raw_spin_unlock(&irq_controller_lock);
303 gic_irq = (status & 0x3ff);
307 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
308 if (unlikely(gic_irq < 32 || gic_irq > 1020))
309 handle_bad_irq(cascade_irq, desc);
311 generic_handle_irq(cascade_irq);
314 chained_irq_exit(chip, desc);
317 static struct irq_chip gic_chip = {
319 .irq_mask = gic_mask_irq,
320 .irq_unmask = gic_unmask_irq,
321 .irq_eoi = gic_eoi_irq,
322 .irq_set_type = gic_set_type,
323 .irq_retrigger = gic_retrigger,
325 .irq_set_affinity = gic_set_affinity,
327 .irq_set_wake = gic_set_wake,
330 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
332 if (gic_nr >= MAX_GIC_NR)
334 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
336 irq_set_chained_handler(irq, gic_handle_cascade_irq);
339 static u8 gic_get_cpumask(struct gic_chip_data *gic)
341 void __iomem *base = gic_data_dist_base(gic);
344 for (i = mask = 0; i < 32; i += 4) {
345 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
353 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
358 static void __init gic_dist_init(struct gic_chip_data *gic)
362 unsigned int gic_irqs = gic->gic_irqs;
363 void __iomem *base = gic_data_dist_base(gic);
365 writel_relaxed(0, base + GIC_DIST_CTRL);
368 * Set all global interrupts to this CPU only.
370 cpumask = gic_get_cpumask(gic);
371 cpumask |= cpumask << 8;
372 cpumask |= cpumask << 16;
373 for (i = 32; i < gic_irqs; i += 4)
374 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
376 gic_dist_config(base, gic_irqs, NULL);
378 writel_relaxed(1, base + GIC_DIST_CTRL);
381 static void gic_cpu_init(struct gic_chip_data *gic)
383 void __iomem *dist_base = gic_data_dist_base(gic);
384 void __iomem *base = gic_data_cpu_base(gic);
385 unsigned int cpu_mask, cpu = smp_processor_id();
389 * Get what the GIC says our CPU mask is.
391 BUG_ON(cpu >= NR_GIC_CPU_IF);
392 cpu_mask = gic_get_cpumask(gic);
393 gic_cpu_map[cpu] = cpu_mask;
396 * Clear our mask from the other map entries in case they're
399 for (i = 0; i < NR_GIC_CPU_IF; i++)
401 gic_cpu_map[i] &= ~cpu_mask;
403 gic_cpu_config(dist_base, NULL);
405 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
406 writel_relaxed(1, base + GIC_CPU_CTRL);
409 void gic_cpu_if_down(void)
411 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
412 writel_relaxed(0, cpu_base + GIC_CPU_CTRL);
417 * Saves the GIC distributor registers during suspend or idle. Must be called
418 * with interrupts disabled but before powering down the GIC. After calling
419 * this function, no interrupts will be delivered by the GIC, and another
420 * platform-specific wakeup source must be enabled.
422 static void gic_dist_save(unsigned int gic_nr)
424 unsigned int gic_irqs;
425 void __iomem *dist_base;
428 if (gic_nr >= MAX_GIC_NR)
431 gic_irqs = gic_data[gic_nr].gic_irqs;
432 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
437 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
438 gic_data[gic_nr].saved_spi_conf[i] =
439 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
441 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
442 gic_data[gic_nr].saved_spi_target[i] =
443 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
445 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
446 gic_data[gic_nr].saved_spi_enable[i] =
447 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
451 * Restores the GIC distributor registers during resume or when coming out of
452 * idle. Must be called before enabling interrupts. If a level interrupt
453 * that occured while the GIC was suspended is still present, it will be
454 * handled normally, but any edge interrupts that occured will not be seen by
455 * the GIC and need to be handled by the platform-specific wakeup source.
457 static void gic_dist_restore(unsigned int gic_nr)
459 unsigned int gic_irqs;
461 void __iomem *dist_base;
463 if (gic_nr >= MAX_GIC_NR)
466 gic_irqs = gic_data[gic_nr].gic_irqs;
467 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
472 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
474 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
475 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
476 dist_base + GIC_DIST_CONFIG + i * 4);
478 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
479 writel_relaxed(0xa0a0a0a0,
480 dist_base + GIC_DIST_PRI + i * 4);
482 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
483 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
484 dist_base + GIC_DIST_TARGET + i * 4);
486 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
487 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
488 dist_base + GIC_DIST_ENABLE_SET + i * 4);
490 writel_relaxed(1, dist_base + GIC_DIST_CTRL);
493 static void gic_cpu_save(unsigned int gic_nr)
497 void __iomem *dist_base;
498 void __iomem *cpu_base;
500 if (gic_nr >= MAX_GIC_NR)
503 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
504 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
506 if (!dist_base || !cpu_base)
509 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
510 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
511 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
513 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
514 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
515 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
519 static void gic_cpu_restore(unsigned int gic_nr)
523 void __iomem *dist_base;
524 void __iomem *cpu_base;
526 if (gic_nr >= MAX_GIC_NR)
529 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
530 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
532 if (!dist_base || !cpu_base)
535 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
536 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
537 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
539 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
540 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
541 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
543 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
544 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
546 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
547 writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
550 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
554 for (i = 0; i < MAX_GIC_NR; i++) {
555 #ifdef CONFIG_GIC_NON_BANKED
556 /* Skip over unused GICs */
557 if (!gic_data[i].get_base)
564 case CPU_PM_ENTER_FAILED:
568 case CPU_CLUSTER_PM_ENTER:
571 case CPU_CLUSTER_PM_ENTER_FAILED:
572 case CPU_CLUSTER_PM_EXIT:
581 static struct notifier_block gic_notifier_block = {
582 .notifier_call = gic_notifier,
585 static void __init gic_pm_init(struct gic_chip_data *gic)
587 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
589 BUG_ON(!gic->saved_ppi_enable);
591 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
593 BUG_ON(!gic->saved_ppi_conf);
595 if (gic == &gic_data[0])
596 cpu_pm_register_notifier(&gic_notifier_block);
599 static void __init gic_pm_init(struct gic_chip_data *gic)
605 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
608 unsigned long flags, map = 0;
610 raw_spin_lock_irqsave(&irq_controller_lock, flags);
612 /* Convert our logical CPU mask into a physical one. */
613 for_each_cpu(cpu, mask)
614 map |= gic_cpu_map[cpu];
617 * Ensure that stores to Normal memory are visible to the
618 * other CPUs before they observe us issuing the IPI.
622 /* this always happens on GIC0 */
623 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
625 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
629 #ifdef CONFIG_BL_SWITCHER
631 * gic_send_sgi - send a SGI directly to given CPU interface number
633 * cpu_id: the ID for the destination CPU interface
634 * irq: the IPI number to send a SGI for
636 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
638 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
639 cpu_id = 1 << cpu_id;
640 /* this always happens on GIC0 */
641 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
645 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
647 * @cpu: the logical CPU number to get the GIC ID for.
649 * Return the CPU interface ID for the given logical CPU number,
650 * or -1 if the CPU number is too large or the interface ID is
651 * unknown (more than one bit set).
653 int gic_get_cpu_id(unsigned int cpu)
655 unsigned int cpu_bit;
657 if (cpu >= NR_GIC_CPU_IF)
659 cpu_bit = gic_cpu_map[cpu];
660 if (cpu_bit & (cpu_bit - 1))
662 return __ffs(cpu_bit);
666 * gic_migrate_target - migrate IRQs to another CPU interface
668 * @new_cpu_id: the CPU target ID to migrate IRQs to
670 * Migrate all peripheral interrupts with a target matching the current CPU
671 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
672 * is also updated. Targets to other CPU interfaces are unchanged.
673 * This must be called with IRQs locally disabled.
675 void gic_migrate_target(unsigned int new_cpu_id)
677 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
678 void __iomem *dist_base;
679 int i, ror_val, cpu = smp_processor_id();
680 u32 val, cur_target_mask, active_mask;
682 if (gic_nr >= MAX_GIC_NR)
685 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
688 gic_irqs = gic_data[gic_nr].gic_irqs;
690 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
691 cur_target_mask = 0x01010101 << cur_cpu_id;
692 ror_val = (cur_cpu_id - new_cpu_id) & 31;
694 raw_spin_lock(&irq_controller_lock);
696 /* Update the target interface for this logical CPU */
697 gic_cpu_map[cpu] = 1 << new_cpu_id;
700 * Find all the peripheral interrupts targetting the current
701 * CPU interface and migrate them to the new CPU interface.
702 * We skip DIST_TARGET 0 to 7 as they are read-only.
704 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
705 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
706 active_mask = val & cur_target_mask;
709 val |= ror32(active_mask, ror_val);
710 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
714 raw_spin_unlock(&irq_controller_lock);
717 * Now let's migrate and clear any potential SGIs that might be
718 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
719 * is a banked register, we can only forward the SGI using
720 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
721 * doesn't use that information anyway.
723 * For the same reason we do not adjust SGI source information
724 * for previously sent SGIs by us to other CPUs either.
726 for (i = 0; i < 16; i += 4) {
728 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
731 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
732 for (j = i; j < i + 4; j++) {
734 writel_relaxed((1 << (new_cpu_id + 16)) | j,
735 dist_base + GIC_DIST_SOFTINT);
742 * gic_get_sgir_physaddr - get the physical address for the SGI register
744 * REturn the physical address of the SGI register to be used
745 * by some early assembly code when the kernel is not yet available.
747 static unsigned long gic_dist_physaddr;
749 unsigned long gic_get_sgir_physaddr(void)
751 if (!gic_dist_physaddr)
753 return gic_dist_physaddr + GIC_DIST_SOFTINT;
756 void __init gic_init_physaddr(struct device_node *node)
759 if (of_address_to_resource(node, 0, &res) == 0) {
760 gic_dist_physaddr = res.start;
761 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
766 #define gic_init_physaddr(node) do { } while (0)
769 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
773 irq_set_percpu_devid(irq);
774 irq_set_chip_and_handler(irq, &gic_chip,
775 handle_percpu_devid_irq);
776 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
778 irq_set_chip_and_handler(irq, &gic_chip,
780 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
782 gic_routable_irq_domain_ops->map(d, irq, hw);
784 irq_set_chip_data(irq, d->host_data);
788 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
790 gic_routable_irq_domain_ops->unmap(d, irq);
793 static int gic_irq_domain_xlate(struct irq_domain *d,
794 struct device_node *controller,
795 const u32 *intspec, unsigned int intsize,
796 unsigned long *out_hwirq, unsigned int *out_type)
798 unsigned long ret = 0;
800 if (d->of_node != controller)
805 /* Get the interrupt number and add 16 to skip over SGIs */
806 *out_hwirq = intspec[1] + 16;
808 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
810 ret = gic_routable_irq_domain_ops->xlate(d, controller,
816 if (IS_ERR_VALUE(ret))
820 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
826 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
829 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
830 gic_cpu_init(&gic_data[0]);
835 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
836 * priority because the GIC needs to be up before the ARM generic timers.
838 static struct notifier_block gic_cpu_notifier = {
839 .notifier_call = gic_secondary_init,
844 static const struct irq_domain_ops gic_irq_domain_ops = {
845 .map = gic_irq_domain_map,
846 .unmap = gic_irq_domain_unmap,
847 .xlate = gic_irq_domain_xlate,
850 /* Default functions for routable irq domain */
851 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
857 static void gic_routable_irq_domain_unmap(struct irq_domain *d,
862 static int gic_routable_irq_domain_xlate(struct irq_domain *d,
863 struct device_node *controller,
864 const u32 *intspec, unsigned int intsize,
865 unsigned long *out_hwirq,
866 unsigned int *out_type)
872 const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
873 .map = gic_routable_irq_domain_map,
874 .unmap = gic_routable_irq_domain_unmap,
875 .xlate = gic_routable_irq_domain_xlate,
878 const struct irq_domain_ops *gic_routable_irq_domain_ops =
879 &gic_default_routable_irq_domain_ops;
881 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
882 void __iomem *dist_base, void __iomem *cpu_base,
883 u32 percpu_offset, struct device_node *node)
885 irq_hw_number_t hwirq_base;
886 struct gic_chip_data *gic;
887 int gic_irqs, irq_base, i;
888 int nr_routable_irqs;
890 BUG_ON(gic_nr >= MAX_GIC_NR);
892 gic = &gic_data[gic_nr];
893 #ifdef CONFIG_GIC_NON_BANKED
894 if (percpu_offset) { /* Frankein-GIC without banked registers... */
897 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
898 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
899 if (WARN_ON(!gic->dist_base.percpu_base ||
900 !gic->cpu_base.percpu_base)) {
901 free_percpu(gic->dist_base.percpu_base);
902 free_percpu(gic->cpu_base.percpu_base);
906 for_each_possible_cpu(cpu) {
907 u32 mpidr = cpu_logical_map(cpu);
908 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
909 unsigned long offset = percpu_offset * core_id;
910 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
911 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
914 gic_set_base_accessor(gic, gic_get_percpu_base);
917 { /* Normal, sane GIC... */
919 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
921 gic->dist_base.common_base = dist_base;
922 gic->cpu_base.common_base = cpu_base;
923 gic_set_base_accessor(gic, gic_get_common_base);
927 * Initialize the CPU interface map to all CPUs.
928 * It will be refined as each CPU probes its ID.
930 for (i = 0; i < NR_GIC_CPU_IF; i++)
931 gic_cpu_map[i] = 0xff;
934 * For primary GICs, skip over SGIs.
935 * For secondary GICs, skip over PPIs, too.
937 if (gic_nr == 0 && (irq_start & 31) > 0) {
940 irq_start = (irq_start & ~31) + 16;
946 * Find out how many interrupts are supported.
947 * The GIC only supports up to 1020 interrupt sources.
949 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
950 gic_irqs = (gic_irqs + 1) * 32;
953 gic->gic_irqs = gic_irqs;
955 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
957 if (of_property_read_u32(node, "arm,routable-irqs",
958 &nr_routable_irqs)) {
959 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
961 if (IS_ERR_VALUE(irq_base)) {
962 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
964 irq_base = irq_start;
967 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
968 hwirq_base, &gic_irq_domain_ops, gic);
970 gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
975 if (WARN_ON(!gic->domain))
980 set_smp_cross_call(gic_raise_softirq);
981 register_cpu_notifier(&gic_cpu_notifier);
983 set_handle_irq(gic_handle_irq);
986 gic_chip.flags |= gic_arch_extn.flags;
993 static int gic_cnt __initdata;
996 gic_of_init(struct device_node *node, struct device_node *parent)
998 void __iomem *cpu_base;
999 void __iomem *dist_base;
1006 dist_base = of_iomap(node, 0);
1007 WARN(!dist_base, "unable to map gic dist registers\n");
1009 cpu_base = of_iomap(node, 1);
1010 WARN(!cpu_base, "unable to map gic cpu registers\n");
1012 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1015 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1017 gic_init_physaddr(node);
1020 irq = irq_of_parse_and_map(node, 0);
1021 gic_cascade_irq(gic_cnt, irq);
1026 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1027 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1028 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1029 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1030 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1031 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);