drivers/iommu/mtk_iommu_v1.c

   1 /*
   2  * IOMMU API for MTK architected m4u v1 implementations
   3  *
   4  * Copyright (c) 2015-2016 MediaTek Inc.
   5  * Author: Honghui Zhang <honghui.zhang@mediatek.com>
   6  *
   7  * Based on driver/iommu/mtk_iommu.c
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18 #include <linux/memblock.h>
  19 #include <linux/bug.h>
  20 #include <linux/clk.h>
  21 #include <linux/component.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dma-iommu.h>
  25 #include <linux/err.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/iommu.h>
  29 #include <linux/iopoll.h>
  30 #include <linux/list.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_iommu.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/of_platform.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/slab.h>
  37 #include <linux/spinlock.h>
  38 #include <asm/barrier.h>
  39 #include <asm/dma-iommu.h>
  40 #include <linux/init.h>
  41 #include <dt-bindings/memory/mt2701-larb-port.h>
  42 #include <soc/mediatek/smi.h>
  43 #include "mtk_iommu.h"
  44
  45 #define REG_MMU_PT_BASE_ADDR                    0x000
  46
  47 #define F_ALL_INVLD                             0x2
  48 #define F_MMU_INV_RANGE                         0x1
  49 #define F_INVLD_EN0                             BIT(0)
  50 #define F_INVLD_EN1                             BIT(1)
  51
  52 #define F_MMU_FAULT_VA_MSK                      0xfffff000
  53 #define MTK_PROTECT_PA_ALIGN                    128
  54
  55 #define REG_MMU_CTRL_REG                        0x210
  56 #define F_MMU_CTRL_COHERENT_EN                  BIT(8)
  57 #define REG_MMU_IVRP_PADDR                      0x214
  58 #define REG_MMU_INT_CONTROL                     0x220
  59 #define F_INT_TRANSLATION_FAULT                 BIT(0)
  60 #define F_INT_MAIN_MULTI_HIT_FAULT              BIT(1)
  61 #define F_INT_INVALID_PA_FAULT                  BIT(2)
  62 #define F_INT_ENTRY_REPLACEMENT_FAULT           BIT(3)
  63 #define F_INT_TABLE_WALK_FAULT                  BIT(4)
  64 #define F_INT_TLB_MISS_FAULT                    BIT(5)
  65 #define F_INT_PFH_DMA_FIFO_OVERFLOW             BIT(6)
  66 #define F_INT_MISS_DMA_FIFO_OVERFLOW            BIT(7)
  67
  68 #define F_MMU_TF_PROTECT_SEL(prot)              (((prot) & 0x3) << 5)
  69 #define F_INT_CLR_BIT                           BIT(12)
  70
  71 #define REG_MMU_FAULT_ST                        0x224
  72 #define REG_MMU_FAULT_VA                        0x228
  73 #define REG_MMU_INVLD_PA                        0x22C
  74 #define REG_MMU_INT_ID                          0x388
  75 #define REG_MMU_INVALIDATE                      0x5c0
  76 #define REG_MMU_INVLD_START_A                   0x5c4
  77 #define REG_MMU_INVLD_END_A                     0x5c8
  78
  79 #define REG_MMU_INV_SEL                         0x5d8
  80 #define REG_MMU_STANDARD_AXI_MODE               0x5e8
  81
  82 #define REG_MMU_DCM                             0x5f0
  83 #define F_MMU_DCM_ON                            BIT(1)
  84 #define REG_MMU_CPE_DONE                        0x60c
  85 #define F_DESC_VALID                            0x2
  86 #define F_DESC_NONSEC                           BIT(3)
  87 #define MT2701_M4U_TF_LARB(TF)                  (6 - (((TF) >> 13) & 0x7))
  88 #define MT2701_M4U_TF_PORT(TF)                  (((TF) >> 8) & 0xF)
  89 /* MTK generation one iommu HW only support 4K size mapping */
  90 #define MT2701_IOMMU_PAGE_SHIFT                 12
  91 #define MT2701_IOMMU_PAGE_SIZE                  (1UL << MT2701_IOMMU_PAGE_SHIFT)
  92
  93 /*
  94  * MTK m4u support 4GB iova address space, and only support 4K page
  95  * mapping. So the pagetable size should be exactly as 4M.
  96  */
  97 #define M2701_IOMMU_PGT_SIZE                    SZ_4M
  98
  99 struct mtk_iommu_domain {
 100         spinlock_t                      pgtlock; /* lock for page table */
 101         struct iommu_domain             domain;
 102         u32                             *pgt_va;
 103         dma_addr_t                      pgt_pa;
 104         struct mtk_iommu_data           *data;
 105 };
 106
 107 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 108 {
 109         return container_of(dom, struct mtk_iommu_domain, domain);
 110 }
 111
 112 static const int mt2701_m4u_in_larb[] = {
 113         LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
 114         LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
 115 };
 116
 117 static inline int mt2701_m4u_to_larb(int id)
 118 {
 119         int i;
 120
 121         for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
 122                 if ((id) >= mt2701_m4u_in_larb[i])
 123                         return i;
 124
 125         return 0;
 126 }
 127
 128 static inline int mt2701_m4u_to_port(int id)
 129 {
 130         int larb = mt2701_m4u_to_larb(id);
 131
 132         return id - mt2701_m4u_in_larb[larb];
 133 }
 134
 135 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 136 {
 137         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 138                         data->base + REG_MMU_INV_SEL);
 139         writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
 140         wmb(); /* Make sure the tlb flush all done */
 141 }
 142
 143 static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
 144                                 unsigned long iova, size_t size)
 145 {
 146         int ret;
 147         u32 tmp;
 148
 149         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 150                 data->base + REG_MMU_INV_SEL);
 151         writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
 152                 data->base + REG_MMU_INVLD_START_A);
 153         writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
 154                 data->base + REG_MMU_INVLD_END_A);
 155         writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
 156
 157         ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
 158                                 tmp, tmp != 0, 10, 100000);
 159         if (ret) {
 160                 dev_warn(data->dev,
 161                          "Partial TLB flush timed out, falling back to full flush\n");
 162                 mtk_iommu_tlb_flush_all(data);
 163         }
 164         /* Clear the CPE status */
 165         writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
 166 }
 167
 168 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 169 {
 170         struct mtk_iommu_data *data = dev_id;
 171         struct mtk_iommu_domain *dom = data->m4u_dom;
 172         u32 int_state, regval, fault_iova, fault_pa;
 173         unsigned int fault_larb, fault_port;
 174
 175         /* Read error information from registers */
 176         int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
 177         fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
 178
 179         fault_iova &= F_MMU_FAULT_VA_MSK;
 180         fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
 181         regval = readl_relaxed(data->base + REG_MMU_INT_ID);
 182         fault_larb = MT2701_M4U_TF_LARB(regval);
 183         fault_port = MT2701_M4U_TF_PORT(regval);
 184
 185         /*
 186          * MTK v1 iommu HW could not determine whether the fault is read or
 187          * write fault, report as read fault.
 188          */
 189         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
 190                         IOMMU_FAULT_READ))
 191                 dev_err_ratelimited(data->dev,
 192                         "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
 193                         int_state, fault_iova, fault_pa,
 194                         fault_larb, fault_port);
 195
 196         /* Interrupt clear */
 197         regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
 198         regval |= F_INT_CLR_BIT;
 199         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
 200
 201         mtk_iommu_tlb_flush_all(data);
 202
 203         return IRQ_HANDLED;
 204 }
 205
 206 static void mtk_iommu_config(struct mtk_iommu_data *data,
 207                              struct device *dev, bool enable)
 208 {
 209         struct mtk_smi_larb_iommu    *larb_mmu;
 210         unsigned int                 larbid, portid;
 211         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 212         int i;
 213
 214         for (i = 0; i < fwspec->num_ids; ++i) {
 215                 larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
 216                 portid = mt2701_m4u_to_port(fwspec->ids[i]);
 217                 larb_mmu = &data->smi_imu.larb_imu[larbid];
 218
 219                 dev_dbg(dev, "%s iommu port: %d\n",
 220                         enable ? "enable" : "disable", portid);
 221
 222                 if (enable)
 223                         larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 224                 else
 225                         larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 226         }
 227 }
 228
 229 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
 230 {
 231         struct mtk_iommu_domain *dom = data->m4u_dom;
 232
 233         spin_lock_init(&dom->pgtlock);
 234
 235         dom->pgt_va = dma_zalloc_coherent(data->dev,
 236                                 M2701_IOMMU_PGT_SIZE,
 237                                 &dom->pgt_pa, GFP_KERNEL);
 238         if (!dom->pgt_va)
 239                 return -ENOMEM;
 240
 241         writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
 242
 243         dom->data = data;
 244
 245         return 0;
 246 }
 247
 248 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 249 {
 250         struct mtk_iommu_domain *dom;
 251
 252         if (type != IOMMU_DOMAIN_UNMANAGED)
 253                 return NULL;
 254
 255         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 256         if (!dom)
 257                 return NULL;
 258
 259         return &dom->domain;
 260 }
 261
 262 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 263 {
 264         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 265         struct mtk_iommu_data *data = dom->data;
 266
 267         dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
 268                         dom->pgt_va, dom->pgt_pa);
 269         kfree(to_mtk_domain(domain));
 270 }
 271
 272 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 273                                    struct device *dev)
 274 {
 275         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 276         struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
 277         int ret;
 278
 279         if (!data)
 280                 return -ENODEV;
 281
 282         if (!data->m4u_dom) {
 283                 data->m4u_dom = dom;
 284                 ret = mtk_iommu_domain_finalise(data);
 285                 if (ret) {
 286                         data->m4u_dom = NULL;
 287                         return ret;
 288                 }
 289         }
 290
 291         mtk_iommu_config(data, dev, true);
 292         return 0;
 293 }
 294
 295 static void mtk_iommu_detach_device(struct iommu_domain *domain,
 296                                     struct device *dev)
 297 {
 298         struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
 299
 300         if (!data)
 301                 return;
 302
 303         mtk_iommu_config(data, dev, false);
 304 }
 305
 306 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 307                          phys_addr_t paddr, size_t size, int prot)
 308 {
 309         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 310         unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
 311         unsigned long flags;
 312         unsigned int i;
 313         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
 314         u32 pabase = (u32)paddr;
 315         int map_size = 0;
 316
 317         spin_lock_irqsave(&dom->pgtlock, flags);
 318         for (i = 0; i < page_num; i++) {
 319                 if (pgt_base_iova[i]) {
 320                         memset(pgt_base_iova, 0, i * sizeof(u32));
 321                         break;
 322                 }
 323                 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
 324                 pabase += MT2701_IOMMU_PAGE_SIZE;
 325                 map_size += MT2701_IOMMU_PAGE_SIZE;
 326         }
 327
 328         spin_unlock_irqrestore(&dom->pgtlock, flags);
 329
 330         mtk_iommu_tlb_flush_range(dom->data, iova, size);
 331
 332         return map_size == size ? 0 : -EEXIST;
 333 }
 334
 335 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 336                               unsigned long iova, size_t size)
 337 {
 338         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 339         unsigned long flags;
 340         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
 341         unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
 342
 343         spin_lock_irqsave(&dom->pgtlock, flags);
 344         memset(pgt_base_iova, 0, page_num * sizeof(u32));
 345         spin_unlock_irqrestore(&dom->pgtlock, flags);
 346
 347         mtk_iommu_tlb_flush_range(dom->data, iova, size);
 348
 349         return size;
 350 }
 351
 352 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 353                                           dma_addr_t iova)
 354 {
 355         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 356         unsigned long flags;
 357         phys_addr_t pa;
 358
 359         spin_lock_irqsave(&dom->pgtlock, flags);
 360         pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
 361         pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
 362         spin_unlock_irqrestore(&dom->pgtlock, flags);
 363
 364         return pa;
 365 }
 366
 367 static const struct iommu_ops mtk_iommu_ops;
 368
 369 /*
 370  * MTK generation one iommu HW only support one iommu domain, and all the client
 371  * sharing the same iova address space.
 372  */
 373 static int mtk_iommu_create_mapping(struct device *dev,
 374                                     struct of_phandle_args *args)
 375 {
 376         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 377         struct mtk_iommu_data *data;
 378         struct platform_device *m4updev;
 379         struct dma_iommu_mapping *mtk_mapping;
 380         struct device *m4udev;
 381         int ret;
 382
 383         if (args->args_count != 1) {
 384                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 385                         args->args_count);
 386                 return -EINVAL;
 387         }
 388
 389         if (!fwspec) {
 390                 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
 391                 if (ret)
 392                         return ret;
 393                 fwspec = dev_iommu_fwspec_get(dev);
 394         } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
 395                 return -EINVAL;
 396         }
 397
 398         if (!fwspec->iommu_priv) {
 399                 /* Get the m4u device */
 400                 m4updev = of_find_device_by_node(args->np);
 401                 if (WARN_ON(!m4updev))
 402                         return -EINVAL;
 403
 404                 fwspec->iommu_priv = platform_get_drvdata(m4updev);
 405         }
 406
 407         ret = iommu_fwspec_add_ids(dev, args->args, 1);
 408         if (ret)
 409                 return ret;
 410
 411         data = fwspec->iommu_priv;
 412         m4udev = data->dev;
 413         mtk_mapping = m4udev->archdata.iommu;
 414         if (!mtk_mapping) {
 415                 /* MTK iommu support 4GB iova address space. */
 416                 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
 417                                                 0, 1ULL << 32);
 418                 if (IS_ERR(mtk_mapping))
 419                         return PTR_ERR(mtk_mapping);
 420
 421                 m4udev->archdata.iommu = mtk_mapping;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int mtk_iommu_add_device(struct device *dev)
 428 {
 429         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 430         struct dma_iommu_mapping *mtk_mapping;
 431         struct of_phandle_args iommu_spec;
 432         struct of_phandle_iterator it;
 433         struct mtk_iommu_data *data;
 434         struct iommu_group *group;
 435         int err;
 436
 437         of_for_each_phandle(&it, err, dev->of_node, "iommus",
 438                         "#iommu-cells", 0) {
 439                 int count = of_phandle_iterator_args(&it, iommu_spec.args,
 440                                         MAX_PHANDLE_ARGS);
 441                 iommu_spec.np = of_node_get(it.node);
 442                 iommu_spec.args_count = count;
 443
 444                 mtk_iommu_create_mapping(dev, &iommu_spec);
 445                 of_node_put(iommu_spec.np);
 446         }
 447
 448         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 449                 return -ENODEV; /* Not a iommu client device */
 450
 451         /*
 452          * This is a short-term bodge because the ARM DMA code doesn't
 453          * understand multi-device groups, but we have to call into it
 454          * successfully (and not just rely on a normal IOMMU API attach
 455          * here) in order to set the correct DMA API ops on @dev.
 456          */
 457         group = iommu_group_alloc();
 458         if (IS_ERR(group))
 459                 return PTR_ERR(group);
 460
 461         err = iommu_group_add_device(group, dev);
 462         iommu_group_put(group);
 463         if (err)
 464                 return err;
 465
 466         data = fwspec->iommu_priv;
 467         mtk_mapping = data->dev->archdata.iommu;
 468         err = arm_iommu_attach_device(dev, mtk_mapping);
 469         if (err) {
 470                 iommu_group_remove_device(dev);
 471                 return err;
 472         }
 473
 474         return iommu_device_link(&data->iommu, dev);;
 475 }
 476
 477 static void mtk_iommu_remove_device(struct device *dev)
 478 {
 479         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 480         struct mtk_iommu_data *data;
 481
 482         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 483                 return;
 484
 485         data = fwspec->iommu_priv;
 486         iommu_device_unlink(&data->iommu, dev);
 487
 488         iommu_group_remove_device(dev);
 489         iommu_fwspec_free(dev);
 490 }
 491
 492 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 493 {
 494         u32 regval;
 495         int ret;
 496
 497         ret = clk_prepare_enable(data->bclk);
 498         if (ret) {
 499                 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
 500                 return ret;
 501         }
 502
 503         regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
 504         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 505
 506         regval = F_INT_TRANSLATION_FAULT |
 507                 F_INT_MAIN_MULTI_HIT_FAULT |
 508                 F_INT_INVALID_PA_FAULT |
 509                 F_INT_ENTRY_REPLACEMENT_FAULT |
 510                 F_INT_TABLE_WALK_FAULT |
 511                 F_INT_TLB_MISS_FAULT |
 512                 F_INT_PFH_DMA_FIFO_OVERFLOW |
 513                 F_INT_MISS_DMA_FIFO_OVERFLOW;
 514         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
 515
 516         /* protect memory,hw will write here while translation fault */
 517         writel_relaxed(data->protect_base,
 518                         data->base + REG_MMU_IVRP_PADDR);
 519
 520         writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
 521
 522         if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
 523                              dev_name(data->dev), (void *)data)) {
 524                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 525                 clk_disable_unprepare(data->bclk);
 526                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
 527                 return -ENODEV;
 528         }
 529
 530         return 0;
 531 }
 532
 533 static const struct iommu_ops mtk_iommu_ops = {
 534         .domain_alloc   = mtk_iommu_domain_alloc,
 535         .domain_free    = mtk_iommu_domain_free,
 536         .attach_dev     = mtk_iommu_attach_device,
 537         .detach_dev     = mtk_iommu_detach_device,
 538         .map            = mtk_iommu_map,
 539         .unmap          = mtk_iommu_unmap,
 540         .iova_to_phys   = mtk_iommu_iova_to_phys,
 541         .add_device     = mtk_iommu_add_device,
 542         .remove_device  = mtk_iommu_remove_device,
 543         .pgsize_bitmap  = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
 544 };
 545
 546 static const struct of_device_id mtk_iommu_of_ids[] = {
 547         { .compatible = "mediatek,mt2701-m4u", },
 548         {}
 549 };
 550
 551 static const struct component_master_ops mtk_iommu_com_ops = {
 552         .bind           = mtk_iommu_bind,
 553         .unbind         = mtk_iommu_unbind,
 554 };
 555
 556 static int mtk_iommu_probe(struct platform_device *pdev)
 557 {
 558         struct mtk_iommu_data           *data;
 559         struct device                   *dev = &pdev->dev;
 560         struct resource                 *res;
 561         struct component_match          *match = NULL;
 562         struct of_phandle_args          larb_spec;
 563         struct of_phandle_iterator      it;
 564         void                            *protect;
 565         int                             larb_nr, ret, err;
 566
 567         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 568         if (!data)
 569                 return -ENOMEM;
 570
 571         data->dev = dev;
 572
 573         /* Protect memory. HW will access here while translation fault.*/
 574         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
 575                         GFP_KERNEL | GFP_DMA);
 576         if (!protect)
 577                 return -ENOMEM;
 578         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
 579
 580         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 581         data->base = devm_ioremap_resource(dev, res);
 582         if (IS_ERR(data->base))
 583                 return PTR_ERR(data->base);
 584
 585         data->irq = platform_get_irq(pdev, 0);
 586         if (data->irq < 0)
 587                 return data->irq;
 588
 589         data->bclk = devm_clk_get(dev, "bclk");
 590         if (IS_ERR(data->bclk))
 591                 return PTR_ERR(data->bclk);
 592
 593         larb_nr = 0;
 594         of_for_each_phandle(&it, err, dev->of_node,
 595                         "mediatek,larbs", NULL, 0) {
 596                 struct platform_device *plarbdev;
 597                 int count = of_phandle_iterator_args(&it, larb_spec.args,
 598                                         MAX_PHANDLE_ARGS);
 599
 600                 if (count)
 601                         continue;
 602
 603                 larb_spec.np = of_node_get(it.node);
 604                 if (!of_device_is_available(larb_spec.np))
 605                         continue;
 606
 607                 plarbdev = of_find_device_by_node(larb_spec.np);
 608                 if (!plarbdev) {
 609                         plarbdev = of_platform_device_create(
 610                                                 larb_spec.np, NULL,
 611                                                 platform_bus_type.dev_root);
 612                         if (!plarbdev) {
 613                                 of_node_put(larb_spec.np);
 614                                 return -EPROBE_DEFER;
 615                         }
 616                 }
 617
 618                 data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev;
 619                 component_match_add_release(dev, &match, release_of,
 620                                             compare_of, larb_spec.np);
 621                 larb_nr++;
 622         }
 623
 624         data->smi_imu.larb_nr = larb_nr;
 625
 626         platform_set_drvdata(pdev, data);
 627
 628         ret = mtk_iommu_hw_init(data);
 629         if (ret)
 630                 return ret;
 631
 632         ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
 633                                      dev_name(&pdev->dev));
 634         if (ret)
 635                 return ret;
 636
 637         iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
 638
 639         ret = iommu_device_register(&data->iommu);
 640         if (ret)
 641                 return ret;
 642
 643         if (!iommu_present(&platform_bus_type))
 644                 bus_set_iommu(&platform_bus_type,  &mtk_iommu_ops);
 645
 646         return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
 647 }
 648
 649 static int mtk_iommu_remove(struct platform_device *pdev)
 650 {
 651         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
 652
 653         iommu_device_sysfs_remove(&data->iommu);
 654         iommu_device_unregister(&data->iommu);
 655
 656         if (iommu_present(&platform_bus_type))
 657                 bus_set_iommu(&platform_bus_type, NULL);
 658
 659         clk_disable_unprepare(data->bclk);
 660         devm_free_irq(&pdev->dev, data->irq, data);
 661         component_master_del(&pdev->dev, &mtk_iommu_com_ops);
 662         return 0;
 663 }
 664
 665 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 666 {
 667         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 668         struct mtk_iommu_suspend_reg *reg = &data->reg;
 669         void __iomem *base = data->base;
 670
 671         reg->standard_axi_mode = readl_relaxed(base +
 672                                                REG_MMU_STANDARD_AXI_MODE);
 673         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
 674         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
 675         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
 676         return 0;
 677 }
 678
 679 static int __maybe_unused mtk_iommu_resume(struct device *dev)
 680 {
 681         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 682         struct mtk_iommu_suspend_reg *reg = &data->reg;
 683         void __iomem *base = data->base;
 684
 685         writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
 686         writel_relaxed(reg->standard_axi_mode,
 687                        base + REG_MMU_STANDARD_AXI_MODE);
 688         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
 689         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
 690         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
 691         writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
 692         return 0;
 693 }
 694
 695 static const struct dev_pm_ops mtk_iommu_pm_ops = {
 696         SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
 697 };
 698
 699 static struct platform_driver mtk_iommu_driver = {
 700         .probe  = mtk_iommu_probe,
 701         .remove = mtk_iommu_remove,
 702         .driver = {
 703                 .name = "mtk-iommu-v1",
 704                 .of_match_table = mtk_iommu_of_ids,
 705                 .pm = &mtk_iommu_pm_ops,
 706         }
 707 };
 708
 709 static int __init m4u_init(void)
 710 {
 711         return platform_driver_register(&mtk_iommu_driver);
 712 }
 713 subsys_initcall(m4u_init);