Merge tag 'iommu-fixes-v5.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git...
[sfrench/cifs-2.6.git] / drivers / iommu / mtk_iommu_v1.c
1 /*
2  * IOMMU API for MTK architected m4u v1 implementations
3  *
4  * Copyright (c) 2015-2016 MediaTek Inc.
5  * Author: Honghui Zhang <honghui.zhang@mediatek.com>
6  *
7  * Based on driver/iommu/mtk_iommu.c
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18 #include <linux/memblock.h>
19 #include <linux/bug.h>
20 #include <linux/clk.h>
21 #include <linux/component.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dma-iommu.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/iommu.h>
29 #include <linux/iopoll.h>
30 #include <linux/list.h>
31 #include <linux/of_address.h>
32 #include <linux/of_iommu.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/slab.h>
37 #include <linux/spinlock.h>
38 #include <asm/barrier.h>
39 #include <asm/dma-iommu.h>
40 #include <linux/init.h>
41 #include <dt-bindings/memory/mt2701-larb-port.h>
42 #include <soc/mediatek/smi.h>
43 #include "mtk_iommu.h"
44
45 #define REG_MMU_PT_BASE_ADDR                    0x000
46
47 #define F_ALL_INVLD                             0x2
48 #define F_MMU_INV_RANGE                         0x1
49 #define F_INVLD_EN0                             BIT(0)
50 #define F_INVLD_EN1                             BIT(1)
51
52 #define F_MMU_FAULT_VA_MSK                      0xfffff000
53 #define MTK_PROTECT_PA_ALIGN                    128
54
55 #define REG_MMU_CTRL_REG                        0x210
56 #define F_MMU_CTRL_COHERENT_EN                  BIT(8)
57 #define REG_MMU_IVRP_PADDR                      0x214
58 #define REG_MMU_INT_CONTROL                     0x220
59 #define F_INT_TRANSLATION_FAULT                 BIT(0)
60 #define F_INT_MAIN_MULTI_HIT_FAULT              BIT(1)
61 #define F_INT_INVALID_PA_FAULT                  BIT(2)
62 #define F_INT_ENTRY_REPLACEMENT_FAULT           BIT(3)
63 #define F_INT_TABLE_WALK_FAULT                  BIT(4)
64 #define F_INT_TLB_MISS_FAULT                    BIT(5)
65 #define F_INT_PFH_DMA_FIFO_OVERFLOW             BIT(6)
66 #define F_INT_MISS_DMA_FIFO_OVERFLOW            BIT(7)
67
68 #define F_MMU_TF_PROTECT_SEL(prot)              (((prot) & 0x3) << 5)
69 #define F_INT_CLR_BIT                           BIT(12)
70
71 #define REG_MMU_FAULT_ST                        0x224
72 #define REG_MMU_FAULT_VA                        0x228
73 #define REG_MMU_INVLD_PA                        0x22C
74 #define REG_MMU_INT_ID                          0x388
75 #define REG_MMU_INVALIDATE                      0x5c0
76 #define REG_MMU_INVLD_START_A                   0x5c4
77 #define REG_MMU_INVLD_END_A                     0x5c8
78
79 #define REG_MMU_INV_SEL                         0x5d8
80 #define REG_MMU_STANDARD_AXI_MODE               0x5e8
81
82 #define REG_MMU_DCM                             0x5f0
83 #define F_MMU_DCM_ON                            BIT(1)
84 #define REG_MMU_CPE_DONE                        0x60c
85 #define F_DESC_VALID                            0x2
86 #define F_DESC_NONSEC                           BIT(3)
87 #define MT2701_M4U_TF_LARB(TF)                  (6 - (((TF) >> 13) & 0x7))
88 #define MT2701_M4U_TF_PORT(TF)                  (((TF) >> 8) & 0xF)
89 /* MTK generation one iommu HW only support 4K size mapping */
90 #define MT2701_IOMMU_PAGE_SHIFT                 12
91 #define MT2701_IOMMU_PAGE_SIZE                  (1UL << MT2701_IOMMU_PAGE_SHIFT)
92
93 /*
94  * MTK m4u support 4GB iova address space, and only support 4K page
95  * mapping. So the pagetable size should be exactly as 4M.
96  */
97 #define M2701_IOMMU_PGT_SIZE                    SZ_4M
98
99 struct mtk_iommu_domain {
100         spinlock_t                      pgtlock; /* lock for page table */
101         struct iommu_domain             domain;
102         u32                             *pgt_va;
103         dma_addr_t                      pgt_pa;
104         struct mtk_iommu_data           *data;
105 };
106
107 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
108 {
109         return container_of(dom, struct mtk_iommu_domain, domain);
110 }
111
112 static const int mt2701_m4u_in_larb[] = {
113         LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
114         LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
115 };
116
117 static inline int mt2701_m4u_to_larb(int id)
118 {
119         int i;
120
121         for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
122                 if ((id) >= mt2701_m4u_in_larb[i])
123                         return i;
124
125         return 0;
126 }
127
128 static inline int mt2701_m4u_to_port(int id)
129 {
130         int larb = mt2701_m4u_to_larb(id);
131
132         return id - mt2701_m4u_in_larb[larb];
133 }
134
135 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
136 {
137         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
138                         data->base + REG_MMU_INV_SEL);
139         writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
140         wmb(); /* Make sure the tlb flush all done */
141 }
142
143 static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
144                                 unsigned long iova, size_t size)
145 {
146         int ret;
147         u32 tmp;
148
149         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
150                 data->base + REG_MMU_INV_SEL);
151         writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
152                 data->base + REG_MMU_INVLD_START_A);
153         writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
154                 data->base + REG_MMU_INVLD_END_A);
155         writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
156
157         ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
158                                 tmp, tmp != 0, 10, 100000);
159         if (ret) {
160                 dev_warn(data->dev,
161                          "Partial TLB flush timed out, falling back to full flush\n");
162                 mtk_iommu_tlb_flush_all(data);
163         }
164         /* Clear the CPE status */
165         writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
166 }
167
168 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
169 {
170         struct mtk_iommu_data *data = dev_id;
171         struct mtk_iommu_domain *dom = data->m4u_dom;
172         u32 int_state, regval, fault_iova, fault_pa;
173         unsigned int fault_larb, fault_port;
174
175         /* Read error information from registers */
176         int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
177         fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
178
179         fault_iova &= F_MMU_FAULT_VA_MSK;
180         fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
181         regval = readl_relaxed(data->base + REG_MMU_INT_ID);
182         fault_larb = MT2701_M4U_TF_LARB(regval);
183         fault_port = MT2701_M4U_TF_PORT(regval);
184
185         /*
186          * MTK v1 iommu HW could not determine whether the fault is read or
187          * write fault, report as read fault.
188          */
189         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
190                         IOMMU_FAULT_READ))
191                 dev_err_ratelimited(data->dev,
192                         "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
193                         int_state, fault_iova, fault_pa,
194                         fault_larb, fault_port);
195
196         /* Interrupt clear */
197         regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
198         regval |= F_INT_CLR_BIT;
199         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
200
201         mtk_iommu_tlb_flush_all(data);
202
203         return IRQ_HANDLED;
204 }
205
206 static void mtk_iommu_config(struct mtk_iommu_data *data,
207                              struct device *dev, bool enable)
208 {
209         struct mtk_smi_larb_iommu    *larb_mmu;
210         unsigned int                 larbid, portid;
211         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
212         int i;
213
214         for (i = 0; i < fwspec->num_ids; ++i) {
215                 larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
216                 portid = mt2701_m4u_to_port(fwspec->ids[i]);
217                 larb_mmu = &data->smi_imu.larb_imu[larbid];
218
219                 dev_dbg(dev, "%s iommu port: %d\n",
220                         enable ? "enable" : "disable", portid);
221
222                 if (enable)
223                         larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
224                 else
225                         larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
226         }
227 }
228
229 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
230 {
231         struct mtk_iommu_domain *dom = data->m4u_dom;
232
233         spin_lock_init(&dom->pgtlock);
234
235         dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
236                                          &dom->pgt_pa, GFP_KERNEL);
237         if (!dom->pgt_va)
238                 return -ENOMEM;
239
240         writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
241
242         dom->data = data;
243
244         return 0;
245 }
246
247 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
248 {
249         struct mtk_iommu_domain *dom;
250
251         if (type != IOMMU_DOMAIN_UNMANAGED)
252                 return NULL;
253
254         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
255         if (!dom)
256                 return NULL;
257
258         return &dom->domain;
259 }
260
261 static void mtk_iommu_domain_free(struct iommu_domain *domain)
262 {
263         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
264         struct mtk_iommu_data *data = dom->data;
265
266         dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
267                         dom->pgt_va, dom->pgt_pa);
268         kfree(to_mtk_domain(domain));
269 }
270
271 static int mtk_iommu_attach_device(struct iommu_domain *domain,
272                                    struct device *dev)
273 {
274         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
275         struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
276         int ret;
277
278         if (!data)
279                 return -ENODEV;
280
281         if (!data->m4u_dom) {
282                 data->m4u_dom = dom;
283                 ret = mtk_iommu_domain_finalise(data);
284                 if (ret) {
285                         data->m4u_dom = NULL;
286                         return ret;
287                 }
288         }
289
290         mtk_iommu_config(data, dev, true);
291         return 0;
292 }
293
294 static void mtk_iommu_detach_device(struct iommu_domain *domain,
295                                     struct device *dev)
296 {
297         struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
298
299         if (!data)
300                 return;
301
302         mtk_iommu_config(data, dev, false);
303 }
304
305 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
306                          phys_addr_t paddr, size_t size, int prot)
307 {
308         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
309         unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
310         unsigned long flags;
311         unsigned int i;
312         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
313         u32 pabase = (u32)paddr;
314         int map_size = 0;
315
316         spin_lock_irqsave(&dom->pgtlock, flags);
317         for (i = 0; i < page_num; i++) {
318                 if (pgt_base_iova[i]) {
319                         memset(pgt_base_iova, 0, i * sizeof(u32));
320                         break;
321                 }
322                 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
323                 pabase += MT2701_IOMMU_PAGE_SIZE;
324                 map_size += MT2701_IOMMU_PAGE_SIZE;
325         }
326
327         spin_unlock_irqrestore(&dom->pgtlock, flags);
328
329         mtk_iommu_tlb_flush_range(dom->data, iova, size);
330
331         return map_size == size ? 0 : -EEXIST;
332 }
333
334 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
335                               unsigned long iova, size_t size)
336 {
337         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
338         unsigned long flags;
339         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
340         unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
341
342         spin_lock_irqsave(&dom->pgtlock, flags);
343         memset(pgt_base_iova, 0, page_num * sizeof(u32));
344         spin_unlock_irqrestore(&dom->pgtlock, flags);
345
346         mtk_iommu_tlb_flush_range(dom->data, iova, size);
347
348         return size;
349 }
350
351 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
352                                           dma_addr_t iova)
353 {
354         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
355         unsigned long flags;
356         phys_addr_t pa;
357
358         spin_lock_irqsave(&dom->pgtlock, flags);
359         pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
360         pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
361         spin_unlock_irqrestore(&dom->pgtlock, flags);
362
363         return pa;
364 }
365
366 static const struct iommu_ops mtk_iommu_ops;
367
368 /*
369  * MTK generation one iommu HW only support one iommu domain, and all the client
370  * sharing the same iova address space.
371  */
372 static int mtk_iommu_create_mapping(struct device *dev,
373                                     struct of_phandle_args *args)
374 {
375         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
376         struct mtk_iommu_data *data;
377         struct platform_device *m4updev;
378         struct dma_iommu_mapping *mtk_mapping;
379         struct device *m4udev;
380         int ret;
381
382         if (args->args_count != 1) {
383                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
384                         args->args_count);
385                 return -EINVAL;
386         }
387
388         if (!fwspec) {
389                 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
390                 if (ret)
391                         return ret;
392                 fwspec = dev_iommu_fwspec_get(dev);
393         } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
394                 return -EINVAL;
395         }
396
397         if (!fwspec->iommu_priv) {
398                 /* Get the m4u device */
399                 m4updev = of_find_device_by_node(args->np);
400                 if (WARN_ON(!m4updev))
401                         return -EINVAL;
402
403                 fwspec->iommu_priv = platform_get_drvdata(m4updev);
404         }
405
406         ret = iommu_fwspec_add_ids(dev, args->args, 1);
407         if (ret)
408                 return ret;
409
410         data = fwspec->iommu_priv;
411         m4udev = data->dev;
412         mtk_mapping = m4udev->archdata.iommu;
413         if (!mtk_mapping) {
414                 /* MTK iommu support 4GB iova address space. */
415                 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
416                                                 0, 1ULL << 32);
417                 if (IS_ERR(mtk_mapping))
418                         return PTR_ERR(mtk_mapping);
419
420                 m4udev->archdata.iommu = mtk_mapping;
421         }
422
423         return 0;
424 }
425
426 static int mtk_iommu_add_device(struct device *dev)
427 {
428         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
429         struct dma_iommu_mapping *mtk_mapping;
430         struct of_phandle_args iommu_spec;
431         struct of_phandle_iterator it;
432         struct mtk_iommu_data *data;
433         struct iommu_group *group;
434         int err;
435
436         of_for_each_phandle(&it, err, dev->of_node, "iommus",
437                         "#iommu-cells", 0) {
438                 int count = of_phandle_iterator_args(&it, iommu_spec.args,
439                                         MAX_PHANDLE_ARGS);
440                 iommu_spec.np = of_node_get(it.node);
441                 iommu_spec.args_count = count;
442
443                 mtk_iommu_create_mapping(dev, &iommu_spec);
444
445                 /* dev->iommu_fwspec might have changed */
446                 fwspec = dev_iommu_fwspec_get(dev);
447
448                 of_node_put(iommu_spec.np);
449         }
450
451         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
452                 return -ENODEV; /* Not a iommu client device */
453
454         /*
455          * This is a short-term bodge because the ARM DMA code doesn't
456          * understand multi-device groups, but we have to call into it
457          * successfully (and not just rely on a normal IOMMU API attach
458          * here) in order to set the correct DMA API ops on @dev.
459          */
460         group = iommu_group_alloc();
461         if (IS_ERR(group))
462                 return PTR_ERR(group);
463
464         err = iommu_group_add_device(group, dev);
465         iommu_group_put(group);
466         if (err)
467                 return err;
468
469         data = fwspec->iommu_priv;
470         mtk_mapping = data->dev->archdata.iommu;
471         err = arm_iommu_attach_device(dev, mtk_mapping);
472         if (err) {
473                 iommu_group_remove_device(dev);
474                 return err;
475         }
476
477         return iommu_device_link(&data->iommu, dev);;
478 }
479
480 static void mtk_iommu_remove_device(struct device *dev)
481 {
482         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
483         struct mtk_iommu_data *data;
484
485         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
486                 return;
487
488         data = fwspec->iommu_priv;
489         iommu_device_unlink(&data->iommu, dev);
490
491         iommu_group_remove_device(dev);
492         iommu_fwspec_free(dev);
493 }
494
495 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
496 {
497         u32 regval;
498         int ret;
499
500         ret = clk_prepare_enable(data->bclk);
501         if (ret) {
502                 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
503                 return ret;
504         }
505
506         regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
507         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
508
509         regval = F_INT_TRANSLATION_FAULT |
510                 F_INT_MAIN_MULTI_HIT_FAULT |
511                 F_INT_INVALID_PA_FAULT |
512                 F_INT_ENTRY_REPLACEMENT_FAULT |
513                 F_INT_TABLE_WALK_FAULT |
514                 F_INT_TLB_MISS_FAULT |
515                 F_INT_PFH_DMA_FIFO_OVERFLOW |
516                 F_INT_MISS_DMA_FIFO_OVERFLOW;
517         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
518
519         /* protect memory,hw will write here while translation fault */
520         writel_relaxed(data->protect_base,
521                         data->base + REG_MMU_IVRP_PADDR);
522
523         writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
524
525         if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
526                              dev_name(data->dev), (void *)data)) {
527                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
528                 clk_disable_unprepare(data->bclk);
529                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
530                 return -ENODEV;
531         }
532
533         return 0;
534 }
535
536 static const struct iommu_ops mtk_iommu_ops = {
537         .domain_alloc   = mtk_iommu_domain_alloc,
538         .domain_free    = mtk_iommu_domain_free,
539         .attach_dev     = mtk_iommu_attach_device,
540         .detach_dev     = mtk_iommu_detach_device,
541         .map            = mtk_iommu_map,
542         .unmap          = mtk_iommu_unmap,
543         .iova_to_phys   = mtk_iommu_iova_to_phys,
544         .add_device     = mtk_iommu_add_device,
545         .remove_device  = mtk_iommu_remove_device,
546         .pgsize_bitmap  = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
547 };
548
549 static const struct of_device_id mtk_iommu_of_ids[] = {
550         { .compatible = "mediatek,mt2701-m4u", },
551         {}
552 };
553
554 static const struct component_master_ops mtk_iommu_com_ops = {
555         .bind           = mtk_iommu_bind,
556         .unbind         = mtk_iommu_unbind,
557 };
558
559 static int mtk_iommu_probe(struct platform_device *pdev)
560 {
561         struct mtk_iommu_data           *data;
562         struct device                   *dev = &pdev->dev;
563         struct resource                 *res;
564         struct component_match          *match = NULL;
565         struct of_phandle_args          larb_spec;
566         struct of_phandle_iterator      it;
567         void                            *protect;
568         int                             larb_nr, ret, err;
569
570         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
571         if (!data)
572                 return -ENOMEM;
573
574         data->dev = dev;
575
576         /* Protect memory. HW will access here while translation fault.*/
577         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
578                         GFP_KERNEL | GFP_DMA);
579         if (!protect)
580                 return -ENOMEM;
581         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
582
583         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
584         data->base = devm_ioremap_resource(dev, res);
585         if (IS_ERR(data->base))
586                 return PTR_ERR(data->base);
587
588         data->irq = platform_get_irq(pdev, 0);
589         if (data->irq < 0)
590                 return data->irq;
591
592         data->bclk = devm_clk_get(dev, "bclk");
593         if (IS_ERR(data->bclk))
594                 return PTR_ERR(data->bclk);
595
596         larb_nr = 0;
597         of_for_each_phandle(&it, err, dev->of_node,
598                         "mediatek,larbs", NULL, 0) {
599                 struct platform_device *plarbdev;
600                 int count = of_phandle_iterator_args(&it, larb_spec.args,
601                                         MAX_PHANDLE_ARGS);
602
603                 if (count)
604                         continue;
605
606                 larb_spec.np = of_node_get(it.node);
607                 if (!of_device_is_available(larb_spec.np))
608                         continue;
609
610                 plarbdev = of_find_device_by_node(larb_spec.np);
611                 if (!plarbdev) {
612                         plarbdev = of_platform_device_create(
613                                                 larb_spec.np, NULL,
614                                                 platform_bus_type.dev_root);
615                         if (!plarbdev) {
616                                 of_node_put(larb_spec.np);
617                                 return -EPROBE_DEFER;
618                         }
619                 }
620
621                 data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev;
622                 component_match_add_release(dev, &match, release_of,
623                                             compare_of, larb_spec.np);
624                 larb_nr++;
625         }
626
627         data->smi_imu.larb_nr = larb_nr;
628
629         platform_set_drvdata(pdev, data);
630
631         ret = mtk_iommu_hw_init(data);
632         if (ret)
633                 return ret;
634
635         ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
636                                      dev_name(&pdev->dev));
637         if (ret)
638                 return ret;
639
640         iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
641
642         ret = iommu_device_register(&data->iommu);
643         if (ret)
644                 return ret;
645
646         if (!iommu_present(&platform_bus_type))
647                 bus_set_iommu(&platform_bus_type,  &mtk_iommu_ops);
648
649         return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
650 }
651
652 static int mtk_iommu_remove(struct platform_device *pdev)
653 {
654         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
655
656         iommu_device_sysfs_remove(&data->iommu);
657         iommu_device_unregister(&data->iommu);
658
659         if (iommu_present(&platform_bus_type))
660                 bus_set_iommu(&platform_bus_type, NULL);
661
662         clk_disable_unprepare(data->bclk);
663         devm_free_irq(&pdev->dev, data->irq, data);
664         component_master_del(&pdev->dev, &mtk_iommu_com_ops);
665         return 0;
666 }
667
668 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
669 {
670         struct mtk_iommu_data *data = dev_get_drvdata(dev);
671         struct mtk_iommu_suspend_reg *reg = &data->reg;
672         void __iomem *base = data->base;
673
674         reg->standard_axi_mode = readl_relaxed(base +
675                                                REG_MMU_STANDARD_AXI_MODE);
676         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
677         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
678         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
679         return 0;
680 }
681
682 static int __maybe_unused mtk_iommu_resume(struct device *dev)
683 {
684         struct mtk_iommu_data *data = dev_get_drvdata(dev);
685         struct mtk_iommu_suspend_reg *reg = &data->reg;
686         void __iomem *base = data->base;
687
688         writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
689         writel_relaxed(reg->standard_axi_mode,
690                        base + REG_MMU_STANDARD_AXI_MODE);
691         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
692         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
693         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
694         writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
695         return 0;
696 }
697
698 static const struct dev_pm_ops mtk_iommu_pm_ops = {
699         SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
700 };
701
702 static struct platform_driver mtk_iommu_driver = {
703         .probe  = mtk_iommu_probe,
704         .remove = mtk_iommu_remove,
705         .driver = {
706                 .name = "mtk-iommu-v1",
707                 .of_match_table = mtk_iommu_of_ids,
708                 .pm = &mtk_iommu_pm_ops,
709         }
710 };
711
712 static int __init m4u_init(void)
713 {
714         return platform_driver_register(&mtk_iommu_driver);
715 }
716 subsys_initcall(m4u_init);