drivers/iommu/intel-svm.c

   1 /*
   2  * Copyright © 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>
  14  */
  15
  16 #include <linux/intel-iommu.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/mm.h>
  20 #include <linux/slab.h>
  21 #include <linux/intel-svm.h>
  22 #include <linux/rculist.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-ats.h>
  25 #include <linux/dmar.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mm_types.h>
  28 #include <asm/page.h>
  29
  30 #include "intel-pasid.h"
  31
  32 #define PASID_ENTRY_P           BIT_ULL(0)
  33 #define PASID_ENTRY_FLPM_5LP    BIT_ULL(9)
  34 #define PASID_ENTRY_SRE         BIT_ULL(11)
  35
  36 static irqreturn_t prq_event_thread(int irq, void *d);
  37
  38 struct pasid_state_entry {
  39         u64 val;
  40 };
  41
  42 int intel_svm_init(struct intel_iommu *iommu)
  43 {
  44         struct page *pages;
  45         int order;
  46
  47         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
  48                         !cap_fl1gp_support(iommu->cap))
  49                 return -EINVAL;
  50
  51         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
  52                         !cap_5lp_support(iommu->cap))
  53                 return -EINVAL;
  54
  55         /* Start at 2 because it's defined as 2^(1+PSS) */
  56         iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
  57
  58         /* Eventually I'm promised we will get a multi-level PASID table
  59          * and it won't have to be physically contiguous. Until then,
  60          * limit the size because 8MiB contiguous allocations can be hard
  61          * to come by. The limit of 0x20000, which is 1MiB for each of
  62          * the PASID and PASID-state tables, is somewhat arbitrary. */
  63         if (iommu->pasid_max > 0x20000)
  64                 iommu->pasid_max = 0x20000;
  65
  66         order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  67         if (ecap_dis(iommu->ecap)) {
  68                 /* Just making it explicit... */
  69                 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
  70                 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  71                 if (pages)
  72                         iommu->pasid_state_table = page_address(pages);
  73                 else
  74                         pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
  75                                 iommu->name);
  76         }
  77
  78         return 0;
  79 }
  80
  81 int intel_svm_exit(struct intel_iommu *iommu)
  82 {
  83         int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  84
  85         if (iommu->pasid_state_table) {
  86                 free_pages((unsigned long)iommu->pasid_state_table, order);
  87                 iommu->pasid_state_table = NULL;
  88         }
  89
  90         return 0;
  91 }
  92
  93 #define PRQ_ORDER 0
  94
  95 int intel_svm_enable_prq(struct intel_iommu *iommu)
  96 {
  97         struct page *pages;
  98         int irq, ret;
  99
 100         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
 101         if (!pages) {
 102                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
 103                         iommu->name);
 104                 return -ENOMEM;
 105         }
 106         iommu->prq = page_address(pages);
 107
 108         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
 109         if (irq <= 0) {
 110                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
 111                        iommu->name);
 112                 ret = -EINVAL;
 113         err:
 114                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 115                 iommu->prq = NULL;
 116                 return ret;
 117         }
 118         iommu->pr_irq = irq;
 119
 120         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
 121
 122         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
 123                                    iommu->prq_name, iommu);
 124         if (ret) {
 125                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
 126                        iommu->name);
 127                 dmar_free_hwirq(irq);
 128                 iommu->pr_irq = 0;
 129                 goto err;
 130         }
 131         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 132         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 133         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
 134
 135         return 0;
 136 }
 137
 138 int intel_svm_finish_prq(struct intel_iommu *iommu)
 139 {
 140         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 141         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 142         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
 143
 144         if (iommu->pr_irq) {
 145                 free_irq(iommu->pr_irq, iommu);
 146                 dmar_free_hwirq(iommu->pr_irq);
 147                 iommu->pr_irq = 0;
 148         }
 149
 150         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 151         iommu->prq = NULL;
 152
 153         return 0;
 154 }
 155
 156 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 157                                        unsigned long address, unsigned long pages, int ih, int gl)
 158 {
 159         struct qi_desc desc;
 160
 161         if (pages == -1) {
 162                 /* For global kernel pages we have to flush them in *all* PASIDs
 163                  * because that's the only option the hardware gives us. Despite
 164                  * the fact that they are actually only accessible through one. */
 165                 if (gl)
 166                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 167                                 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
 168                 else
 169                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 170                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
 171                 desc.high = 0;
 172         } else {
 173                 int mask = ilog2(__roundup_pow_of_two(pages));
 174
 175                 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 176                         QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
 177                 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
 178                         QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
 179         }
 180         qi_submit_sync(&desc, svm->iommu);
 181
 182         if (sdev->dev_iotlb) {
 183                 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
 184                         QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
 185                 if (pages == -1) {
 186                         desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
 187                 } else if (pages > 1) {
 188                         /* The least significant zero bit indicates the size. So,
 189                          * for example, an "address" value of 0x12345f000 will
 190                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 191                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 192                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 193
 194                         desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 195                 } else {
 196                         desc.high = QI_DEV_EIOTLB_ADDR(address);
 197                 }
 198                 qi_submit_sync(&desc, svm->iommu);
 199         }
 200 }
 201
 202 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 203                                   unsigned long pages, int ih, int gl)
 204 {
 205         struct intel_svm_dev *sdev;
 206
 207         /* Try deferred invalidate if available */
 208         if (svm->iommu->pasid_state_table &&
 209             !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
 210                 return;
 211
 212         rcu_read_lock();
 213         list_for_each_entry_rcu(sdev, &svm->devs, list)
 214                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
 215         rcu_read_unlock();
 216 }
 217
 218 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
 219                              unsigned long address, pte_t pte)
 220 {
 221         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 222
 223         intel_flush_svm_range(svm, address, 1, 1, 0);
 224 }
 225
 226 /* Pages have been freed at this point */
 227 static void intel_invalidate_range(struct mmu_notifier *mn,
 228                                    struct mm_struct *mm,
 229                                    unsigned long start, unsigned long end)
 230 {
 231         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 232
 233         intel_flush_svm_range(svm, start,
 234                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
 235 }
 236
 237
 238 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
 239 {
 240         struct qi_desc desc;
 241
 242         desc.high = 0;
 243         desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
 244
 245         qi_submit_sync(&desc, svm->iommu);
 246 }
 247
 248 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 249 {
 250         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 251         struct intel_svm_dev *sdev;
 252
 253         /* This might end up being called from exit_mmap(), *before* the page
 254          * tables are cleared. And __mmu_notifier_release() will delete us from
 255          * the list of notifiers so that our invalidate_range() callback doesn't
 256          * get called when the page tables are cleared. So we need to protect
 257          * against hardware accessing those page tables.
 258          *
 259          * We do it by clearing the entry in the PASID table and then flushing
 260          * the IOTLB and the PASID table caches. This might upset hardware;
 261          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 262          * page) so that we end up taking a fault that the hardware really
 263          * *has* to handle gracefully without affecting other processes.
 264          */
 265         rcu_read_lock();
 266         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 267                 intel_pasid_clear_entry(sdev->dev, svm->pasid);
 268                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 269                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 270         }
 271         rcu_read_unlock();
 272
 273 }
 274
 275 static const struct mmu_notifier_ops intel_mmuops = {
 276         .flags = MMU_INVALIDATE_DOES_NOT_BLOCK,
 277         .release = intel_mm_release,
 278         .change_pte = intel_change_pte,
 279         .invalidate_range = intel_invalidate_range,
 280 };
 281
 282 static DEFINE_MUTEX(pasid_mutex);
 283 static LIST_HEAD(global_svm_list);
 284
 285 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 286 {
 287         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 288         struct pasid_entry *entry;
 289         struct intel_svm_dev *sdev;
 290         struct intel_svm *svm = NULL;
 291         struct mm_struct *mm = NULL;
 292         u64 pasid_entry_val;
 293         int pasid_max;
 294         int ret;
 295
 296         if (!iommu)
 297                 return -EINVAL;
 298
 299         if (dev_is_pci(dev)) {
 300                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 301                 if (pasid_max < 0)
 302                         return -EINVAL;
 303         } else
 304                 pasid_max = 1 << 20;
 305
 306         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 307                 if (!ecap_srs(iommu->ecap))
 308                         return -EINVAL;
 309         } else if (pasid) {
 310                 mm = get_task_mm(current);
 311                 BUG_ON(!mm);
 312         }
 313
 314         mutex_lock(&pasid_mutex);
 315         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 316                 struct intel_svm *t;
 317
 318                 list_for_each_entry(t, &global_svm_list, list) {
 319                         if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
 320                                 continue;
 321
 322                         svm = t;
 323                         if (svm->pasid >= pasid_max) {
 324                                 dev_warn(dev,
 325                                          "Limited PASID width. Cannot use existing PASID %d\n",
 326                                          svm->pasid);
 327                                 ret = -ENOSPC;
 328                                 goto out;
 329                         }
 330
 331                         list_for_each_entry(sdev, &svm->devs, list) {
 332                                 if (dev == sdev->dev) {
 333                                         if (sdev->ops != ops) {
 334                                                 ret = -EBUSY;
 335                                                 goto out;
 336                                         }
 337                                         sdev->users++;
 338                                         goto success;
 339                                 }
 340                         }
 341
 342                         break;
 343                 }
 344         }
 345
 346         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 347         if (!sdev) {
 348                 ret = -ENOMEM;
 349                 goto out;
 350         }
 351         sdev->dev = dev;
 352
 353         ret = intel_iommu_enable_pasid(iommu, sdev);
 354         if (ret || !pasid) {
 355                 /* If they don't actually want to assign a PASID, this is
 356                  * just an enabling check/preparation. */
 357                 kfree(sdev);
 358                 goto out;
 359         }
 360         /* Finish the setup now we know we're keeping it */
 361         sdev->users = 1;
 362         sdev->ops = ops;
 363         init_rcu_head(&sdev->rcu);
 364
 365         if (!svm) {
 366                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 367                 if (!svm) {
 368                         ret = -ENOMEM;
 369                         kfree(sdev);
 370                         goto out;
 371                 }
 372                 svm->iommu = iommu;
 373
 374                 if (pasid_max > intel_pasid_max_id)
 375                         pasid_max = intel_pasid_max_id;
 376
 377                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 378                 ret = intel_pasid_alloc_id(svm,
 379                                            !!cap_caching_mode(iommu->cap),
 380                                            pasid_max - 1, GFP_KERNEL);
 381                 if (ret < 0) {
 382                         kfree(svm);
 383                         kfree(sdev);
 384                         goto out;
 385                 }
 386                 svm->pasid = ret;
 387                 svm->notifier.ops = &intel_mmuops;
 388                 svm->mm = mm;
 389                 svm->flags = flags;
 390                 INIT_LIST_HEAD_RCU(&svm->devs);
 391                 INIT_LIST_HEAD(&svm->list);
 392                 ret = -ENOMEM;
 393                 if (mm) {
 394                         ret = mmu_notifier_register(&svm->notifier, mm);
 395                         if (ret) {
 396                                 intel_pasid_free_id(svm->pasid);
 397                                 kfree(svm);
 398                                 kfree(sdev);
 399                                 goto out;
 400                         }
 401                         pasid_entry_val = (u64)__pa(mm->pgd) | PASID_ENTRY_P;
 402                 } else
 403                         pasid_entry_val = (u64)__pa(init_mm.pgd) |
 404                                           PASID_ENTRY_P | PASID_ENTRY_SRE;
 405                 if (cpu_feature_enabled(X86_FEATURE_LA57))
 406                         pasid_entry_val |= PASID_ENTRY_FLPM_5LP;
 407
 408                 entry = intel_pasid_get_entry(dev, svm->pasid);
 409                 entry->val = pasid_entry_val;
 410
 411                 wmb();
 412
 413                 /*
 414                  * Flush PASID cache when a PASID table entry becomes
 415                  * present.
 416                  */
 417                 if (cap_caching_mode(iommu->cap))
 418                         intel_flush_pasid_dev(svm, sdev, svm->pasid);
 419
 420                 list_add_tail(&svm->list, &global_svm_list);
 421         }
 422         list_add_rcu(&sdev->list, &svm->devs);
 423
 424  success:
 425         *pasid = svm->pasid;
 426         ret = 0;
 427  out:
 428         mutex_unlock(&pasid_mutex);
 429         if (mm)
 430                 mmput(mm);
 431         return ret;
 432 }
 433 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 434
 435 int intel_svm_unbind_mm(struct device *dev, int pasid)
 436 {
 437         struct intel_svm_dev *sdev;
 438         struct intel_iommu *iommu;
 439         struct intel_svm *svm;
 440         int ret = -EINVAL;
 441
 442         mutex_lock(&pasid_mutex);
 443         iommu = intel_svm_device_to_iommu(dev);
 444         if (!iommu)
 445                 goto out;
 446
 447         svm = intel_pasid_lookup_id(pasid);
 448         if (!svm)
 449                 goto out;
 450
 451         list_for_each_entry(sdev, &svm->devs, list) {
 452                 if (dev == sdev->dev) {
 453                         ret = 0;
 454                         sdev->users--;
 455                         if (!sdev->users) {
 456                                 list_del_rcu(&sdev->list);
 457                                 /* Flush the PASID cache and IOTLB for this device.
 458                                  * Note that we do depend on the hardware *not* using
 459                                  * the PASID any more. Just as we depend on other
 460                                  * devices never using PASIDs that they have no right
 461                                  * to use. We have a *shared* PASID table, because it's
 462                                  * large and has to be physically contiguous. So it's
 463                                  * hard to be as defensive as we might like. */
 464                                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 465                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 466                                 kfree_rcu(sdev, rcu);
 467                                 intel_pasid_clear_entry(dev, svm->pasid);
 468
 469                                 if (list_empty(&svm->devs)) {
 470                                         intel_pasid_free_id(svm->pasid);
 471                                         if (svm->mm)
 472                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 473
 474                                         list_del(&svm->list);
 475
 476                                         /* We mandate that no page faults may be outstanding
 477                                          * for the PASID when intel_svm_unbind_mm() is called.
 478                                          * If that is not obeyed, subtle errors will happen.
 479                                          * Let's make them less subtle... */
 480                                         memset(svm, 0x6b, sizeof(*svm));
 481                                         kfree(svm);
 482                                 }
 483                         }
 484                         break;
 485                 }
 486         }
 487  out:
 488         mutex_unlock(&pasid_mutex);
 489
 490         return ret;
 491 }
 492 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 493
 494 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 495 {
 496         struct intel_iommu *iommu;
 497         struct intel_svm *svm;
 498         int ret = -EINVAL;
 499
 500         mutex_lock(&pasid_mutex);
 501         iommu = intel_svm_device_to_iommu(dev);
 502         if (!iommu)
 503                 goto out;
 504
 505         svm = intel_pasid_lookup_id(pasid);
 506         if (!svm)
 507                 goto out;
 508
 509         /* init_mm is used in this case */
 510         if (!svm->mm)
 511                 ret = 1;
 512         else if (atomic_read(&svm->mm->mm_users) > 0)
 513                 ret = 1;
 514         else
 515                 ret = 0;
 516
 517  out:
 518         mutex_unlock(&pasid_mutex);
 519
 520         return ret;
 521 }
 522 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 523
 524 /* Page request queue descriptor */
 525 struct page_req_dsc {
 526         u64 srr:1;
 527         u64 bof:1;
 528         u64 pasid_present:1;
 529         u64 lpig:1;
 530         u64 pasid:20;
 531         u64 bus:8;
 532         u64 private:23;
 533         u64 prg_index:9;
 534         u64 rd_req:1;
 535         u64 wr_req:1;
 536         u64 exe_req:1;
 537         u64 priv_req:1;
 538         u64 devfn:8;
 539         u64 addr:52;
 540 };
 541
 542 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 543
 544 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 545 {
 546         unsigned long requested = 0;
 547
 548         if (req->exe_req)
 549                 requested |= VM_EXEC;
 550
 551         if (req->rd_req)
 552                 requested |= VM_READ;
 553
 554         if (req->wr_req)
 555                 requested |= VM_WRITE;
 556
 557         return (requested & ~vma->vm_flags) != 0;
 558 }
 559
 560 static bool is_canonical_address(u64 addr)
 561 {
 562         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 563         long saddr = (long) addr;
 564
 565         return (((saddr << shift) >> shift) == saddr);
 566 }
 567
 568 static irqreturn_t prq_event_thread(int irq, void *d)
 569 {
 570         struct intel_iommu *iommu = d;
 571         struct intel_svm *svm = NULL;
 572         int head, tail, handled = 0;
 573
 574         /* Clear PPR bit before reading head/tail registers, to
 575          * ensure that we get a new interrupt if needed. */
 576         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 577
 578         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 579         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 580         while (head != tail) {
 581                 struct intel_svm_dev *sdev;
 582                 struct vm_area_struct *vma;
 583                 struct page_req_dsc *req;
 584                 struct qi_desc resp;
 585                 int result;
 586                 vm_fault_t ret;
 587                 u64 address;
 588
 589                 handled = 1;
 590
 591                 req = &iommu->prq[head / sizeof(*req)];
 592
 593                 result = QI_RESP_FAILURE;
 594                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 595                 if (!req->pasid_present) {
 596                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 597                                iommu->name, ((unsigned long long *)req)[0],
 598                                ((unsigned long long *)req)[1]);
 599                         goto bad_req;
 600                 }
 601
 602                 if (!svm || svm->pasid != req->pasid) {
 603                         rcu_read_lock();
 604                         svm = intel_pasid_lookup_id(req->pasid);
 605                         /* It *can't* go away, because the driver is not permitted
 606                          * to unbind the mm while any page faults are outstanding.
 607                          * So we only need RCU to protect the internal idr code. */
 608                         rcu_read_unlock();
 609
 610                         if (!svm) {
 611                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 612                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 613                                        ((unsigned long long *)req)[1]);
 614                                 goto no_pasid;
 615                         }
 616                 }
 617
 618                 result = QI_RESP_INVALID;
 619                 /* Since we're using init_mm.pgd directly, we should never take
 620                  * any faults on kernel addresses. */
 621                 if (!svm->mm)
 622                         goto bad_req;
 623                 /* If the mm is already defunct, don't handle faults. */
 624                 if (!mmget_not_zero(svm->mm))
 625                         goto bad_req;
 626
 627                 /* If address is not canonical, return invalid response */
 628                 if (!is_canonical_address(address))
 629                         goto bad_req;
 630
 631                 down_read(&svm->mm->mmap_sem);
 632                 vma = find_extend_vma(svm->mm, address);
 633                 if (!vma || address < vma->vm_start)
 634                         goto invalid;
 635
 636                 if (access_error(vma, req))
 637                         goto invalid;
 638
 639                 ret = handle_mm_fault(vma, address,
 640                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 641                 if (ret & VM_FAULT_ERROR)
 642                         goto invalid;
 643
 644                 result = QI_RESP_SUCCESS;
 645         invalid:
 646                 up_read(&svm->mm->mmap_sem);
 647                 mmput(svm->mm);
 648         bad_req:
 649                 /* Accounting for major/minor faults? */
 650                 rcu_read_lock();
 651                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 652                         if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
 653                                 break;
 654                 }
 655                 /* Other devices can go away, but the drivers are not permitted
 656                  * to unbind while any page faults might be in flight. So it's
 657                  * OK to drop the 'lock' here now we have it. */
 658                 rcu_read_unlock();
 659
 660                 if (WARN_ON(&sdev->list == &svm->devs))
 661                         sdev = NULL;
 662
 663                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 664                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 665                                 (req->exe_req << 1) | (req->priv_req);
 666                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
 667                 }
 668                 /* We get here in the error case where the PASID lookup failed,
 669                    and these can be NULL. Do not use them below this point! */
 670                 sdev = NULL;
 671                 svm = NULL;
 672         no_pasid:
 673                 if (req->lpig) {
 674                         /* Page Group Response */
 675                         resp.low = QI_PGRP_PASID(req->pasid) |
 676                                 QI_PGRP_DID((req->bus << 8) | req->devfn) |
 677                                 QI_PGRP_PASID_P(req->pasid_present) |
 678                                 QI_PGRP_RESP_TYPE;
 679                         resp.high = QI_PGRP_IDX(req->prg_index) |
 680                                 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
 681
 682                         qi_submit_sync(&resp, iommu);
 683                 } else if (req->srr) {
 684                         /* Page Stream Response */
 685                         resp.low = QI_PSTRM_IDX(req->prg_index) |
 686                                 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
 687                                 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
 688                         resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
 689                                 QI_PSTRM_RESP_CODE(result);
 690
 691                         qi_submit_sync(&resp, iommu);
 692                 }
 693
 694                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 695         }
 696
 697         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 698
 699         return IRQ_RETVAL(handled);
 700 }